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seyedmaysamlavasani/GorillaPP | apps/lib/floatingPoints/common/coreGen/virtex-6/multiplier/floating_point_v5_0.vhd | 1 | 4,929 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file floating_point_v5_0.vhd when simulating
-- the core, floating_point_v5_0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY floating_point_v5_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END floating_point_v5_0;
ARCHITECTURE floating_point_v5_0_a OF floating_point_v5_0 IS
-- synthesis translate_off
COMPONENT wrapped_floating_point_v5_0
PORT (
a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_floating_point_v5_0 USE ENTITY XilinxCoreLib.floating_point_v5_0(behavioral)
GENERIC MAP (
c_a_fraction_width => 53,
c_a_width => 64,
c_b_fraction_width => 53,
c_b_width => 64,
c_compare_operation => 8,
c_has_a_nd => 0,
c_has_a_negate => 0,
c_has_a_rfd => 0,
c_has_aclr => 0,
c_has_add => 0,
c_has_b_nd => 0,
c_has_b_negate => 0,
c_has_b_rfd => 0,
c_has_ce => 0,
c_has_compare => 0,
c_has_cts => 0,
c_has_divide => 0,
c_has_divide_by_zero => 0,
c_has_exception => 0,
c_has_fix_to_flt => 0,
c_has_flt_to_fix => 0,
c_has_flt_to_flt => 0,
c_has_inexact => 0,
c_has_invalid_op => 0,
c_has_multiply => 1,
c_has_operation_nd => 0,
c_has_operation_rfd => 0,
c_has_overflow => 0,
c_has_rdy => 0,
c_has_sclr => 0,
c_has_sqrt => 0,
c_has_status => 0,
c_has_subtract => 0,
c_has_underflow => 0,
c_latency => 15,
c_mult_usage => 2,
c_optimization => 1,
c_rate => 1,
c_result_fraction_width => 53,
c_result_width => 64,
c_speed => 2,
c_status_early => 0,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_floating_point_v5_0
PORT MAP (
a => a,
b => b,
clk => clk,
result => result
);
-- synthesis translate_on
END floating_point_v5_0_a;
| bsd-3-clause | af39ae41736631537ceff5156a07873d | 0.534591 | 4.124686 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/20x15/vgatimehelper.vhd | 1 | 4,696 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 20x15 Resolution, Timer Helper VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vgatimehelper is
port(
clk, reset: in std_logic; --send in 50mhz clock
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic; --p_tick is the 25mhz clock you will
--not need to use, video_on is when you
--can display a pixel
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vgatimehelper;
architecture arch of vgatimehelper is
-- VGA 640-by-480 sync parameters
constant HD: integer:=640; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace
constant VD: integer:=480; --vertical display area
constant VF: integer:=10; --v. front porch
constant VB: integer:=33; --v. back porch
constant VR: integer:=2; --v. retrace
-- mod-2 counter
signal mod2_reg, mod2_next: std_logic;
-- sync counters
signal v_count_reg, v_count_next: unsigned(9 downto 0);
signal h_count_reg, h_count_next: unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
-- registers
process (clk,reset)
begin
if reset='1' then
mod2_reg <= '0';
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '0';
h_sync_reg <= '0';
elsif (clk'event and clk='1') then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg='1' else '0';
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end,pixel_tick)
begin
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg>=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg>=(VD+VF)) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'0';
-- video on/off
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
| gpl-3.0 | 353e87e30973b4522670d92b4e1fdd28 | 0.568477 | 3.39971 | false | false | false | false |
seyedmaysamlavasani/GorillaPP | apps/lib/floatingPoints/common/coreGen/virtex-7/multiplier/floating_point_v5_0.vhd | 1 | 4,929 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file floating_point_v5_0.vhd when simulating
-- the core, floating_point_v5_0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY floating_point_v5_0 IS
PORT (
a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END floating_point_v5_0;
ARCHITECTURE floating_point_v5_0_a OF floating_point_v5_0 IS
-- synthesis translate_off
COMPONENT wrapped_floating_point_v5_0
PORT (
a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_floating_point_v5_0 USE ENTITY XilinxCoreLib.floating_point_v5_0(behavioral)
GENERIC MAP (
c_a_fraction_width => 53,
c_a_width => 64,
c_b_fraction_width => 53,
c_b_width => 64,
c_compare_operation => 8,
c_has_a_nd => 0,
c_has_a_negate => 0,
c_has_a_rfd => 0,
c_has_aclr => 0,
c_has_add => 0,
c_has_b_nd => 0,
c_has_b_negate => 0,
c_has_b_rfd => 0,
c_has_ce => 0,
c_has_compare => 0,
c_has_cts => 0,
c_has_divide => 0,
c_has_divide_by_zero => 0,
c_has_exception => 0,
c_has_fix_to_flt => 0,
c_has_flt_to_fix => 0,
c_has_flt_to_flt => 0,
c_has_inexact => 0,
c_has_invalid_op => 0,
c_has_multiply => 1,
c_has_operation_nd => 0,
c_has_operation_rfd => 0,
c_has_overflow => 0,
c_has_rdy => 0,
c_has_sclr => 0,
c_has_sqrt => 0,
c_has_status => 0,
c_has_subtract => 0,
c_has_underflow => 0,
c_latency => 15,
c_mult_usage => 2,
c_optimization => 1,
c_rate => 1,
c_result_fraction_width => 53,
c_result_width => 64,
c_speed => 2,
c_status_early => 0,
c_xdevicefamily => "virtex7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_floating_point_v5_0
PORT MAP (
a => a,
b => b,
clk => clk,
result => result
);
-- synthesis translate_on
END floating_point_v5_0_a;
| bsd-3-clause | 212cba19923f2280d206e14588a6564f | 0.534591 | 4.124686 | false | false | false | false |
Hyvok/HardHeat | src/pid.vhd | 1 | 3,354 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity pid is
generic
(
-- Coefficients are shifted left is positive and right if negative
-- Proportional coefficient
P_SHIFT_N : integer;
-- Integral coefficient
I_SHIFT_N : integer;
-- Number of bits in the filter
BITS_N : positive;
-- Initial output value
INIT_OUT_VAL : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
upd_clk_in : in std_logic;
setpoint_in : in signed(BITS_N - 1 downto 0);
pid_in : in signed(BITS_N - 1 downto 0);
pid_out : out signed(BITS_N - 1 downto 0)
);
end entity;
architecture rtl of pid is
begin
pid_p: process(clk, reset)
variable step : std_logic;
variable setpoint_err : signed(BITS_N - 1 downto 0);
variable prop : signed(BITS_N + 2 downto 0);
variable integ : signed(BITS_N + 2 downto 0);
variable sum : signed(BITS_N + 2 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
step := '0';
pid_out <= to_signed(INIT_OUT_VAL, pid_out'length);
setpoint_err := (others => '0');
integ := (others => '0');
prop := (others => '0');
sum := (others => '0');
last_state := '0';
elsif rising_edge(clk) then
if not upd_clk_in = last_state and upd_clk_in = '1' then
setpoint_err := setpoint_in - pid_in;
if P_SHIFT_N < 0 then
prop := shift_right(resize(setpoint_err, prop'length)
, -P_SHIFT_N);
else
prop := shift_left(resize(setpoint_err, prop'length)
, P_SHIFT_N);
end if;
-- Stop integrating to precent windup
if integ + setpoint_err >= 2**(integ'length - 2) - 1 then
integ := to_signed(2**(integ'length - 2) - 1
, integ'length);
elsif integ + setpoint_err <= -2**(integ'length - 2) + 1 then
integ := to_signed(-2**(integ'length - 2) + 1
, integ'length);
else
integ := integ + setpoint_err;
end if;
if I_SHIFT_N < 0 then
sum := prop + shift_right(integ, -I_SHIFT_N);
else
sum := prop + shift_left(integ, I_SHIFT_N);
end if;
step := '1';
elsif step = '1' then
if sum >= 2**(pid_out'length - 1) - 1 then
sum := to_signed(2**(pid_out'length - 1) - 1, sum'length);
elsif sum <= -2**(pid_out'length - 1) + 1 then
sum := to_signed(-2**(pid_out'length - 1) + 1, sum'length);
end if;
pid_out <= resize(sum, pid_out'length);
step := '0';
end if;
last_state := upd_clk_in;
end if;
end process;
end;
| mit | c59e1e227f1f26ca7376c3008db1631d | 0.444842 | 4.060533 | false | false | false | false |
Hyvok/HardHeat | src/epdm.vhd | 1 | 3,816 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity epdm is
port
(
clk : in std_logic;
reset : in std_logic;
-- Modulation level input, supports five pulse density levels
mod_lvl_in : in unsigned(2 downto 0);
mod_lvl_in_f : in std_logic;
-- Signal in, should have 50% duty cycle so no deadtime etc.
sig_in : in std_logic;
-- Left high-side switch etc.
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic
);
end entity;
architecture rtl of epdm is
begin
epdm_p: process(clk, reset)
variable count : unsigned(3 downto 0);
variable last_state : std_logic;
variable skip : std_logic;
variable alternate : std_logic;
begin
if reset = '1' then
sig_lh_out <= '0';
sig_ll_out <= '0';
sig_rh_out <= '0';
sig_rl_out <= '0';
count := (others => '0');
last_state := '0';
alternate := '0';
skip := '1';
elsif rising_edge(clk) then
-- New modulation level, reset counter
if mod_lvl_in_f = '1' then
count := (others => '0');
end if;
if not sig_in = last_state then
-- Count on rising and falling edge
if sig_in = '1' then
count := count + 1;
elsif sig_in = '0' then
count := count + 1;
end if;
-- Skip every sixth cycle
if to_integer(mod_lvl_in) = 3 then
if count = 6 then
skip := '1';
else
skip := '0';
end if;
-- Skip every fourth cycle
elsif to_integer(mod_lvl_in) = 2 then
if count mod 4 = 0 then
skip := '1';
else
skip := '0';
end if;
-- Skip every second cycle
elsif to_integer(mod_lvl_in) = 1 then
if count mod 2 = 0 then
skip := '1';
else
skip := '0';
end if;
-- Skip every cycle except every fourth
elsif to_integer(mod_lvl_in) = 0 then
if not (count mod 4 = 2) then
skip := '1';
else
skip := '0';
end if;
-- No skipping, full power
else
skip := '0';
end if;
-- Reset counter
if count = 12 then
-- Alternate switch pairs so one pair is not constantly on
if count mod 2 = 0 then
alternate := not alternate;
end if;
count := (others => '0');
end if;
end if;
-- Apply skipping
if skip = '1' then
sig_lh_out <= '0';
sig_ll_out <= '1';
sig_rh_out <= '0';
sig_rl_out <= '1';
else
sig_lh_out <= sig_in xor alternate;
sig_ll_out <= not sig_in xor alternate;
sig_rh_out <= not sig_in xor alternate;
sig_rl_out <= sig_in xor alternate;
end if;
last_state := sig_in;
end if;
end process;
end;
| mit | 87a166e725e5d3dbd54a6dfcf0e5a231 | 0.390985 | 4.592058 | false | false | false | false |
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
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| gpl-3.0 | edf9d98673a5e664f2ffbc895ef554c0 | 0.954982 | 1.828517 | false | false | false | false |
Hyvok/HardHeat | src/lock_detector.vhd | 1 | 1,727 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lock_detector is
generic
(
-- Number of bits in the phase-difference input
PHASE_TIME_IN_N : positive;
-- Number of bits in the lock counter
LOCK_COUNT_N : positive;
-- Number of bits in the unlock counter
ULOCK_COUNT_N : positive;
-- Value under which the phase is considered to be locked
LOCK_LIMIT : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
phase_time_in : in signed(PHASE_TIME_IN_N - 1 downto 0);
lock_out : out std_logic
);
end entity;
architecture rtl of lock_detector is
begin
lock_detector_p: process(clk, reset)
variable lock_count : unsigned(LOCK_COUNT_N - 1 downto 0);
variable ulock_count : unsigned(ULOCK_COUNT_N - 1 downto 0);
begin
if reset = '1' then
lock_count := (others => '0');
ulock_count := (others => '0');
lock_out <= '0';
elsif rising_edge(clk) then
if phase_time_in <= LOCK_LIMIT and phase_time_in >= -LOCK_LIMIT then
lock_count := lock_count + 1;
if lock_count = 2**lock_count'length - 1 then
lock_out <= '1';
end if;
else
lock_count := (others => '0');
ulock_count := ulock_count + 1;
if ulock_count = 2**ulock_count'length - 1 then
lock_out <= '0';
end if;
end if;
end if;
end process;
end;
| mit | 2894362094508fba096b713db70b66f4 | 0.490446 | 4.082742 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 1 | 142,619 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | adc79fa7c753e4485480c593132111c9 | 0.954291 | 1.830796 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 1 | 80,739 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-3.0 | cb76ec6c1d27aa834a8f8fb73491399b | 0.951052 | 1.839325 | false | false | false | false |
seyedmaysamlavasani/GorillaPP | apps/lib/floatingPoints/common/ieee_FP_pkg/aesl_fp_wrapper.vhd | 1 | 61,508 | -- Version: release . Copyright (C) 2011 XILINX, Inc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package AESL_FPSIM_UTIL is
function esl_conv_real(lv : UNSIGNED) return real;
function esl_conv_real(lv : SIGNED) return real;
end package;
package body AESL_FPSIM_UTIL is
function esl_conv_real(lv : UNSIGNED) return real is
variable ret : real;
variable power : integer;
variable msb : integer;
variable lv2 : UNSIGNED(lv'length - 1 downto 0);
begin
msb := lv'length - 1;
power := 2 ** 16;
ret := 0.0;
lv2 := lv;
while msb >= 16 loop
ret := ret * real(power);
ret := ret + real(CONV_INTEGER(lv2(msb downto (msb - 15))));
msb := msb - 16;
end loop;
power := 2 ** (msb + 1);
ret := ret * real(power);
ret := ret + real(CONV_INTEGER(lv2(msb downto 0)));
return ret;
end function;
function esl_conv_real(lv : SIGNED) return real is
variable ret : real;
variable sig : real;
variable msb : integer;
variable lv2 : UNSIGNED(lv'length - 1 downto 0);
begin
msb := lv'length - 1;
ret := 0.0;
if lv(msb) = '0' then
sig := 1.0;
lv2 := UNSIGNED(lv);
else
sig := -1.0;
lv2 := UNSIGNED(not STD_LOGIC_VECTOR(lv));
lv2 := lv2 + 1;
end if;
ret := esl_conv_real(lv2);
ret := ret * sig;
return ret;
end function;
end package body;
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FAdd is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FAdd;
architecture rtl of AESL_WP_FAdd is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= add(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FSub;
architecture rtl of AESL_WP_FSub is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= subtract(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FAddFSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
opcode: std_logic_vector(1 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FAddFSub;
architecture rtl of AESL_WP_FAddFSub is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
proc_dout_tmp : process(din0, din1, opcode)
begin
if (opcode(0) = '0') then
dout_tmp <= add(to_float(din0, 8, 23), to_float(din1, 8, 23));
else
dout_tmp <= subtract(to_float(din0, 8, 23), to_float(din1, 8, 23));
end if;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Mul
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FMul is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FMul;
architecture rtl of AESL_WP_FMul is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= multiply(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Div
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FDiv is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FDiv;
architecture rtl of AESL_WP_FDiv is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= divide(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Sqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FSqrt;
architecture rtl of AESL_WP_FSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= sqrt(to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision RSqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FRSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FRSqrt;
architecture rtl of AESL_WP_FRSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= reciprocal(sqrt(to_float(din1, 8, 23)));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Recip
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FRecip is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FRecip;
architecture rtl of AESL_WP_FRecip is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= reciprocal(to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DAdd is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DAdd;
architecture rtl of AESL_WP_DAdd is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= add(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DSub;
architecture rtl of AESL_WP_DSub is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= subtract(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DAddDSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
opcode : std_logic_vector(1 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DAddDSub;
architecture rtl of AESL_WP_DAddDSub is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
proc_dout_tmp : process(din0, din1, opcode)
begin
if (opcode(0) = '0') then
dout_tmp <= add(to_float(din0, 11, 52), to_float(din1, 11, 52));
else
dout_tmp <= subtract(to_float(din0, 11, 52), to_float(din1, 11, 52));
end if;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Mul
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DMul is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DMul;
architecture rtl of AESL_WP_DMul is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= multiply(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Div
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DDiv is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DDiv;
architecture rtl of AESL_WP_DDiv is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= divide(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Sqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DSqrt;
architecture rtl of AESL_WP_DSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= sqrt(to_float(din1, 11, 52), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision RSqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DRSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DRSqrt;
architecture rtl of AESL_WP_DRSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= reciprocal(sqrt(to_float(din1, 11, 52)), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Recip
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DRecip is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DRecip;
architecture rtl of AESL_WP_DRecip is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= reciprocal(to_float(din1, 11, 52), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FCmp is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 1 );
port (
clk : std_logic;
reset, ce: std_logic;
opcode: IN std_logic_VECTOR(4 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout: OUT std_logic_VECTOR(0 downto 0));
end AESL_WP_FCmp;
architecture rtl of AESL_WP_FCmp is
-- Predicate values:
constant FCMP_FALSE : std_logic_vector(3 downto 0) := "0000"; -- Always false (always folded)
constant FCMP_OEQ : std_logic_vector(3 downto 0) := "0001"; -- True if ordered and equal
constant FCMP_OGT : std_logic_vector(3 downto 0) := "0010"; -- True if ordered and greater than
constant FCMP_OGE : std_logic_vector(3 downto 0) := "0011"; -- True if ordered and greater than or equal
constant FCMP_OLT : std_logic_vector(3 downto 0) := "0100"; -- True if ordered and less than
constant FCMP_OLE : std_logic_vector(3 downto 0) := "0101"; -- True if ordered and less than or equal
constant FCMP_ONE : std_logic_vector(3 downto 0) := "0110"; -- True if ordered and operands are unequal
constant FCMP_ORD : std_logic_vector(3 downto 0) := "0111"; -- True if ordered (no nans)
constant FCMP_UNO : std_logic_vector(3 downto 0) := "1000"; -- True if unordered: isnan(X) | isnan(Y)
constant FCMP_UEQ : std_logic_vector(3 downto 0) := "1001"; -- True if unordered or equal
constant FCMP_UGT : std_logic_vector(3 downto 0) := "1010"; -- True if unordered or greater than
constant FCMP_UGE : std_logic_vector(3 downto 0) := "1011"; -- True if unordered, greater than, or equal
constant FCMP_ULT : std_logic_vector(3 downto 0) := "1100"; -- True if unordered or less than
constant FCMP_ULE : std_logic_vector(3 downto 0) := "1101"; -- True if unordered, less than, or equal
constant FCMP_UNE : std_logic_vector(3 downto 0) := "1110"; -- True if unordered or not equal
constant FCMP_TRUE : std_logic_vector(3 downto 0) := "1111"; -- Always true (always folded)
signal ordered : boolean;
signal dout_tmp : std_logic_vector(0 downto 0);
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(0 downto 0);
signal dout_buff : buff_type;
begin
ordered <= ((not Isnan(to_float(din0, 8, 23))) and (not Isnan(to_float(din1, 8, 23))));
proc_dout_tmp : process(opcode, din0, din1, ordered)
begin
case (opcode(3 downto 0)) is
when FCMP_FALSE => dout_tmp <= "0";
when FCMP_OEQ =>
if (ordered and eq(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OGT =>
if (ordered and gt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OGE =>
if (ordered and ge(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OLT =>
if (ordered and lt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OLE =>
if (ordered and le(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ONE =>
if (ordered and ne(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ORD =>
if (ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UNO =>
if (not ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UEQ =>
if ((not ordered) or eq(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UGT =>
if ((not ordered) or gt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UGE =>
if ((not ordered) or ge(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ULT =>
if ((not ordered) or lt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ULE =>
if ((not ordered) or le(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UNE =>
if ((not ordered) or ne(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_TRUE => dout_tmp <= "1";
when others => dout_tmp <= "0";
end case;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DCmp is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 1 );
port (
clk : std_logic;
reset, ce: std_logic;
opcode: IN std_logic_VECTOR(4 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout: OUT std_logic_VECTOR(0 downto 0));
end AESL_WP_DCmp;
architecture rtl of AESL_WP_DCmp is
-- Predicate values:
constant DCMP_FALSE : std_logic_vector(3 downto 0) := "0000"; -- Always false (always folded)
constant DCMP_OEQ : std_logic_vector(3 downto 0) := "0001"; -- True if ordered and equal
constant DCMP_OGT : std_logic_vector(3 downto 0) := "0010"; -- True if ordered and greater than
constant DCMP_OGE : std_logic_vector(3 downto 0) := "0011"; -- True if ordered and greater than or equal
constant DCMP_OLT : std_logic_vector(3 downto 0) := "0100"; -- True if ordered and less than
constant DCMP_OLE : std_logic_vector(3 downto 0) := "0101"; -- True if ordered and less than or equal
constant DCMP_ONE : std_logic_vector(3 downto 0) := "0110"; -- True if ordered and operands are unequal
constant DCMP_ORD : std_logic_vector(3 downto 0) := "0111"; -- True if ordered (no nans)
constant DCMP_UNO : std_logic_vector(3 downto 0) := "1000"; -- True if unordered: isnan(X) | isnan(Y)
constant DCMP_UEQ : std_logic_vector(3 downto 0) := "1001"; -- True if unordered or equal
constant DCMP_UGT : std_logic_vector(3 downto 0) := "1010"; -- True if unordered or greater than
constant DCMP_UGE : std_logic_vector(3 downto 0) := "1011"; -- True if unordered, greater than, or equal
constant DCMP_ULT : std_logic_vector(3 downto 0) := "1100"; -- True if unordered or less than
constant DCMP_ULE : std_logic_vector(3 downto 0) := "1101"; -- True if unordered, less than, or equal
constant DCMP_UNE : std_logic_vector(3 downto 0) := "1110"; -- True if unordered or not equal
constant DCMP_TRUE : std_logic_vector(3 downto 0) := "1111"; -- Always true (always folded)
signal ordered : boolean;
signal dout_tmp : std_logic_vector(0 downto 0);
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(0 downto 0);
signal dout_buff : buff_type;
begin
ordered <= ((not Isnan(to_float(din0, 11, 52))) and (not Isnan(to_float(din1, 11, 52))));
proc_dout_tmp : process(opcode, din0, din1, ordered)
begin
case (opcode(3 downto 0)) is
when DCMP_FALSE => dout_tmp <= "0";
when DCMP_OEQ =>
if (ordered and eq(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OGT =>
if (ordered and gt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OGE =>
if (ordered and ge(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OLT =>
if (ordered and lt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OLE =>
if (ordered and le(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ONE =>
if (ordered and ne(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ORD =>
if (ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UNO =>
if (not ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UEQ =>
if ((not ordered) or eq(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UGT =>
if ((not ordered) or gt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UGE =>
if ((not ordered) or ge(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ULT =>
if ((not ordered) or lt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ULE =>
if ((not ordered) or le(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UNE =>
if ((not ordered) or ne(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_TRUE => dout_tmp <= "1";
when others => dout_tmp <= "0";
end case;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_SPToSI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToSI;
architecture rtl of AESL_WP_SPToSI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH-1 downto 0);
begin
dout_tmp <= CONV_STD_LOGIC_VECTOR(to_integer(to_float(din0, 8, 23), round_zero, true), dout_WIDTH);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DPToSI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToSI;
architecture rtl of AESL_WP_DPToSI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH - 1 downto 0);
begin
dout_tmp <= CONV_STD_LOGIC_VECTOR(to_integer(to_float(din0, 11, 52), round_zero, true), dout_WIDTH);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_SIToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SIToSP;
architecture rtl of AESL_WP_SIToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
--dout_tmp <= to_float(CONV_INTEGER(signed(din0)), 8, 23);
dout_tmp <= to_float(esl_conv_real(SIGNED(din0)), 8, 23);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_SIToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SIToDP;
architecture rtl of AESL_WP_SIToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
--dout_tmp <= to_float(conv_integer(SIGNED(din0)), 11, 52);
dout_tmp <= to_float(esl_conv_real(SIGNED(din0)), 11, 52);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_SPToUI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToUI;
architecture rtl of AESL_WP_SPToUI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH-1 downto 0);
begin
dout_tmp <= CONV_STD_LOGIC_VECTOR(to_integer(to_float(din0, 8, 23), round_zero, true), dout_WIDTH);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DPToUI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToUI;
architecture rtl of AESL_WP_DPToUI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH - 1 downto 0);
begin
dout_tmp <= CONV_STD_LOGIC_VECTOR(to_integer(to_float(din0, 11, 52), round_zero, true), dout_WIDTH);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_UIToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_UIToSP;
architecture rtl of AESL_WP_UIToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= to_float(esl_conv_real(UNSIGNED(din0)), 8, 23);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_UIToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_UIToDP;
architecture rtl of AESL_WP_UIToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= to_float(esl_conv_real(UNSIGNED(din0)), 11, 52);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_SPToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToDP;
architecture rtl of AESL_WP_SPToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= to_float(to_real(to_float(din0, 8, 23)), 11, 52);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DPToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToSP;
architecture rtl of AESL_WP_DPToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= to_float(to_real(to_float(din0, 11, 52)), 8, 23);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
| bsd-3-clause | b1cf20de691943fb11e26253493ee20e | 0.501918 | 3.631576 | false | false | false | false |
Hyvok/HardHeat | src/pwr_sequencer.vhd | 1 | 3,690 | library ieee;
library work;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
use work.status_t_pkg.all;
entity pwr_sequencer is
generic
(
LEVELS_N : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
start_in : in std_logic;
fail_in : in std_logic_vector(LEVELS_N - 1 downto 0);
en_out : out std_logic_vector(LEVELS_N - 1 downto 0);
status_out : out status_t(LEVELS_N - 1 downto 0);
main_pwr_en_out : out std_logic;
main_pwr_fail_out : out std_logic
);
end entity;
architecture rtl of pwr_sequencer is
begin
pwr_sequencer_p: process(clk, reset)
type state_t is (idle, sequencing, power_on, power_fail);
variable state : state_t;
variable level_num : natural;
variable fail_states : std_logic_vector(LEVELS_N - 1 downto 0);
variable status : status_t(status_out'range);
variable last_start_state : std_logic;
begin
if reset = '1' then
state := idle;
level_num := 0;
fail_states := (others => '0');
status := (others => (others => '0'));
last_start_state := '0';
en_out <= (others => '0');
status_out <= (others => (others => '0'));
main_pwr_en_out <= '0';
main_pwr_fail_out <= '0';
elsif rising_edge(clk) then
if state = idle then
level_num := 0;
en_out <= (others => '0');
status := (others => (others => '0'));
status_out <= (others => (others => '0'));
-- Start power sequence with a rising edge
if not last_start_state = start_in and start_in = '1' then
state := sequencing;
main_pwr_fail_out <= '0';
end if;
elsif state = sequencing then
-- Enable sequencing level
en_out(level_num) <= '1';
-- Enable according status output (for LED etc.)
status(level_num)(0) := '1';
status_out <= status;
-- Wait for fail output to clear
if fail_in(level_num) = '0' then
status(level_num) := shift_left_vec(status(level_num), 1);
status_out <= status;
level_num := level_num + 1;
-- Sequencing done
if level_num = status_out'length then
state := power_on;
main_pwr_en_out <= '1';
end if;
end if;
elsif state = power_on then
-- Detect rising edges on fail inputs
for i in 0 to fail_in'high loop
if not fail_in(i) = fail_states(i) and fail_in(i) = '1' then
status(i) := "100";
status_out <= status;
state := power_fail;
main_pwr_en_out <= '0';
main_pwr_fail_out <= '1';
end if;
end loop;
elsif state = power_fail then
-- Restart sequencing
if not last_start_state = start_in and start_in = '0' then
state := idle;
end if;
end if;
fail_states := fail_in;
last_start_state := start_in;
end if;
end process;
end;
| mit | 70966a260fc94a7014ece2558ff5ecac | 0.439295 | 4.256055 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/40x30/vga_ip_core.vhd | 1 | 22,878 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, IP Core VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- vga_ip_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: vga_ip_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Oct 19 14:01:59 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library vga_ip_core_v1_00_a;
use vga_ip_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity vga_ip_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity vga_ip_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of vga_ip_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 7;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity vga_ip_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
hsync => hsync,
vsync => vsync,
rgb => rgb,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 | bc184af9edd53660ae5b16e504eb1bcb | 0.457053 | 4.441274 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/xbip_addsub_v3_0_vh_rfs.vhd | 1 | 33,878 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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BZMzpmih9LCNcJNzRMB/ak5dKvb9yXhQlyWQll12
`protect end_protected
| gpl-3.0 | 104e6bce26207e0630997c02a79352a1 | 0.945215 | 1.85755 | false | false | false | false |
kacaperek/serdescrc16 | crc16_tb.vhd | 1 | 2,659 | ----------------------------------------------------------------------------------
-- Company: PWr
-- Engineer: Kacper Witkowski
-- Module Name: Test Bench
-- Project Name: Nadajnik i odbiornik szeregowy z kontrolą poprawności przesyłu CRC16
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY serdes_tb IS
END serdes_tb;
ARCHITECTURE behavior OF serdes_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT serdes
PORT(
we : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
reset : IN std_logic;
wy : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal we : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal wy : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: serdes PORT MAP (
we => we,
clk => clk,
reset => reset,
wy => wy
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
we <= "01111110";
wait for clk_period;
reset <= '1';
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "10101011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "01101011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "10101011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*8;
we <= "11101011";
wait for clk_period*8;
we <= "01101011";
wait for clk_period*10;
we <= "01111110";
wait for clk_period*20;
we <= "11101011";
wait for clk_period*8;
we <= "10101011";
wait for clk_period*8;
we <= "11100011";
wait for clk_period*8;
we <= "10001010";
wait for clk_period*80;
assert false severity failure;
end process;
END;
| gpl-2.0 | 8f0f1fda348f58d144782ac92961be4e | 0.53238 | 3.584345 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/40x30/main.vhd | 1 | 3,988 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, Main VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity vga is
port (
clk: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
we: in std_logic;
add_bus1: in std_logic_vector(10 downto 0);
add_bus2: in std_logic_vector(10 downto 0);
add_bus3: in std_logic_vector(10 downto 0);
data_bus1: in std_logic_vector(4 downto 0);
data_bus2: in std_logic_vector(4 downto 0);
data_bus3: in std_logic_vector(3 downto 0)
);
end vga;
architecture Behavioral of vga is
signal rgb_reg: std_logic_vector(2 downto 0);
signal video_on: std_logic;
signal pixel_x, pixel_y : std_logic_vector(9 downto 0);
-- Foreground Tile-map : 40x30
Type tile_map is array(0 to 1199) of std_logic_vector(4 downto 0);
signal fore_map : tile_map; --(RAM 1)
-- Background Tile-map : 40x30
signal back_map : tile_map; --(RAM 2)
-- Sprites-map of 64x32
Type sprites_map is array(0 to 2047) of std_logic_vector(3 downto 0);
signal sprites : sprites_map; -- (RAM 3)
component vgatimehelper
port (
clk, reset : in std_logic;
hsync, vsync : out std_logic;
video_on, p_tick : out std_logic;
pixel_x, pixel_y : out std_logic_vector(9 downto 0));
end component;
signal index, index1, index2: integer;
signal reset: std_logic := '0';
begin
-- instantiate VGA sync circuit
vga_unit: vgatimehelper
port map(clk=>clk, reset=>reset, hsync=>hsync,
vsync=>vsync, video_on=>video_on,
p_tick=>open, pixel_x=>pixel_x, pixel_y=>pixel_y);
-- Creating and writing RAM 1:
ram1: process
begin
if rising_edge(clk) then
if( we = '1' ) then
fore_map(conv_integer(add_bus1)) <= data_bus1;
end if;
end if;
end process;
-- Creating and writing RAM 2:
ram2: process
begin
if rising_edge(clk) then
if( we = '1' ) then
back_map(conv_integer(add_bus2)) <= data_bus2;
end if;
end if;
end process;
-- Creating and writing RAM 3:
ram3: process
begin
if rising_edge(clk) then
if( we = '1' ) then
sprites(conv_integer(add_bus3)) <= data_bus3;
end if;
end if;
end process;
-- Draw on the LCD screen:
-- Conversion from 640x480 scale to 40x30 scale:
index <= conv_integer(pixel_y(9 downto 4))*40 + conv_integer(pixel_x(9 downto 4));
index1 <= (conv_integer(pixel_y(3 downto 1)))*8 + (conv_integer(pixel_x(3 downto 1))) +
(conv_integer(fore_map(index))*64);
index2 <= (conv_integer(pixel_y(3 downto 1)))*8 + (conv_integer(pixel_x(3 downto 1))) +
(conv_integer(back_map(index))*64);
rgb_reg <= sprites(index1)(2 downto 0) when sprites(index1)(3) = '0' else sprites(index2)(2 downto 0);
rgb <= rgb_reg when video_on='1' else "000";
end Behavioral;
| gpl-3.0 | a6e8a5a86c6bd9e8c9c0077f94dd38ab | 0.629546 | 3.151779 | false | false | false | false |
aylons/concordic | hdl/modules/cordic_vectoring/cordic_vectoring_slv.vhd | 1 | 5,122 | -------------------------------------------------------------------------------
-- Title : Vectoring-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_vectoring_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-13
-- Last update: 2014-09-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a top-block for vectoring mode using concordic,
-- constrained standard_logic_vector version.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-13 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity cordic_vectoring_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32
);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0');
valid_o : out std_logic
);
end entity cordic_vectoring_slv;
-------------------------------------------------------------------------------
architecture str of cordic_vectoring_slv is
signal adjusted_x : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_y : signed(g_width-1 downto 0) := (others => '0');
signal adjusted_z : signed(g_width-1 downto 0) := (others => '0');
signal mag_temp : signed(g_width-1 downto 0) := (others => '0');
signal phase_temp : signed(g_width-1 downto 0) := (others => '0');
signal y_temp : signed(g_width-1 downto 0) := (others => '0');
signal valid_temp : std_logic := '0';
component inversion_stage is
generic (
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component inversion_stage;
component cordic_core is
generic (
g_stages : natural;
g_mode : string;
g_bit_growth : natural);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic);
end component cordic_core;
begin -- architecture str
cmp_inversion : inversion_stage
generic map (
g_mode => "rect_to_polar")
port map (
x_i => signed(x_i),
y_i => signed(y_i),
z_i => (g_width-1 downto 0 => '0'),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
x_o => adjusted_x,
y_o => adjusted_y,
z_o => adjusted_z,
valid_o => valid_temp);
cmp_core : cordic_core
generic map (
g_stages => g_stages,
g_mode => "rect_to_polar",
g_bit_growth => natural(ceil(log2(real(g_stages)))))
port map (
x_i => adjusted_x,
y_i => adjusted_y,
z_i => adjusted_z,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_temp,
x_o => mag_temp,
y_o => y_temp,
z_o => phase_temp,
valid_o => valid_o);
mag_o <= std_logic_vector(mag_temp);
phase_o <= std_logic_vector(phase_temp);
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 27343a4cf8be89b33ece1df49f2019f2 | 0.482038 | 3.658571 | false | false | false | false |
summershrimp/VHDLClock | Counter60.vhd | 1 | 946 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Counter60 is
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Entity Counter60;
Architecture ArchCounter60 of Counter60 is
Begin
Process(clk, rst)
Variable tlow:std_logic_vector(3 downto 0);
Variable thigh:std_logic_vector(2 downto 0);
Begin
If rst = '1' then
tlow := (Others => '0' );
thigh := (Others => '0' );
Elsif clk'event and clk='1' Then
co<='0';
If en = '1' Then
If tlow < 10 Then
tlow := tlow + 1;
End If;
If tlow = 10 Then
thigh := thigh + 1;
tlow := (Others => '0' );
End If;
If thigh = 6 Then
thigh := (Others => '0');
co<='1';
End If;
h<=thigh;
l<=tlow;
End If;
End If;
End Process;
End Architecture;
| gpl-2.0 | 37ae8d5ff0c519ee1fe1bf85a02f2983 | 0.573996 | 2.774194 | false | false | false | false |
sudov/options-accel | final_design/verilog/ieee_FP_pkg/aesl_fp_wrapper.vhd | 1 | 69,144 | -- Version: release . Copyright (C) 2011 XILINX, Inc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package AESL_FPSIM_UTIL is
function esl_conv_real(lv : UNSIGNED) return real;
function esl_conv_real(lv : SIGNED) return real;
end package;
package body AESL_FPSIM_UTIL is
function esl_conv_real(lv : UNSIGNED) return real is
variable ret : real;
variable power : integer;
variable msb : integer;
variable lv2 : UNSIGNED(lv'length - 1 downto 0);
begin
msb := lv'length - 1;
power := 2 ** 16;
ret := 0.0;
lv2 := lv;
while msb >= 16 loop
ret := ret * real(power);
ret := ret + real(to_integer(lv2(msb downto (msb - 15))));
msb := msb - 16;
end loop;
power := 2 ** (msb + 1);
ret := ret * real(power);
ret := ret + real(to_integer(lv2(msb downto 0)));
return ret;
end function;
function esl_conv_real(lv : SIGNED) return real is
variable ret : real;
variable sig : real;
variable msb : integer;
variable lv2 : UNSIGNED(lv'length - 1 downto 0);
begin
msb := lv'length - 1;
ret := 0.0;
if lv(msb) = '0' then
sig := 1.0;
lv2 := UNSIGNED(lv);
else
sig := -1.0;
lv2 := UNSIGNED(not STD_LOGIC_VECTOR(lv));
lv2 := lv2 + 1;
end if;
ret := esl_conv_real(lv2);
ret := ret * sig;
return ret;
end function;
end package body;
-- --------------------------------------------------------------------
-- Title : float_alg_pkg.vhd
-- These are the algorithemic functions. In this package you will find
-- routines for doing complex arithmetic and basic Trig functions. These
-- functions are not optomized, and are placed here as examples. In the
-- future, a new complex number format will be used and placed into the
-- floating point packages. The names of the routines have been changed
-- from "fp_*" to "fpalg_*" so that there will be no name space violations.
-- Last Modified: $Date: 2011/01/26 16:06:55 $
-- RCS ID: $Id: float_alg_pkg.vhdl,v 2.0 2011/01/26 16:06:55 l435385 Exp l435385 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-- ---------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
package float_alg_pkg is
-- This differed constant will tell you if the package body is synthesizable
-- or implimented as real numbers.
constant fpalgsynth_or_real : BOOLEAN; -- differed constant
-- Used to generate the constants.
type gen_number_type is (pi, half_pi, e, log2x, onef, mone, twof);
-- returns ln(arg)
function ln (
arg : float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize;
constant iterations : NATURAL := 0)
return float;
end package float_alg_pkg;
library ieee;
use ieee.math_real.all;
package body float_alg_pkg is
-- Set to "true" if synthesizable, "false" if done with real numbers
constant fpalgsynth_or_real : BOOLEAN := false; -- differed constant
function ln (
arg : float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize;
constant iterations : NATURAL := 0)
return float is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable arg_real, result : REAL; -- Real versions
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
begin
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan => -- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_normal | neg_denormal | neg_inf => -- log (neg)
-- Return quiet NAN, IEEE754-1985-7.1,5*
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf => -- log (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero => -- log (0), return negative infinity
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
arg_real := to_real (arg => arg,
denormalize => denormalize);
result := log (arg_real);
fpresult := to_float (arg => result,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize);
end case classcase;
return fpresult;
end function ln;
end package body float_alg_pkg;
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FAdd is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FAdd;
architecture rtl of AESL_WP_FAdd is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= add(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FSub;
architecture rtl of AESL_WP_FSub is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= subtract(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FAddFSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
opcode: std_logic_vector(1 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FAddFSub;
architecture rtl of AESL_WP_FAddFSub is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
proc_dout_tmp : process(din0, din1, opcode)
begin
if (opcode(0) = '0') then
dout_tmp <= add(to_float(din0, 8, 23), to_float(din1, 8, 23));
else
dout_tmp <= subtract(to_float(din0, 8, 23), to_float(din1, 8, 23));
end if;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Mul
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FMul is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FMul;
architecture rtl of AESL_WP_FMul is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= multiply(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Div
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FDiv is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FDiv;
architecture rtl of AESL_WP_FDiv is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= divide(to_float(din0, 8, 23), to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Sqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FSqrt;
architecture rtl of AESL_WP_FSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= sqrt(to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision RSqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FRSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FRSqrt;
architecture rtl of AESL_WP_FRSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= reciprocal(sqrt(to_float(din1, 8, 23)));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Recip
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FRecip is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FRecip;
architecture rtl of AESL_WP_FRecip is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= reciprocal(to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Log
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.float_alg_pkg.all;
entity AESL_WP_FLog is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_FLog;
architecture rtl of AESL_WP_FLog is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= ln(to_float(din1, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DAdd is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DAdd;
architecture rtl of AESL_WP_DAdd is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= add(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DSub;
architecture rtl of AESL_WP_DSub is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= subtract(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DAddDSub is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
opcode : std_logic_vector(1 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DAddDSub;
architecture rtl of AESL_WP_DAddDSub is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
proc_dout_tmp : process(din0, din1, opcode)
begin
if (opcode(0) = '0') then
dout_tmp <= add(to_float(din0, 11, 52), to_float(din1, 11, 52));
else
dout_tmp <= subtract(to_float(din0, 11, 52), to_float(din1, 11, 52));
end if;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Mul
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DMul is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DMul;
architecture rtl of AESL_WP_DMul is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= multiply(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Div
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DDiv is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DDiv;
architecture rtl of AESL_WP_DDiv is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= divide(to_float(din0, 11, 52), to_float(din1, 11, 52));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Sqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DSqrt;
architecture rtl of AESL_WP_DSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= sqrt(to_float(din1, 11, 52), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision RSqrt
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DRSqrt is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DRSqrt;
architecture rtl of AESL_WP_DRSqrt is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= reciprocal(sqrt(to_float(din1, 11, 52)), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Recip
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DRecip is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DRecip;
architecture rtl of AESL_WP_DRecip is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= reciprocal(to_float(din1, 11, 52), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Log
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_alg_pkg.all;
entity AESL_WP_DLog is
generic (
NUM_STAGE : INTEGER := 13;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 64);
port (
clk, reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0));
end AESL_WP_DLog;
architecture rtl of AESL_WP_DLog is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= ln(to_float(din1, 11, 52), round_nearest, 10);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_FCmp is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
din1_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 1 );
port (
clk : std_logic;
reset, ce: std_logic;
opcode: IN std_logic_VECTOR(4 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout: OUT std_logic_VECTOR(0 downto 0));
end AESL_WP_FCmp;
architecture rtl of AESL_WP_FCmp is
-- Predicate values:
constant FCMP_FALSE : std_logic_vector(3 downto 0) := "0000"; -- Always false (always folded)
constant FCMP_OEQ : std_logic_vector(3 downto 0) := "0001"; -- True if ordered and equal
constant FCMP_OGT : std_logic_vector(3 downto 0) := "0010"; -- True if ordered and greater than
constant FCMP_OGE : std_logic_vector(3 downto 0) := "0011"; -- True if ordered and greater than or equal
constant FCMP_OLT : std_logic_vector(3 downto 0) := "0100"; -- True if ordered and less than
constant FCMP_OLE : std_logic_vector(3 downto 0) := "0101"; -- True if ordered and less than or equal
constant FCMP_ONE : std_logic_vector(3 downto 0) := "0110"; -- True if ordered and operands are unequal
constant FCMP_ORD : std_logic_vector(3 downto 0) := "0111"; -- True if ordered (no nans)
constant FCMP_UNO : std_logic_vector(3 downto 0) := "1000"; -- True if unordered: isnan(X) | isnan(Y)
constant FCMP_UEQ : std_logic_vector(3 downto 0) := "1001"; -- True if unordered or equal
constant FCMP_UGT : std_logic_vector(3 downto 0) := "1010"; -- True if unordered or greater than
constant FCMP_UGE : std_logic_vector(3 downto 0) := "1011"; -- True if unordered, greater than, or equal
constant FCMP_ULT : std_logic_vector(3 downto 0) := "1100"; -- True if unordered or less than
constant FCMP_ULE : std_logic_vector(3 downto 0) := "1101"; -- True if unordered, less than, or equal
constant FCMP_UNE : std_logic_vector(3 downto 0) := "1110"; -- True if unordered or not equal
constant FCMP_TRUE : std_logic_vector(3 downto 0) := "1111"; -- Always true (always folded)
signal ordered : boolean;
signal dout_tmp : std_logic_vector(0 downto 0);
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(0 downto 0);
signal dout_buff : buff_type;
begin
ordered <= ((not Isnan(to_float(din0, 8, 23))) and (not Isnan(to_float(din1, 8, 23))));
proc_dout_tmp : process(opcode, din0, din1, ordered)
begin
case (opcode(3 downto 0)) is
when FCMP_FALSE => dout_tmp <= "0";
when FCMP_OEQ =>
if (ordered and eq(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OGT =>
if (ordered and gt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OGE =>
if (ordered and ge(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OLT =>
if (ordered and lt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_OLE =>
if (ordered and le(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ONE =>
if (ordered and ne(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ORD =>
if (ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UNO =>
if (not ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UEQ =>
if ((not ordered) or eq(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UGT =>
if ((not ordered) or gt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UGE =>
if ((not ordered) or ge(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ULT =>
if ((not ordered) or lt(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_ULE =>
if ((not ordered) or le(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_UNE =>
if ((not ordered) or ne(to_float(din0, 8, 23), to_float(din1, 8, 23))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when FCMP_TRUE => dout_tmp <= "1";
when others => dout_tmp <= "0";
end case;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
Library IEEE;
use IEEE.std_logic_1164.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DCmp is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
din1_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 1 );
port (
clk : std_logic;
reset, ce: std_logic;
opcode: IN std_logic_VECTOR(4 downto 0);
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout: OUT std_logic_VECTOR(0 downto 0));
end AESL_WP_DCmp;
architecture rtl of AESL_WP_DCmp is
-- Predicate values:
constant DCMP_FALSE : std_logic_vector(3 downto 0) := "0000"; -- Always false (always folded)
constant DCMP_OEQ : std_logic_vector(3 downto 0) := "0001"; -- True if ordered and equal
constant DCMP_OGT : std_logic_vector(3 downto 0) := "0010"; -- True if ordered and greater than
constant DCMP_OGE : std_logic_vector(3 downto 0) := "0011"; -- True if ordered and greater than or equal
constant DCMP_OLT : std_logic_vector(3 downto 0) := "0100"; -- True if ordered and less than
constant DCMP_OLE : std_logic_vector(3 downto 0) := "0101"; -- True if ordered and less than or equal
constant DCMP_ONE : std_logic_vector(3 downto 0) := "0110"; -- True if ordered and operands are unequal
constant DCMP_ORD : std_logic_vector(3 downto 0) := "0111"; -- True if ordered (no nans)
constant DCMP_UNO : std_logic_vector(3 downto 0) := "1000"; -- True if unordered: isnan(X) | isnan(Y)
constant DCMP_UEQ : std_logic_vector(3 downto 0) := "1001"; -- True if unordered or equal
constant DCMP_UGT : std_logic_vector(3 downto 0) := "1010"; -- True if unordered or greater than
constant DCMP_UGE : std_logic_vector(3 downto 0) := "1011"; -- True if unordered, greater than, or equal
constant DCMP_ULT : std_logic_vector(3 downto 0) := "1100"; -- True if unordered or less than
constant DCMP_ULE : std_logic_vector(3 downto 0) := "1101"; -- True if unordered, less than, or equal
constant DCMP_UNE : std_logic_vector(3 downto 0) := "1110"; -- True if unordered or not equal
constant DCMP_TRUE : std_logic_vector(3 downto 0) := "1111"; -- Always true (always folded)
signal ordered : boolean;
signal dout_tmp : std_logic_vector(0 downto 0);
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(0 downto 0);
signal dout_buff : buff_type;
begin
ordered <= ((not Isnan(to_float(din0, 11, 52))) and (not Isnan(to_float(din1, 11, 52))));
proc_dout_tmp : process(opcode, din0, din1, ordered)
begin
case (opcode(3 downto 0)) is
when DCMP_FALSE => dout_tmp <= "0";
when DCMP_OEQ =>
if (ordered and eq(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OGT =>
if (ordered and gt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OGE =>
if (ordered and ge(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OLT =>
if (ordered and lt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_OLE =>
if (ordered and le(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ONE =>
if (ordered and ne(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ORD =>
if (ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UNO =>
if (not ordered) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UEQ =>
if ((not ordered) or eq(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UGT =>
if ((not ordered) or gt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UGE =>
if ((not ordered) or ge(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ULT =>
if ((not ordered) or lt(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_ULE =>
if ((not ordered) or le(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_UNE =>
if ((not ordered) or ne(to_float(din0, 11, 52), to_float(din1, 11, 52))) then
dout_tmp <= "1";
else
dout_tmp <= "0";
end if;
when DCMP_TRUE => dout_tmp <= "1";
when others => dout_tmp <= "0";
end case;
end process;
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_SPToSI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToSI;
architecture rtl of AESL_WP_SPToSI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH-1 downto 0);
begin
dout_tmp <= std_logic_vector(resize(to_signed(to_float(din0, 8, 23), 32, round_zero, true), dout_WIDTH));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DPToSI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToSI;
architecture rtl of AESL_WP_DPToSI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH - 1 downto 0);
begin
dout_tmp <= std_logic_vector(resize(to_signed(to_float(din0, 11, 52), 64, round_zero, true), dout_WIDTH));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_SIToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce : std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SIToSP;
architecture rtl of AESL_WP_SIToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= to_float(esl_conv_real(SIGNED(din0)), 8, 23);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_SIToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SIToDP;
architecture rtl of AESL_WP_SIToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= to_float(esl_conv_real(SIGNED(din0)), 11, 52);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_SPToUI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToUI;
architecture rtl of AESL_WP_SPToUI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH-1 downto 0);
begin
dout_tmp <= std_logic_vector(resize(to_unsigned(to_float(din0, 8, 23), 32, round_zero, true), dout_WIDTH));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.float_pkg.all;
entity AESL_WP_DPToUI is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToUI;
architecture rtl of AESL_WP_DPToUI is
type buff_type is array (0 to NUM_STAGE - 2) of std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_buff : buff_type;
signal dout_tmp : std_logic_vector(dout_WIDTH - 1 downto 0);
begin
dout_tmp <= std_logic_vector(resize(to_unsigned(to_float(din0, 11, 52), 64, round_zero, true), dout_WIDTH));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= dout_buff(NUM_STAGE - 2);
else
dout <= dout_tmp;
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_UIToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_UIToSP;
architecture rtl of AESL_WP_UIToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
dout_tmp <= to_float(esl_conv_real(UNSIGNED(din0)), 8, 23);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.AESL_FPSIM_UTIL.all;
entity AESL_WP_UIToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_UIToDP;
architecture rtl of AESL_WP_UIToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= to_float(esl_conv_real(UNSIGNED(din0)), 11, 52);
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_SPToDP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 32;
dout_WIDTH : INTEGER := 64 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_SPToDP;
architecture rtl of AESL_WP_SPToDP is
type buff_type is array (0 to NUM_STAGE - 2) of float64;
signal dout_buff : buff_type;
signal dout_tmp : float64;
begin
dout_tmp <= to_float64(to_float(din0, 8, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library work;
use work.all;
Library ieee_proposed;
use ieee_proposed.float_pkg.all;
use ieee_proposed.fixed_float_types.all;
entity AESL_WP_DPToSP is
generic (
NUM_STAGE : INTEGER := 12;
din0_WIDTH : INTEGER := 64;
dout_WIDTH : INTEGER := 32 );
port (
clk : std_logic;
reset, ce: std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0) );
end AESL_WP_DPToSP;
architecture rtl of AESL_WP_DPToSP is
type buff_type is array (0 to NUM_STAGE - 2) of float32;
signal dout_buff : buff_type;
signal dout_tmp : float32;
begin
-- NOTE:
-- the following line returns incorrect result(inf) when din0 is a 'denomalized number'
-- dout_tmp <= to_float32(to_float(din0, 11, 52));
dout_tmp <= to_float32(resize(resize(to_float(din0, 11, 52), 10, 23), 9, 23));
proc_dout : process(dout_tmp, dout_buff)
begin
if (NUM_STAGE > 1) then
dout <= to_slv(dout_buff(NUM_STAGE - 2));
else
dout <= to_slv(dout_tmp);
end if;
end process;
proc_buff : process(clk)
variable i: integer;
begin
if (clk'event and clk = '1') then
if (NUM_STAGE > 1 and ce = '1') then
for i in 0 to NUM_STAGE - 2 loop
if (i = 0) then
dout_buff(i) <= dout_tmp;
else
dout_buff(i) <= dout_buff(i - 1);
end if;
end loop;
end if;
end if;
end process;
end rtl;
| apache-2.0 | ce70b40e1618b3b11c4d5648cdc05885 | 0.507058 | 3.668895 | false | false | false | false |
upci/upci | Projeto/controller.vhd | 1 | 4,865 | ---- Controller --------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY controller IS
PORT (clk, nrst: IN std_logic;
CONTROL_bus: INOUT std_logic_vector(n-1 DOWNTO 0);
state_7seg: OUT std_logic_vector(0 TO 7);
-- IR
IR_opcode: IN opcode;
IR_load: OUT std_logic;
IR_valid: OUT std_logic;
-- PC
PC_inc: OUT std_logic;
PC_load: OUT std_logic;
PC_valid: OUT std_logic;
-- Memory
MDR_load: OUT std_logic;
MAR_load: OUT std_logic;
MEM_valid: OUT std_logic;
MEM_en: OUT std_logic;
MEM_rw: OUT std_logic;
-- ALU
ALU_zero: IN std_logic;
ALU_valid: OUT std_logic;
ALU_slt: IN std_logic;
ALU_enable: OUT std_logic;
ALU_cmd: OUT std_logic_vector(3 DOWNTO 0);
-- IO
IODR_load: OUT STD_LOGIC;
IOAR_load: OUT STD_LOGIC;
IO_valid: OUT STD_LOGIC;
IO_en: OUT STD_LOGIC;
IO_rw: OUT STD_LOGIC;
-- WAKE
WAKE_signal: IN STD_LOGIC;
waiting: OUT STD_LOGIC);
END ENTITY controller;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE RTL OF controller IS
TYPE states IS (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10);
SIGNAL current_state, next_state: states;
SIGNAL BRANCH_trigger: std_logic;
SIGNAL state_vector: STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT bcd_to_7seg IS
PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
en: IN std_logic;
output: OUT STD_LOGIC_VECTOR (0 TO 7));
END COMPONENT;
BEGIN
-- Converte o estado atual para um std_logic_vector com sua posicao na lista
state_vector <= std_logic_vector(to_unsigned(states'pos(current_state), 4));
-- Gera a visualizacao 7seg
state7seg: bcd_to_7seg PORT MAP(state_vector, seg_en, state_7seg);
-- Indicador de se o branch deve ser aceito
BRANCH_trigger <= '1' WHEN ((IR_opcode = BZERO AND ALU_zero = '1') OR (IR_opcode = BLESS AND ALU_slt = '1') OR (IR_opcode = BGREATER AND ALU_zero = '0' AND ALU_slt = '0')) ELSE '0';
-- Esta em waiting?
waiting <= '1' WHEN current_state = s10 ELSE '0';
-- Processo que gerencia a transicao do current_state para o next_state
-- e a configuracao de reset
state_sequence: PROCESS (clk, nrst) BEGIN
IF nrst = '0' THEN -- reset assincrono
current_state <= s0;
ELSE
IF rising_edge(clk) THEN -- mudanca de estado eh sincrona
current_state <= next_state;
END IF;
END IF;
END PROCESS state_sequence;
-- espera a mudanca de estado ou opcode
-- processo que de fato mudam os sinais de controle conforme a transicao
state_machine: PROCESS ( current_state, IR_opcode ) IS
BEGIN
-- Reset all the control SIGNALs
IR_load <= '0';
IR_valid <= '0';
PC_inc <= '0';
PC_load <= '0';
PC_valid <= '0';
MDR_load <= '0';
MAR_load <= '0';
MEM_valid <= '0';
MEM_en <= '0';
MEM_rw <= '0';
ALU_valid <= '0';
ALU_enable <= '0';
ALU_cmd <= "0000";
IODR_load <= '0';
IOAR_load <= '0';
IO_valid <= '0';
IO_en <= '0';
IO_rw <= '0';
CASE current_state IS
WHEN s0 =>
MAR_load <= '1';
PC_valid <= '1';
PC_inc <= '1';
next_state <= s1;
WHEN s1 =>
MEM_en <='1';
next_state <= s2;
WHEN s2 =>
MEM_valid <= '1';
IR_load <= '1';
next_state <= s3;
WHEN s3 =>
IR_valid <= '1';
MAR_load <= '1';
IOAR_load <= '1';
IF (IR_opcode = INC) THEN
next_state <= s7;
ELSIF (IR_opcode = JUMP) THEN
next_state <= s9;
ELSIF (IR_opcode = BZERO OR IR_opcode = BGREATER OR IR_opcode = BLESS) THEN
next_state <= s8;
ELSIF (IR_opcode = NOP) THEN
next_state <= s0;
ELSIF (IR_opcode = WAITT) THEN
next_state <= s10;
ELSIF (IR_opcode = STORE) THEN
next_state <= s4;
ELSE
next_state <= s6;
END IF;
WHEN s4 =>
ALU_valid <= '1';
MDR_load <= '1';
IODR_load <= '1';
next_state <= s5;
WHEN s5 =>
MEM_en <= '1';
MEM_rw <= '1';
IO_en <= '1';
IO_rw <= '1';
next_state <= s0;
WHEN s6 =>
MEM_en <= '1';
IO_en <= '1';
next_state <= s7;
WHEN s7 =>
MEM_valid <= '1';
IO_valid <= '1';
ALU_enable <= '1';
ALU_cmd <= cmdDecode(IR_opcode);
next_state <= s0;
WHEN s8 =>
IF (BRANCH_trigger = '1') THEN
next_state <= s9;
ELSE
next_state <= s0;
END IF;
WHEN s9 =>
PC_load <= '1';
IR_valid <= '1';
next_state <= s0;
WHEN s10 =>
IF (WAKE_signal = '0') THEN
next_state <= s0;
END IF;
END CASE;
END PROCESS state_machine;
END ARCHITECTURE;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 | c1faa0914ef16b236baef6f8a0cbae1d | 0.531661 | 2.933655 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/clk_div.vhd | 3 | 1,020 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_div is
generic (MAXD: natural:=5);
port(
clk: in std_logic;
reset: in std_logic;
div: in integer range 0 to MAXD;
div_clk: out std_logic
);
end clk_div;
architecture Behavioral of clk_div is
begin
process(clk,reset)
variable M: integer range 0 to MAXD;
begin
if reset='1' then --reset clock divider
M := 0;
div_clk <= '0';
elsif(rising_edge(clk)) then -- generate a pulse when the counter = (the division magnitude -1)
if M=div-1 then
div_clk <= '1';
M := 0;
else
M := M +1 ;
div_clk <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | d2130a833739e2889f790eae6bd5a29e | 0.565686 | 3.566434 | false | false | false | false |
kjellhar/ArtixPi | spi_test/src/hdl/spi_slave_old.vhd | 1 | 5,579 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 04:17:04 AM
-- Design Name:
-- Module Name: spi_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_slave is
Generic (
N : positive := 8;
CPOL : std_logic := '0';
CPHA : std_logic := '0'
);
Port ( clk : in STD_LOGIC;
-- External SPI signals
spi_ss_n : in STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_mosi : in STD_LOGIC;
spi_miso : out STD_LOGIC;
-- Internal data signals
di : out STD_LOGIC_VECTOR (N-1 downto 0); -- Data received from SPI
do : in STD_LOGIC_VECTOR (N-1 downto 0); -- Data to be transmitted over SPI
di_valid : out std_logic; -- High for one clock cycle to indicate a new word is present
do_wren : in std_logic; -- Write a data word to the transmit register
do_wrack : out std_logic); -- High for one clock cycle when the transmission starts.
-- The next data word can be written as soon as this signal goes low.
end spi_slave;
architecture Behavioral of spi_slave is
-- constants to control FlipFlop synthesis
constant CAPTURE_EDGE : std_logic := (CPOL xnor CPHA);
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA);
type spi_state_t is (
IDLE,
INIT_TRANSACTION,
SHIFTING_DATA,
WORD_COMPLETE
);
signal spi_state : spi_state_t := IDLE;
signal spi_state_next : spi_state_t;
signal spi_clk_buf : std_logic := CPOL;
signal spi_capture_edge : std_logic;
signal spi_change_edge : std_logic;
signal di_buf : std_logic;
signal di_reg : std_logic_vector(N-1 downto 0);
signal do_reg : std_logic_vector(N-1 downto 0);
signal do_i : std_logic_vector(N-1 downto 0);
signal bit_counter : integer range 0 to N-1 := 0;
begin
-- state register
process
begin
wait until rising_edge (clk);
if spi_ss_n='1' then
spi_state <= IDLE;
else
spi_state <= spi_state_next;
end if;
end process;
-- Next state logic
process (
spi_state,
spi_ss_n,
bit_counter)
begin
spi_state_next <= spi_state;
case (spi_state) is
when IDLE =>
if spi_ss_n='0' then
spi_state_next <= INIT_TRANSACTION;
end if;
when INIT_TRANSACTION =>
spi_state_next <= SHIFTING_DATA;
when SHIFTING_DATA =>
if bit_counter=N-1 then
spi_state_next <= WORD_COMPLETE;
end if;
when WORD_COMPLETE =>
if bit_counter = 0 then
spi_state_next <= INIT_TRANSACTION;
end if;
when others =>
spi_state_next <= IDLE;
end case;
end process;
-- SPI clock edge detector
process
begin
wait until rising_edge(clk);
spi_clk_buf <= spi_clk;
if (spi_clk_buf= not spi_clk) and spi_clk=CAPTURE_EDGE then
spi_capture_edge <= '1';
else
spi_capture_edge <= '0';
end if;
if (spi_clk_buf= not spi_clk) and spi_clk=CHANGE_EDGE then
spi_change_edge <= '1';
else
spi_change_edge <= '0';
end if;
end process;
-- Input shift register
process
begin
wait until rising_edge(clk);
di_buf <= spi_mosi;
if spi_capture_edge='1' then
di_reg <= di_reg(N-2 downto 0) & di_buf;
bit_counter <= bit_counter + 1;
end if;
end process;
-- output received data word
process
begin
wait until rising_edge(clk);
di_valid <= '0';
if spi_state=WORD_COMPLETE and bit_counter=0 then
di <= di_reg;
di_valid <= '1';
end if;
end process;
-- get data word for tx
process
begin
wait until rising_edge(clk);
if do_wren='1' then
do_i <= do;
end if;
end process;
-- output shift register
process
begin
wait until rising_edge(clk);
do_wrack <= '0';
if spi_state = IDLE then
do_reg <= X"00";
elsif spi_state = INIT_TRANSACTION then
do_reg <= do_i;
do_wrack <= '1';
elsif spi_change_edge='1' and bit_counter /= 0 then
do_reg <= do_reg(N-2 downto 0) & '0';
end if;
end process;
spi_miso <= do_reg(7);
end Behavioral;
| gpl-3.0 | 11286bfeeafa6ca8b94ab5ca585b55a8 | 0.495788 | 4.210566 | false | false | false | false |
aylons/concordic | hdl/modules/cordic_core/cordic_core.vhd | 1 | 6,935 | -------------------------------------------------------------------------------
-- Title : Configurable Cordic core
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_core.vhd
-- Author : Aylons <aylons@aylons-yoga2>
-- Company :
-- Created : 2014-05-03
-- Last update: 2015-03-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This CORDIC allow configuration of its number of stages and
-- accepts any bus size for its inputs and ouputs. The calculation to be done
-- is defined by a generic value, and there's no need for external codes due to
-- any parameter change.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity cordic_core is
generic (
g_stages : natural := 20;
g_bit_growth : natural := 2;
g_mode : string := "rect_to_polar"
);
-- x represents the x axis in rectangular coordinates or amplitude in polar
-- y represents the y axis in rectangular coordinates
-- z represents phase in polar coordinates
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic
);
end entity cordic_core;
-------------------------------------------------------------------------------
architecture str of cordic_core is
constant c_width : natural := x_i'length + g_bit_growth + 2;
type wiring is array (0 to g_stages) of signed(c_width-1 downto 0);
type control_wiring is array (0 to g_stages) of boolean;
type z_wiring is array (0 to g_stages) of signed(x_i'length-1 downto 0);
signal x_inter : wiring := (others => (others => '0'));
signal y_inter : wiring := (others => (others => '0'));
signal z_inter : z_wiring := (others => (others => '0'));
signal x_shifted : wiring := (others => (others => '0'));
signal y_shifted : wiring := (others => (others => '0'));
signal control_x : control_wiring := (others => false);
signal control_y : control_wiring := (others => false);
component addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean);
end component addsub;
component pipeline is
generic (
g_width : natural;
g_depth : natural);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component pipeline;
function stage_constant(mode, stage, width : natural) return signed is
variable const_vector : signed(width-1 downto 0) := (others => '0');
begin
-- Each iteration must sum or subtract arctg(1/(2^(stage-1)))
-- Only works for cordics up to 32 bits. Wider constants require
-- pre-generated tables, due to limitations in most VHDL tool's
const_vector := to_signed(integer(arctan(2.0**(real(1-stage)))/(MATH_2_PI)*(2.0**real(width))), width);
return const_vector;
end function;
begin -- architecture str
--TODO: for now, it only generates a rect_to_polar CORDIC. Adapt so we can
--generate other algorithms while reusing as much code as possible, so it
--will be easy to maintain and evolve - hardware is already hard enough.
x_inter(0) <= resize(x_i, x_i'length+2) & (g_bit_growth-1 downto 0 => '0');
y_inter(0) <= resize(y_i, y_i'length+2) & (g_bit_growth-1 downto 0 => '0');
z_inter(0) <= z_i; -- left aligned
control_x(0) <= y_i(y_i'left) = '1';
control_y(0) <= y_i(y_i'left) = '0';
cmp_valid_pipe : pipeline
generic map (
g_width => 1,
g_depth => g_stages)
port map (
data_i(0) => valid_i,
clk_i => clk_i,
ce_i => ce_i,
data_o(0) => valid_o);
CORE_STAGES : for stage in 1 to g_stages generate
--control_x(stage) <= y_inter(stage-1) < 0;
--control_y(stage) <= y_inter(stage-1) > 0;
x_shifted(stage) <= shift_right(x_inter(stage-1), stage-1);
y_shifted(stage) <= shift_right(y_inter(stage-1), stage-1);
cmp_x_stage : addsub
port map(
a_i => x_inter(stage-1),
b_i => y_shifted(stage),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => x_inter(stage),
positive_o => open,
negative_o => open);
cmp_y_stage : addsub
port map(
a_i => y_inter(stage-1),
b_i => x_shifted(stage),
sub_i => control_y(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => y_inter(stage),
positive_o => control_y(stage),
negative_o => control_x(stage));
cmp_z_stage : addsub
port map (
a_i => z_inter(stage-1),
b_i => stage_constant(1, stage, x_i'length),
sub_i => control_x(stage-1),
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
result_o => z_inter(stage),
positive_o => open,
negative_o => open);
end generate;
--TODO: Round the output
x_o <= x_inter(g_stages)(c_width-1 downto g_bit_growth+2);
y_o <= y_inter(g_stages)(c_width-1 downto g_bit_growth+2);
z_o <= z_inter(g_stages);
end architecture str;
| gpl-3.0 | f8c02c9cc2681105055c33e49d5fe790 | 0.532084 | 3.569223 | false | false | false | false |
samrose3/trex-runner | DisplayDiver.vhd | 1 | 1,488 | ----------------------------------------------------------------------------------
-- Description: Driver for 4-digit 7-segment display.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_UNSIGNED.ALL;
entity SegmentDriver is
Port ( disp1 : in std_logic_vector (6 downto 0);
disp2 : in std_logic_vector (6 downto 0);
disp3 : in std_logic_vector (6 downto 0);
disp4 : in std_logic_vector (6 downto 0);
clk : in std_logic;
display_seg : out std_logic_vector (6 downto 0);
display_ena : out std_logic_vector (3 downto 0));
end SegmentDriver;
architecture Behavioral of SegmentDriver is
signal cnt : std_logic_vector (1 downto 0);
begin
process (clk) begin
if (rising_edge(clk)) then
cnt <= cnt + 1;
if (cnt = "11") then
cnt <= "00";
end if;
case (cnt) is
when "00" =>
display_seg <= disp1;
display_ena <= "1110";
when "01" =>
display_seg <= disp2;
display_ena <= "1101";
when "10" =>
display_seg <= disp3;
display_ena <= "1011";
when "11" =>
display_seg <= disp4;
display_ena <= "0111";
when others =>
display_seg <= (others => '0');
display_ena <= "0000";
end case;
end if;
end process;
end Behavioral; | mit | 28aac14103be926402ae67bf814e5a19 | 0.471774 | 4.043478 | false | false | false | false |
aylons/concordic | hdl/modules/cordic_core/addsub.vhd | 1 | 3,341 | -------------------------------------------------------------------------------
-- Title : Dynamic adder/subtractor
-- Project :
-------------------------------------------------------------------------------
-- File : addsub.vhd
-- Author : Aylons <[email protected]>
-- Company :
-- Created : 2014-05-03
-- Last update: 2014-07-21
-- Platform :
-- Standard : VHDL'93/02/08
-------------------------------------------------------------------------------
-- Description: Depening on sub_i, result_o may be a_i + b_i or a_i - b_i.
-- The three widths must all be the same.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity addsub is
port (
a_i : in signed;
b_i : in signed;
sub_i : in boolean;
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
result_o : out signed;
positive_o : out boolean;
negative_o : out boolean
);
end entity addsub;
-------------------------------------------------------------------------------
architecture str of addsub is
constant width : natural := a_i'length;
signal a_1, b_1 : signed(width-1 downto 0) := (others => '0');
signal mux_result : signed (width-1 downto 0) := (others => '0');
begin -- architecture str
assert a_i'length = b_i'length
report "a_i and b_i have different widths"
severity error;
assert a_i'length = result_o'length
report "invalid result_o width"
severity error;
process(clk_i) is
variable result : signed(width-1 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_i = '1' then
result_o <= (width-1 downto 0 => '0');
positive_o <= true;
negative_o <= false;
else
if ce_i = '1' then
result := mux_result;
positive_o <= result(result'left) = '0';
negative_o <= result(result'left) = '1';
result_o <= result;
end if;
end if;
end if;
end process;
mux_result <= a_i + b_i when (not sub_i) else a_i - b_i;
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 38fd7824076bc0b00af4bb8a9a21038a | 0.4783 | 4.245235 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/spi_master.vhd | 1 | 8,992 | --------------------------------------------------------------------------------
--
-- FileName: spi_master.vhd
-- Dependencies: none
-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 7/23/2010 Scott Larson
-- Initial Public Release
-- Version 1.1 4/11/2013 Scott Larson
-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY spi_master IS
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2); --data bus width
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
END spi_master;
ARCHITECTURE logic OF spi_master IS
TYPE machine IS(ready, execute); --state machine data type
SIGNAL state : machine; --current state
SIGNAL slave : INTEGER; --slave selected for current transaction
SIGNAL clk_ratio : INTEGER; --current clk_div
SIGNAL count : INTEGER; --counter to trigger sclk from system clock
SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
SIGNAL continue : STD_LOGIC; --flag to continue transaction
SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
BEGIN
PROCESS(clock, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset system
busy <= '1'; --set busy signal
ss_n <= (OTHERS => '1'); --deassert all slave select lines
mosi <= '0'; --set master out to high impedance
rx_data <= (OTHERS => '0'); --clear receive data port
state <= ready; --go to ready state when reset is exited
ELSIF(clock'EVENT AND clock = '1') THEN
CASE state IS --state machine
WHEN ready =>
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave select outputs high
mosi <= '0'; --set mosi output high impedance
continue <= '0'; --clear continue flag
--user input to initiate transaction
IF(enable = '1') THEN
busy <= '1'; --set busy signal
IF(addr < slaves) THEN --check for valid slave address
slave <= addr; --clock in current slave selection if valid
ELSE
slave <= 0; --set to first slave if not valid
END IF;
IF(clk_div = 0) THEN --check for valid spi speed
clk_ratio <= 1; --set to maximum speed if zero
count <= 1; --initiate system-to-spi clock counter
ELSE
clk_ratio <= clk_div; --set to input selection if valid
count <= clk_div; --initiate system-to-spi clock counter
END IF;
sclk <= cpol; --set spi clock polarity
assert_data <= NOT cpha; --set spi clock phase
tx_buffer <= tx_data; --clock in data for transmit into buffer
clk_toggles <= 0; --initiate clock toggle counter
last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
state <= execute; --proceed to execute state
ELSE
state <= ready; --remain in ready state
END IF;
WHEN execute =>
busy <= '1'; --set busy signal
ss_n(slave) <= '0'; --set proper slave select output
--system clock to sclk ratio is met
IF(count = clk_ratio) THEN
count <= 1; --reset system-to-spi clock counter
assert_data <= NOT assert_data; --switch transmit/receive indicator
IF(clk_toggles = d_width*2 + 1) THEN
clk_toggles <= 0; --reset spi clock toggles counter
ELSE
clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
END IF;
--spi clock toggle needed
IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
sclk <= NOT sclk; --toggle spi clock
END IF;
--receive spi clock toggle
IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
END IF;
--transmit spi clock toggle
IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
mosi <= tx_buffer(d_width-1); --clock out data bit
tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
END IF;
--last data receive, but continue
IF(clk_toggles = last_bit_rx AND cont = '1') THEN
tx_buffer <= tx_data; --reload transmit buffer
clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
continue <= '1'; --set continue flag
END IF;
--normal end of transaction, but continue
IF(continue = '1') THEN
continue <= '0'; --clear continue flag
busy <= '0'; --clock out signal that first receive data is ready
rx_data <= rx_buffer; --clock out received data to output port
END IF;
--end of transaction
IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
busy <= '0'; --clock out not busy signal
ss_n <= (OTHERS => '1'); --set all slave selects high
mosi <= '0'; --set mosi output high impedance
rx_data <= rx_buffer; --clock out received data to output port
state <= ready; --return to ready state
ELSE --not end of transaction
state <= execute; --remain in execute state
END IF;
ELSE --system clock to sclk ratio not met
count <= count + 1; --increment counter
state <= execute; --remain in execute state
END IF;
END CASE;
END IF;
END PROCESS;
END logic;
| gpl-3.0 | f977e674360c390ea05b4afe22fcc7a0 | 0.498888 | 4.625514 | false | false | false | false |
Hyvok/HardHeat | quartus/altera_pll_top.vhd | 1 | 17,629 | -- megafunction wizard: %Altera PLL v15.0%
-- GENERATION: XML
-- altera_pll_top.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_pll_top is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end entity altera_pll_top;
architecture rtl of altera_pll_top is
component altera_pll_top_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component altera_pll_top_0002;
begin
altera_pll_top_inst : component altera_pll_top_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => locked -- locked.export
);
end architecture rtl; -- of altera_pll_top
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="15.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : altera_pll_top.vho
-- RELATED_FILES: altera_pll_top.vhd, altera_pll_top_0002.v
| mit | 5f6ba931a5b8d54b38e2e1989e339efd | 0.68444 | 3.08415 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/LSB_INSERT.vhd | 1 | 3,295 | --LSB_INSERT entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY LSB_INSERT IS
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
A_COL: IN COLOR;
A_ROW: IN COLOR;
B_COL: IN COLOR;
B_ROW: IN COLOR;
C_COL: IN COLOR;
C_ROW: IN COLOR;
FIXED_Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END ENTITY LSB_INSERT;
ARCHITECTURE ART1 OF LSB_INSERT IS
CONSTANT SEQ1: STD_LOGIC_VECTOR(0 TO 4):="01101";
CONSTANT SEQ2: STD_LOGIC_VECTOR(0 TO 4):="10101";
CONSTANT SEQ3: STD_LOGIC_VECTOR(0 TO 4):="11001";
SIGNAL AA: INTEGER RANGE 0 TO 65535;
SIGNAL BB: INTEGER RANGE 0 TO 65535;
SIGNAL CC: INTEGER RANGE 0 TO 65535;
BEGIN
COMPUTE: PROCESS(A_ROW,A_COL,B_ROW,B_COL,C_ROW,C_COL)
BEGIN
AA<=256*A_ROW+A_COL+1;
BB<=256*B_ROW+B_COL+1;
CC<=256*C_ROW+C_COL+1;
END PROCESS;
CLOCK: PROCESS(CLK,RESET,ENABLE)
VARIABLE FIXED_Y_REM: COLOR;
VARIABLE GREY_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE SEQ1_I: INTEGER RANGE 0 TO 9;
VARIABLE SEQ2_I: INTEGER RANGE 0 TO 9;
VARIABLE SEQ3_I: INTEGER RANGE 0 TO 9;
--COUNT的范围是256*256
VARIABLE COUNT: INTEGER RANGE 0 TO 65536;
BEGIN
IF(RESET='1' OR ENABLE='0') THEN
COUNT:=0;
SEQ1_I:=0;
SEQ2_I:=0;
SEQ3_I:=0;
FIXED_Y_OUT<=0;
U_OUT<=0;
V_OUT<=0;
ELSIF(COUNT=65536) THEN
FIXED_Y_OUT<=0;
U_OUT<=0;
V_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
IF( (COUNT>=AA) AND (COUNT<=AA+SEQ1'HIGH)) THEN
-- 取出灰度的8 bit 数据
GREY_REM:= CONV_STD_LOGIC_VECTOR(Y_IN, 8);
-- 更改 LSB位
GREY_REM(0):= SEQ1(SEQ1_I);
SEQ1_I:=SEQ1_I+1;
-- 将更改输出
FIXED_Y_REM:= CONV_INTEGER(UNSIGNED(GREY_REM));
FIXED_Y_OUT<= FIXED_Y_REM;
ELSIF( (COUNT>=BB) AND (COUNT<=BB+SEQ2'HIGH)) THEN
-- 取出灰度的8 bit 数据
GREY_REM:= CONV_STD_LOGIC_VECTOR(Y_IN, 8);
-- 更改 LSB位
GREY_REM(0):= SEQ2(SEQ2_I);
SEQ2_I:=SEQ2_I+1;
-- 将更改输出
FIXED_Y_REM:= CONV_INTEGER(UNSIGNED(GREY_REM));
FIXED_Y_OUT<= FIXED_Y_REM;
ELSIF( (COUNT>=CC) AND (COUNT<=CC+SEQ3'HIGH)) THEN
-- 取出灰度的8 bit 数据
GREY_REM:= CONV_STD_LOGIC_VECTOR(Y_IN, 8);
-- 更改 LSB位
GREY_REM(0):= SEQ3(SEQ3_I);
SEQ3_I:=SEQ3_I+1;
-- 将更改输出
FIXED_Y_REM:= CONV_INTEGER(UNSIGNED(GREY_REM));
FIXED_Y_OUT<= FIXED_Y_REM;
ELSE
FIXED_Y_OUT<=Y_IN;
END IF;
U_OUT<=U_IN;
V_OUT<=V_IN;
COUNT:=COUNT+1;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 63bedde83d1f1d2fd36572913dfea4c3 | 0.493901 | 3.226034 | false | false | false | false |
suoto/hdlcc | .ci/test_support/test_project/another_library/foo.vhd | 1 | 1,185 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
entity foo is
generic (
DIVIDER_A : integer := 10;
DIVIDER_B : integer := 20
);
port (
rst_a, clk_in_a : in std_logic;
clk_out_a : out std_logic;
rst_b, clk_in_b : in std_logic;
clk_out_b : out std_logic
);
end foo;
architecture foo of foo is
-- A signal declaration that generates a warning
signal neat_signal : std_logic_vector(DIVIDER_A + DIVIDER_B - 1 downto 0) := (others => '0');
begin
clk_div_a : entity basic_library.clock_divider
generic map (
DIVIDER => DIVIDER_A
)
port map (
reset => rst_a,
clk_input => clk_in_a,
clk_output => clk_out_a
);
clk_div_b : entity basic_library.clock_divider
generic map (
DIVIDER => DIVIDER_B
)
port map (
reset => rst_b,
clk_input => clk_in_b,
clk_output => clk_out_b
);
-----------------------------
-- Asynchronous asignments --
-----------------------------
end foo;
| gpl-3.0 | 6551619ce9d80dbba4a0cd1e09a18713 | 0.490295 | 3.785942 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/i2c_master.vhd | 2 | 19,620 | ----------------------------------------------------------------------------------
--This is adapted from this code: https://eewiki.net/pages/viewpage.action?pageId=10125324
<<<<<<< HEAD
--modification: now sends 3 I2C packets with only a single ena signal pulse:
--write: [device id | register address | value]
--read: [device id |w| register address |device id|r| value]
--Also had to modify it to do the correct read sequence
--fixed the scl stretch bug
=======
--modification: now sends 3 I2C packets with only a single ena signal pulse. [device id | register address | value]
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
--by: Jie (Jack) Zhang MWL-MIT
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity i2c_master is
generic (
<<<<<<< HEAD
input_clk : integer := 20_000_000; --input clock speed from user logic in Hz
bus_clk : integer := 200_000); --speed the i2c bus (scl) will run at in Hz
port (
clk : in std_logic; --system clock
reset : in std_logic; --active high reset
ena : in std_logic; --latch in command
devid : in std_logic_vector(6 downto 0); --device id of target slave
addr : in std_logic_vector(7 downto 0);
rw : in std_logic; --'0' is write, '1' is read
data_wr : in std_logic_vector(7 downto 0); --data to write to slave
busy : out std_logic; --indicates transaction in progress
data_rd : out std_logic_vector(7 downto 0); --data read from slave
ack_error : buffer std_logic; --flag if improper acknowledge from slave
rd_from_remote : in std_logic;
sda : inout std_logic; --serial data output of i2c bus
scl : inout std_logic); --serial clock output of i2c bus
=======
input_clk : integer := 50_000_000; --input clock speed from user logic in Hz
bus_clk : integer := 500_000); --speed the i2c bus (scl) will run at in Hz
port (
clk : in std_logic; --system clock
reset : in std_logic; --active high reset
ena : in std_logic; --latch in command
devid : in std_logic_vector(6 downto 0); --device id of target slave
addr : in std_logic_vector(7 downto 0);
rw : in std_logic; --'0' is write, '1' is read
data_wr : in std_logic_vector(7 downto 0); --data to write to slave
busy : out std_logic; --indicates transaction in progress
data_rd : out std_logic_vector(7 downto 0); --data read from slave
ack_error : buffer std_logic; --flag if improper acknowledge from slave
sda : inout std_logic; --serial data output of i2c bus
scl : inout std_logic); --serial clock output of i2c bus
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
end i2c_master;
architecture Behavioral of i2c_master is
constant divider : integer := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
type machine is(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
<<<<<<< HEAD
signal state : machine; --state machine
signal data_clk : std_logic; --data clock for sda
signal data_clk_prev : std_logic; --data clock during previous system clock
signal scl_clk : std_logic; --constantly running internal scl
signal scl_ena : std_logic := '0'; --enables internal scl to output
signal sda_int : std_logic := '1'; --internal sda
signal sda_ena_n : std_logic; --enables internal sda to output
signal devid_rw : std_logic_vector(7 downto 0); --latched in device id and read/write
signal regaddr : std_logic_vector(7 downto 0);
signal data_tx : std_logic_vector(7 downto 0); --latched in data to write to slave
signal data_rx : std_logic_vector(7 downto 0); --data received from slave
signal bit_cnt : integer range 0 to 7 := 7; --tracks bit number in transaction
signal stretch : std_logic := '0'; --identifies if slave is stretching scl
signal datacnt : std_logic := '0';
signal rd_cnt : std_logic := '0';
signal scl_cnt : unsigned(6 downto 0);
begin
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
process (clk, reset, scl)
=======
signal state : machine; --state machine
signal data_clk : std_logic; --data clock for sda
signal data_clk_prev : std_logic; --data clock during previous system clock
signal scl_clk : std_logic; --constantly running internal scl
signal scl_ena : std_logic := '0'; --enables internal scl to output
signal sda_int : std_logic := '1'; --internal sda
signal sda_ena_n : std_logic; --enables internal sda to output
signal devid_rw : std_logic_vector(7 downto 0); --latched in device id and read/write
signal regaddr : std_logic_vector(7 downto 0);
signal data_tx : std_logic_vector(7 downto 0); --latched in data to write to slave
signal data_rx : std_logic_vector(7 downto 0); --data received from slave
signal bit_cnt : integer range 0 to 7 := 7; --tracks bit number in transaction
signal stretch : std_logic := '0'; --identifies if slave is stretching scl
signal datacnt : std_logic := '0';
--signal count_unsigned : unsigned(10 downto 0);
begin
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
process (clk, reset)
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
variable count : integer range 0 to divider * 4; --timing for clock generation
begin
--count_unsigned <= to_unsigned(count, 11);
if (reset = '1') then --reset asserted
stretch <= '0';
count := 0;
elsif (rising_edge(clk)) then
data_clk_prev <= data_clk; --store previous value of data clock
if (count = divider * 4 - 1) then --end of timing cycle
count := 0; --reset timer
elsif (stretch = '0') then --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
end if;
case count is
when 0 to divider - 1 => --first 1/4 cycle of clocking
<<<<<<< HEAD
scl_clk <= '0';
data_clk <= '0';
when divider to divider * 2 - 1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
when divider * 2 to divider * 3 - 1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
if count = (divider * 2 + 1) then
if (scl = '0') then --detect if slave is stretching clock
stretch <= '1';
else
stretch <= '0';
end if;
end if;
data_clk <= '1';
when others => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
end case;
end if;
scl_cnt <= to_unsigned(count, 7);
end process;
--state machine and writing to sda during scl low (data_clk rising edge)
process (clk, reset, datacnt, rd_cnt, bit_cnt, rd_from_remote)
begin
if (reset = '1') then --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
datacnt <= '0';
rd_cnt <= '0';
=======
scl_clk <= '0';
data_clk <= '0';
when divider to divider * 2 - 1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
when divider * 2 to divider * 3 - 1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
if (scl = '0') then --detect if slave is stretching clock
stretch <= '1';
else
stretch <= '0';
end if;
data_clk <= '1';
when others => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
end case;
end if;
end process;
--state machine and writing to sda during scl low (data_clk rising edge)
process (clk, reset, datacnt)
begin
if (reset = '1') then --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
datacnt <= '0';
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
elsif (rising_edge(clk)) then
if (data_clk = '1' and data_clk_prev = '0') then --data clock rising edge
case state is
when ready => --idle state
if (ena = '1') then --transaction requested
<<<<<<< HEAD
busy <= '1'; --flag busy
devid_rw <= devid & rw; --collect requested slave device id and command
data_tx <= data_wr; --collect requested data to write
regaddr <= addr;
state <= start; --go to start bit
else --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
end if;
datacnt <= '0'; --reset data counter
rd_cnt <= '0'; --set the ready counter
when start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= devid_rw(bit_cnt); --set first device id bit to bus
state <= command; --go to command
when command => --device id and command byte of transaction
if rd_from_remote = '0' then
if (bit_cnt = 0) then --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
elsif (bit_cnt = 1) then
if devid_rw(0) = '0' then
sda_int <= devid_rw(bit_cnt - 1);
else
if rd_cnt = '0' then
sda_int <= '0';
else
sda_int <= '1';
end if;
end if;
bit_cnt <= bit_cnt - 1;
state <= command;
else --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= command; --continue with command
sda_int <= devid_rw(bit_cnt - 1); --write device id/command bit to bus
end if;
else
if (bit_cnt = 0) then --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
elsif (bit_cnt = 1) then
if devid_rw(0) = '0' then
sda_int <= devid_rw(bit_cnt - 1);
state <= command;
bit_cnt <= bit_cnt - 1;
else
if rd_cnt = '0' then
sda_int <= '1';
bit_cnt <= bit_cnt - 1;
state <= command;
else
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
end if;
end if;
else --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= command; --continue with command
sda_int <= devid_rw(bit_cnt - 1); --write device id/command bit to bus
end if;
=======
busy <= '1'; --flag busy
devid_rw <= devid & rw; --collect requested slave device id and command
data_tx <= data_wr; --collect requested data to write
regaddr <= addr;
state <= start; --go to start bit
else --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
end if;
datacnt <= '0'; --reset data counter
when start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= devid_rw(bit_cnt); --set first device id bit to bus
state <= command; --go to command
when command => --device id and command byte of transaction
if (bit_cnt = 0) then --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
else --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= devid_rw(bit_cnt - 1); --write device id/command bit to bus
state <= command; --continue with command
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
end if;
when slv_ack1 => --slave acknowledge bit (command)
if (devid_rw(0) = '0') then --write command
sda_int <= regaddr(bit_cnt); --write first bit of data
<<<<<<< HEAD
state <= wr; --go to write byte
else --read command
if rd_cnt = '0' then
sda_int <= regaddr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
rd_cnt <= '1';
else
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
end if;
=======
state <= wr; --go to write byte
else --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
end if;
when wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
if (bit_cnt = 0) then --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
<<<<<<< HEAD
state <= slv_ack2; --go to slave acknowledge (write)
=======
state <= slv_ack2; --go to slave acknowledge (write)
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
else --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
if datacnt = '0' then
sda_int <= regaddr(bit_cnt - 1); --write next bit to bus
else
sda_int <= data_tx(bit_cnt - 1); --write next bit to bus
end if;
state <= wr; --continue writing
end if;
when rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
if (bit_cnt = 0) then --read byte receive finished
if (ena = '1' and devid_rw = devid & rw) then --continuing with another read at same device id
sda_int <= '0'; --acknowledge the byte has been received
else --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
end if;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
<<<<<<< HEAD
state <= mstr_ack; --go to master acknowledge
else --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
end if;
when slv_ack2 => --slave acknowledge bit (write)
if rw = '0' then --write
if (datacnt = '0') then --continue transaction
busy <= '1'; --continue is accepted
--devid_rw <= devid & rw; --collect requested slave device id and command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
datacnt <= '1';
else --complete transaction
state <= stop; --go to stop bit
end if;
else
state <= start;
devid_rw <= devid & rw;
bit_cnt <= 7;
end if;
when mstr_ack => --master acknowledge bit after a read
if (ena = '1') then --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
devid_rw <= devid & rw; --collect requested slave device id and command
data_tx <= data_wr; --collect requested data to write
if (devid_rw = devid & rw) then --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
else --continue transaction with a write or new slave
state <= start; --repeated start
end if;
=======
state <= mstr_ack; --go to master acknowledge
else --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
end if;
when slv_ack2 => --slave acknowledge bit (write)
if (datacnt = '0') then --continue transaction
busy <= '1'; --continue is accepted
--devid_rw <= devid & rw; --collect requested slave device id and command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
datacnt <= '1';
else --complete transaction
state <= stop; --go to stop bit
end if;
when mstr_ack => --master acknowledge bit after a read
if (ena = '1') then --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
devid_rw <= devid & rw; --collect requested slave device id and command
data_tx <= data_wr; --collect requested data to write
if (devid_rw = devid & rw) then --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
else --continue transaction with a write or new slave
state <= start; --repeated start
end if;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
else --complete transaction
state <= stop; --go to stop bit
end if;
when stop => --stop bit of transaction
<<<<<<< HEAD
busy <= '0'; --unflag busy
state <= ready; --go to idle state
end case;
=======
busy <= '0'; --unflag busy
state <= ready; --go to idle state
end case;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
elsif (data_clk = '0' and data_clk_prev = '1') then --data clock falling edge
case state is
when start =>
if (scl_ena = '0') then --starting new transaction
<<<<<<< HEAD
scl_ena <= '1'; --enable scl output
=======
scl_ena <= '1'; --enable scl output
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
ack_error <= '0'; --reset acknowledge error output
end if;
when slv_ack1 => --receiving slave acknowledge (command)
if (sda /= '0' or ack_error = '1') then --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
end if;
when rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
when slv_ack2 => --receiving slave acknowledge (write)
if (sda /= '0' or ack_error = '1') then --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
end if;
when stop =>
scl_ena <= '0'; --disable scl
when others =>
null;
end case;
end if;
end if;
<<<<<<< HEAD
end process;
=======
end process;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
--set sda output
with state select
sda_ena_n <= data_clk_prev when start, --generate start condition
not data_clk_prev when stop, --generate stop condition
<<<<<<< HEAD
sda_int when others; --set to internal sda signal
=======
sda_int when others; --set to internal sda signal
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
--set scl and sda outputs
scl <= '0' when (scl_ena = '1' and scl_clk = '0') else 'Z';
sda <= '0' when sda_ena_n = '0' else 'Z';
end Behavioral; | mit | 22d9e036ab505cc34ac05f3256168ad5 | 0.592151 | 3.451795 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/CHOOSE.vhd | 1 | 1,776 | --CHOOSE entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CHOOSE IS
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
TO_TRANS: OUT STD_LOGIC;
TO_INSERT: OUT STD_LOGIC;
TO_DETECT: OUT STD_LOGIC;
TO_HIDE: OUT STD_LOGIC;
TO_UNHIDE: OUT STD_LOGIC);
END ENTITY CHOOSE;
ARCHITECTURE ART1 OF CHOOSE IS
BEGIN
PROCESS(SEL,RESET)
BEGIN
IF(RESET='1') THEN
--TO_TRANS连接的是RGB2YUV,因为隐藏/解隐藏信息直接利用RGB
TO_TRANS<= '0';
TO_INSERT<= '0';
TO_DETECT<= '0';
TO_HIDE<= '0';
TO_UNHIDE<= '0';
ELSE
IF(SEL="00") THEN
TO_TRANS<= '1';
TO_INSERT<= '1';
TO_DETECT<= '0';
TO_HIDE<= '0';
TO_UNHIDE<= '0';
ELSIF(SEL="01") THEN
TO_TRANS<= '1';
TO_INSERT<= '0';
TO_DETECT<= '1';
TO_HIDE<= '0';
TO_UNHIDE<= '0';
ELSIF(SEL="10") THEN
TO_TRANS<= '0';
TO_INSERT<= '0';
TO_DETECT<= '0';
TO_HIDE<= '1';
TO_UNHIDE<= '0';
ELSIF(SEL="11") THEN
TO_TRANS<= '0';
TO_INSERT<= '0';
TO_DETECT<= '0';
TO_HIDE<= '0';
TO_UNHIDE<= '1';
ELSE
TO_TRANS<= '0';
TO_INSERT<= '0';
TO_DETECT<= '0';
TO_HIDE<= '0';
TO_UNHIDE<= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 0ea61d94ec79ce9d72649325aa83e9e4 | 0.401837 | 3.555102 | false | false | false | false |
summershrimp/VHDLClock | Timer.vhd | 1 | 1,185 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Timer is
Port(
clk, seth, setm: in std_logic;
ssig: out std_logic;
hsigh, msigh: out std_logic_vector(2 downto 0);
hsigl, msigl: out std_logic_vector(3 downto 0)
);
End Entity;
Architecture ArchTimer of Timer is
Component Counter60
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter60;
Component Counter24
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter24;
Signal hclk, mclk, hco, mco, srst, en, gnd: std_logic;
Begin
en <= '1';
gnd <= '0';
Sec:Counter60
Port Map(co=> mco, en=>en, clk=>clk, rst=>srst );
Min:Counter60
Port Map(msigh, msigl, hco, en, mclk , gnd);
Hor:Counter24
Port Map(h=>hsigh, l=>hsigl, en=>en, clk=>hclk, rst=>gnd );
ssig <= clk;
hclk<= seth or hco;
mclk<= setm or mco;
srst<= seth or setm;
End Architecture;
| gpl-2.0 | 66daf41af5a731a1d80ff94bc5a39c40 | 0.636287 | 2.615894 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/c_addsub_v12_0_vh_rfs.vhd | 1 | 402,790 | `protect begin_protected
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| gpl-3.0 | 2d9bcb4ceaa6346121c7bf0f723094e8 | 0.955138 | 1.827806 | false | false | false | false |
Hyvok/HardHeat | src/hardheat_top.vhd | 1 | 7,904 | library ieee;
library work;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.altera_pll_top_pkg.all;
use altera.altera_syn_attributes.all;
entity hardheat_top is
generic
(
-- Number of bits in time-to-digital converter
TDC_N : positive := 12;
-- Number of bitshifts to left for the filter proportional coefficient
FILT_P_SHIFT_N : integer := 0;
-- Number of bitshifts to right for the filter integral coefficient
FILT_I_SHIFT_N : integer := -5;
-- Initial output value from the filter
FILT_INIT_OUT_VAL : positive := 2**11 - 1;
-- Filter output offset
FILT_OUT_OFFSET : natural := 2**21;
-- Filter output value clamping limit
FILT_OUT_LIM : positive := 2**22;
-- Number of bits in the phase accumulator
ACCUM_BITS_N : positive := 32;
-- Number of bits in the tuning word for the phase accumulator
ACCUM_WORD_N : positive := 23;
-- Number of bits in the deadtime counter
DT_N : positive := 16;
-- Amount of deadtime in clock cycles
DT_VAL : natural := 100;
-- Number of bits in the lock detector "locked" counter
LD_LOCK_N : positive := 20;
-- Number of bits in the lock detector "unlocked" counter
LD_ULOCK_N : positive := 16;
-- Phase difference value under which we are considered to be locked
LD_LOCK_LIMIT : natural := 100;
-- Temperature conversion interval in clock cycles
TEMP_CONV_D : natural := 100000000;
-- Delay between conversion command and reading in clock cycles
TEMP_CONV_CMD_D : natural := 75000000;
-- Number of clock cycles for 1us delay for the 1-wire module
TEMP_OW_US_D : positive := 100;
-- Number of bits in the temperature PWM controller
TEMP_PWM_N : positive := 12;
-- Minimum PWM level (duty cycle)
TEMP_PWM_MIN_LVL : natural := 2**12 / 5;
-- Output maximum duty cycle on enable, measured in PWM cycles!
TEMP_PWM_EN_ON_D : natural := 100000;
-- Number of bitshifts to left for the PID-filter proportional coeff
TEMP_P_SHIFT_N : integer := 4;
-- Number of bitshifts to right for the PID-filter integral coeff
TEMP_I_SHIFT_N : integer := -11;
-- PID input offset applied to the temperature sensor output
TEMP_SETPOINT : integer := 320;
DEBOUNCE_D : natural := 1000000;
DEBOUNCE_FF_N : natural := 5
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
ref_in : in std_logic;
sig_in : in std_logic;
ow_in : in std_logic;
mod_lvl_in : in std_logic_vector(2 downto 0);
ow_out : out std_logic;
ow_pullup_out : out std_logic;
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic;
lock_out : out std_logic;
pwm_out : out std_logic;
temp_err_out : out std_logic
);
end entity;
architecture rtl_top of hardheat_top is
attribute noprune : boolean;
attribute preserve : boolean;
attribute keep : boolean;
signal clk : std_logic;
attribute noprune of clk : signal is true;
attribute keep of clk : signal is true;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
attribute keep of temp : signal is true;
attribute keep of temp_f : signal is true;
attribute noprune of temp : signal is true;
attribute noprune of temp_f : signal is true;
attribute preserve of temp : signal is true;
signal pll_clk : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
signal mod_lvl : std_logic_vector(mod_lvl_in'range);
signal mod_lvl_f : std_logic;
signal debounced_sws : std_logic_vector(mod_lvl_in'range);
begin
-- Main clock from PLL on the SoCkit board
pll_p: altera_pll_top
port map
(
refclk => clk_in,
rst => not reset_in,
outclk_0 => pll_clk,
locked => pll_locked
);
clk <= pll_clk;
reset <= not pll_locked;
-- Read modulation level state from switches, debounce
debouncing_p: for i in 0 to mod_lvl_in'high generate
debouncer_p: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => DEBOUNCE_D,
FLIPFLOPS_N => DEBOUNCE_FF_N
)
port map
(
clk => clk,
reset => reset,
sig_in => mod_lvl_in(i),
sig_out => debounced_sws(i)
);
end generate;
-- Change modulation level when debounced modulation level changes
mod_lvl_p: process(clk, reset)
variable state : std_logic_vector(mod_lvl_in'high downto 0);
begin
if reset = '1' then
state := (others => '1');
mod_lvl <= state;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
mod_lvl_f <= '0';
if not debounced_sws = state then
state := debounced_sws;
mod_lvl <= state;
mod_lvl_f <= '1';
end if;
end if;
end process;
-- TODO: Sig is internally connected!
hardheat_p: entity work.hardheat(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIM => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT,
DT_N => DT_N,
DT_VAL => DT_VAL,
TEMP_CONV_D => TEMP_CONV_D,
TEMP_CONV_CMD_D => TEMP_CONV_CMD_D,
TEMP_OW_US_D => TEMP_OW_US_D,
TEMP_PWM_N => TEMP_PWM_N,
TEMP_PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
TEMP_PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
TEMP_P_SHIFT_N => TEMP_P_SHIFT_N,
TEMP_I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref_in,
sig_in => sig_in,
mod_lvl_in => unsigned(mod_lvl),
mod_lvl_in_f => mod_lvl_f,
sig_lh_out => sig_lh_out,
sig_ll_out => sig_ll_out,
sig_rh_out => sig_rh_out,
sig_rl_out => sig_rl_out,
lock_out => lock_out,
ow_in => ow_in,
ow_out => ow_out,
ow_pullup_out => ow_pullup_out,
temp_out => temp,
temp_out_f => temp_f,
temp_err_out => temp_err_out,
pwm_out => pwm_out
);
end;
| mit | 2cdf1e533b187ee6a09d77db4f7d5c88 | 0.484185 | 3.938216 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/YUV2RGB.vhd | 1 | 1,681 | --YUV2RGB entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY YUV2RGB IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
FIXED_Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR);
END ENTITY YUV2RGB;
ARCHITECTURE ART1 OF YUV2RGB IS
BEGIN
CLOCK: PROCESS(CLK,RESET)
VARIABLE R_REG: COLOR;
VARIABLE G_REG: COLOR;
VARIABLE B_REG: COLOR;
VARIABLE TEMP: INTEGER RANGE -512 TO 512;
BEGIN
IF(RESET='1') THEN
R_OUT<=0;
G_OUT<=0;
B_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
TEMP:= FIXED_Y_IN + 113983*(V_IN-128)/100000;
--调整
IF(TEMP<0) THEN
R_REG:=0;
ELSIF(TEMP>255) THEN
R_REG:=255;
ELSE
R_REG:=TEMP;
END IF;
TEMP:=FIXED_Y_IN - 39465*(U_IN-128)/100000 - 58060*(V_IN-128)/100000;
--调整
IF(TEMP<0) THEN
G_REG:=0;
ELSIF(TEMP>255) THEN
G_REG:=255;
ELSE
G_REG:=TEMP;
END IF;
TEMP:=FIXED_Y_IN + 203211*(U_IN-128)/100000;
--调整
IF(TEMP<0) THEN
B_REG:=0;
ELSIF(TEMP>255) THEN
B_REG:=255;
ELSE
B_REG:=TEMP;
END IF;
R_OUT<=R_REG;
G_OUT<=G_REG;
B_OUT<=B_REG;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | f16435828fd81e625937950ecc816822 | 0.463751 | 3.392276 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/LED_DISP.vhd | 1 | 1,489 | --Led Display
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_DISP IS
PORT( CLK_DISP :IN STD_LOGIC;
DATA_IN_1 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_2 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_3 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA2LED :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY LED_DISP;
ARCHITECTURE ART1 OF LED_DISP IS
SIGNAL DOUT_OCT: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (CLK_DISP)
VARIABLE VAR: STD_LOGIC_VECTOR (1 DOWNTO 0):="00";
BEGIN
IF(CLK_DISP 'EVENT AND CLK_DISP='1') THEN
IF(VAR="11")THEN
VAR:="00";
END IF;
IF(VAR="00")THEN
SEL2LED <="001";
DOUT_OCT <= DATA_IN_1;
ELSIF(VAR="01")THEN
SEL2LED <="010";
DOUT_OCT <= DATA_IN_2;
ELSE
SEL2LED <="100";
DOUT_OCT <= DATA_IN_3;
END IF;
VAR:=VAR+1;
END IF;
END PROCESS;
PROCESS(DOUT_OCT)
BEGIN
CASE DOUT_OCT IS
WHEN"0000"=> DATA2LED <="1111110";
WHEN"0001"=> DATA2LED <="0110000";
WHEN"0010"=> DATA2LED <="1101101";
WHEN"0011"=> DATA2LED <="1111001";
WHEN"0100"=> DATA2LED <="0110011";
WHEN"0101"=> DATA2LED <="1011011";
WHEN"0110"=> DATA2LED <="1011111";
WHEN"0111"=> DATA2LED <="1110000";
WHEN"1000"=> DATA2LED <="1111111";
WHEN"1001"=> DATA2LED <="1111011";
WHEN OTHERS => DATA2LED <="0000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 7babd3f92403538ed2c91353248cc554 | 0.620551 | 2.712204 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/pwm.vhd | 1 | 5,515 | --------------------------------------------------------------------------------
--
-- FileName: pwm.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 8/1/2013 Scott Larson
-- Initial Public Release
-- Version 2.0 1/9/2015 Scott Larson
-- Transistion between duty cycles always starts at center of pulse to avoid
-- anomalies in pulse shapes
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 50_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 100_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(clk, reset_n)
variable v_compute : unsigned(bits_resolution+24-1 downto 0);
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
pwm_n_out <= (OTHERS => '0'); --clear pwm inverse outputs
ELSIF(clk'EVENT AND clk = '1') THEN --rising system clock edge
IF(ena = '1') THEN --latch in new duty cycle
v_compute := unsigned(duty)*to_unsigned(period,24)/(2**(bits_resolution+1));
half_duty_new <= to_integer(v_compute(31-1 downto 0));--(unsigned(duty)*period/(2**(bits_resolution))/2));--conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
pwm_n_out(i) <= '1'; --assert the pwm inverse output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
pwm_n_out(i) <= '0'; --deassert the pwm inverse output
END IF;
END LOOP;
END IF;
END PROCESS;
END logic;
| gpl-3.0 | b084abc4119073e171fd846f639886dc | 0.492475 | 4.588186 | false | false | false | false |
quicky2000/image_controler_640_480_1b | image_controler.vhd | 1 | 4,501 | --
-- This file is part of image_controler_640_480_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_controler is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
r : out STD_LOGIC_VECTOR (5 downto 0);
g : out STD_LOGIC_VECTOR (5 downto 0);
b : out STD_LOGIC_VECTOR (5 downto 0);
x : in STD_LOGIC_VECTOR (9 downto 0);
y : in STD_LOGIC_VECTOR (8 downto 0);
enable_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
write_enable : in std_logic;
write_addr : in std_logic_vector(18 downto 0);
data_in : in std_logic;
enable_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic);
end image_controler;
architecture Behavioral of image_controler is
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ram
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(18 downto 0);
dina: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(18 downto 0);
doutb: OUT std_logic_VECTOR(0 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of ram: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- Signals needed to write in memory
signal s_write_enable : std_logic_vector(0 downto 0);
--TEST signal write_addr : std_logic_vector(18 downto 0);
signal s_data_in : std_logic_vector(0 downto 0);
-- Signals needed to read from memory
signal read_addr : std_logic_vector(18 downto 0) := (others => '0');
signal data_out : std_logic_vector(0 downto 0);
constant controler_delay : natural := 1;
begin
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ram
port map (
clka => clk,
wea => s_write_enable,
addra => write_addr,
dina => s_data_in,
clkb => clk,
addrb => read_addr,
doutb => data_out);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- Block to introduce delays need to have control signals
-- synchronous with colour signals
hsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => hsync_in,
output => hsync_out);
vsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => vsync_in,
output => vsync_out);
enable_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => enable_in,
output => enable_out);
-- Process controling adress of read port
process(clk,rst)
begin
if rst = '1' then
read_addr <= (others => '0');
elsif rising_edge(clk) and enable_in = '1' then
if unsigned(read_addr) /= 307199 then
read_addr <= std_logic_vector(unsigned(read_addr) + 1);
else
read_addr <= (others => '0');
end if;
end if;
end process;
s_write_enable <= (others => write_enable);
s_data_in <= (others => data_in);
r <= (others => data_out(0));
g <= (others => data_out(0));
b <= (others => data_out(0));
end Behavioral;
| gpl-3.0 | 713fe1aecc03856c9fd2d075c37b096f | 0.623417 | 3.757095 | false | false | false | false |
aylons/concordic | hdl/top/cordic_rotate/cordic_rotate_slv.vhd | 1 | 4,250 | -------------------------------------------------------------------------------
-- Title : Rotation-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_rotate_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-13
-- Last update: 2014-05-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a top-block for rotation mode using concordic,
-- constrained standard_logic_vector version.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-13 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity cordic_rotate_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32
);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := "11000000";
y_i : in std_logic_vector(g_width-1 downto 0) := "11000000";
clk_i : in std_logic;
ce_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0);
phase_o : out std_logic_vector(g_width-1 downto 0)
);
end entity cordic_rotate_slv;
-------------------------------------------------------------------------------
architecture str of cordic_rotate_slv is
signal adjusted_x : signed(g_width-1 downto 0);
signal adjusted_y : signed(g_width-1 downto 0);
signal adjusted_z : signed(g_width-1 downto 0);
signal mag_temp : signed(g_width-1 downto 0);
signal phase_temp : signed(g_width-1 downto 0);
signal y_temp : signed(g_width-1 downto 0);
component inversion_stage is
generic (
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed);
end component inversion_stage;
component cordic_core is
generic (
g_stages : natural;
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed);
end component cordic_core;
begin -- architecture str
cmp_inversion : inversion_stage
generic map (
g_mode => "rect_to_polar")
port map (
x_i => signed(x_i),
y_i => signed(y_i),
z_i => (g_width-1 downto 0 => '0'),
clk_i => clk_i,
ce_i => ce_i,
x_o => adjusted_x,
y_o => adjusted_y,
z_o => adjusted_z);
cmp_core : cordic_core
generic map (
g_stages => g_stages,
g_mode => "rect_to_polar")
port map (
x_i => adjusted_x,
y_i => adjusted_y,
z_i => adjusted_z,
clk_i => clk_i,
ce_i => ce_i,
x_o => mag_temp,
y_o => y_temp,
z_o => phase_temp);
mag_o <= std_logic_vector(mag_temp);
phase_o <= std_logic_vector(phase_temp);
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 0d46ba5255a8477159d03efb3be048a1 | 0.492941 | 3.771074 | false | false | false | false |
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| gpl-3.0 | 610a17e51d018d2e562931e4939c8f30 | 0.95406 | 1.833643 | false | false | false | false |
iamllama/EE2020 | ee2020.srcs/sources_1/imports/hdl/MouseCtl.vhd | 1 | 48,811 | ------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller uses the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity MouseCtl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
CHECK_PERIOD_MS : integer := 500; -- Period in miliseconds to check if the mouse is present
TIMEOUT_PERIOD_MS : integer := 100 -- Timeout period in miliseconds when the mouse presence is checked
);
port(
clk : in std_logic;
rst : in std_logic;
xpos : out std_logic_vector(11 downto 0);
ypos : out std_logic_vector(11 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
value : in std_logic_vector(11 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end MouseCtl;
architecture Behavioral of MouseCtl is
------------------------------------------------------------------------
-- Ps2 Interface component declaration
------------------------------------------------------------------------
COMPONENT Ps2Interface
PORT(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
END COMPONENT;
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(11 downto 0) := x"31F";
-- 799
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(11 downto 0) := x"257";
-- 599
-- Mouse check tick constants
constant CHECK_PERIOD_CLOCKS : integer := ((CHECK_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ));
constant TIMEOUT_PERIOD_CLOCKS : integer := ((TIMEOUT_PERIOD_MS*1000000)/(1000000000/SYSCLK_FREQUENCY_HZ));
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(11 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max: std_logic_vector(11 downto 0) := DEFAULT_MAX_X;
signal y_max: std_logic_vector(11 downto 0) := DEFAULT_MAX_Y;
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,
check_read_id,check_read_id_wait_ack,check_read_id_wait_id,
mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
-- PS2 Interface and Mouse Controller interconnection signals
-- read_data - from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - 8 bits, from ps2interface
-- - the byte received from the mouse.
-- tx_data - 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write_data - to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
signal read_data : std_logic;
signal err : std_logic;
signal rx_data: std_logic_vector (7 downto 0);
signal tx_data: std_logic_vector (7 downto 0);
signal write_data : std_logic;
-- Periodic checking counter, reset and tick signal
-- The periodic checking counter acts as a watchdog, periodically
-- reading the Mouse ID, therefore checking if the mouse is present
-- If there is no answer, after the timeout period passed, then the
-- state machine is reinitialized
signal periodic_check_cnt : integer range 0 to (CHECK_PERIOD_CLOCKS - 1) := 0;
signal reset_periodic_check_cnt : STD_LOGIC := '0';
signal periodic_check_tick : STD_LOGIC := '0';
-- Self-blocking Timeout checking counter, reset and timeout indication signal
signal timeout_cnt : integer range 0 to (TIMEOUT_PERIOD_CLOCKS - 1) := 0;
signal reset_timeout_cnt : STD_LOGIC := '0';
signal timeout : STD_LOGIC := '0';
begin
Inst_Ps2Interface: Ps2Interface
PORT MAP
(
ps2_clk => ps2_clk,
ps2_data => ps2_data,
clk => clk,
rst => rst,
tx_data => tx_data,
write_data => write_data,
rx_data => rx_data,
read_data => read_data,
busy => open,
err => err
);
-- Create the periodic_check_cnt counter
Count_periodic_check: process (clk, periodic_check_cnt, reset_periodic_check_cnt)
begin
if clk'EVENT AND clk = '1' then
if reset_periodic_check_cnt = '1' then
periodic_check_cnt <= 0;
elsif periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) then
periodic_check_cnt <= 0;
else
periodic_check_cnt <= periodic_check_cnt + 1;
end if;
end if;
end process Count_periodic_check;
periodic_check_tick <= '1' when periodic_check_cnt = (CHECK_PERIOD_CLOCKS - 1) else '0';
-- Create the timeout counter
Count_timeout: process (clk, timeout_cnt, reset_timeout_cnt)
begin
if clk'EVENT AND clk = '1' then
if reset_timeout_cnt = '1' then
timeout_cnt <= 0;
elsif timeout_cnt = (TIMEOUT_PERIOD_CLOCKS - 1) then
timeout_cnt <= (TIMEOUT_PERIOD_CLOCKS - 1);
else
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process Count_timeout;
timeout <= '1' when timeout_cnt = (TIMEOUT_PERIOD_CLOCKS - 1) else '0';
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(11 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(11 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(11 downto 0);
variable inc: std_logic_vector(11 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "111000000000";
else
-- inc is sign extended x_inc
inc := "1111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(11) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "000100000000";
else
-- inc is sign extended x_inc
inc := "0000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(11 downto 0);
variable inc: std_logic_vector(11 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "111100000000";
else
-- inc is sign extended y_inc
inc := "1111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(11) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "000100000000";
else
-- inc is sign extended y_inc
inc := "0000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > (y_max)) then
y_pos <= y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
reset_periodic_check_cnt <= '1';
reset_timeout_cnt <= '1';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write_data <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write_data <= '1';
reset_periodic_check_cnt <= '1';
reset_timeout_cnt <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read_data = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read_data = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read_data = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write_data <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write_data <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write_data <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write_data <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read_data = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write_data <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write_data <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write_data <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write_data <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write_data <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- Start periodic check counter
reset_periodic_check_cnt <= '0';
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read_data = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read_data = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read_data = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read_data = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif periodic_check_tick = '1' then -- Check periodically if the mouse is present
state <= check_read_id;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- From timer to time determined by the CHECK_TICK_PERIOD_MS,
-- Read ID command is sent to the mouse.
when check_read_id =>
-- Start the timeout counter
reset_timeout_cnt <= '0';
tx_data <= READ_ID;
write_data <= '1';
state <= check_read_id_wait_ack;
-- wait ack for sending the read id command
when check_read_id_wait_ack =>
if(read_data = '1') then
if(rx_data = FA) then
state <= check_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
elsif (timeout = '1') then -- Timeout ocurred, so the mouse is not present, go to the reset state
state <= reset;
else
state <= check_read_id_wait_ack;
end if;
-- received the mouse id
-- It means that the mouse is present and reading data
-- can continue
-- if anything else is received or timeout or an error occurred
-- then the FSM transitions to reset state.
when check_read_id_wait_id =>
if(read_data = '1') then
if(rx_data = "000000000") or (rx_data = "00000011") then
-- The mouse is present, so reset the timeout counter
reset_timeout_cnt <= '1';
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
elsif (timeout = '1') then-- Timeout ocurred, so the mouse is not present, go to the reset state
state <= reset;
else
state <= check_read_id_wait_id;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral; | gpl-3.0 | a5a8fbed6bc452f09b85138979b9dfd0 | 0.51304 | 4.474379 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/qsys/pio_n/pio_n.vhd | 1 | 3,094 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pio_n is
generic (
RegCnt : positive := 256;
ByteEnable: boolean := false
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
data_in_value : in std_logic_vector(RegCnt*32-1 downto 0) := (others => '0'); -- data.data_in_value
data_in_read : out std_logic_vector(RegCnt-1 downto 0); -- .data_in_read
data_out_value : out std_logic_vector(RegCnt*32-1 downto 0); -- .data_out_value
data_out_write : out std_logic_vector(RegCnt-1 downto 0); -- .data_out_write
avl_mm_address : in std_logic_vector(7 downto 0) := (others => '0'); -- avl_mm.address
avl_mm_writebyteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .writebyteenable
avl_mm_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_mm_chipselect : in std_logic := '0'; -- .chipselect
avl_mm_readdata : out std_logic_vector(31 downto 0); -- .readdata
avl_mm_read : in std_logic := '0' -- .read
);
end entity pio_n;
architecture rtl of pio_n is
begin
p_sync_rd: process(clk,reset) is
begin
if reset = '1' then
avl_mm_readdata <= (others=>'0');
data_in_read <= (others=>'0');
elsif rising_edge(clk) then
data_in_read <= (others=>'0');
for i in 0 to RegCnt-1 loop
if i = unsigned(avl_mm_address) then
avl_mm_readdata <= data_in_value((i+1)*32-1 downto i*32);
if avl_mm_chipselect = '1' and avl_mm_read = '1' then
data_in_read(i) <= '1';
end if;
end if;
end loop;
end if;
end process;
p_sync_wr: process(clk,reset) is
begin
if reset = '1' then
data_out_value <= (others=>'0');
data_out_write <= (others=>'0');
elsif rising_edge(clk) then
data_out_write <= (others=>'0');
for i in 0 to RegCnt-1 loop
if i = unsigned(avl_mm_address) and avl_mm_chipselect = '1' then--and avl_mm_writebyteenable /= "0000" then
for b in 0 to 4-1 loop
if avl_mm_writebyteenable(b) = '1' then
data_out_value((i)*32+(b+1)*8-1 downto b*8+i*32) <= avl_mm_writedata((b+1)*8-1 downto b*8);
data_out_write(i) <= '1';
end if;
end loop;
end if;
end loop;
end if;
end process;
end architecture rtl; -- of new_component
| gpl-3.0 | 8cdf2d61ecd43df27a0899e9c205e381 | 0.450873 | 3.773171 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/simulation/modelsim/TB_IMG_LSB.vhd | 1 | 6,397 | -- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "07/06/2015 20:11:56"
-- Vhdl Test Bench template for design : IMG_LSB
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
--Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE std.textio.all;
USE ieee.std_logic_textio.all;
library work;
USE work.mytype.all;
ENTITY IMG_LSB_vhd_tst IS
END IMG_LSB_vhd_tst;
ARCHITECTURE IMG_LSB_arch OF IMG_LSB_vhd_tst IS
-- constants
-- signals
FILE INTEXT_R: TEXT IS IN "INTEXT_R.txt";
FILE INTEXT_G: TEXT IS IN "INTEXT_G.txt";
FILE INTEXT_B: TEXT IS IN "INTEXT_B.txt";
FILE OUTTEXT_R: TEXT IS OUT "OUTTEXT_R.txt";
FILE OUTTEXT_G: TEXT IS OUT "OUTTEXT_G.txt";
FILE OUTTEXT_B: TEXT IS OUT "OUTTEXT_B.txt";
CONSTANT CLK_PERIOD:TIME:=10 NS;
SIGNAL A_COL : COLOR;
SIGNAL A_ROW : COLOR;
SIGNAL B_COL : COLOR;
SIGNAL B_ROW : COLOR;
SIGNAL C_COL : COLOR;
SIGNAL C_ROW : COLOR;
SIGNAL B_IN : COLOR;
SIGNAL B_OUT : COLOR;
SIGNAL CHAR_OUT : CHARACTER;
SIGNAL CLK : STD_LOGIC;
SIGNAL DETECT_RESULT : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL G_IN : COLOR;
SIGNAL G_OUT : COLOR;
SIGNAL HB_OUT : COLOR;
SIGNAL HG_OUT : COLOR;
SIGNAL HR_OUT : COLOR;
SIGNAL R_IN : COLOR;
SIGNAL R_OUT : COLOR;
SIGNAL RESET : STD_LOGIC;
SIGNAL SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL STR : STRING(1 TO 20);
SIGNAL STR_LEN : INTEGER RANGE 0 TO 8192;
SIGNAL XX : COLOR;
SIGNAL YY : COLOR;
SIGNAL ZZ : INTEGER RANGE 0 TO 2;
COMPONENT IMG_LSB
PORT (
A_COL : IN COLOR;
A_ROW : IN COLOR;
B_COL : IN COLOR;
B_IN : IN COLOR;
B_OUT : BUFFER COLOR;
B_ROW : IN COLOR;
C_COL : IN COLOR;
C_ROW : IN COLOR;
CHAR_OUT : BUFFER CHARACTER;
CLK : IN STD_LOGIC;
DETECT_RESULT : BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);
G_IN : IN COLOR;
G_OUT : BUFFER COLOR;
HB_OUT : BUFFER COLOR;
HG_OUT : BUFFER COLOR;
HR_OUT : BUFFER COLOR;
R_IN : IN COLOR;
R_OUT : BUFFER COLOR;
RESET : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
STR : IN STRING;
STR_LEN : IN INTEGER RANGE 0 TO 8192;
XX : IN COLOR;
YY : IN COLOR;
ZZ : IN INTEGER RANGE 0 TO 2
);
END COMPONENT;
BEGIN
i1 : IMG_LSB
PORT MAP (
-- list connections between master ports and signals
A_COL => A_COL,
A_ROW => A_ROW,
B_COL => B_COL,
B_IN => B_IN,
B_OUT => B_OUT,
B_ROW => B_ROW,
C_COL => C_COL,
C_ROW => C_ROW,
CHAR_OUT => CHAR_OUT,
CLK => CLK,
DETECT_RESULT => DETECT_RESULT,
G_IN => G_IN,
G_OUT => G_OUT,
HB_OUT => HB_OUT,
HG_OUT => HG_OUT,
HR_OUT => HR_OUT,
R_IN => R_IN,
R_OUT => R_OUT,
RESET => RESET,
SEL => SEL,
STR => STR,
STR_LEN => STR_LEN,
XX => XX,
YY => YY,
ZZ => ZZ
);
init : PROCESS
-- variable declarations
BEGIN
--只作为赋初值使用
RESET<='1';
SEL<="11";
A_COL<=2;
A_ROW<=2;
B_COL<=1;
B_ROW<=1;
C_COL<=3;
C_ROW<=0;
XX<=0;
YY<=6;
ZZ<=1;
STR_LEN<=12;
STR(1 TO 12)<="Hello World!";
WAIT FOR (CLK_PERIOD/4);
RESET<='0';
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
VARIABLE INLINE_R: LINE;
VARIABLE INLINE_G: LINE;
VARIABLE INLINE_B: LINE;
VARIABLE OUTLINE_R : LINE;
VARIABLE OUTLINE_G : LINE;
VARIABLE OUTLINE_B : LINE;
VARIABLE INR_V,ING_V,INB_V,OUTR_V,OUTG_V,OUTB_V: COLOR;
VARIABLE INCOL: INTEGER RANGE 0 TO 256 :=0;
VARIABLE I: INTEGER RANGE 0 TO 9:=0;
--SEL选择不同功能(00和11)时DELAY是不同的，分别为3和1
CONSTANT DELAY: INTEGER:=1;
VARIABLE OUTCOL: INTEGER RANGE 0 TO 256 :=0;
VARIABLE OUTROW: INTEGER RANGE 0 TO 256 :=0;
BEGIN
-- code executes for every event on sensitivity list
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
--读入数据
IF(NOT ENDFILE(INTEXT_R)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_R,INLINE_R);
END IF;
READ(INLINE_R,INR_V);
R_IN<=INR_V;
END IF;
IF(NOT ENDFILE(INTEXT_G)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_G,INLINE_G);
END IF; READ(INLINE_G,ING_V); G_IN<=ING_V;
END IF;
IF(NOT ENDFILE(INTEXT_B)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_B,INLINE_B);
END IF;
READ(INLINE_B,INB_V);
B_IN<=INB_V;
END IF;
--写数据
--延迟N(N=DELAY)个时钟周期
IF (I<DELAY) THEN
I:=I+1;
ELSE
WRITE(OUTLINE_R,HR_OUT);
--WRITE(OUTLINE_R,R_OUT);
--以TAB分隔，VHDL定义的emum里tab就为HT
WRITE(OUTLINE_R,HT);
WRITE(OUTLINE_G,HG_OUT);
--WRITE(OUTLINE_G,G_OUT);
WRITE(OUTLINE_G,HT);
WRITE(OUTLINE_B,HB_OUT);
--WRITE(OUTLINE_B,B_OUT);
WRITE(OUTLINE_B,HT);
IF(OUTCOL=255 AND OUTROW<=255) THEN
OUTROW:=OUTROW+1;
WRITELINE(OUTTEXT_R,OUTLINE_R);
WRITELINE(OUTTEXT_G,OUTLINE_G);
WRITELINE(OUTTEXT_B,OUTLINE_B);
END IF;
IF(OUTCOL<=255) THEN
OUTCOL:=OUTCOL+1;
END IF;
IF(OUTCOL=256) THEN
OUTCOL:=0;
END IF;
END IF;
IF(INCOL<=255) THEN
INCOL:=INCOL+1;
END IF;
IF(INCOL=256) THEN
INCOL:=0;
END IF;
WAIT FOR CLK_PERIOD/2;
END PROCESS always;
END IMG_LSB_arch;
| apache-2.0 | 49bf4c2e92d19857ed03156c014dc31b | 0.618035 | 3.051841 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/xillydemo.vhd | 1 | 11,024 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.myDeclare.all;
entity xillydemo is
port (
PCIE_PERST_B_LS : IN std_logic;
PCIE_REFCLK_N : IN std_logic;
PCIE_REFCLK_P : IN std_logic;
PCIE_RX_N : IN std_logic_vector(7 DOWNTO 0);
PCIE_RX_P : IN std_logic_vector(7 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_N : OUT std_logic_vector(7 DOWNTO 0);
PCIE_TX_P : OUT std_logic_vector(7 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PCIE_PERST_B_LS : IN std_logic;
PCIE_REFCLK_N : IN std_logic;
PCIE_REFCLK_P : IN std_logic;
PCIE_RX_N : IN std_logic_vector(7 DOWNTO 0);
PCIE_RX_P : IN std_logic_vector(7 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_N : OUT std_logic_vector(7 DOWNTO 0);
PCIE_TX_P : OUT std_logic_vector(7 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
user_r_async_read_8_rden : OUT std_logic;
user_r_async_read_8_empty : IN std_logic;
user_r_async_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_async_read_8_eof : IN std_logic;
user_r_async_read_8_open : OUT std_logic;
user_r_cmd_mem_32_rden : OUT std_logic;
user_r_cmd_mem_32_empty : IN std_logic;
user_r_cmd_mem_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_cmd_mem_32_eof : IN std_logic;
user_r_cmd_mem_32_open : OUT std_logic;
user_w_cmd_mem_32_wren : OUT std_logic;
user_w_cmd_mem_32_full : IN std_logic;
user_w_cmd_mem_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_cmd_mem_32_open : OUT std_logic;
user_cmd_mem_32_addr : OUT std_logic_vector(4 DOWNTO 0);
user_cmd_mem_32_addr_update : OUT std_logic;
user_r_data_read_32_rden : OUT std_logic;
user_r_data_read_32_empty : IN std_logic;
user_r_data_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_data_read_32_eof : IN std_logic;
user_r_data_read_32_open : OUT std_logic);
end component;
component fifo_xillybus_8
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
COMPONENT fifo_xillybus_32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
--asynchronous communication channel controller
component async_com_control is
port (
bus_clk : in std_logic;
reset : in std_logic;
--pclk : in std_logic;
--din : in std_logic_vector(11 downto 0); --headstage communication input from the Deserilizer
dev_reset_in : in std_logic; --a temp debug signal to mimic the communication via magic number to the headstage
conf_ack : in std_logic;
conf_nack : in std_logic;
conf_done : in std_logic;
conf_mem_in : in mem_type;
--cobs fifo output
async_fifo_wr_enb : out std_logic;
async_fifo_wr_data : out std_logic_vector(7 downto 0)
);
end component;
--configuration memory controller
component mem_conf_control is
port (
bus_clk : in std_logic;
reset : in std_logic;
user_mem_32_addr : in std_logic_vector(3 downto 0);
user_w_mem_32_wren : in std_logic;
user_r_mem_32_rden : in std_logic;
user_w_mem_32_data : in std_logic_vector(31 downto 0);
user_r_mem_32_data : out std_logic_vector(31 downto 0);
dev_reset_out : out std_logic;
conf_ack : out std_logic;
conf_nack : out std_logic;
mem_out : out mem_type
);
end component;
component hs_com_control is
port (
bus_clk : in std_logic;
global_reset : in std_logic;
dev_reset_in : in std_logic;
hs_com_fifo_data : out std_logic_vector(31 downto 0);
hs_com_fifo_enb : out std_logic
);
end component;
--a simple clock divider
component clk_div is
generic (MAXD: natural:=5);
port(
clk: in std_logic;
reset: in std_logic;
div: in integer range 0 to MAXD;
div_clk: out std_logic
);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_xillybus_32: component is true;
attribute syn_black_box of fifo_xillybus_8: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal conf_ack, conf_nack : std_logic;
signal conf_mem : mem_type;
signal hs_com_fifo_data : std_logic_vector(31 downto 0);
signal hs_com_fifo_enb : std_logic;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal user_r_async_read_8_rden : std_logic;
signal user_r_async_read_8_empty : std_logic;
signal user_r_async_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_async_read_8_eof : std_logic;
signal user_r_async_read_8_open : std_logic;
signal user_r_cmd_mem_32_rden : std_logic;
signal user_r_cmd_mem_32_empty : std_logic;
signal user_r_cmd_mem_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_cmd_mem_32_eof : std_logic;
signal user_r_cmd_mem_32_open : std_logic;
signal user_w_cmd_mem_32_wren : std_logic;
signal user_w_cmd_mem_32_full : std_logic;
signal user_w_cmd_mem_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_cmd_mem_32_open : std_logic;
signal user_cmd_mem_32_addr : std_logic_vector(4 DOWNTO 0);
signal user_cmd_mem_32_addr_update : std_logic;
signal user_r_data_read_32_rden : std_logic;
signal user_r_data_read_32_empty : std_logic;
signal user_r_data_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_data_read_32_eof : std_logic;
signal user_r_data_read_32_open : std_logic;
signal async_fifo_wr_enb : std_logic;
signal async_fifo_wr_data : std_logic_vector(7 downto 0);
signal clk0p5Hz : std_logic;
signal clk_slow : std_logic;
signal dev_reset : std_logic;
signal hs_com_reset : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_async_read_8
-- FPGA to CPU signals:
user_r_async_read_8_rden => user_r_async_read_8_rden,
user_r_async_read_8_empty => user_r_async_read_8_empty,
user_r_async_read_8_data => user_r_async_read_8_data,
user_r_async_read_8_eof => user_r_async_read_8_eof,
user_r_async_read_8_open => user_r_async_read_8_open,
-- Ports related to /dev/xillybus_cmd_mem_32
-- FPGA to CPU signals:
user_r_cmd_mem_32_rden => user_r_cmd_mem_32_rden,
user_r_cmd_mem_32_empty => user_r_cmd_mem_32_empty,
user_r_cmd_mem_32_data => user_r_cmd_mem_32_data,
user_r_cmd_mem_32_eof => user_r_cmd_mem_32_eof,
user_r_cmd_mem_32_open => user_r_cmd_mem_32_open,
-- CPU to FPGA signals:
user_w_cmd_mem_32_wren => user_w_cmd_mem_32_wren,
user_w_cmd_mem_32_full => user_w_cmd_mem_32_full,
user_w_cmd_mem_32_data => user_w_cmd_mem_32_data,
user_w_cmd_mem_32_open => user_w_cmd_mem_32_open,
-- Address signals:
user_cmd_mem_32_addr => user_cmd_mem_32_addr,
user_cmd_mem_32_addr_update => user_cmd_mem_32_addr_update,
-- Ports related to /dev/xillybus_data_read_32
-- FPGA to CPU signals:
user_r_data_read_32_rden => user_r_data_read_32_rden,
user_r_data_read_32_empty => user_r_data_read_32_empty,
user_r_data_read_32_data => user_r_data_read_32_data,
user_r_data_read_32_eof => user_r_data_read_32_eof,
user_r_data_read_32_open => user_r_data_read_32_open,
-- General signals
PCIE_PERST_B_LS => PCIE_PERST_B_LS,
PCIE_REFCLK_N => PCIE_REFCLK_N,
PCIE_REFCLK_P => PCIE_REFCLK_P,
PCIE_RX_N => PCIE_RX_N,
PCIE_RX_P => PCIE_RX_P,
GPIO_LED => GPIO_LED,
PCIE_TX_N => PCIE_TX_N,
PCIE_TX_P => PCIE_TX_P,
bus_clk => bus_clk,
quiesce => quiesce
);
highspeed_data: hs_com_control
port map(
bus_clk => bus_clk,
global_reset => quiesce,
--device_num : in std_logic_vector(LOG2_MAX_DEVICE_NUMBER-1 downto 0);
dev_reset_in => hs_com_reset,
hs_com_fifo_data => hs_com_fifo_data,
hs_com_fifo_enb => hs_com_fifo_enb
);
hs_com_reset <= dev_reset or reset_32;
-- 32bit uni-directional data bus to the host
fifo_32 : fifo_xillybus_32
port map(
wr_clk => bus_clk,
rd_clk => bus_clk,
rst => hs_com_reset,
din => hs_com_fifo_data,
wr_en => hs_com_fifo_enb,
rd_en => user_r_data_read_32_rden,
dout => user_r_data_read_32_data,
full => open,
empty => user_r_data_read_32_empty
);
reset_32 <= not (user_r_data_read_32_open);
user_r_data_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_xillybus_8
port map(
clk => bus_clk,
srst => reset_8,
din => async_fifo_wr_data,--async_fifo_wr_data,
wr_en => async_fifo_wr_enb,
rd_en => user_r_async_read_8_rden,
dout => user_r_async_read_8_data,
full => open,
empty => user_r_async_read_8_empty
);
reset_8 <= not (user_r_async_read_8_open);
user_r_async_read_8_eof <= '0';
-- Async communication controller
async_communication: async_com_control PORT MAP (
bus_clk => bus_clk,
reset => reset_8,
dev_reset_in => dev_reset,
conf_ack => conf_ack,
conf_nack => '1',
conf_done => '1',
conf_mem_in => conf_mem,
async_fifo_wr_enb => async_fifo_wr_enb,
async_fifo_wr_data => async_fifo_wr_data
);
mem_controller: mem_conf_control PORT MAP (
bus_clk => bus_clk,
reset => quiesce,
user_mem_32_addr => user_cmd_mem_32_addr(3 downto 0),
user_w_mem_32_wren => user_w_cmd_mem_32_wren,
user_r_mem_32_rden => user_r_cmd_mem_32_rden,
user_w_mem_32_data => user_w_cmd_mem_32_data,
user_r_mem_32_data => user_r_cmd_mem_32_data,
dev_reset_out => dev_reset,
conf_ack => conf_ack,
conf_nack => conf_nack,
mem_out => conf_mem
);
clk_div_0p5Hz: clk_div generic map (MAXD => 500_000_000)
port map ( clk => bus_clk, reset => quiesce, div => 500_000_000, div_clk => clk0p5Hz);
end sample_arch;
| mit | 373c7041831e724346a50821bf62b55d | 0.598422 | 2.969828 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/uart_pkg.vhd | 1 | 1,286 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package uart_pkg is
component UART is
generic (
CLK_FREQ : integer := 50e6; -- set system clock frequency in Hz
BAUD_RATE : integer := 115200; -- baud rate value
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic; -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end component;
end package;
| gpl-3.0 | 2abc48498a646cc3455dcd37d8e8304b | 0.582426 | 3.653409 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/config.vhd | 2 | 29,449 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
end config;
| mit | 1bbabde8905996dee1ba30c077f8e7ea | 0.630887 | 3.543803 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXMacRx.vhd | 1 | 6,501 | ---------------------------------------------------------------------------------
-- Title : 1000 BASE X MAC RX Layer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXMacRx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to GTP interface to 1000 BASE X Ethernet.
-- Receiver passes bytes out.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity Eth1000BaseXMacRx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Incoming data from the 16-to-8 mux
macDataIn : in EthMacDataType;
-- Outgoing bytes and flags to the applications
macRxData : out slv(7 downto 0);
macRxDataValid : out sl;
macRxDataLast : out sl;
macRxBadFrame : out sl;
-- Monitoring flags
macBadCrcCount : out slv(15 downto 0)
);
end Eth1000BaseXMacRx;
-- Define architecture
architecture rtl of Eth1000BaseXMacRx is
type StateType is (S_IDLE, S_PREAMBLE, S_FRAME_DATA, S_WAIT_CRC,
S_CHECK_CRC);
type RegType is record
state : StateType;
rxDataValid : sl;
rxDataLast : sl;
rxDataOut : slv(7 downto 0);
rxBadFrame : sl;
crcReset : sl;
crcDataValid : sl;
byteCount : slv(15 downto 0);
badCrcCount : slv(15 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => S_IDLE,
rxDataOut => (others => '0'),
rxDataValid => '0',
rxDataLast => '0',
rxBadFrame => '0',
crcReset => '0',
crcDataValid => '0',
byteCount => (others => '0'),
badCrcCount => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal crcOut : slv(31 downto 0);
-- signal crcData : slv(31 downto 0);
signal crcDataWidth : slv(2 downto 0);
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- crcData <= x"000000" & r.rxDataOut;
crcDataWidth <= "000";
U_Crc32 : entity work.Crc32
generic map (
BYTE_WIDTH_G => 1,
CRC_INIT_G => x"FFFFFFFF",
GATE_DELAY_G => GATE_DELAY_G
)
port map (
crcOut => crcOut,
crcClk => ethRxClk,
crcDataValid => r.crcDataValid,
crcDataWidth => crcDataWidth,
crcIn => r.rxDataOut,
crcReset => r.crcReset
);
comb : process(r,macDataIn,ethRxRst,crcOut) is
variable v : RegType;
begin
v := r;
v.rxDataOut := macDataIn.data;
case(r.state) is
when S_IDLE =>
v.crcReset := '1';
v.crcDataValid := '0';
v.rxDataValid := '0';
v.rxDataLast := '0';
v.rxBadFrame := '0';
v.byteCount := (others => '0');
-- If we see start of packet then we should move on to accept preamble
if (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and macDataIn.data = K_SOP_C) then
v.state := S_PREAMBLE;
end if;
when S_PREAMBLE =>
v.crcReset := '0';
if (macDataIn.dataValid = '1' and macDataIn.dataK = '0' and macDataIn.data = ETH_SOF_C) then
v.state := S_FRAME_DATA;
-- Bail out if we see a comma, error, carrier
elsif (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and
(macDataIn.data = K_COM_C or macDataIn.data = K_EOP_C or macDataIn.data = K_CAR_C or macDataIn.data = K_ERR_C)) then
v.state := S_IDLE;
end if;
when S_FRAME_DATA =>
v.rxDataValid := macDataIn.dataValid;
v.crcDataValid := '1';
v.byteCount := r.byteCount + 1;
-- Possible errors: K_ERR_C, misplaced comma (K_COM_C)
if (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and
(macDataIn.data = K_ERR_C or macDataIn.data = K_COM_C)) then
v.rxDataValid := '0';
v.rxBadFrame := '1';
v.rxDataLast := '1';
v.state := S_IDLE;
-- Otherwise, should be frame data until we see end of packet
elsif (macDataIn.dataValid = '1' and macDataIn.dataK = '1' and macDataIn.data = K_EOP_C) then
v.rxDataValid := '0';
v.crcDataValid := '0';
v.state := S_WAIT_CRC;
end if;
-- Wait one cycle to account for latency of the CRC module
when S_WAIT_CRC =>
v.state := S_CHECK_CRC;
-- Check whether the CRC is valid
when S_CHECK_CRC =>
v.rxDataLast := '1';
-- Check for packet length and valid CRC
if (crcOut = CRC_CHECK_C and r.byteCount >= 46) then
v.rxBadFrame := '0';
-- Otherwise, it's a bad frame
else
v.rxBadFrame := '1';
v.badCrcCount := r.badCrcCount + 1;
end if;
v.state := S_IDLE;
when others =>
v.state := S_IDLE;
end case;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
macRxData <= r.rxDataOut;
macRxDataValid <= r.rxDataValid;
macRxDataLast <= r.rxDataLast;
macRxBadFrame <= r.rxBadFrame;
macBadCrcCount <= r.badCrcCount;
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 2def59e43252069f63a9665444f1bc5c | 0.503461 | 4.119772 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/Video.vhd | 1 | 135,828 | ----------------------------------------------------------------------------------
-- Company: Digilent Romania
-- Engineer: Elod Gyorgy
--
-- Create Date: 11:44:47 01/12/2009
-- Modify Date: 18:00:00 04/21/2011
-- Design Name:
-- Module Name: Video - package
-- Project Name: Digilent VHDL Library
-- Target Devices:
--
-- Tool versions:
-- Description: This package defines video timing constants and the Digilent logo
-- bitmap.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.03 - Moved the Active Video area to the first part of the counter
-- Revision 0.02 - Added additional resolutions
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package Video is
constant H_MAX : NATURAL := 1600;
constant V_MAX : NATURAL := 900;
----------------------------------------------------------------------------------
-- Resolution selector enumeration
----------------------------------------------------------------------------------
type RESOLUTION is (R480_272P, R640_480P, R720_480P, R1280_720P, R1600_900P, R800_600P);
----------------------------------------------------------------------------------
-- Timing Constants for 480x272 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_480_272p_S : NATURAL := 45; --sync
constant H_480_272p_FP : NATURAL := 0; --front porch
constant H_480_272p_AV : NATURAL := 480; --active video
constant H_480_272p_BP : NATURAL := 0; --back porch
--vertical constants
constant V_480_272p_S : NATURAL := 16; --sync
constant V_480_272p_FP : NATURAL := 0; --front porch
constant V_480_272p_AV : NATURAL := 272; --active video
constant V_480_272p_BP : NATURAL := 0; --back porch
constant H_480_272p_AV_FP : NATURAL := H_480_272p_AV + H_480_272p_FP;
constant H_480_272p_AV_FP_S : NATURAL := H_480_272p_AV + H_480_272p_FP + H_480_272p_S;
constant H_480_272p_AV_FP_S_BP : NATURAL := H_480_272p_AV + H_480_272p_FP + H_480_272p_S + H_480_272p_BP;
constant V_480_272p_AV_FP : NATURAL := V_480_272p_AV + V_480_272p_FP;
constant V_480_272p_AV_FP_S : NATURAL := V_480_272p_AV + V_480_272p_FP + V_480_272p_S;
constant V_480_272p_AV_FP_S_BP : NATURAL := V_480_272p_AV + V_480_272p_FP + V_480_272p_S + V_480_272p_BP;
constant H_480_272p_POL : BOOLEAN := false; -- negative polarity
constant V_480_272p_POL : BOOLEAN := false; -- negative polarity
----------------------------------------------------------------------------------
-- Timing Constants for 640x480 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_640_480p_S : NATURAL := 96; --sync
constant H_640_480p_FP : NATURAL := 16; --front porch
constant H_640_480p_AV : NATURAL := 640; --active video
constant H_640_480p_BP : NATURAL := 48; --back porch
--vertical constants
constant V_640_480p_S : NATURAL := 2; --sync
constant V_640_480p_FP : NATURAL := 33; --front porch
constant V_640_480p_AV : NATURAL := 480; --active video
constant V_640_480p_BP : NATURAL := 10; --back porch
constant H_640_480p_AV_FP : NATURAL := H_640_480p_AV + H_640_480p_FP;
constant H_640_480p_AV_FP_S : NATURAL := H_640_480p_AV + H_640_480p_FP + H_640_480p_S;
constant H_640_480p_AV_FP_S_BP : NATURAL := H_640_480p_AV + H_640_480p_FP + H_640_480p_S + H_640_480p_BP;
constant V_640_480p_AV_FP : NATURAL := V_640_480p_AV + V_640_480p_FP;
constant V_640_480p_AV_FP_S : NATURAL := V_640_480p_AV + V_640_480p_FP + V_640_480p_S;
constant V_640_480p_AV_FP_S_BP : NATURAL := V_640_480p_AV + V_640_480p_FP + V_640_480p_S + V_640_480p_BP;
constant H_640_480p_POL : BOOLEAN := false; -- negative polarity
constant V_640_480p_POL : BOOLEAN := false; -- negative polarity
----------------------------------------------------------------------------------
-- Timing Constants for 720x480 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_720_480p_S : NATURAL := 62; --sync
constant H_720_480p_FP : NATURAL := 16; --front porch
constant H_720_480p_AV : NATURAL := 720; --active video
constant H_720_480p_BP : NATURAL := 60; --back porch
--vertical constants
constant V_720_480p_S : NATURAL := 6; --sync
constant V_720_480p_FP : NATURAL := 9; --front porch
constant V_720_480p_AV : NATURAL := 480; --active video
constant V_720_480p_BP : NATURAL := 30; --back porch
constant H_720_480p_AV_FP : NATURAL := H_720_480p_AV + H_720_480p_FP;
constant H_720_480p_AV_FP_S : NATURAL := H_720_480p_AV + H_720_480p_FP + H_720_480p_S;
constant H_720_480p_AV_FP_S_BP : NATURAL := H_720_480p_AV + H_720_480p_FP + H_720_480p_S + H_720_480p_BP;
constant V_720_480p_AV_FP : NATURAL := V_720_480p_AV + V_720_480p_FP;
constant V_720_480p_AV_FP_S : NATURAL := V_720_480p_AV + V_720_480p_FP + V_720_480p_S;
constant V_720_480p_AV_FP_S_BP : NATURAL := V_720_480p_AV + V_720_480p_FP + V_720_480p_S + V_720_480p_BP;
constant H_720_480p_POL : BOOLEAN := false; -- negative polarity
constant V_720_480p_POL : BOOLEAN := false; -- negative polarity
----------------------------------------------------------------------------------
-- Timing Constants for 1280x720 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_1280_720p_S : NATURAL := 40; --sync
constant H_1280_720p_FP : NATURAL := 110; --front porch
constant H_1280_720p_AV : NATURAL := 1280; --active video
constant H_1280_720p_BP : NATURAL := 220; --back porch
--vertical constants
constant V_1280_720p_S : NATURAL := 5; --sync
constant V_1280_720p_FP : NATURAL := 5; --front porch
constant V_1280_720p_AV : NATURAL := 720; --active video
constant V_1280_720p_BP : NATURAL := 20; --back porch
constant H_1280_720p_AV_FP : NATURAL := H_1280_720p_AV + H_1280_720p_FP;
constant H_1280_720p_AV_FP_S : NATURAL := H_1280_720p_AV + H_1280_720p_FP + H_1280_720p_S;
constant H_1280_720p_AV_FP_S_BP : NATURAL := H_1280_720p_AV + H_1280_720p_FP + H_1280_720p_S + H_1280_720p_BP;
constant V_1280_720p_AV_FP : NATURAL := V_1280_720p_AV + V_1280_720p_FP;
constant V_1280_720p_AV_FP_S : NATURAL := V_1280_720p_AV + V_1280_720p_FP + V_1280_720p_S;
constant V_1280_720p_AV_FP_S_BP : NATURAL := V_1280_720p_AV + V_1280_720p_FP + V_1280_720p_S + V_1280_720p_BP;
constant H_1280_720p_POL : BOOLEAN := true; -- positive polarity
constant V_1280_720p_POL : BOOLEAN := true; -- positive polarity
----------------------------------------------------------------------------------
-- Timing Constants for 1600x900 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_1600_900p_S : NATURAL := 20; --sync
constant H_1600_900p_FP : NATURAL := 60; --front porch
constant H_1600_900p_AV : NATURAL := 1600; --active video
constant H_1600_900p_BP : NATURAL := 120; --back porch
--vertical constants
constant V_1600_900p_S : NATURAL := 10; --sync
constant V_1600_900p_FP : NATURAL := 20; --front porch
constant V_1600_900p_AV : NATURAL := 900; --active video
constant V_1600_900p_BP : NATURAL := 70; --back porch
constant H_1600_900p_AV_FP : NATURAL := H_1600_900p_AV + H_1600_900p_FP;
constant H_1600_900p_AV_FP_S : NATURAL := H_1600_900p_AV + H_1600_900p_FP + H_1600_900p_S;
constant H_1600_900p_AV_FP_S_BP : NATURAL := H_1600_900p_AV + H_1600_900p_FP + H_1600_900p_S + H_1600_900p_BP;
constant V_1600_900p_AV_FP : NATURAL := V_1600_900p_AV + V_1600_900p_FP;
constant V_1600_900p_AV_FP_S : NATURAL := V_1600_900p_AV + V_1600_900p_FP + V_1600_900p_S;
constant V_1600_900p_AV_FP_S_BP : NATURAL := V_1600_900p_AV + V_1600_900p_FP + V_1600_900p_S + V_1600_900p_BP;
constant H_1600_900p_POL : BOOLEAN := true; -- positive polarity
constant V_1600_900p_POL : BOOLEAN := true; -- positive polarity
----------------------------------------------------------------------------------
-- Timing Constants for 800x600 @60Hz
----------------------------------------------------------------------------------
--horizontal constants
constant H_800_600p_S : NATURAL := 128; --sync
constant H_800_600p_FP : NATURAL := 40; --front porch
constant H_800_600p_AV : NATURAL := 800; --active video
constant H_800_600p_BP : NATURAL := 88; --back porch
--vertical constants
constant V_800_600p_S : NATURAL := 4; --sync
constant V_800_600p_FP : NATURAL := 1; --front porch
constant V_800_600p_AV : NATURAL := 600; --active video
constant V_800_600p_BP : NATURAL := 23; --back porch
constant H_800_600p_AV_FP : NATURAL := H_800_600p_AV + H_800_600p_FP;
constant H_800_600p_AV_FP_S : NATURAL := H_800_600p_AV + H_800_600p_FP + H_800_600p_S;
constant H_800_600p_AV_FP_S_BP : NATURAL := H_800_600p_AV + H_800_600p_FP + H_800_600p_S + H_800_600p_BP;
constant V_800_600p_AV_FP : NATURAL := V_800_600p_AV + V_800_600p_FP;
constant V_800_600p_AV_FP_S : NATURAL := V_800_600p_AV + V_800_600p_FP + V_800_600p_S;
constant V_800_600p_AV_FP_S_BP : NATURAL := V_800_600p_AV + V_800_600p_FP + V_800_600p_S + V_800_600p_BP;
constant H_800_600p_POL : BOOLEAN := true; -- positive polarity
constant V_800_600p_POL : BOOLEAN := true; -- positive polarity
----------------------------------------------------------------------------------
-- Video ROM
----------------------------------------------------------------------------------
constant VROM_WIDTH : NATURAL := 250;
constant VROM_HEIGHT : NATURAL := 56;
constant VROM_COLOR_DEPTH : NATURAL := 16;
type vromt is array (0 to VROM_WIDTH*VROM_HEIGHT-1) of
std_logic_vector (VROM_COLOR_DEPTH-1 downto 0);
constant vrom : vromt := (
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attribute rom_extract : string;
attribute rom_style : string;
attribute rom_extract of vrom : constant is "yes";
attribute rom_style of vrom : constant is "block";
end Video; | gpl-3.0 | 9431dd98be34f72fc6c7c9d3f9b9ce30 | 0.557352 | 2.088152 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/simple_core.vhd | 1 | 74,222 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/10/2018 06:05:22 PM
-- Module Name: simple_core - Behavioral
-- Description: Incremental build of the simplified processor core
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
reggie: out regfile_arr;
pc_curr: out doubleword;
DEBUG_halt: in std_logic := '0';
MMU_addr_in: out doubleword; -- 64-bits address for load/store
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_store: out std_logic; -- High to toggle store
MMU_load: out std_logic; -- High to toggle load
MMU_busy: in std_logic; -- High when busy
MMU_ready_instr: out std_logic; -- Ready for a new instruction (initiates fetch)
MMU_addr_instr: out doubleword; -- Instruction Address (AKA PC)
MMU_alignment: out std_logic_vector(3 downto 0);-- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_instr_out: in word; -- 64-Bits instruction out for fetch
MMU_error: in std_logic_vector(5 downto 0) -- Error bits from MMU
);
end simple_core;
architecture Behavioral of simple_core is
----------------------------------------------------------------------------------
-- Component instantiation
----------------------------------------------------------------------------------
component ALU is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end component;
component fence is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control has data to be written back
ready_output: in std_logic; -- MMU is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in doubleword; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out doubleword -- MMU destination for output data
);
end component;
component decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end component;
component regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end component;
component mux is
Port(
sel: in std_logic; -- Select from zero, one ports
zero_port: in doubleword; -- Data in, zero select port
one_port: in doubleword; -- Data in, one select port
out_port: out doubleword -- Output data
);
end component;
component sext is
Port(
imm12: in std_logic_vector(11 downto 0);
imm20: in std_logic_vector(19 downto 0);
output_imm12: out std_logic_vector(63 downto 0);
output_imm20: out std_logic_vector(63 downto 0)
);
end component;
----------------------------------------------------------------------------------
-- Signals and constants
----------------------------------------------------------------------------------
-- Feedback signals
signal s_rst: std_logic; -- internal reset
signal s_halts: std_logic_vector(2 downto 0); -- IM, REG, ALU halt signals
signal s_ALU_op: ctrl_t; -- ALU operation control
signal s_request_IM_in: std_logic; -- Signal pending write to IM
signal s_request_IM_inack: std_logic; -- Acknowledge above write handled
signal s_request_IM_out: std_logic; -- Signal ready for instruction
signal s_request_IM_outack: std_logic; -- Acknowledge instruction data is fresh
signal s_wb_select: std_logic; -- Select from ALU result or MMU data to Regfile write
signal s_PC_next: doubleword:= x"0000000090000000"; -- Next PC address
signal s_PC_curr: doubleword; -- Preserves current PC for jumps
signal s_MMU_store: std_logic; -- Signal MMU to store
signal s_MMU_load: std_logic; -- Signal MMU to load
signal s_MMU_busy: std_logic; -- MMU is loading, storing, or fetching
signal s_ATU_busy: std_logic; -- Atomic unit is doing its thing
signal s_ATU_stage:std_logic; -- After resuming, need to know what stage of atomic instruction we are in
signal s_ALU_source_select: std_logic; -- Switch in immediate values
-- Decoded instruction parts
signal s_instr_code: instr_t; -- Exact instruction encoding
signal s_opcode: opcode_t; -- Opcode category abstraction
signal s_rs1: reg_t; -- Regfile read address
signal s_rs2: reg_t; -- Regfile read address
signal s_rs3: reg_t; -- Regfile read address
signal s_rd: reg_t; -- Regfile write address
signal s_shamt: std_logic_vector(4 downto 0); -- Shift amount, immediate shifts
signal s_imm12: std_logic_vector(11 downto 0); -- Immediate value, 12 bit style
signal s_imm20: std_logic_vector(19 downto 0); -- Immediate value, 20 bit style
signal s_csr_bits: std_logic_vector(11 downto 0); -- CSR address for CSR instructions
signal s_functs: std_logic_vector(15 downto 0); -- Holds concatenation of funct3, funct6, funct7
-- ALU connectors
signal s_ALU_input2: doubleword;
signal s_ALU_result: doubleword;
signal s_ALU_Error: std_logic_vector(2 downto 0);
signal s_ALU_Imm: doubleword;
signal s_ALU_Imm_select: std_logic;
-- Instruction memory connectors
signal s_IM_input_addr: doubleword;
signal s_IM_input_data: doubleword;
signal s_IM_output_addr: doubleword;
signal s_IM_output_data: doubleword;
-- Register file connectors
signal s_REG_raddr1: reg_t;
signal s_REG_raddr2: reg_t;
signal s_REG_rdata1: doubleword;
signal s_REG_rdata2: doubleword;
signal s_REG_wdata: doubleword;
signal s_REG_waddr: reg_t;
signal s_REG_write: std_logic;
signal s_REG_error: std_logic;
signal s_REG_debug: regfile_arr;
-- MMU connectors
signal s_MMU_input_addr: doubleword;
signal s_MMU_input_data: doubleword;
signal s_MMU_alignment: std_logic_vector(3 downto 0) := "1000"; -- One-hot selection in bytes
signal s_MMU_output_data: doubleword;
signal s_MMU_output_instr: word;
signal s_MMU_error: std_logic_vector(5 downto 0);
signal s_MMU_asynchronous_interrupt: doubleword; -- Signals type of external interrupt in the style of MIP/MIE
signal s_MMU_bad_address: doubleword; -- For faulting addresses, pass back the bad address to the exception handler
signal s_MMU_privilege_mode: std_logic_vector(1 downto 0); -- Expose active privilege mode
signal s_MMU_modify_privilege: std_logic; -- Expose the privilege level for loads and stores.
signal s_MMU_satp: doubleword; -- Expose the supervisor address translation & protection mode
-- Jump and branch connectors
signal s_wb_to_jal: doubleword; -- Connects output of mem/alu wb mux to input of jump mux
signal s_jump_select: std_logic; -- Select from output of mem/alu mux or jump address data
signal s_jump_wdata: doubleword; -- Data representing the jump return address or AUIPC result
signal s_jump_target: doubleword; -- Address of the jump targer
signal s_jump_sext: doubleword; -- Intermediate helper variable for clarity's sake
-- Load/Store connectors
signal s_load_base: doubleword; -- Base address from regfile
signal s_load_offset: doubleword; -- Offset from sext(imm12 value)
signal s_store_base: doubleword; -- Base address from regfile
signal s_store_offset: doubleword; -- Offset from sext(imm12 value)
signal s_load_type : std_logic_vector(7 downto 0); -- Record type so we can properly extend later
signal s_load_dest : reg_t; -- Record rd so we can access it later
signal s_load_wb_data: doubleword; -- Extended data to be written back to regfile
signal fetch: std_logic;
-- Exception handling
signal csr_exceptions: std_logic := '0'; -- in order to act appropriately on CSR exceptions, drive and track them separately
signal exception_offending_instr : doubleword := (others => '0');
-- High-level states of operation (distinct from modes)
type state is (setup, teardown, normal, waiting, exception, resume);
signal curr_state, next_state: state;
-- Control status registers followed by scratch
type CSR_t is array (0 to 64) of doubleword;
signal CSR: CSR_t;
-- Others
signal s_sext_12: doubleword; -- Sign extended immediate value
signal s_sext_20: doubleword; -- Sign extended immediate value
signal waiting_reason: std_logic_vector(2 downto 0); -- If in waiting state, reason determines actions on exit
signal privilege_mode: std_logic_vector(1 downto 0) := MACHINE_MODE;
----------------------------------------------------------------------------------
-- Helper Procedures
----------------------------------------------------------------------------------
-- Handle complicated CSR read behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The value to be read back
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO add in interrupt setting
-- TODO handle cycle and time readings externally
procedure CSR_read(CSR_bits: in std_logic_vector(11 downto 0); value: out doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0); exceptions: inout std_logic) is
begin
-- TODO handle mode fails and offending instruction logging
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
value := CSR(CSR_MSTATUS) and x"000000000000001f";
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
value := CSR(CSR_MSTATUS) and x"00000000000000e0";
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
value := CSR(CSR_MSTATUS) and x"0000000000006000";
end if;
when CSR_ADDR_CYCLE =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and mode = USER_MODE ) then
-- Error if user mode not allowed to read
exceptions := '1';
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and mode = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
exceptions := '1';
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_TIME =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and mode = USER_MODE ) then
-- Error if user mode not allowed to read
exceptions := '1';
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and mode = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
exceptions := '1';
else
-- TODO tie this to external time signal
end if;
when CSR_ADDR_INSTRET =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and mode = USER_MODE ) then
-- Error if user mode not allowed to read
exceptions := '1';
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and mode = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
exceptions := '1';
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_HPMCOUNTER3 | CSR_ADDR_HPMCOUNTER4 | CSR_ADDR_HPMCOUNTER5 | CSR_ADDR_HPMCOUNTER6 | CSR_ADDR_HPMCOUNTER7 |
CSR_ADDR_HPMCOUNTER8 | CSR_ADDR_HPMCOUNTER9 | CSR_ADDR_HPMCOUNTER10 | CSR_ADDR_HPMCOUNTER11 | CSR_ADDR_HPMCOUNTER12 |
CSR_ADDR_HPMCOUNTER13| CSR_ADDR_HPMCOUNTER14 | CSR_ADDR_HPMCOUNTER15 | CSR_ADDR_HPMCOUNTER16 | CSR_ADDR_HPMCOUNTER17 |
CSR_ADDR_HPMCOUNTER18| CSR_ADDR_HPMCOUNTER19 | CSR_ADDR_HPMCOUNTER20 | CSR_ADDR_HPMCOUNTER21 | CSR_ADDR_HPMCOUNTER22 |
CSR_ADDR_HPMCOUNTER23| CSR_ADDR_HPMCOUNTER24 | CSR_ADDR_HPMCOUNTER25 | CSR_ADDR_HPMCOUNTER26 | CSR_ADDR_HPMCOUNTER27 |
CSR_ADDR_HPMCOUNTER28| CSR_ADDR_HPMCOUNTER29 | CSR_ADDR_HPMCOUNTER30 | CSR_ADDR_HPMCOUNTER31 =>
-- From notes: *counteren(x) needs to be checked, where x = 1 << integer(address(4 downto 0))
-- Since this is always a single bit, just convert directly to an integer and use it to index the register
-- Example: hpmcounter17 -> x = 1 << 17 = (0100000000000000000)_2. Or, just use bit 17.
if( (CSR(CSR_SCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and mode = USER_MODE ) then
-- Error if user mode not allowed to read
exceptions := '1';
elsif( (CSR(CSR_MCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and mode = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
exceptions := '1';
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_SSTATUS =>
if(mode = USER_MODE) then
exceptions := '1';
else
if( CSR(CSR_MSTATUS)( 16 downto 15 ) = "11" or CSR(CSR_MSTATUS)( 14 downto 13 ) = "11") then
value := CSR(CSR_MSTATUS) and x"000000000005e122";
else
value := CSR(CSR_MSTATUS) and x"800000000005e122";
end if;
end if;
when CSR_ADDR_SIE =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_MIE) and CSR(CSR_MIDELEG);
end if;
when CSR_ADDR_STVEC =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_STVEC);
end if;
when CSR_ADDR_SCOUNTEREN =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_SCOUNTEREN);
end if;
when CSR_ADDR_SSCRATCH =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_SSCRATCH);
end if;
when CSR_ADDR_SEPC =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_SEPC);
end if;
when CSR_ADDR_SCAUSE =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_SCAUSE);
end if;
when CSR_ADDR_STVAL =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_STVAL);
end if;
when CSR_ADDR_SIP =>
if(mode = USER_MODE) then
exceptions := '1';
else
value := CSR(CSR_MIP) and CSR(CSR_MIDELEG);
end if;
when CSR_ADDR_SATP =>
if(CSR(CSR_MSTATUS)( 20 ) = '1' and not (mode = MACHINE_MODE)) then
-- Error if not in machine mode
exceptions := '1';
else
value := CSR(CSR_SATP);
end if;
when CSR_ADDR_MVENDORID =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when CSR_ADDR_MARCHID =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when CSR_ADDR_MIMPID =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when CSR_ADDR_MHARTID =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when CSR_ADDR_MSTATUS =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MSTATUS);
end if;
when CSR_ADDR_MISA =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MISA);
end if;
when CSR_ADDR_MEDELEG =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MEDELEG);
end if;
when CSR_ADDR_MIDELEG =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MIDELEG);
end if;
when CSR_ADDR_MIE =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MIE);
end if;
when CSR_ADDR_MTVEC =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MTVEC);
end if;
when CSR_ADDR_MCOUNTEREN =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MCOUNTEREN);
end if;
when CSR_ADDR_MSCRATCH =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MSCRATCH);
end if;
when CSR_ADDR_MEPC =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MEPC);
end if;
when CSR_ADDR_MCAUSE =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MCAUSE);
end if;
when CSR_ADDR_MTVAL =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MTVAL);
end if;
when CSR_ADDR_MIP =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := CSR(CSR_MIP);
end if;
when CSR_ADDR_MHPMCOUNTER3 | CSR_ADDR_MHPMCOUNTER4 | CSR_ADDR_MHPMCOUNTER5 | CSR_ADDR_MHPMCOUNTER6 |
CSR_ADDR_MHPMCOUNTER7 | CSR_ADDR_MHPMCOUNTER8 | CSR_ADDR_MHPMCOUNTER9 | CSR_ADDR_MHPMCOUNTER10 |
CSR_ADDR_MHPMCOUNTER11 | CSR_ADDR_MHPMCOUNTER12 | CSR_ADDR_MHPMCOUNTER13 | CSR_ADDR_MHPMCOUNTER14 |
CSR_ADDR_MHPMCOUNTER15 | CSR_ADDR_MHPMCOUNTER16 | CSR_ADDR_MHPMCOUNTER17 | CSR_ADDR_MHPMCOUNTER18 |
CSR_ADDR_MHPMCOUNTER19 | CSR_ADDR_MHPMCOUNTER20 | CSR_ADDR_MHPMCOUNTER21 | CSR_ADDR_MHPMCOUNTER22 |
CSR_ADDR_MHPMCOUNTER23 | CSR_ADDR_MHPMCOUNTER24 | CSR_ADDR_MHPMCOUNTER25 | CSR_ADDR_MHPMCOUNTER26 |
CSR_ADDR_MHPMCOUNTER27 | CSR_ADDR_MHPMCOUNTER28 | CSR_ADDR_MHPMCOUNTER29 | CSR_ADDR_MHPMCOUNTER30 |
CSR_ADDR_MHPMCOUNTER31 =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when CSR_ADDR_MHPMEVENT3 | CSR_ADDR_MHPMEVENT4 | CSR_ADDR_MHPMEVENT5 | CSR_ADDR_MHPMEVENT6 |
CSR_ADDR_MHPMEVENT7 | CSR_ADDR_MHPMEVENT8 | CSR_ADDR_MHPMEVENT9 | CSR_ADDR_MHPMEVENT10 |
CSR_ADDR_MHPMEVENT11 | CSR_ADDR_MHPMEVENT12 | CSR_ADDR_MHPMEVENT13 | CSR_ADDR_MHPMEVENT14 |
CSR_ADDR_MHPMEVENT15 | CSR_ADDR_MHPMEVENT16 | CSR_ADDR_MHPMEVENT17 | CSR_ADDR_MHPMEVENT18 |
CSR_ADDR_MHPMEVENT19 | CSR_ADDR_MHPMEVENT20 | CSR_ADDR_MHPMEVENT21 | CSR_ADDR_MHPMEVENT22 |
CSR_ADDR_MHPMEVENT23 | CSR_ADDR_MHPMEVENT24 | CSR_ADDR_MHPMEVENT25 | CSR_ADDR_MHPMEVENT26 |
CSR_ADDR_MHPMEVENT27 | CSR_ADDR_MHPMEVENT28 | CSR_ADDR_MHPMEVENT29 | CSR_ADDR_MHPMEVENT30 |
CSR_ADDR_MHPMEVENT31 =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
value := zero_word & zero_word;
end if;
when others =>
-- All others not implemented, set trap
exceptions := '1';
end case;
end; -- CSR_read procedure
-- Handle complicated CSR write behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The write value
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO handle cycle and time readings externally
procedure CSR_write(CSR_bits: in std_logic_vector(11 downto 0); value: in doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0); exceptions: inout std_logic) is
begin
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(4 downto 0) := value(4 downto 0); -- Set FP flags passed in
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 5) := value(2 downto 0); -- Set FP rounging mode passed in
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
exceptions := '1';
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 0) := value(7 downto 0); -- Set FP rounging mode and flags passed in
end if;
when CSR_ADDR_SSTATUS =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR(CSR_MSTATUS)( 18 ) := value(18); -- Update Smode portion of MSTATUS
CSR(CSR_MSTATUS)( 16 downto 15 ) := value(16 downto 15);
CSR(CSR_MSTATUS)( 14 downto 13 ) := value(14 downto 13);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 1 ) := value(1);
end if;
when CSR_ADDR_SIE => -- Update Smode interrupts to and of MIE and delegations
if (mode = USER_MODE) then
exceptions := '1';
else
CSR(CSR_MIE)( 12 ) := value(12) and CSR(CSR_MIDELEG)( 12 );
CSR(CSR_MIE)( 9 ) := value(9) and CSR(CSR_MIDELEG)( 9 );
CSR(CSR_MIE)( 7 ) := value(7) and CSR(CSR_MIDELEG)( 7 );
CSR(CSR_MIE)( 5 ) := value(5) and CSR(CSR_MIDELEG)( 5 );
CSR(CSR_MIE)( 3 ) := value(3) and CSR(CSR_MIDELEG)( 3 );
CSR(CSR_MIE)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 );
end if;
when CSR_ADDR_STVEC => -- update STVec to the shifted address in 63:2
if (mode = USER_MODE) then
exceptions := '1';
else
CSR(CSR_STVEC)(63 downto 2) := value(63 downto 2);
end if;
when CSR_ADDR_SCOUNTEREN =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR( CSR_SCOUNTEREN ) := value; -- Pass through new enbale value
end if;
when CSR_ADDR_SSCRATCH =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR( CSR_SSCRATCH ) := value; -- Pass through new scratch value
end if;
when CSR_ADDR_SEPC =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR( CSR_SEPC ) := value; -- Pass through new scratch value
end if;
when CSR_ADDR_SCAUSE =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR( CSR_SCAUSE ) := value; -- Pass through new scratch value
end if;
when CSR_ADDR_STVAL =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR( CSR_STVAL ) := value; -- Pass through new scratch value
end if;
when CSR_ADDR_SIP =>
if (mode = USER_MODE) then
exceptions := '1';
else
CSR(CSR_MIP)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 ); -- Pass through new scratch value
end if;
when CSR_ADDR_SATP =>
if (mode = USER_MODE) then
exceptions := '1';
else
if(CSR(CSR_MSTATUS)(20) = '1') then
exceptions := '1';
elsif( (value(63 downto 60) = "0000") or
(value(63 downto 60) = "1000") or
(value(63 downto 60) = "1001") ) then
-- This won't actually do anything, since we aren't implementing address translations for Smode
CSR(CSR_SATP)(63 downto 60) := value(63 downto 60);
CSR(CSR_SATP)(43 downto 0) := value(43 downto 0);
end if;
end if;
when CSR_ADDR_MSTATUS =>
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
-- update status
if(value(14 downto 13) = "00") then -- if not dirty
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '0';
else
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '1';
end if;
end if;
when CSR_ADDR_MISA => -- Do nothing
if not (mode = MACHINE_MODE) then
exceptions := '1';
end if;
when CSR_ADDR_MEDELEG => -- Update delegation of synchronous exceptions
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MEDELEG ) := value;
end if;
when CSR_ADDR_MIDELEG => -- Update delegation of aynschronous exceptions
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR(CSR_MIDELEG)( 12 ) := value(12);
CSR(CSR_MIDELEG)( 9 ) := value(9);
CSR(CSR_MIDELEG)( 5 ) := value(5);
CSR(CSR_MIDELEG)( 1 ) := value(1);
end if;
when CSR_ADDR_MIE => -- Update enabled exceptions
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR(CSR_MIE)( 12 ) := value(12);
CSR(CSR_MIE)( 9 ) := value(9);
CSR(CSR_MIE)( 7 ) := value(7);
CSR(CSR_MIE)( 5 ) := value(5);
CSR(CSR_MIE)( 3 ) := value(3);
CSR(CSR_MIE)( 1 ) := value(1);
end if;
when CSR_ADDR_MTVEC => -- Update shifted base address for machine mode trap handler
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
-- Note: bit 1 is reserved because reasons
CSR(CSR_MTVEC)(63 downto 2) := value(63 downto 2);
CSR(CSR_MTVEC)( 0 ) := value(0);
end if;
when CSR_ADDR_MCOUNTEREN => -- Pass through new counter enable bit
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MCOUNTEREN ) := value;
end if;
when CSR_ADDR_MSCRATCH => -- Pass through new scratch value
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MSCRATCH ) := value;
end if;
when CSR_ADDR_MEPC => -- Pass through new exception PC
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MEPC ) := value;
end if;
when CSR_ADDR_MCAUSE => -- Pass through new exception cause
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MCAUSE ) := value;
end if;
when CSR_ADDR_MTVAL => -- Pass through address of the bad address for relevant interrupts (store/load misaligned, page fault)
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR( CSR_MTVAL ) := value;
end if;
when CSR_ADDR_MIP => -- Allow Smode timer and software interrupts to be signalled
if not (mode = MACHINE_MODE) then
exceptions := '1';
else
CSR(CSR_MIP)( 5 ) := value(5);
CSR(CSR_MIP)( 1 ) := value(1);
end if;
when CSR_ADDR_MHPMCOUNTER3 => -- Ignore writes
when CSR_ADDR_MHPMCOUNTER4 =>
when CSR_ADDR_MHPMCOUNTER5 =>
when CSR_ADDR_MHPMCOUNTER6 =>
when CSR_ADDR_MHPMCOUNTER7 =>
when CSR_ADDR_MHPMCOUNTER8 =>
when CSR_ADDR_MHPMCOUNTER9 =>
when CSR_ADDR_MHPMCOUNTER10 =>
when CSR_ADDR_MHPMCOUNTER11 =>
when CSR_ADDR_MHPMCOUNTER12 =>
when CSR_ADDR_MHPMCOUNTER13 =>
when CSR_ADDR_MHPMCOUNTER14 =>
when CSR_ADDR_MHPMCOUNTER15 =>
when CSR_ADDR_MHPMCOUNTER16 =>
when CSR_ADDR_MHPMCOUNTER17 =>
when CSR_ADDR_MHPMCOUNTER18 =>
when CSR_ADDR_MHPMCOUNTER19 =>
when CSR_ADDR_MHPMCOUNTER20 =>
when CSR_ADDR_MHPMCOUNTER21 =>
when CSR_ADDR_MHPMCOUNTER22 =>
when CSR_ADDR_MHPMCOUNTER23 =>
when CSR_ADDR_MHPMCOUNTER24 =>
when CSR_ADDR_MHPMCOUNTER25 =>
when CSR_ADDR_MHPMCOUNTER26 =>
when CSR_ADDR_MHPMCOUNTER27 =>
when CSR_ADDR_MHPMCOUNTER28 =>
when CSR_ADDR_MHPMCOUNTER29 =>
when CSR_ADDR_MHPMCOUNTER30 =>
when CSR_ADDR_MHPMCOUNTER31 =>
when CSR_ADDR_MHPMEVENT3 =>
when CSR_ADDR_MHPMEVENT4 =>
when CSR_ADDR_MHPMEVENT5 =>
when CSR_ADDR_MHPMEVENT6 =>
when CSR_ADDR_MHPMEVENT7 =>
when CSR_ADDR_MHPMEVENT8 =>
when CSR_ADDR_MHPMEVENT9 =>
when CSR_ADDR_MHPMEVENT10 =>
when CSR_ADDR_MHPMEVENT11 =>
when CSR_ADDR_MHPMEVENT12 =>
when CSR_ADDR_MHPMEVENT13 =>
when CSR_ADDR_MHPMEVENT14 =>
when CSR_ADDR_MHPMEVENT15 =>
when CSR_ADDR_MHPMEVENT16 =>
when CSR_ADDR_MHPMEVENT17 =>
when CSR_ADDR_MHPMEVENT18 =>
when CSR_ADDR_MHPMEVENT19 =>
when CSR_ADDR_MHPMEVENT20 =>
when CSR_ADDR_MHPMEVENT21 =>
when CSR_ADDR_MHPMEVENT22 =>
when CSR_ADDR_MHPMEVENT23 =>
when CSR_ADDR_MHPMEVENT24 =>
when CSR_ADDR_MHPMEVENT25 =>
when CSR_ADDR_MHPMEVENT26 =>
when CSR_ADDR_MHPMEVENT27 =>
when CSR_ADDR_MHPMEVENT28 =>
when CSR_ADDR_MHPMEVENT29 =>
when CSR_ADDR_MHPMEVENT30 =>
when CSR_ADDR_MHPMEVENT31 =>
when others =>
-- All others not implemented, set trap
exceptions := '1';
end case;
end; -- CSR_write procedure
----------------------------------------------------------------------------------
-- Architecture Begin
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
-- Component instantiations and mapping
----------------------------------------------------------------------------------
myDecode: decode
port map(
instr => s_IM_output_data,
instr_code => s_instr_code,
funct3 => s_functs(15 downto 13),
funct6 => s_functs(12 downto 7),
funct7 => s_functs(6 downto 0),
imm12 => s_imm12,
imm20 => s_imm20,
opcode => s_opcode,
rs1 => s_rs1,
rs2 => s_rs2,
rs3 => s_rs3,
rd => s_rd,
shamt => s_shamt,
csr => s_csr_bits
);
myALU: ALU
port map(
clk => clk,
rst => s_rst,
halt => s_halts(0),
ctrl => s_instr_code,
rs1 => s_REG_rdata1,
rs2 => s_ALU_input2,
shamt => s_shamt,
rout => s_ALU_result,
error => s_ALU_error(2),
overflow => s_ALU_error(1),
zero => s_ALU_error(0)
);
myIM: fence -- MMU writes back instructions and data to core
port map(
clk => clk,
rst => s_rst,
halt => s_halts(2),
ready_input => s_request_IM_in,
ready_output => s_request_IM_out,
output_OK => s_request_IM_outack,
input_OK => s_request_IM_inack,
input_data => s_IM_input_data,
input_address => s_IM_input_addr,
output_data => s_IM_output_data,
output_address => s_IM_output_addr
);
WBMux: mux
port map(
sel => s_WB_select,
zero_port => s_ALU_result,
one_port => s_load_wb_data,
out_port => s_wb_to_jal
);
JumpReturn: mux
port map(
sel => s_jump_select,
zero_port => s_wb_to_jal,
one_port => s_jump_wdata,
out_port => s_REG_wdata
);
ALUMux: mux
port map(
sel => s_ALU_source_select,
zero_port => s_REG_rdata2,
one_port => s_ALU_Imm,
out_port => s_ALU_input2
);
ALUImmMux: mux
port map(
sel => s_ALU_Imm_select,
zero_port => s_sext_12,
one_port => s_sext_20,
out_port => s_ALU_Imm
);
myREG: regfile
port map(
clk => clk,
rst => s_rst,
read_addr_1 => s_REG_raddr1,
read_addr_2 => s_REG_raddr2,
write_addr => s_REG_waddr,
write_data => s_REG_wdata,
halt => s_halts(1),
write_en => s_REG_write,
read_data_1 => s_REG_rdata1,
read_data_2 => s_REG_rdata2,
write_error => s_REG_error,
debug_out => s_REG_debug
);
mySext: sext
port map(
imm12 => s_imm12,
imm20 => s_imm20,
output_imm12 => s_sext_12,
output_imm20 => s_sext_20
);
----------------------------------------------------------------------------------
-- Main Logic
----------------------------------------------------------------------------------
advance_state: process(clk)
begin
if(rising_edge(clk)) then
curr_state <= next_state;
end if;
end process;
process(clk, rst, curr_state)
--s_jump_target, s_jump_sext
variable s_store_offset, s_load_offset, s_load_base, s_store_base: doubleword;
begin
-- Default values reset at every cycle
s_rst <= '0';
s_halts <= "000";
s_MMU_load <= '0';
s_MMU_store <= '0';
-- Always signal that we are ready for a fetch
s_request_IM_in <= '1';
s_request_IM_out <= '1';
--s_request_IM_out <= '0';
if('1' = rst) then
s_jump_target <= (others => '0');
s_rst <= '1';
s_PC_next <= x"0000000090000000";
s_MMU_alignment <= "1000";
next_state <= normal;
--s_PC_next <= (31 => '1', others => '0'); -- base address should be x80000000
elsif(rising_edge(clk)) then
-- Pre-execute interrupt check, only taken if:
-- interrupts are currently enabled
-- machine interrupt enable has matching bits
-- the matching machine interrupt pending bit is set
if( '1' = CSR(CSR_MSTATUS)(3) and (unsigned( CSR(CSR_MIP) and CSR(CSR_MIE) ) > 0)) then
s_halts <= "111";
-- update last instruction handled
exception_offending_instr <= s_IM_output_data;
-- Handle exception logic in the exception state
next_state <= exception;
-- If we saw an ALU error last time
elsif( '1' = CSR(CSR_MSTATUS)(3) and '1' = s_ALU_error(0) and '1' = CSR(CSR_MIE)(2)) then
-- update last instruction handled
exception_offending_instr <= s_IM_output_data;
s_halts <= "111";
next_state <= exception;
-- Asynchronous external interrupt triggered and allowed
elsif( '1' = CSR(CSR_MSTATUS)(3) and (unsigned( CSR(CSR_MIP) and s_MMU_asynchronous_interrupt) > 0)) then
s_halts <= "111";
-- special case store the instruction which has yet to execute
exception_offending_instr <= s_IM_output_data;
-- handle exception logic in te exception state
next_state <= exception;
else
case curr_state is
when setup => -- TODO add code here if CPU needs to stall during come-up
s_halts <= "111";
when teardown => -- TODO add code here if CPU needs to stall during tear-down
s_halts <= "111";
when exception =>
-- Can Supervisor mode handle this?
if( (unsigned(CSR(CSR_MIP) and CSR(CSR_MEDELEG)) > 0) or ( unsigned(s_MMU_asynchronous_interrupt and CSR(CSR_MIDELEG)) > 0 )) then
-- Handling exceptions entails:
-- Store offending instruction:
-- For synchronous internal interrupts, store the offending instruction
-- For asynchronous external interrupts, store what would be the next instruction (one and the same in this case)
CSR(CSR_SEPC) <= exception_offending_instr;
-- Set scauseappropriately depending on the type of exception
if(unsigned( CSR(CSR_MIP) and CSR(CSR_MIDELEG)) > 0) then -- case synchronous exception
-- Mask off disabled interrupts, convert to integer, convert to binary, then de-assert MSB
CSR(CSR_SCAUSE) <= x"7FFFFFFFFFFFFFFF" and std_logic_vector(unsigned(CSR(CSR_MIP) and CSR(CSR_MIDELEG)));
CSR(CSR_STVAL) <= exception_offending_instr;
else
-- Mask off disabled interrupts, convert to integer, convert to binary, then assert MSB
CSR(CSR_SCAUSE) <= x"8000000000000000" or std_logic_vector(unsigned(s_MMU_asynchronous_interrupt and CSR(CSR_MIE) and CSR(CSR_MIDELEG)));
end if;
-- Set mtval based on the type of interrupt
if('1' = (CSR(CSR_MIP)(2) and CSR(CSR_MIDELEG)(2)) ) then
-- illegal instructions store the offending instruction
CSR(CSR_STVAL) <= exception_offending_instr;
elsif(
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 0 ) or -- Case instruction address misaligned
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 1 ) or -- Case instruction access fault
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 4 ) or -- Case load address misaligned
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 5 ) or -- Case load access fault
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 6 ) or -- Case store address misaligned
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 7 ) or -- Case store access fault
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 12 ) or -- Case instruction page fault
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 13 ) or -- Case load page fault
( unsigned(CSR(CSR_SCAUSE)(62 downto 0)) = 15 ) -- Case store page fault
) then
-- Addressing faults store the bad address
CSR(CSR_STVAL) <= s_MMU_bad_address;
else
-- Everything else stores 0
CSR(CSR_STVAL) <= (others => '0');
end if;
-- Disable interrupts (will be explicitly re-enabled later)
CSR(CSR_MSTATUS)(5) <= CSR(CSR_MSTATUS)(1); -- Record previous value
CSR(CSR_MSTATUS)(1) <= '0'; -- Disable interrupts
-- Preserve current operating mode and switch to S mode.
if(privilege_mode = SUPERVISOR_MODE) then
CSR(CSR_MSTATUS)(8) <= '1';
else
CSR(CSR_MSTATUS)(8) <= '0';
end if;
privilege_mode <= SUPERVISOR_MODE;
-- set PCnext to interupt handler address
s_PC_next <= CSR(CSR_STVEC);
else -- Case machine mode must handle
-- Handling exceptions entails:
-- Store offending instruction:
-- For synchronous internal interrupts, store the offending instruction
-- For asynchronous external interrupts, store what would be the next instruction (one and the same in this case)
CSR(CSR_MEPC) <= exception_offending_instr;
-- Set mcauseappropriately depending on the type of exception
if(unsigned(CSR(CSR_MIP)) > 0) then -- case synchronous exception
-- Mask off disabled interrupts, convert to integer, convert to binary, then de-assert MSB
CSR(CSR_MCAUSE) <= x"7FFFFFFFFFFFFFFF" and std_logic_vector(unsigned(CSR(CSR_MIP) and CSR(CSR_MIE)));
CSR(CSR_MTVAL) <= exception_offending_instr;
else
-- Mask off disabled interrupts, convert to integer, convert to binary, then assert MSB
CSR(CSR_MCAUSE) <= x"8000000000000000" or std_logic_vector(unsigned(s_MMU_asynchronous_interrupt and CSR(CSR_MIE)));
end if;
-- Set mtval based on the type of interrupt
if('1' = CSR(CSR_MIP)(2)) then
-- illegal instructions store the offending instruction
CSR(CSR_MTVAL) <= exception_offending_instr;
elsif(
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 0 ) or -- Case instruction address misaligned
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 1 ) or -- Case instruction access fault
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 4 ) or -- Case load address misaligned
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 5 ) or -- Case load access fault
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 6 ) or -- Case store address misaligned
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 7 ) or -- Case store access fault
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 12 ) or -- Case instruction page fault
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 13 ) or -- Case load page fault
( unsigned(CSR(CSR_MCAUSE)(62 downto 0)) = 15 ) -- Case store page fault
) then
-- Addressing faults store the bad address
CSR(CSR_MTVAL) <= s_MMU_bad_address;
else
CSR(CSR_MTVAL) <= (others => '0');
end if;
-- Disable interrupts (will be explicitly re-enabled later)
CSR(CSR_MSTATUS)(7) <= CSR(CSR_MSTATUS)(3); -- Record previous value
CSR(CSR_MSTATUS)(3) <= '0'; -- Disable interrupts
-- Preserve current operating mode and swithch to M mode.
if(privilege_mode = MACHINE_MODE) then
CSR(CSR_MSTATUS)(12 downto 11) <= "11";
elsif(privilege_mode = SUPERVISOR_MODE) then
CSR(CSR_MSTATUS)(12 downto 11) <= "01";
else
CSR(CSR_MSTATUS)(12 downto 11) <= "00";
end if;
privilege_mode <= MACHINE_MODE;
-- set PCnext to interupt handler address
s_PC_next <= CSR(CSR_MTVEC);
end if; -- if supervisor delegated...
s_halts <= "111";
-- clear exceptions vector ? No, rely on interrupt handling code to do so
-- clear csr exceptions bit ? Yes
csr_exceptions <= '0';
when waiting => -- Check waiting conditions, resume when false
-- Waiting conditions
-- Waiting on load value
-- Waiting on store
case waiting_reason is
when "000" => -- case waiting on atomic unit
if('0' = s_ATU_busy) then
next_state <= resume;
end if;
when "001" => -- case waiting on load
if('0' = s_MMU_busy) then
-- route the value to be written back to the regfile
s_wb_select <= '1';
s_REG_waddr <= s_load_dest;
case s_load_type is
when instr_LB =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
else
s_load_wb_data <= ones_word & "111111111111111111111111" & s_MMU_output_data(7 downto 0);
end if;
when instr_LBU =>
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
when instr_LH =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
else
s_load_wb_data <= ones_word & "1111111111111111" & s_MMU_output_data(15 downto 0);
end if;
when instr_LHU =>
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
when instr_LW =>
if('0' = s_MMU_output_data(31)) then
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
else
s_load_wb_data <= ones_word & s_MMU_output_data(31 downto 0);
end if;
when instr_LWU =>
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
when others =>
s_load_wb_data <= s_MMU_output_data;
end case;
next_state <= normal;
end if;
when others => -- if we were waiting on something else, simply switch back to normal when the MMU is ready
if('0' = s_MMU_busy) then
next_state <= normal;
end if;
end case;
when resume => -- Complete action we were waiting on (atomic instructions)
when normal =>
if('1' = s_request_IM_outack) then -- if the current instruction is valid
-- Update PC so we get a new instruction,
-- Note that loads and stores will be taken before fetches
-- Fetch in doubleword increments relative to current PC
s_MMU_alignment <= "1000";
s_PC_curr <= s_PC_next;
s_PC_next <= std_logic_vector((unsigned(s_PC_next) + 4));
end if; -- '1' = s_request ...
if( '1' = s_MMU_busy) then -- Waiting for an indeterminate reason, stall 1 cycle
s_halts <= "111";
else -- if we are not waiting on MMU, do work
case s_opcode is
when ALUW_T => -- Case word, R-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_raddr2 <= s_rs2;
s_REG_waddr <= s_rd;
s_REG_write <= '1';
-- Use rdata2 instead of sign extended immediate
s_ALU_source_select <= '0';
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when ALU_T => -- Case regular, R-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_raddr2 <= s_rs2;
s_REG_waddr <= s_rd;
s_REG_write <= '1';
-- Use rdata2 instead of sign extended immediate
s_ALU_source_select <= '0';
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when ALUIW_T => -- Case word, I-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
s_REG_write <= '1';
-- Use sign extended immediate instead of rdata2
s_ALU_source_select <= '1';
-- use the 20-bit immediate interpretation
s_ALU_Imm_select <= '1';
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when ALUI_T => -- Case regular, I-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
s_REG_write <= '1';
-- Use sign extended immediate instead of rdata2
s_ALU_source_select <= '1';
-- use the 20-bit immediate interpretation
s_ALU_Imm_select <= '1';
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when LOAD_T =>
-- Little endian byte ordering
-- Need to signal MMU: full word, half word, quarter word
-- effective address is sext(regFile[rs1]) + sext(imm12)
case s_instr_code is
when instr_LB =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LB;
when instr_LBU =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LBU;
when instr_LH =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LH;
when instr_LHU =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LHU;
when instr_LW =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LW;
when instr_LWU =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LWU;
when others =>
s_MMU_alignment <= "1000";
s_load_type <= instr_LD;
end case;
s_load_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_load_offset := zero_word & "00000000000000000000" & s_imm12;
else
s_load_offset := ones_word & "11111111111111111111" & s_imm12;
end if;
s_load_dest <= s_rd;
s_MMU_input_addr <= std_logic_vector(signed(s_load_base) + signed(s_load_offset));
s_MMU_load <= '1';
next_state <= waiting;
waiting_reason <= "001";
when STORE_T =>
-- Little endian byte ordering
s_store_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_store_offset := zero_word & "00000000000000000000" & s_imm12;
else
s_store_offset := ones_word & "11111111111111111111" & s_imm12;
end if;
s_MMU_input_addr <= std_logic_vector(signed(s_store_base) + signed(s_store_offset));
case s_instr_code is
when instr_SB =>
s_MMU_input_data <= byte_mask_1 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SH =>
s_MMU_input_data <= byte_mask_2 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SW =>
s_MMU_input_data <= byte_mask_4 and s_REG_debug(to_integer(unsigned(s_rs2)));
when others => -- store doubleword
s_MMU_input_data <= s_REG_debug(to_integer(unsigned(s_rs2)));
end case;
s_MMU_store <= '1';
when BRANCH_T =>
case s_instr_code is
when instr_BEQ =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) = signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BNE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) /= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BLT =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) < signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BGE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) >= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BLTU =>
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) < unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when others => --instr_BGEU
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) >= unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
end case;
when JAL_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm20(19)) then
s_jump_target <= zero_word & "00000000000" & s_imm20 & "0";
else
s_jump_target <= ones_word & "11111111111" & s_imm20 & "0";
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when JALR_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm12(11)) then
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext <= zero_word & "00000000000000000000" & s_imm12;
s_jump_target <= std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) <= '0';
else
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext <= ones_word & "11111111111111111111" & s_imm12;
s_jump_target <= std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) <= '0';
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when AUIPC_T =>
s_jump_select <= '1';
s_REG_waddr <= s_rd;
if('0' = s_imm20(19)) then
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( zero_word & s_imm20 & "000000000000" ))
);
else
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( ones_word & s_imm20 & "000000000000" ))
); end if;
when others =>
-- Do nothing
end case;
end if; -- '1' = s_MMU_busy ...
if('1' = csr_exceptions) then
-- update next state
next_state <= exception;
-- update pending exceptions vector for illegal instruction
CSR(CSR_MIP)(2) <= '1';
end if;
-- update last instruction handled
exception_offending_instr <= s_IM_output_data;
end case;
end if; -- if (unsigned(exceptions) > 0) ...
end if; -- if('1' = rst) ...
end process;
-- Map outbound signals
status <= s_MMU_busy;
MMU_addr_in <= s_MMU_input_addr; -- 64-bits address for load/store
MMU_data_in <= s_MMU_input_data; -- 64-bits data for store
MMU_satp <= (others => '0'); -- Signals address translation privilege
MMU_mode <= privilege_mode; -- Current operating mode (Machine, Supervisor, Etc)
MMU_store <= s_MMU_store; -- High to toggle store
MMU_load <= s_MMU_load; -- High to toggle load
MMU_addr_instr <= s_PC_next; -- Instruction Address (AKA PC)
MMU_alignment <= s_MMU_alignment; -- alignment in bytes
MMU_ready_instr <= s_request_IM_inack; -- signal that PC is valid
reggie <= s_REG_debug;
pc_curr <= s_PC_curr;
-- Map inbound signals
s_IM_input_data <= zero_word & MMU_instr_out;
s_MMU_output_data <= MMU_data_out;
s_MMU_error <= MMU_error;
s_MMU_busy <= MMU_busy;
end Behavioral;
| mit | 61f496f915c20aa91c22b1e115dbd7c6 | 0.445286 | 4.746866 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/UART_TX_CTRL.vhd | 1 | 4,747 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit | 849a273841496e41847bbb6333269958 | 0.550453 | 3.714397 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp/onewire_control.vhd | 1 | 15,117 | -------------------------------------------------------------------------------
--! @file onewire_control.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Control all 1-wire interfaces.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
use work.onewire_idtemp_pkg.all;
--! @brief Entity declaration of onewire_control
entity onewire_control is
generic (
--! System clock frequency in Hz
clk_frequency_g : natural := 40e6;
--! Maximum number of devices on a bus
max_devices_g : positive := 16);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Status and control signals
--! @{
--! Discover devices on the 1-wire bus
discover_i : in std_ulogic;
--! Convert and retrieve temperature values
get_temp_i : in std_ulogic;
--! Busy flag
busy_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! Number of detected devices
device_count_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g + 1)))) - 1 downto 0);
--! Error flag if too many devices are detected
error_too_many_o : out std_ulogic;
--! Enable strong pull-up circuit to provide more current during temperature conversion
strong_pullup_o : out std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Start search algorithm
discover_o : out std_ulogic;
--! Discovered device ID enable
id_en_i : in std_ulogic;
--! Done flag
done_i : in std_ulogic;
--! @}
--! @name Memory interface signals
--! @{
--! Write address
mem_wr_addr_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g * 2)))) - 1 downto 0);
--! Write enable
mem_wr_en_o : out std_ulogic;
--! Data output
mem_wr_data_o : out std_ulogic_vector(63 downto 0);
--! Write done flag
mem_wr_done_i : in std_ulogic;
--! Read address
mem_rd_addr_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g * 2)))) - 1 downto 0);
--! Read enable
mem_rd_en_o : out std_ulogic;
--! Data input
mem_rd_data_i : in std_ulogic_vector(63 downto 0);
--! Data input enable
mem_rd_data_en_i : in std_ulogic;
--! @}
--! @name Bus interface signals
--! @{
--! Send a bus reset command
bus_rst_o : out std_ulogic;
--! Send data bit
bit_send_o : out std_ulogic;
--! The data bit to be sent
bit_o : out std_ulogic;
--! Receive data bit
bit_recv_o : out std_ulogic;
--! The received data bit
bit_i : in std_ulogic;
--! The received data bit enable
bit_en_i : in std_ulogic;
--! Done flag
bit_done_i : in std_ulogic);
--! @}
end entity onewire_control;
--! RTL implementation of onewire_control
architecture rtl of onewire_control is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
--! Time to hold strong pull-up high during conversion
constant t_pullup_c : real := 0.750;
--! Time to recover from strong pull-up
constant t_pullup_recvr_c : real := t_pullup_c + 0.000002;
constant clk_period_c : real := 1.0 / real(clk_frequency_g);
constant cnt_pullup_c : natural := natural(ceil(t_pullup_c / clk_period_c));
constant cnt_pullup_recvr_c : natural := natural(ceil(t_pullup_recvr_c / clk_period_c));
constant lfsr_len_c : natural := lfsr_length(cnt_pullup_recvr_c);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant max_id_c : lfsr_t := lfsr_shift(lfsr_seed_c, mem_wr_data_o'length - 1);
constant max_cmd_c : lfsr_t := lfsr_shift(lfsr_seed_c, cmd_match_c'length - 1);
constant max_pullup_c : lfsr_t := "1110100111110000010100010"; --lfsr_shift(lfsr_seed_c, cnt_pullup_c - 1);
constant max_pullup_recvr_c : lfsr_t := "0101100010000101001011101"; --lfsr_shift(lfsr_seed_c, cnt_pullup_recvr_c - 1);
type state_t is (IDLE, ERASE, DISCOVER, CONVERT, SKIP_COMMAND, CONVERT_COMMAND,
WAIT_CONVERSION, WAIT_RESET, MATCH_COMMAND, GET_ID, SEND_ID, READ_COMMAND,
SCRATCHPAD, SCRATCHPAD_CRC, SAVE_DATA, CHECK_NUM);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
busy : std_ulogic;
done : std_ulogic;
device_count : unsigned(device_count_o'range);
too_many : std_ulogic;
strong_pullup : std_ulogic;
discover : std_ulogic;
mem_addr : unsigned(mem_wr_addr_o'range);
mem_wr_en : std_ulogic;
mem_rd_en : std_ulogic;
crc_reset : std_ulogic;
bus_rst : std_ulogic;
bit_send : std_ulogic;
bit_recv : std_ulogic;
data : std_ulogic_vector(mem_wr_data_o'range);
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
busy => '0',
done => '0',
device_count => to_unsigned(0, device_count_o'length),
too_many => '0',
strong_pullup => '0',
discover => '0',
mem_addr => to_unsigned(0, mem_wr_addr_o'length),
mem_wr_en => '0',
mem_rd_en => '0',
crc_reset => '0',
bus_rst => '0',
bit_send => '0',
bit_recv => '0',
data => (others => '0'));
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
signal crc_valid : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
busy_o <= reg.busy;
done_o <= reg.done;
device_count_o <= std_ulogic_vector(reg.device_count);
error_too_many_o <= reg.too_many;
strong_pullup_o <= reg.strong_pullup;
discover_o <= reg.discover;
mem_wr_addr_o <= std_ulogic_vector(reg.mem_addr);
mem_wr_en_o <= reg.mem_wr_en;
mem_wr_data_o <= reg.data;
mem_rd_addr_o <= std_ulogic_vector(reg.mem_addr);
mem_rd_en_o <= reg.mem_rd_en;
bus_rst_o <= reg.bus_rst;
bit_send_o <= reg.bit_send;
bit_o <= reg.data(reg.data'low);
bit_recv_o <= reg.bit_recv;
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
crc_inst : entity work.onewire_crc
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
reset_i => reg.crc_reset,
data_i => bit_i,
data_en_i => bit_en_i,
valid_o => crc_valid);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, discover_i, get_temp_i, id_en_i, done_i, crc_valid,
mem_wr_done_i, mem_rd_data_i, mem_rd_data_en_i, bit_i, bit_en_i, bit_done_i) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.discover <= init_c.discover;
nxt_reg.mem_wr_en <= init_c.mem_wr_en;
nxt_reg.mem_rd_en <= init_c.mem_rd_en;
nxt_reg.bus_rst <= init_c.bus_rst;
nxt_reg.bit_send <= init_c.bit_send;
nxt_reg.bit_recv <= init_c.bit_recv;
nxt_reg.crc_reset <= init_c.crc_reset;
case reg.state is
when IDLE =>
if discover_i = '1' then
nxt_reg <= init_c;
nxt_reg.busy <= '1';
nxt_reg.mem_wr_en <= '1';
nxt_reg.state <= ERASE;
elsif get_temp_i = '1' then
nxt_reg.busy <= '1';
nxt_reg.bus_rst <= '1';
nxt_reg.mem_addr <= init_c.mem_addr;
nxt_reg.state <= CONVERT;
end if;
when ERASE =>
if mem_wr_done_i = '1' then
if to_integer(reg.mem_addr) < (max_devices_g * 2) - 1 then
nxt_reg.mem_wr_en <= '1';
nxt_reg.mem_addr <= reg.mem_addr + 1;
else
nxt_reg.discover <= '1';
nxt_reg.mem_addr <= init_c.mem_addr;
nxt_reg.state <= DISCOVER;
end if;
end if;
when DISCOVER =>
if id_en_i = '1' then
nxt_reg.device_count <= reg.device_count + 1;
nxt_reg.mem_addr <= reg.mem_addr + 2;
if to_integer(reg.device_count) = max_devices_g then
nxt_reg.too_many <= '1';
end if;
end if;
if done_i = '1' then
nxt_reg.state <= IDLE;
nxt_reg.busy <= '0';
nxt_reg.done <= '1';
end if;
when CONVERT =>
if bit_done_i = '1' then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_skip_c;
nxt_reg.state <= SKIP_COMMAND;
end if;
when SKIP_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_convert_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= CONVERT_COMMAND;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when CONVERT_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.strong_pullup <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= WAIT_CONVERSION;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when WAIT_CONVERSION =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_pullup_c then
nxt_reg.strong_pullup <= '0';
end if;
if reg.lfsr = max_pullup_recvr_c then
nxt_reg.bus_rst <= '1';
nxt_reg.state <= WAIT_RESET;
end if;
when WAIT_RESET =>
if bit_done_i = '1' then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_match_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= MATCH_COMMAND;
end if;
when MATCH_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.mem_rd_en <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= GET_ID;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when GET_ID =>
if mem_rd_data_en_i = '1' then
if mem_rd_data_i(7 downto 0) = code_ds18b20_c then
nxt_reg.data <= mem_rd_data_i;
nxt_reg.bit_send <= '1';
nxt_reg.state <= SEND_ID;
else
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.state <= CHECK_NUM;
end if;
end if;
when SEND_ID =>
if bit_done_i = '1' then
if reg.lfsr = max_id_c then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_read_sp_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= READ_COMMAND;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when READ_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.bit_recv <= '1';
nxt_reg.crc_reset <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= SCRATCHPAD;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SCRATCHPAD =>
if bit_en_i = '1' then
nxt_reg.data <= bit_i & reg.data(reg.data'high downto reg.data'low + 1);
if reg.lfsr = max_id_c then
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= SCRATCHPAD_CRC;
else
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SCRATCHPAD_CRC =>
if bit_en_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.state <= SAVE_DATA;
else
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SAVE_DATA =>
if crc_valid = '0' then
nxt_reg.data <= (others => '1');
end if;
nxt_reg.mem_wr_en <= '1';
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.state <= CHECK_NUM;
when CHECK_NUM =>
if reg.mem_addr < (max_devices_g * 2) - 1 then
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.bus_rst <= '1';
nxt_reg.state <= WAIT_RESET;
else
nxt_reg.state <= IDLE;
nxt_reg.busy <= '0';
nxt_reg.done <= '1';
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | 7b934c1fc606512a40cb255ed67ad2e3 | 0.475425 | 3.485589 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/keyboard.vhd | 1 | 2,172 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
ARCHITECTURE a OF keyboard IS
SIGNAL INCNT : std_logic_vector(3 downto 0);
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
SIGNAL READ_CHAR : std_logic;
SIGNAL INFLAG, ready_set : std_logic;
SIGNAL keyboard_clk_filtered : std_logic;
SIGNAL filter : std_logic_vector(7 downto 0);
BEGIN
PROCESS (read, ready_set)
BEGIN
IF read = '1' THEN scan_ready <= '0';
ELSIF ready_set'EVENT and ready_set = '1' THEN
scan_ready <= '1';
END IF;
END PROCESS;
--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
Clock_filter: PROCESS
BEGIN
WAIT UNTIL clock_25Mhz'EVENT AND clock_25Mhz= '1';
filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
filter(7) <= keyboard_clk;
IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
ELSIF filter= "00000000" THEN keyboard_clk_filtered <= '0';
END IF;
END PROCESS Clock_filter;
--This process reads in serial data coming from the terminal
PROCESS
BEGIN
WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
IF RESET='1' THEN
INCNT <= "0000";
READ_CHAR <= '0';
ELSE
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
READ_CHAR<= '1';
ready_set<= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1;
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
SHIFTIN(8) <= KEYBOARD_DATA;
ready_set <= '0';
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN(7 DOWNTO 0);
READ_CHAR <='0';
ready_set <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
| mit | 35f15a2a3b9a81946272d01681a5cf3c | 0.605893 | 3.170803 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/MMU.vhd | 1 | 33,423 | ----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out word; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end MMU;
architecture Behavioral of MMU is
-- Components
component ram_controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
write, read: in STD_LOGIC;
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(63 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end component;
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
component SPIFlashModule is
port(clk, reset, io_flash_en, io_flash_write, io_read_id: in std_logic;
io_quad_io: in std_logic_vector(3 downto 0);
io_flash_addr: in std_logic_vector(23 downto 0);
io_flash_data_in: in std_logic_vector(31 downto 0);
io_flash_data_out: out std_logic_vector(31 downto 0);
io_state_to_cpu: out std_logic_vector(11 downto 0);
io_sck_gate, io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: out std_logic);
end component;
constant ROM_period : integer := 150;
type instsmem is array(0 to 100) of word;
signal instr_mem: instsmem := (others => (others => '0'));
signal ROM_mem: instsmem := (
0 => x"00001137",
1 => x"8071011b",
2 => x"01411113",
3 => x"0040006f",
4 => x"01300793",
5 => x"01b79793",
6 => x"00100713",
7 => x"00e79023",
8 => x"098017b7",
9 => x"00000697",
10 => x"09468693",
11 => x"02100713",
12 => x"00479793",
13 => x"00100593",
14 => x"0047c603",
15 => x"0ff67613",
16 => x"fe060ce3",
17 => x"00e781a3",
18 => x"00b782a3",
19 => x"00168693",
20 => x"0006c703",
21 => x"fe0712e3",
22 => x"09801737",
23 => x"01300513",
24 => x"00100693",
25 => x"00471713",
26 => x"00100593",
27 => x"01b51513",
28 => x"00174783",
29 => x"0ff7f793",
30 => x"fe078ce3",
31 => x"00074603",
32 => x"0016869b",
33 => x"03069693",
34 => x"00b70123",
35 => x"0306d693",
36 => x"0ff67613",
37 => x"00d51023",
38 => x"00474783",
39 => x"0ff7f793",
40 => x"fe078ce3",
41 => x"00c701a3",
42 => x"00b702a3",
43 => x"fc5ff06f",
46 => x"45212121",
47 => x"204F4843",
48 => x"56524553",
49 => x"45522121",
50 => x"0000A021",
others => (others => '0'));
-- SPI signals
signal io_flash_en: std_logic;
signal io_flash_write: std_logic;
signal io_quad_io: std_logic_vector(3 downto 0);
signal io_flash_addr: std_logic_vector(23 downto 0);
signal io_flash_data_in: std_logic_vector(31 downto 0);
signal io_flash_data_out: std_logic_vector(63 downto 0);
signal io_read_id: std_logic;
signal io_state_to_cpu: std_logic_vector(11 downto 0);
signal io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: std_logic;
signal io_srl, io_cr : std_logic_vector(7 downto 0);
signal io_sckgate: std_logic;
signal io_rst: std_logic;
type MMU_state is (idle, loading, storing, fetching, decode_state,page_walk,loading_ram_page_walk, loading_ram, loading_rom, done_uart_rx, done_uart_tx, storing_ram);
signal curr_state: MMU_state := idle;
signal next_state: MMU_state := idle;
signal paused_state : MMU_state := idle; --Bit of a misnomer, this is
signal LED_reg: std_logic_vector(15 downto 0);
-- RAM signals
signal w_en: std_logic := '0';
signal RAM_en, ROM_en: std_logic := '0';
type RAM_state is (idle, read_low, read_low_mid, read_upper_mid, read_upper,write_low, write_low_mid, write_upper_mid, write_upper, done);
signal RAM_curr_state : RAM_state := idle;
signal RAM_next_state : RAM_state := idle;
signal RAM_masks: std_logic_vector(7 downto 0);
signal RAM_timeout_counter: integer:= 0;
signal RAM_data_in: std_logic_vector(15 downto 0);
signal RAM_data_out: std_logic_vector(15 downto 0);
signal RAM_address_in: std_logic_vector(26 downto 0);
signal RAM_lb, RAM_ub: std_logic := '1';
signal s_RAM_data_out: doubleword := (others => '0'); -- The register holding the ram doubleword
signal ROM_done, RAM_done: std_logic := '0';
signal BRAM_toggle : std_logic_vector(1 downto 0) := "00";
--32 Bits acceses for ROM, either, too slow
type ROM_state is (idle, reading_lower, reading_higher, done);
signal ROM_curr_state : ROM_state := idle;
signal ROM_next_state : ROM_state := idle;
signal gated_clk: std_logic := '0';
signal s_ROM_data_out: doubleword := (others => '0'); --Register holding the rom doubleword
signal ROM_address_in : std_logic_vector(23 downto 0);
signal s_ROM_done: std_logic;
-- UART out data signal, for reading UART registers
signal ROM_Counter: integer := 0;
signal UART_out: STD_LOGIC_VECTOR(7 downto 0);
signal UART_toggle : std_logic := '0';
signal SATP_mode: std_logic_vector(63 downto 0) := (others => '0');
signal SATP_PPN: std_logic_vector(63 downto 0) := (others => '0');
signal s_internal_data : std_logic_vector(63 downto 0);
signal s_internal_address: doubleword;
signal clk_100, clk_200, clk_25, locked: std_logic;
signal page_address_in: doubleword := (others => '0');
signal uart_data_in, uart_data_out: std_logic_vector(7 downto 0);
signal uart_data_available, uart_ready: std_logic;
signal uart_reset_read, uart_send: std_logic;
signal UART_data: doubleword;
signal m_timer: integer := 0;
Type PAGE_WALK_STATE is (idle,level_i_read, level_i_decode, done);
signal PAGE_WALK_next_state, PAGE_WALK_current_state: PAGE_WALK_STATE := idle;
signal s_page_walk,page_walk_request_read, page_walk_done: std_logic := '0';
signal page_walk_address_out, page_address_final: doubleword;
signal Intermitent_Address_In: doubleword;
signal addr_in_latch: doubleword;
-- Debugging
signal s_debugging_out: std_logic_vector(5 downto 0);
signal qd: std_logic_vector(3 downto 0);
signal gated_clock, clock_gate: std_logic;
signal io_sck_gate: std_logic;
begin
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => clk_100,
clk_200MHz_o => clk_200,
clk_25MHz_o => clk_25,
locked => locked
);
myRAMController: ram_controller port map
(
clk_200 => clk_200,
clk_100 => clk_100,
rst => rst,
data_in => RAM_data_in,
data_out => RAM_data_out,
mask_lb => RAM_lb,
mask_ub => RAM_ub,
done => RAM_done,
write => w_en,
read => RAM_en,
contr_addr_in => RAM_address_in,
ddr2_addr => ddr2_addr ,
ddr2_ba => ddr2_ba ,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p ,
ddr2_ck_n => ddr2_ck_n ,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
myROMController: ROM_controller_SPI port map(clk_25 => clk_25, rst => io_rst, read =>io_flash_en,
address_in => ROM_address_in, data_out => io_flash_data_out,
si_i =>io_SI, wp => io_WP, si_t => io_tri_si, wp_t => io_tri_wp,
cs_n => io_cs, qd => qd, done =>s_ROM_done);
--myROMController: SPIFlashModule port map(
-- clk => clk_25, reset => io_rst, io_flash_en => io_flash_en, io_flash_write => io_flash_write, io_read_id => io_read_id,
-- io_quad_io => qd, io_flash_addr => ROM_address_in, io_flash_data_in => io_flash_data_in,
-- io_flash_data_out => io_flash_data_out, io_state_to_cpu => io_state_to_cpu,
-- io_sck_gate => io_sckgate, io_SI => io_SI, io_WP => io_WP, io_tri_si => io_tri_si, io_tri_wp => io_tri_wp, io_cs => io_cs,
-- io_ready => io_ready);
cs_n <= io_cs;
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => CLK,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
-- Advance state
STATE_ADVANCE: process(clk, rst, RAM_done, ROM_done)
begin
if('1' = rst) then
curr_state <= idle;
ROM_curr_state <= idle;
RAM_curr_state <= idle;
PAGE_WALK_current_state <= idle;
m_timer <= 0;
elsif(rising_edge(clk)) then
curr_state <= next_state;
RAM_curr_state <= RAM_next_state;
ROM_curr_state <= ROM_next_state;
PAGE_WALK_current_state <= PAGE_WALK_next_state;
m_timer <= m_timer + 1;
end if;
end process;
MMU_FSM: process(clk, rst)
-- variable s_internal_address: doubleword := (others => '0'); --Realized Physical Address
-- variable paused_state: MMU_state; -- When we find the mode from SATP, we resume from the state saved here
begin
if rst = '1' then
s_internal_address <= (others => '0');
instr_out <= (others => '0');
error <= (others => '0');
io_flash_write <= '0';
io_read_id <= '0';
next_state <= idle;
busy <= '0';
BRAM_toggle <= "11";
LED <= (others => '0');
UART_data <= (others => '0');
data_out <= (others => '0');
elsif(rising_edge(clk)) then
busy <= '1';
next_state <= curr_state;
case curr_state is
-- Idling by like the leech you are MMU arent U
when idle =>
busy <= '1';
UART_toggle <= '0';
s_debugging_out <= "000000";
--s_internal_address <= addr_in;
uart_reset_read <= '0';
uart_send <= '0';
if(load = '1') then
next_state <= decode_state;
paused_state <= loading;
s_internal_address <= addr_in;
elsif(store = '1') then
next_state <= decode_state;
paused_state <= storing;
s_internal_address <= addr_in;
elsif(ready_instr = '1') then
next_state <= decode_state;
s_internal_address <= addr_instr;
paused_state <= fetching;
else
busy <= '0';
end if;
-- Figure out what state are we at
when decode_state =>
s_debugging_out <= "000001";
case satp_mode(3 downto 0) is
when x"0" => -- No translation is assumed
next_state <= paused_state;
when others =>
next_state <= page_walk; --SV39 is assumed whenever anything else is written, no SV48 shenanigans
end case;
-- Walk the thing blue page walk line
when page_walk =>
s_debugging_out <= "000010";
s_page_walk <= '1'; --We enable the page walk process
if(page_walk_done = '1') then --Page walk is done
s_internal_address <= page_walk_address_out; -- We assign the newly discovered address
next_state <= paused_state; --Resume wherever we left off matey
elsif(page_walk_request_read = '1') then
RAM_en <= '1';
end if;
-- Intermediate fetching state, just check if there is any misalignment errors
when fetching =>
busy <= '1';
s_debugging_out <= "000011";
--Fetches have to be aligned
if(unsigned(s_internal_address) mod 4 > 0) then
error(4) <= '1'; -- Misaligned error, geback geback
next_state <= idle;
elsif( s_internal_address(31 downto 16) = x"0000" ) then
next_state <= idle;
instr_out <= instr_mem(to_integer(unsigned(addr_instr(31 downto 0)))/4); --Block RAM access
else
--s_internal_address <= std_logic_vector(unsigned(addr_instr)/2);
next_state <= loading; --Loading instructions from elsewhere
end if;
-- Loading states
when loading =>
s_debugging_out <= "000100";
if(s_internal_address(31 downto 16) = x"0000" ) then --BRAM
next_state <= idle; --Instruction already goes out here, so no need to do anything,
-- We do this to preserve the instr_out port, even though it's really not necesary.
elsif(s_internal_address(31 downto 16) = x"9801") then --UART Registers
next_state <= idle; -- By default go to idle
UART_toggle <= '1';
case s_internal_address(3 downto 0) is
when X"0" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_in;
when X"1" => data_out <= zero_word & zero_word(31 downto 1) & uart_data_available;
when X"2" => data_out <= zero_word & zero_word(31 downto 1) & uart_reset_read;
when X"3" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_out;
when X"4" => data_out <= zero_word & zero_word(31 downto 1) & uart_ready;
when X"5" => data_out <= zero_word & zero_word(31 downto 1) & uart_send;
when others => NULL;
end case;
elsif(s_internal_address(31 downto 24) = x"98") then --LEDS Registers
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock Register
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"9") then --ROM
next_state <= loading_rom;
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= loading_ram;
else
next_state <= idle;
end if;
-- Special load cases
when loading_rom =>
s_debugging_out <= "000101";
ROM_en <= '1';
if(ROM_counter > (2 * ROM_period)) then
ROM_en <= '0';
if(paused_state = fetching) then
instr_out <= s_ROM_data_out(31 downto 0);
else
data_out <= s_ROM_data_out;
end if;
next_state <= idle;
end if;
when loading_ram =>
s_debugging_out <= "000110";
RAM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= s_RAM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
-- Stores and such
when storing =>
s_debugging_out <= "000111";
next_state <= idle; -- By default go back
if(addr_in(31 downto 16) = x"9801") then --UART
case addr_in(3 downto 0) is
when X"0" => NULL; -- Nothing here really, why would you write to buffer in?
when X"1" => NULL; -- Why?
when X"2" => uart_reset_read <= '1';
next_state <= done_uart_rx;
when X"3" => uart_data_out <= data_in(7 downto 0);
when X"4" => NULL; -- No no no write
when X"5" => uart_send <= '1'; -- Assuming if you are writing is to send something
next_state <= done_uart_tx; -- After writing to this register we reset it automatically
when others => UART_data <= (others => '0');
end case;
elsif(addr_in(31 downto 24) = x"98") then --LEDS
LED <= data_in(15 downto 0) OR data_in(31 downto 16);
next_state <= idle;
elsif(addr_in(31 downto 24) = x"97") then --m_clock
next_state <= idle;
-- elsif(addr_in(31 downto 28) = x"9") then --ROM
-- next_state <= idle; --Can't write to ROM, I mean you could, but hwhy? Don't write to ROM
elsif(addr_in(31 downto 28) = x"8") then --RAM
next_state <= storing_ram;
end if;
-- Special stores section
when storing_ram =>
s_debugging_out <= "001000";
w_en <= '1';
if(RAM_done = '1') then
w_en <= '0';
next_state <= idle;
end if;
-- Special done states, to reset whatever needs to be reset
when done_uart_tx =>
uart_send <= '0';
if(uart_ready = '0') then
next_state <= done_uart_tx;
else
next_state <= idle;
end if;
when done_uart_rx =>
uart_reset_read <= '0';
next_state <= idle;
when others =>
end case;
end if;
end process;
-- Walk the page
PAGE_WALK_FSM: process(clk, rst, s_page_walk)
variable level: Integer := 0;
begin
if(rst = '1') then
elsif(rising_edge(clk)) then
PAGE_WALK_next_state <= PAGE_WALK_current_state;
case PAGE_WALK_current_state is
when idle =>
if(s_page_walk = '1') then
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & addr_in(31 downto 22) & "00";--SATP PPN will give us the root page table location
PAGE_WALK_next_state <= level_i_read;
level := 0; --Start at level 0
end if;
when level_i_read =>
if(level < 3) then
page_walk_request_read <= '1';
if(RAM_done = '1') then
level := level + 1;
PAGE_WALK_next_state <= level_i_decode;
end if;
else
--Raise exception here
--More levels than 3
PAGE_WALK_next_state <= done;
end if;
when level_i_decode =>
PAGE_WALK_next_state <= idle;
if(s_RAM_data_out(0) = '0') then --Invalid PTE Raise the roof
NULL;
elsif(s_RAM_data_out(1) = '0' and s_RAM_data_out(7) = '1') then -- Not Valid and Dirty
NULL;
elsif(s_RAM_data_out(1) = '1' or s_RAM_data_out(3) = '1') then --So far this address is final
-- Check if the PTE is in user mode and we are in user mode
if(mode = "00" and s_RAM_data_out(4) = '1') then
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
-- If the PTE U bit is '0' and we are in Supervisor mode, it's still good
-- We leave this separate in case other actions need to happen in S mode
elsif(mode = "01" and s_RAM_data_out(4) = '0') then
-- If PTE A is 0 or PTE D is 0 and we are storing, then we could raise an exception
-- or set the bits to 1 ourselves
if(s_RAM_data_out(6) = '0' or (paused_state = storing and s_RAM_data_out(7) = '0')) then
-- Raise exception
end if;
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
else
page_walk_next_state <= idle;
--Raise exception when the user has no permission to access this PTE
end if;
page_walk_done <= '1';
else -- We still have to dig deeper m8
page_walk_next_state <= level_i_read;
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & s_internal_address(31 downto 22) & "00";
end if;
when done =>
PAGE_WALK_next_state <= idle;
end case;
end if;
end process;
--busy <= '0' when curr_state = idle else '1';
-- Z high impedance
dq(0) <= 'Z' when io_tri_si = '1' else io_SI;
dq(1) <= 'Z';
dq(2) <= 'Z' when io_tri_wp = '1' else io_WP;
dq(3) <= 'Z';
qd(0) <= dq(0) when io_tri_si = '1' else 'Z';
qd(1) <= dq(1);
qd(2) <= dq(2) when io_tri_wp = '1' else 'Z';
qd(3) <= dq(3);
gated_clock <= '0' when gated_clk = '1' else not(clk_25);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 10.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => gated_clock, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);
-- ROM SPI Clock Generation
ROM_CLK: process(clk_25, rst) begin
if(rst = '1') then
gated_clk <= '1';
elsif(rising_edge(clk_25)) then
if (io_cs = '0') then
gated_clk <= '0';
else
gated_clk <= '1';
end if;
end if;
end process;
---- ROM State Machine
---- To enable rom set ROM_en high
---- Will wait for 600 cycles and give back a 64 bit word
ROM_FSM: process(clk,rst)
begin
if(rst = '1') then
io_rst <= '1';
ROM_next_state <= idle;
elsif(rising_edge(clk)) then
if(ROM_curr_state /= idle) then
ROM_counter <= ROM_counter + 1; -- Wait a good amount of time to let the device react
end if;
ROM_next_state <= ROM_curr_state;
case ROM_curr_state is
when idle =>
ROM_next_state <= idle;
ROM_counter <= 0;
io_rst <= '0';
if(ROM_en = '1') then
ROM_done <= '0';
--io_rst <= '0';
ROM_address_in <= s_internal_address(23 downto 0); --24 Bits in
ROM_next_state <= reading_lower;
end if;
when reading_lower =>
ROM_next_state <= reading_lower;
io_flash_en <= '1';
if(ROM_counter > (2 * ROM_period)) then
s_ROM_data_out <= io_flash_data_out;
ROM_next_state <= done;
--ROM_address_in <= std_logic_vector(unsigned(s_internal_address(23 downto 0)) + 4); --24 Bits in
end if;
when reading_higher =>
when done =>
ROM_done <= '1';
if(ROM_en <= '0') then
ROM_next_state <= idle;
end if;
io_rst <= '1';
end case;
end if;
end process;
-- RAM State Machine
-- For reading from RAM, the ideal waiting time is of 230 ns
-- For writing into RAM, the ideal waiting time is of 270 ns
-- To make things easier we use 300 ns for both cases.
RAM_FSM: process(clk, RAM_en, w_en)
variable RAM_counter :integer := 0;
begin
if(rising_edge(clk)) then
if(RAM_curr_state /= idle) then
RAM_counter := RAM_counter + 1;
else
RAM_counter := 0;
end if;
RAM_next_state <= RAM_curr_state;
-- Forget about it
-- If for whatever reason we take long than
-- 1200 cycles, timeout and throw some error
if(RAM_timeout_counter >= 1200) then
RAM_next_state <= idle;
else
case RAM_curr_state is
-- Idle state, read before write
when idle =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_en = '1') then
RAM_next_state <= read_low;
elsif(w_en = '1') then
RAM_next_state <= write_low;
end if;
-- Load States
when read_low =>
if(RAM_counter > 30) then
s_RAM_data_out(15 downto 0) <= RAM_data_out;
RAM_next_state <= read_low_mid;
RAM_counter := 0;
end if;
when read_low_mid =>
if(RAM_counter > 30) then --Valid Data
s_RAM_data_out(31 downto 16) <= RAM_data_out;
RAM_next_state <= read_upper_mid;
RAM_counter := 0;
end if;
when read_upper_mid =>
if(RAM_counter > 30) then
s_RAM_data_out(47 downto 32) <= RAM_data_out;
RAM_next_state <= read_upper;
RAM_counter := 0;
end if;
when read_upper =>
if(RAM_counter > 30) then
s_RAM_data_out(63 downto 48) <= RAM_data_out;
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- Store States (LSB first)
-- Bytes 1 and 2
when write_low =>
--Alignment 0001 means Byte-wise access
if(alignment(0) = '1') then
RAM_ub <= '0'; --Disable the upper byte from controller
end if;
if(RAM_counter > 30) then
if(alignment(0) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_low_mid;
end if;
RAM_counter := 0;
-- Alignment 0100 means Upper Word access
elsif(alignment(2) = '1') then
RAM_counter := 0;
RAM_next_state <= write_upper_mid;
end if;
-- Byte 3 and 4
when write_low_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then --Valid Data
-- Alignment 0010 is Lower Word access
if(alignment(1) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_upper_mid;
RAM_counter := 0;
end if;
end if;
-- Bytes 5 and 6
when write_upper_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= write_upper;
RAM_counter := 0;
end if;
when write_upper =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- We are done here
when others =>
RAM_next_state <= idle;
end case;
end if;
end if;
end process;
-- Latches the last obtained datas (dati, datum? datae?)
--LAST_OBTAINED_DATA: process(clk,rst, UART_toggle) begin
-- if(rst = '1') then
-- data_out <= (others => '0');
-- elsif(rising_edge(clk)) then
-- if(RAM_curr_state = done) then
-- data_out <= s_RAM_data_out;
-- elsif(ROM_curr_state = done) then
-- data_out <= s_ROM_data_out;
-- elsif(UART_toggle = '1') then
-- data_out(7 downto 0) <= UART_data(7 downto 0);
-- data_out(63 downto 8) <= (others => '0');
-- end if;
-- end if;
--end process;
-- Muxes for addresses and data
-- Intermitent address is internal RAM address, whenever we need to use the RAM
-- to access something else, we will make use of this intermitent_address_in signal
Intermitent_Address_In <= addr_in when s_page_walk = '0' else page_address_in;
s_internal_data <= data_in; --For the moment this is right
-- Might change this to sequential logic if needed, I don't think it necessary
RAM_address_in <= std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 0) when RAM_curr_state = idle or RAM_curr_state = read_low or RAM_curr_state = write_low else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 2) when RAM_curr_state = read_low_mid or RAM_curr_state = write_low_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 4) when RAM_curr_state = read_upper_mid or RAM_curr_state = write_upper_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 6) when RAM_curr_state = read_upper or RAM_curr_state = write_upper
else (others => '0');
RAM_data_in <= s_internal_data(15 downto 0 ) when RAM_curr_state = idle or RAM_curr_state = write_low else
s_internal_data(31 downto 16) when RAM_curr_state = write_low_mid else
s_internal_data(47 downto 32) when RAM_curr_state = write_upper_mid else
s_internal_data(63 downto 48) when RAM_curr_state = write_upper else
(others => '0');
-- The CSR telling us where the page table start
SATP_mode(3 downto 0) <= satp(63 downto 60);
SATP_PPN(43 downto 0) <= satp(43 downto 0);
end Behavioral;
| mit | b0ecc6f340a3787aeda4678886218a13 | 0.544356 | 3.382895 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/sim/CoreDataSim.vhd | 1 | 7,796 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:36:20 08/28/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Google Drive/mTC/svn/src/Ethernet/General/sim/IPv4Test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4Tx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
use work.Eth1000BaseXPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CoreDataSim IS
END CoreDataSim;
ARCHITECTURE behavior OF CoreDataSim IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4Tx
PORT(
ethTxClk : IN std_logic;
ethTxRst : IN std_logic;
ipPacketLength : IN std_logic_vector(15 downto 0);
ipPacketId : IN std_logic_vector(15 downto 0);
ipMoreFragments : IN std_logic;
ipFragOffset : IN std_logic_vector(12 downto 0);
ipProtocol : IN std_logic_vector(7 downto 0);
ipSrcAddr : IN IpAddrType;
ipDstAddr : IN IpAddrType;
ipData : IN std_logic_vector(31 downto 0);
ipDataValid : IN std_logic;
ipDataReady : OUT std_logic;
ethTxDataIn : OUT std_logic_vector(7 downto 0);
ethTxDataValid : OUT std_logic;
ethTxDataLastByte : OUT std_logic;
ethTxDataReady : IN std_logic
);
END COMPONENT;
--Inputs
signal ethClk125 : std_logic := '0';
signal ethClk125Rst : std_logic := '0';
signal ethClk62 : std_logic := '0';
signal ethClk62Rst : std_logic := '0';
signal ethCoreMacAddr : MacAddrType := MAC_ADDR_DEFAULT_C;
signal ethCoreIpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal phyRxLaneIn : EthRxPhyLaneInType;
signal phyTxLaneOut : EthTxPhyLaneOutType;
signal dummyPhyRxLaneIn : EthRxPhyLaneInType;
signal dummyPhyTxLaneOut : EthTxPhyLaneOutType;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
-- User Data signals
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl := '0';
signal tpDataReady : sl;
-- Clock period definitions
constant ethClk125_period : time := 8 ns;
constant ethClk62_period : time := 16 ns;
constant GATE_DELAY_C : time := 1 ns;
BEGIN
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_Eth1000BaseXCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr),
udpPorts => (0 => x"07D0"), --x7D0 = 2000
-- Data to/from GT
phyRxData => phyRxLaneIn,
phyTxData => phyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData),
userTxDataValid => (0 => tpDataValid),
userTxDataLast => (0 => tpDataLast),
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
U_TpGenTx : entity work.TpGenTx
generic map (
NUM_WORDS_G => 1000,
WAIT_CYCLES_G => 5,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst or not(ethAutoNegDone),
-- Connection to user logic
userTxData => tpData,
userTxDataValid => tpDataValid,
userTxDataLast => tpDataLast,
userTxDataReady => tpDataReady
);
--------------------------------
-- DummyCore Ethernet Interface --
--------------------------------
U_DummyCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr),
udpPorts => (0 => x"07D0"), --x7D0 = 2000
-- Data to/from GT
phyRxData => dummyPhyRxLaneIn,
phyTxData => dummyPhyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData),
userTxDataValid => (0 => tpDataValid),
userTxDataLast => (0 => tpDataLast),
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
-- Match up B TX to A RX
phyRxLaneIn.data <= dummyPhyTxLaneOut.data;
phyRxLaneIn.dataK <= dummyPhyTxLaneOut.dataK;
phyRxLaneIn.dispErr <= (others => '0');
phyRxLaneIn.decErr <= (others => '0');
-- Match up A TX to B RX
dummyPhyRxLaneIn.data <= phyTxLaneOut.data;
dummyPhyRxLaneIn.dataK <= phyTxLaneOut.dataK;
dummyPhyRxLaneIn.dispErr <= (others => '0');
dummyPhyRxLaneIn.decErr <= (others => '0');
-- Clock process definitions
ethClk125_process : process
begin
ethClk125 <= '0';
wait for ethClk125_period/2;
ethClk125 <= '1';
wait for ethClk125_period/2;
end process;
ethClk62_process : process
begin
ethClk62 <= '0';
wait for ethClk62_period/2;
ethClk62 <= '1';
wait for ethClk62_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ethClk125Rst <= '1';
ethClk62Rst <= '1';
wait for 100 ns;
ethClk125Rst <= '0';
ethClk62Rst <= '0';
wait for ethClk125_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-2.1 | 4a8556b090c279b0ec611fb32d8468f4 | 0.549513 | 4.467622 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/sid_voice.vhd | 1 | 5,109 | ----------------------------------------------------------------------------------
--
-- Generate a single SID voice
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sid_voice is port (
clk1M : in std_logic;
freq : in unsigned (15 downto 0);
pw : in unsigned (11 downto 0);
wvfm : in std_logic_vector (3 downto 0);
test : in std_logic;
rmod : in std_logic;
sync : in std_logic;
gate : in std_logic;
enva : in unsigned (3 downto 0);
envd : in unsigned (3 downto 0);
envs : in unsigned (3 downto 0);
envr : in unsigned (3 downto 0);
envo : out unsigned (7 downto 0);
osco : out unsigned (7 downto 0);
uout : out unsigned (7 downto 0)
);
end sid_voice;
architecture sid_voice_impl of sid_voice is
subtype u8 is unsigned (7 downto 0);
subtype byte is std_logic_vector (7 downto 0);
subtype u9 is unsigned (8 downto 0);
subtype u12 is unsigned (11 downto 0);
subtype word is std_logic_vector (15 downto 0);
subtype u17 is unsigned (16 downto 0);
subtype u23 is unsigned (22 downto 0);
subtype u24 is unsigned (23 downto 0);
subtype word24 is std_logic_vector (23 downto 0);
subtype dword is std_logic_vector (31 downto 0);
signal count24 : u24 := x"000000";
signal lfsr : word := x"1337";
signal chg_ph : std_logic;
signal taps : std_logic;
signal wv_tri : u8;
signal wv_saw : u8;
signal wv_pul : u8;
signal wv_wht : u8;
signal wv_raw : u8;
signal env : u9;
signal wv_mul : u17;
-- pipelining
signal wv_raw_reg : u8;
signal env_reg : u9;
begin
NCO: process(clk1M, freq, test, count24) is
variable cur : u24;
begin
if (test='1') then
count24 <= x"000000";
--count24 <= "000" & x"00000";
chg_ph <= '0';
else
if (rising_edge(clk1M)) then
cur := count24;
cur := cur + freq;
chg_ph <= cur(23) xor count24(23);
--chg_ph <= cur(22) xor count24(22);
count24 <= cur;
end if;
end if;
end process NCO;
taps <= ((lfsr(0) xor lfsr(2)) xor lfsr(3)) xor lfsr(5);
noise: process(clk1M,test,chg_ph,taps,lfsr(15 downto 0)) is
begin
if (test='1') then
lfsr <= x"1337";
else
if (rising_edge(clk1M) and chg_ph='1') then
lfsr <= taps & lfsr(15 downto 1);
end if;
end if;
end process noise;
gen_tri: process(count24) is
variable calc : byte;
begin
for i in 0 to 6 loop
calc(i+1) := count24(16+i) xor count24(23);
--calc(i+1) := count24(15+i) xor count24(22);
end loop;
calc(0) := count24(23);
--calc(0) := count24(22);
wv_tri <= u8(calc);
end process gen_tri;
gen_saw: process(count24(22 downto 15)) is
begin
wv_saw <= count24(23 downto 16);
--wv_saw <= count24(22 downto 15);
end process gen_saw;
gen_pul: process(count24(22 downto 11),pw) is
variable sample : u12;
begin
sample := count24(23 downto 12);
--sample := count24(22 downto 11);
if ((pw = x"fff") or (sample < pw)) then
wv_pul <= x"ff";
else
wv_pul <= x"00";
end if;
end process gen_pul;
gen_wht: process(lfsr) is
begin
wv_wht <= lfsr(15) & lfsr(14) & lfsr(10) & lfsr( 9) &
lfsr( 5) & lfsr( 4) & lfsr( 3) & lfsr( 0);
end process gen_wht;
-- Handling of waveform selection signals
--
-- The ANDing of multiple waveforms when
-- multiple signals are on is supported
-- (excluding noise).
--
-- We are not replicating the noise-lock bug
-- when noise is combined with other waveforms
-- and c64 programs don't combine noise due to
-- this bug so it's not worthwhile to do so.
with wvfm select wv_raw <=
x"80" when "0000",
wv_tri when "0001",
wv_saw when "0010",
wv_tri and wv_saw when "0011",
wv_pul when "0100",
wv_pul and wv_tri when "0101",
wv_pul and wv_saw when "0110",
wv_pul and wv_tri and wv_saw when "0111",
wv_wht when others;
hold_wvraw: process(clk1M,wv_raw) is
begin
if (rising_edge(clk1M)) then
wv_raw_reg <= wv_raw;
end if;
end process hold_wvraw;
-- TODO: envelope generation
env <= '0' & x"ff";
hold_env: process(clk1M,env) is
begin
if (rising_edge(clk1M)) then
env_reg <= env+1;
end if;
end process hold_env;
hold_vmult: process(clk1M, env_reg, wv_raw_reg) is
begin
if (rising_edge(clk1M)) then
wv_mul <= env_reg * wv_raw_reg;
end if;
end process hold_vmult;
uout <= wv_mul(15 downto 8);
envo <= env_reg(7 downto 0);
osco <= wv_raw_reg;
end sid_voice_impl;
| gpl-3.0 | 6a20e6f66586924e907ed95253519aa7 | 0.527696 | 3.294004 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/shell.vhd | 1 | 8,378 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.config.all;
entity shell is
Port(
clk_100: in std_logic;
clk_25: in std_logic;
rst: in std_logic;
status: out std_logic;
DEBUG_halt: in std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end shell;
architecture Behavioral of shell is
--------------------------------------------------------------------------------
-- Components Forward Declarations
--------------------------------------------------------------------------------
component simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
DEBUG_halt: in std_logic;
SUM: out std_logic;
MXR: out std_logic;
MTIP: in std_logic;
MSIP: in std_logic;
MMU_addr_in: out doubleword; -- 64-bits address for load/store/fetch
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_type: out std_logic_vector(1 downto 0); -- High to toggle store / low means load
MMU_done: in std_logic; -- High when busy
MMU_request: out std_logic; -- request has been made
MMU_num_bytes: out std_logic_vector(1 downto 0); -- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_error: in std_logic_vector(6 downto 0); -- Error bits from MMU
MMU_debug_phys: in doubleword;
MMU_debug_virt: in doubleword
);
end component;
component MMU is
Port(
clk_100: in std_logic; -- 100 Mhz Clock
clk: in std_logic;
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
r_type: in std_logic_vector(1 downto 0); -- High to toggle store
done: out std_logic; -- High when busy
request: in std_logic; -- CPU request
num_bytes: in std_logic_vector(1 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
error: out std_logic_vector(6 downto 0); -- Error
debug_phys: out doubleword;
debug_virt: out doubleword;
SUM: in std_logic;
MXR: in std_logic;
MTIP: out std_logic;
MSIP: out std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end component;
--------------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------------
signal s_MMU_addr_in: doubleword; -- 64-bits address for load/store/fetch
signal s_MMU_data_in: doubleword; -- 64-bits data for store
signal s_MMU_satp: doubleword; -- Signals address translation privilege
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
signal s_MMU_type: std_logic_vector(1 downto 0); -- High to toggle store / low means load
signal s_MMU_done: std_logic; -- High when busy
signal s_MMU_request: std_logic; -- request has been made
signal s_MMU_num_bytes: std_logic_vector(1 downto 0); -- alignment in bytes
signal s_MMU_data_out: doubleword; -- 64-Bits data out for load
signal s_MMU_error: std_logic_vector(6 downto 0); -- Error bits from MMU
signal s_MMU_debug_phys: doubleword;
signal s_MMU_debug_virt: doubleword;
signal s_SUM: std_logic;
signal s_MXR: std_logic;
signal s_MTIP: std_logic;
signal s_MSIP: std_logic;
signal s_LED: std_logic_vector(15 downto 0);
signal s_MEM_request: std_logic;
signal s_MEM_status: std_logic;
begin
LED( 11 downto 0 ) <= s_LED( 11 downto 0 );
LED(12) <= s_MMU_request;
LED(13) <= s_MMU_done;
LED(14) <= s_MEM_request;
LED(15) <= s_MEM_status;
MEM_request <= s_MEM_request;
s_MEM_status <= MEM_status;
--------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------
bestCore: simple_core
port map(
status => status,
clk => clk_25,
rst => rst,
DEBUG_halt => DEBUG_halt,
SUM => s_SUM,
MXR => s_MXR,
MTIP => s_MTIP,
MSIP => s_MSIP,
MMU_addr_in => s_MMU_addr_in,
MMU_data_in => s_MMU_data_in,
MMU_satp => s_MMU_satp,
MMU_mode => s_MMU_mode,
MMU_type => s_MMU_type,
MMU_done => s_MMU_done,
MMU_request => s_MMU_request,
MMU_num_bytes => s_MMU_num_bytes,
MMU_data_out => s_MMU_data_out,
MMU_error => s_MMU_error,
MMU_debug_phys => s_MMU_debug_phys,
MMU_debug_virt => s_MMU_debug_virt
);
memmy: MMU
port map(
clk_100 => clk_100,
clk => clk_25,
rst => rst,
addr_in => s_MMU_addr_in,
data_in => s_MMU_data_in,
satp => s_MMU_satp,
mode => s_MMU_mode,
r_type => s_MMU_type,
done => s_MMU_done,
request => s_MMU_request,
num_bytes => s_MMU_num_bytes,
data_out => s_MMU_data_out,
error => s_MMU_error,
debug_phys => s_MMU_debug_phys,
debug_virt => s_MMU_debug_virt,
SUM => s_SUM,
MXR => s_MXR,
MTIP => s_MTIP,
MSIP => s_MSIP,
-- LEDS out
LED => s_LED,
-- UART out
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- ROM / RAM lines --
MEM_addr => MEM_addr,
MEM_data_in => MEM_data_in,
MEM_data_out => MEM_data_out,
MEM_ram => MEM_ram,
MEM_write => MEM_write,
MEM_request => s_MEM_request,
MEM_status => s_MEM_status,
MEM_err => MEM_err
);
--------------------------------------------------------------------------------
-- Do Work
--------------------------------------------------------------------------------
end Behavioral;
| mit | 3451df3fa05e210469a8c5155994fcbb | 0.454762 | 3.933333 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/RAM_Controller.vhd | 1 | 8,148 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
write, read: in STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
component ram2ddrxadc
port(
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
-- The RAM is accessing 2 bytes per access
ram_a : in std_logic_vector(26 downto 0); -- input address
ram_dq_i : in std_logic_vector(15 downto 0); -- input data
ram_dq_o : out std_logic_vector(15 downto 0); -- output data
ram_cen : in std_logic; -- chip enable
ram_oen : in std_logic; -- output enable
ram_wen : in std_logic; -- write enable
ram_ub : in std_logic; -- upper byte
ram_lb : in std_logic; -- lower byte
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
-- Physical RAM Pin Signals
signal ram_cen, ram_oen, ram_wen, ram_ub, ram_lb: std_logic;
signal ram_dq_o, ram_dq_i: std_logic_vector (15 downto 0);
type memory_states IS (IDLE_STATE, PREPARE_STATE, READ_STATE, WRITE_STATE, INTERMITENT_STATE);
-- Where current state and next_state are pretty self-forward, last state will check
signal current_state, next_state, last_state: memory_states := IDLE_STATE;
signal temp_data_write, temp_data_read: std_logic_vector(63 downto 0);
signal ram_a: std_logic_vector(26 downto 0);
-- Result
signal read_out: std_logic_vector(15 downto 0) := (others => '0');
-- Counters
signal hundred_nano_seconds_elapsed, wait_counter : integer range 0 to 150 := 0;
signal s_read : std_logic := '0';
signal writeOnce, readOnce : std_logic := '0';
begin
ram2ddr: ram2ddrxadc
port map(
clk_200MHz_i=>clk_200,
rst_i=>rst,
device_temp_i=>"000000000000",
ram_a=>ram_a,
ram_dq_i=>ram_dq_o,
ram_dq_o=>ram_dq_i,
ram_cen=>ram_cen,
ram_oen=>ram_oen,
ram_wen=>ram_wen,
ram_ub=>ram_ub,
ram_lb=>ram_lb,
ddr2_addr=>ddr2_addr,
ddr2_ba=>ddr2_ba,
ddr2_ras_n=>ddr2_ras_n,
ddr2_cas_n=>ddr2_cas_n,
ddr2_we_n=>ddr2_we_n,
ddr2_ck_p=>ddr2_ck_p,
ddr2_ck_n=>ddr2_ck_n,
ddr2_cke=>ddr2_cke,
ddr2_cs_n=>ddr2_cs_n,
ddr2_dm=>ddr2_dm,
ddr2_odt=>ddr2_odt,
ddr2_dq=>ddr2_dq,
ddr2_dqs_p=>ddr2_dqs_p,
ddr2_dqs_n=>ddr2_dqs_n
);
process(clk_100,rst) begin
if(rst = '1') then
current_state <= IDLE_STATE;
elsif(rising_edge(clk_100)) then
current_state <= next_state;
end if;
end process;
process(current_state, rst, clk_100) begin
if(rst = '1') then
read_out <= (others => '0');
readOnce <= '0';
writeOnce <= '0';
elsif(rising_edge(clk_100)) then
next_state <= current_state;
case current_state is
-- State IDLE_STATE: Disable chip enable, write and read
when IDLE_STATE =>
ram_cen <= '1';
ram_oen <= '1';
ram_wen <= '1';
if(read = '1') then
s_read <= '1';
next_state <= PREPARE_STATE;
elsif(write = '1') then
s_read <= '0';
next_state <= PREPARE_STATE;
end if;
-- State PREPARE_STATE: Assert whatever needs to be asserted
when PREPARE_STATE =>
-- Reset the counters
hundred_nano_seconds_elapsed <= 0;
wait_counter <= 0;
-- Read
if(s_read = '1') then
readOnce <= '1';
ram_oen <= '0';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '1';
next_state <= READ_STATE;
-- Write
else
writeOnce <= '1';
ram_oen <= '1';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '0';
next_state <= WRITE_STATE;
end if;
-- State READ_STATE: Waits until the delta time indicated by the
-- data sheet has elapsed to finish reading
when READ_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
-- Wait till the necessary clock cycles elapsed while it's recording the data
if(hundred_nano_seconds_elapsed > 22) then
read_out <= ram_dq_i;
next_state <= INTERMITENT_STATE;
end if;
-- Once we're at the write state, the upper and lower byte masks had been asserted
-- to start writing, after which we are free to select the mask combination we need.
when WRITE_STATE =>
ram_lb <= mask_lb;
ram_ub <= mask_ub;
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
if(hundred_nano_seconds_elapsed > 27) then
next_state <= INTERMITENT_STATE;
-- Dummy read_out to signal we are done writing
read_out <= (5 => '1', others => '0');
end if;
-- State INTERMITENT_STATE: The done flag will be raised to allow the MMU
-- to continue onto the next byte
when INTERMITENT_STATE =>
read_out <= ram_dq_i;
next_state <= IDLE_STATE;
when others =>
next_state <= IDLE_STATE;
end case;
end if;
end process;
ram_dq_o <= data_in;
ram_a <= contr_addr_in;
data_out <= read_out;
done <= '1' when current_state = INTERMITENT_STATE else '0';
end Behavioral;
| mit | 3b25c3d65480a15ce37312448d788cef | 0.504664 | 3.634255 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/Shifter.vhd | 1 | 20,680 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Left/Right shifter arithmetic/logic 32/64 bits.
--!
--! @details Vivado synthesizer (2016.2) doesn't support shift
--! from dynamic value, so implement this mux.
-- Modified to remove custom types.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library config;
use work.config.all;
entity Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end;
architecture arch_Shifter of Shifter is
signal o_sll : doubleword;
signal o_sllw : doubleword;
signal o_srl : doubleword;
signal o_sra : doubleword;
signal o_srlw : doubleword;
signal o_sraw : doubleword;
begin
comb : process(clk) -- not edge sensitive to ensure result is ready at next rising edge
variable wb_sll : std_logic_vector(63 downto 0);
variable wb_srl : std_logic_vector(63 downto 0);
variable wb_sra : std_logic_vector(63 downto 0);
variable wb_srlw : std_logic_vector(31 downto 0);
variable wb_sraw : std_logic_vector(63 downto 0);
variable v64 : std_logic_vector(63 downto 0);
variable v32 : std_logic_vector(31 downto 0);
variable msk64 : std_logic_vector(63 downto 0);
variable msk32 : std_logic_vector(63 downto 0);
variable shift64 : integer range 0 to 63;
variable shift32 : integer range 0 to 31;
begin
v64 := i_a1;
v32 := i_a1(31 downto 0);
msk64 := (others => i_a1(63));
msk32 := (others => i_a1(31));
shift64 := to_integer(unsigned(i_a2));
shift32 := to_integer(unsigned(i_a2(4 downto 0)));
case shift64 is
when 0 =>
wb_sll := v64;
wb_srl := v64;
wb_sra := v64;
when 1 =>
wb_sll := v64(62 downto 0) & "0";
wb_srl := "0" & v64(63 downto 1);
wb_sra := (msk64(63 downto 63) & v64(63 downto 1));
when 2 =>
wb_sll := v64(61 downto 0) & "00";
wb_srl := "00" & v64(63 downto 2);
wb_sra := (msk64(63 downto 62) & v64(63 downto 2));
when 3 =>
wb_sll := v64(60 downto 0) & "000";
wb_srl := "000" & v64(63 downto 3);
wb_sra := (msk64(63 downto 61) & v64(63 downto 3));
when 4 =>
wb_sll := v64(59 downto 0) & X"0";
wb_srl := X"0" & v64(63 downto 4);
wb_sra := (msk64(63 downto 60) & v64(63 downto 4));
when 5 =>
wb_sll := v64(58 downto 0) & X"0" & "0";
wb_srl := X"0" & "0" & v64(63 downto 5);
wb_sra := (msk64(63 downto 59) & v64(63 downto 5));
when 6 =>
wb_sll := v64(57 downto 0) & X"0" & "00";
wb_srl := X"0" & "00" & v64(63 downto 6);
wb_sra := (msk64(63 downto 58) & v64(63 downto 6));
when 7 =>
wb_sll := v64(56 downto 0) & X"0" & "000";
wb_srl := X"0" & "000" & v64(63 downto 7);
wb_sra := (msk64(63 downto 57) & v64(63 downto 7));
when 8 =>
wb_sll := v64(55 downto 0) & X"00";
wb_srl := X"00" & v64(63 downto 8);
wb_sra := (msk64(63 downto 56) & v64(63 downto 8));
when 9 =>
wb_sll := v64(54 downto 0) & X"00" & "0";
wb_srl := X"00" & "0" & v64(63 downto 9);
wb_sra := (msk64(63 downto 55) & v64(63 downto 9));
when 10 =>
wb_sll := v64(53 downto 0) & X"00" & "00";
wb_srl := X"00" & "00" & v64(63 downto 10);
wb_sra := (msk64(63 downto 54) & v64(63 downto 10));
when 11 =>
wb_sll := v64(52 downto 0) & X"00" & "000";
wb_srl := X"00" & "000" & v64(63 downto 11);
wb_sra := (msk64(63 downto 53) & v64(63 downto 11));
when 12 =>
wb_sll := v64(51 downto 0) & X"000";
wb_srl := X"000" & v64(63 downto 12);
wb_sra := (msk64(63 downto 52) & v64(63 downto 12));
when 13 =>
wb_sll := v64(50 downto 0) & X"000" & "0";
wb_srl := X"000" & "0" & v64(63 downto 13);
wb_sra := (msk64(63 downto 51) & v64(63 downto 13));
when 14 =>
wb_sll := v64(49 downto 0) & X"000" & "00";
wb_srl := X"000" & "00" & v64(63 downto 14);
wb_sra := (msk64(63 downto 50) & v64(63 downto 14));
when 15 =>
wb_sll := v64(48 downto 0) & X"000" & "000";
wb_srl := X"000" & "000" & v64(63 downto 15);
wb_sra := (msk64(63 downto 49) & v64(63 downto 15));
when 16 =>
wb_sll := v64(47 downto 0) & X"0000";
wb_srl := X"0000" & v64(63 downto 16);
wb_sra := (msk64(63 downto 48) & v64(63 downto 16));
when 17 =>
wb_sll := v64(46 downto 0) & X"0000" & "0";
wb_srl := X"0000" & "0" & v64(63 downto 17);
wb_sra := (msk64(63 downto 47) & v64(63 downto 17));
when 18 =>
wb_sll := v64(45 downto 0) & X"0000" & "00";
wb_srl := X"0000" & "00" & v64(63 downto 18);
wb_sra := (msk64(63 downto 46) & v64(63 downto 18));
when 19 =>
wb_sll := v64(44 downto 0) & X"0000" & "000";
wb_srl := X"0000" & "000" & v64(63 downto 19);
wb_sra := (msk64(63 downto 45) & v64(63 downto 19));
when 20 =>
wb_sll := v64(43 downto 0) & X"00000";
wb_srl := X"00000" & v64(63 downto 20);
wb_sra := (msk64(63 downto 44) & v64(63 downto 20));
when 21 =>
wb_sll := v64(42 downto 0) & X"00000" & "0";
wb_srl := X"00000" & "0" & v64(63 downto 21);
wb_sra := (msk64(63 downto 43) & v64(63 downto 21));
when 22 =>
wb_sll := v64(41 downto 0) & X"00000" & "00";
wb_srl := X"00000" & "00" & v64(63 downto 22);
wb_sra := (msk64(63 downto 42) & v64(63 downto 22));
when 23 =>
wb_sll := v64(40 downto 0) & X"00000" & "000";
wb_srl := X"00000" & "000" & v64(63 downto 23);
wb_sra := (msk64(63 downto 41) & v64(63 downto 23));
when 24 =>
wb_sll := v64(39 downto 0) & X"000000";
wb_srl := X"000000" & v64(63 downto 24);
wb_sra := (msk64(63 downto 40) & v64(63 downto 24));
when 25 =>
wb_sll := v64(38 downto 0) & X"000000" & "0";
wb_srl := X"000000" & "0" & v64(63 downto 25);
wb_sra := (msk64(63 downto 39) & v64(63 downto 25));
when 26 =>
wb_sll := v64(37 downto 0) & X"000000" & "00";
wb_srl := X"000000" & "00" & v64(63 downto 26);
wb_sra := (msk64(63 downto 38) & v64(63 downto 26));
when 27 =>
wb_sll := v64(36 downto 0) & X"000000" & "000";
wb_srl := X"000000" & "000" & v64(63 downto 27);
wb_sra := (msk64(63 downto 37) & v64(63 downto 27));
when 28 =>
wb_sll := v64(35 downto 0) & X"0000000";
wb_srl := X"0000000" & v64(63 downto 28);
wb_sra := (msk64(63 downto 36) & v64(63 downto 28));
when 29 =>
wb_sll := v64(34 downto 0) & X"0000000" & "0";
wb_srl := X"0000000" & "0" & v64(63 downto 29);
wb_sra := (msk64(63 downto 35) & v64(63 downto 29));
when 30 =>
wb_sll := v64(33 downto 0) & X"0000000" & "00";
wb_srl := X"0000000" & "00" & v64(63 downto 30);
wb_sra := (msk64(63 downto 34) & v64(63 downto 30));
when 31 =>
wb_sll := v64(32 downto 0) & X"0000000" & "000";
wb_srl := X"0000000" & "000" & v64(63 downto 31);
wb_sra := (msk64(63 downto 33) & v64(63 downto 31));
when 32 =>
wb_sll := v64(31 downto 0) & X"00000000";
wb_srl := X"00000000" & v64(63 downto 32);
wb_sra := (msk64(63 downto 32) & v64(63 downto 32));
when 33 =>
wb_sll := v64(30 downto 0) & X"00000000" & "0";
wb_srl := X"00000000" & "0" & v64(63 downto 33);
wb_sra := (msk64(63 downto 31) & v64(63 downto 33));
when 34 =>
wb_sll := v64(29 downto 0) & X"00000000" & "00";
wb_srl := X"00000000" & "00" & v64(63 downto 34);
wb_sra := (msk64(63 downto 30) & v64(63 downto 34));
when 35 =>
wb_sll := v64(28 downto 0) & X"00000000" & "000";
wb_srl := X"00000000" & "000" & v64(63 downto 35);
wb_sra := (msk64(63 downto 29) & v64(63 downto 35));
when 36 =>
wb_sll := v64(27 downto 0) & X"000000000";
wb_srl := X"000000000" & v64(63 downto 36);
wb_sra := (msk64(63 downto 28) & v64(63 downto 36));
when 37 =>
wb_sll := v64(26 downto 0) & X"000000000" & "0";
wb_srl := X"000000000" & "0" & v64(63 downto 37);
wb_sra := (msk64(63 downto 27) & v64(63 downto 37));
when 38 =>
wb_sll := v64(25 downto 0) & X"000000000" & "00";
wb_srl := X"000000000" & "00" & v64(63 downto 38);
wb_sra := (msk64(63 downto 26) & v64(63 downto 38));
when 39 =>
wb_sll := v64(24 downto 0) & X"000000000" & "000";
wb_srl := X"000000000" & "000" & v64(63 downto 39);
wb_sra := (msk64(63 downto 25) & v64(63 downto 39));
when 40 =>
wb_sll := v64(23 downto 0) & X"0000000000";
wb_srl := X"0000000000" & v64(63 downto 40);
wb_sra := (msk64(63 downto 24) & v64(63 downto 40));
when 41 =>
wb_sll := v64(22 downto 0) & X"0000000000" & "0";
wb_srl := X"0000000000" & "0" & v64(63 downto 41);
wb_sra := (msk64(63 downto 23) & v64(63 downto 41));
when 42 =>
wb_sll := v64(21 downto 0) & X"0000000000" & "00";
wb_srl := X"0000000000" & "00" & v64(63 downto 42);
wb_sra := (msk64(63 downto 22) & v64(63 downto 42));
when 43 =>
wb_sll := v64(20 downto 0) & X"0000000000" & "000";
wb_srl := X"0000000000" & "000" & v64(63 downto 43);
wb_sra := (msk64(63 downto 21) & v64(63 downto 43));
when 44 =>
wb_sll := v64(19 downto 0) & X"00000000000";
wb_srl := X"00000000000" & v64(63 downto 44);
wb_sra := (msk64(63 downto 20) & v64(63 downto 44));
when 45 =>
wb_sll := v64(18 downto 0) & X"00000000000" & "0";
wb_srl := X"00000000000" & "0" & v64(63 downto 45);
wb_sra := (msk64(63 downto 19) & v64(63 downto 45));
when 46 =>
wb_sll := v64(17 downto 0) & X"00000000000" & "00";
wb_srl := X"00000000000" & "00" & v64(63 downto 46);
wb_sra := (msk64(63 downto 18) & v64(63 downto 46));
when 47 =>
wb_sll := v64(16 downto 0) & X"00000000000" & "000";
wb_srl := X"00000000000" & "000" & v64(63 downto 47);
wb_sra := (msk64(63 downto 17) & v64(63 downto 47));
when 48 =>
wb_sll := v64(15 downto 0) & X"000000000000";
wb_srl := X"000000000000" & v64(63 downto 48);
wb_sra := (msk64(63 downto 16) & v64(63 downto 48));
when 49 =>
wb_sll := v64(14 downto 0) & X"000000000000" & "0";
wb_srl := X"000000000000" & "0" & v64(63 downto 49);
wb_sra := (msk64(63 downto 15) & v64(63 downto 49));
when 50 =>
wb_sll := v64(13 downto 0) & X"000000000000" & "00";
wb_srl := X"000000000000" & "00" & v64(63 downto 50);
wb_sra := (msk64(63 downto 14) & v64(63 downto 50));
when 51 =>
wb_sll := v64(12 downto 0) & X"000000000000" & "000";
wb_srl := X"000000000000" & "000" & v64(63 downto 51);
wb_sra := (msk64(63 downto 13) & v64(63 downto 51));
when 52 =>
wb_sll := v64(11 downto 0) & X"0000000000000";
wb_srl := X"0000000000000" & v64(63 downto 52);
wb_sra := (msk64(63 downto 12) & v64(63 downto 52));
when 53 =>
wb_sll := v64(10 downto 0) & X"0000000000000" & "0";
wb_srl := X"0000000000000" & "0" & v64(63 downto 53);
wb_sra := (msk64(63 downto 11) & v64(63 downto 53));
when 54 =>
wb_sll := v64(9 downto 0) & X"0000000000000" & "00";
wb_srl := X"0000000000000" & "00" & v64(63 downto 54);
wb_sra := (msk64(63 downto 10) & v64(63 downto 54));
when 55 =>
wb_sll := v64(8 downto 0) & X"0000000000000" & "000";
wb_srl := X"0000000000000" & "000" & v64(63 downto 55);
wb_sra := (msk64(63 downto 9) & v64(63 downto 55));
when 56 =>
wb_sll := v64(7 downto 0) & X"00000000000000";
wb_srl := X"00000000000000" & v64(63 downto 56);
wb_sra := (msk64(63 downto 8) & v64(63 downto 56));
when 57 =>
wb_sll := v64(6 downto 0) & X"00000000000000" & "0";
wb_srl := X"00000000000000" & "0" & v64(63 downto 57);
wb_sra := (msk64(63 downto 7) & v64(63 downto 57));
when 58 =>
wb_sll := v64(5 downto 0) & X"00000000000000" & "00";
wb_srl := X"00000000000000" & "00" & v64(63 downto 58);
wb_sra := (msk64(63 downto 6) & v64(63 downto 58));
when 59 =>
wb_sll := v64(4 downto 0) & X"00000000000000" & "000";
wb_srl := X"00000000000000" & "000" & v64(63 downto 59);
wb_sra := (msk64(63 downto 5) & v64(63 downto 59));
when 60 =>
wb_sll := v64(3 downto 0) & X"000000000000000";
wb_srl := X"000000000000000" & v64(63 downto 60);
wb_sra := (msk64(63 downto 4) & v64(63 downto 60));
when 61 =>
wb_sll := v64(2 downto 0) & X"000000000000000" & "0";
wb_srl := X"000000000000000" & "0" & v64(63 downto 61);
wb_sra := (msk64(63 downto 3) & v64(63 downto 61));
when 62 =>
wb_sll := v64(1 downto 0) & X"000000000000000" & "00";
wb_srl := X"000000000000000" & "00" & v64(63 downto 62);
wb_sra := (msk64(63 downto 2) & v64(63 downto 62));
when 63 =>
wb_sll := v64(0) & X"000000000000000" & "000";
wb_srl := X"000000000000000" & "000" & v64(63);
wb_sra := (msk64(63 downto 1) & v64(63));
when others =>
wb_sll := (others => '0');
wb_srl := (others => '0');
wb_sra := (others => '0');
end case;
case shift32 is
when 0 =>
wb_srlw := v32;
wb_sraw := (msk32(63 downto 32) & v32);
when 1 =>
wb_srlw := "0" & v32(31 downto 1);
wb_sraw := (msk32(63 downto 31) & v32(31 downto 1));
when 2 =>
wb_srlw := "00" & v32(31 downto 2);
wb_sraw := (msk32(63 downto 30) & v32(31 downto 2));
when 3 =>
wb_srlw := "000" & v32(31 downto 3);
wb_sraw := (msk32(63 downto 29) & v32(31 downto 3));
when 4 =>
wb_srlw := X"0" & v32(31 downto 4);
wb_sraw := (msk32(63 downto 28) & v32(31 downto 4));
when 5 =>
wb_srlw := X"0" & "0" & v32(31 downto 5);
wb_sraw := (msk32(63 downto 27) & v32(31 downto 5));
when 6 =>
wb_srlw := X"0" & "00" & v32(31 downto 6);
wb_sraw := (msk32(63 downto 26) & v32(31 downto 6));
when 7 =>
wb_srlw := X"0" & "000" & v32(31 downto 7);
wb_sraw := (msk32(63 downto 25) & v32(31 downto 7));
when 8 =>
wb_srlw := X"00" & v32(31 downto 8);
wb_sraw := (msk32(63 downto 24) & v32(31 downto 8));
when 9 =>
wb_srlw := X"00" & "0" & v32(31 downto 9);
wb_sraw := (msk32(63 downto 23) & v32(31 downto 9));
when 10 =>
wb_srlw := X"00" & "00" & v32(31 downto 10);
wb_sraw := (msk32(63 downto 22) & v32(31 downto 10));
when 11 =>
wb_srlw := X"00" & "000" & v32(31 downto 11);
wb_sraw := (msk32(63 downto 21) & v32(31 downto 11));
when 12 =>
wb_srlw := X"000" & v32(31 downto 12);
wb_sraw := (msk32(63 downto 20) & v32(31 downto 12));
when 13 =>
wb_srlw := X"000" & "0" & v32(31 downto 13);
wb_sraw := (msk32(63 downto 19) & v32(31 downto 13));
when 14 =>
wb_srlw := X"000" & "00" & v32(31 downto 14);
wb_sraw := (msk32(63 downto 18) & v32(31 downto 14));
when 15 =>
wb_srlw := X"000" & "000" & v32(31 downto 15);
wb_sraw := (msk32(63 downto 17) & v32(31 downto 15));
when 16 =>
wb_srlw := X"0000" & v32(31 downto 16);
wb_sraw := (msk32(63 downto 16) & v32(31 downto 16));
when 17 =>
wb_srlw := X"0000" & "0" & v32(31 downto 17);
wb_sraw := (msk32(63 downto 15) & v32(31 downto 17));
when 18 =>
wb_srlw := X"0000" & "00" & v32(31 downto 18);
wb_sraw := (msk32(63 downto 14) & v32(31 downto 18));
when 19 =>
wb_srlw := X"0000" & "000" & v32(31 downto 19);
wb_sraw := (msk32(63 downto 13) & v32(31 downto 19));
when 20 =>
wb_srlw := X"00000" & v32(31 downto 20);
wb_sraw := (msk32(63 downto 12) & v32(31 downto 20));
when 21 =>
wb_srlw := X"00000" & "0" & v32(31 downto 21);
wb_sraw := (msk32(63 downto 11) & v32(31 downto 21));
when 22 =>
wb_srlw := X"00000" & "00" & v32(31 downto 22);
wb_sraw := (msk32(63 downto 10) & v32(31 downto 22));
when 23 =>
wb_srlw := X"00000" & "000" & v32(31 downto 23);
wb_sraw := (msk32(63 downto 9) & v32(31 downto 23));
when 24 =>
wb_srlw := X"000000" & v32(31 downto 24);
wb_sraw := (msk32(63 downto 8) & v32(31 downto 24));
when 25 =>
wb_srlw := X"000000" & "0" & v32(31 downto 25);
wb_sraw := (msk32(63 downto 7) & v32(31 downto 25));
when 26 =>
wb_srlw := X"000000" & "00" & v32(31 downto 26);
wb_sraw := (msk32(63 downto 6) & v32(31 downto 26));
when 27 =>
wb_srlw := X"000000" & "000" & v32(31 downto 27);
wb_sraw := (msk32(63 downto 5) & v32(31 downto 27));
when 28 =>
wb_srlw := X"0000000" & v32(31 downto 28);
wb_sraw := (msk32(63 downto 4) & v32(31 downto 28));
when 29 =>
wb_srlw := X"0000000" & "0" & v32(31 downto 29);
wb_sraw := (msk32(63 downto 3) & v32(31 downto 29));
when 30 =>
wb_srlw := X"0000000" & "00" & v32(31 downto 30);
wb_sraw := (msk32(63 downto 2) & v32(31 downto 30));
when 31 =>
wb_srlw := X"0000000" & "000" & v32(31 downto 31);
wb_sraw := (msk32(63 downto 1) & v32(31 downto 31));
when others =>
wb_srlw := (others => '0');
wb_sraw := (others => '0');
end case;
o_sll <= wb_sll;
o_sllw(31 downto 0) <= wb_sll(31 downto 0);
o_sllw(63 downto 32) <= (others => wb_sll(31));
o_srl <= wb_srl;
o_sra <= wb_sra;
o_srlw <= X"00000000" & wb_srlw;
o_sraw <= wb_sraw;
end process;
result <= o_sll when ctrl = instr_SLL or ctrl = instr_SLLI else
o_srl when ctrl = instr_SRL or ctrl = instr_SRLI else
o_sra when ctrl = instr_SRA or ctrl = instr_SRAI else
o_sllw when ctrl = instr_SLLW or ctrl = instr_SLLIW else
o_srlw when ctrl = instr_SRLW or ctrl = instr_SRLIW else
o_sraw when ctrl = instr_SRAW or ctrl = instr_SRAIW else
(others => '0');
end;
| mit | fec1e819ae3e0ceebf964fa43001485f | 0.466006 | 3.250039 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ddr.vhd | 1 | 70,937 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.9
-- \ \ Application : MIG
-- / / Filename : ddr.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in example design (example_top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr is
generic
(
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
DATA_WIDTH : integer := 16;
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
ECC_WIDTH : integer := 8;
MC_ERR_ADDR_WIDTH : integer := 31;
MEM_ADDR_ORDER
: string := "TG_TEST";
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IODELAY_HP_MODE : string := "ON";
-- to phy_top
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP : string := "IODELAY_MIG";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency.
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL";
-- # = "INTERNAL", "EXTERNAL"
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port
(
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr;
architecture arch_ddr of ddr is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
function TEMP_MON return string is
begin
if(SIMULATION = "FALSE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant RANK_WIDTH : integer := clogb2(RANKS);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v1_9_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic;
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic
);
end component mig_7series_v1_9_iodelay_ctrl;
component mig_7series_v1_9_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v1_9_clk_ibuf;
component mig_7series_v1_9_infrastructure is
generic (
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
RST_ACT_LOW : integer
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic;
clk : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v1_9_infrastructure;
component mig_7series_v1_9_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v1_9_tempmon;
component mig_7series_v1_9_memc_ui_top_std is
generic (
TCQ : integer;
PAYLOAD_WIDTH : integer;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
CK_WIDTH : integer;
COL_WIDTH : integer;
CS_WIDTH : integer;
nCS_PER_RANK : integer;
CKE_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DRAM_WIDTH : integer;
ECC : string;
nBANK_MACHS : integer;
DATA_WIDTH : integer;
ECC_TEST : string;
ECC_WIDTH : integer;
MC_ERR_ADDR_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_DATA_WIDTH : integer;
APP_MASK_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
MASTER_PHY_CTL : integer;
AL : string;
nAL : integer;
BURST_MODE : string;
BURST_TYPE : string;
CL : integer;
OUTPUT_DRV : string;
RTT_NOM : string;
ADDR_CMD_MODE : string;
REG_CTRL : string;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
SIM_BYPASS_INIT_CAL : string;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
IODELAY_HP_MODE : string;
IBUF_LPWR_MODE : string;
DATA_IO_IDLE_PWRDWN : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
CKE_ODT_AUX : string;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
ORDERING : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
IODELAY_GRP : string;
CMD_PIPE_PLUS1 : string;
DRAM_TYPE : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
STARVE_LIMIT : integer;
REFCLK_FREQ : real;
tCK : integer;
nCK_PER_CLK : integer;
DEBUG_PORT : string
);
port (
clk : in std_logic;
clk_ref : in std_logic;
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
rst : in std_logic;
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector(2*nCK_PER_CLK-1 downto 0);
app_ecc_multiple_err : out std_logic_vector(2*nCK_PER_CLK-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
device_temp : in std_logic_vector(11 downto 0);
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0)
);
end component mig_7series_v1_9_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic;
signal iodelay_ctrl_rdy : std_logic;
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector(2*nCK_PER_CLK-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
signal device_temp_i : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector(6*RANKS-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector(6*DQS_WIDTH-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector(3*DQS_WIDTH-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector(DRAM_WIDTH*16-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector(6*DQS_WIDTH-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector(3*DQS_WIDTH-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(3 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector(6*RANKS-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector(6*RANKS-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector(2*nCK_PER_CLK-1 downto 0) := (others => '0');
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v1_9_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP => IODELAY_GRP,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v1_9_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v1_9_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref,
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v1_9_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v1_9_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
IODELAY_HP_MODE => IODELAY_HP_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP => IODELAY_GRP,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK
)
port map (
clk => clk,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
device_temp => device_temp,
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
init_calib_complete => init_calib_complete_i
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr;
| mit | 30cabc338c53d6f059f9a33df06f0309 | 0.438389 | 4.272798 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9_exdes.vhd | 1 | 5,962 | -- file: dcm_TFT9_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- performance, such as life-support or safety devices or
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-- applications related to the deployment of airbags, or any
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-- Applications, subject only to applicable laws and
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_TFT9_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm_TFT9_exdes;
architecture xilinx of dcm_TFT9_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
-- Need to buffer input clocks that aren't already buffered
signal clk_in1_buf : std_logic;
component dcm_TFT9 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK9 : out std_logic;
CLK9_180 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
-- Insert BUFGs on all input clocks that don't already have them
----------------------------------------------------------------
clkin1_buf : BUFG
port map
(O => clk_in1_buf,
I => CLK_IN1);
-- Instantiation of the clocking network
----------------------------------------
clknetwork : dcm_TFT9
port map
(-- Clock in ports
CLK_IN1 => clk_in1_buf,
-- Clock out ports
CLK9 => clk_int(1),
CLK9_180 => clk_int(2),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen)) begin
if (rising_edge(clk(count_gen))) then
if (reset_int = '1') then
counter(count_gen) <= (others => '0') after TCQ;
else
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| gpl-3.0 | c87800f1c368750f1b6e280a1a8a7d36 | 0.618081 | 4.252496 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/MMU.vhd | 1 | 34,616 | ----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out word; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end MMU;
architecture Behavioral of MMU is
-- Components
component ram_controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
write, read: in STD_LOGIC;
mask_lb, mask_ub: in std_logic;
done: out STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(63 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end component;
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
component SPIFlashModule is
port(clk, reset, io_flash_en, io_flash_write, io_read_id: in std_logic;
io_quad_io: in std_logic_vector(3 downto 0);
io_flash_addr: in std_logic_vector(23 downto 0);
io_flash_data_in: in std_logic_vector(31 downto 0);
io_flash_data_out: out std_logic_vector(31 downto 0);
io_state_to_cpu: out std_logic_vector(11 downto 0);
io_sck_gate, io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: out std_logic);
end component;
constant ROM_period : integer := 150;
type instsmem is array(0 to 100) of word;
signal instr_mem: instsmem := (others => (others => '0'));
signal ROM_mem: instsmem := (
0 => x"00001137",
1 => x"8071011b",
2 => x"01411113",
3 => x"0040006f",
4 => x"01300793",
5 => x"01b79793",
6 => x"00100713",
7 => x"00e79023",
8 => x"098017b7",
9 => x"00000697",
10 => x"09468693",
11 => x"02100713",
12 => x"00479793",
13 => x"00100593",
14 => x"0047c603",
15 => x"0ff67613",
16 => x"fe060ce3",
17 => x"00e781a3",
18 => x"00b782a3",
19 => x"00168693",
20 => x"0006c703",
21 => x"fe0712e3",
22 => x"09801737",
23 => x"01300513",
24 => x"00100693",
25 => x"00471713",
26 => x"00100593",
27 => x"01b51513",
28 => x"00174783",
29 => x"0ff7f793",
30 => x"fe078ce3",
31 => x"00074603",
32 => x"0016869b",
33 => x"03069693",
34 => x"00b70123",
35 => x"0306d693",
36 => x"0ff67613",
37 => x"00d51023",
38 => x"00474783",
39 => x"0ff7f793",
40 => x"fe078ce3",
41 => x"00c701a3",
42 => x"00b702a3",
43 => x"fc5ff06f",
46 => x"45212121",
47 => x"204F4843",
48 => x"56524553",
49 => x"45522121",
50 => x"0000A021",
others => (others => '0'));
-- SPI signals
signal io_flash_en: std_logic;
signal io_flash_write: std_logic;
signal io_quad_io: std_logic_vector(3 downto 0);
signal io_flash_addr: std_logic_vector(23 downto 0);
signal io_flash_data_in: std_logic_vector(31 downto 0);
signal io_flash_data_out: std_logic_vector(31 downto 0);
signal io_read_id: std_logic;
signal io_state_to_cpu: std_logic_vector(11 downto 0);
signal io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: std_logic;
signal io_srl, io_cr : std_logic_vector(7 downto 0);
signal io_sckgate: std_logic;
signal io_rst: std_logic;
type MMU_state is (idle, loading, storing, fetching, decode_state,page_walk,loading_ram_page_walk, loading_ram, loading_rom, done_uart_rx, done_uart_tx, storing_ram);
signal curr_state: MMU_state := idle;
signal next_state: MMU_state := idle;
signal paused_state : MMU_state := idle; --Bit of a misnomer, this is
signal LED_reg: std_logic_vector(15 downto 0);
-- RAM signals
signal w_en: std_logic := '0';
signal RAM_en, ROM_en: std_logic := '0';
type RAM_state is (idle, read_low, read_low_mid, read_upper_mid, read_upper,write_low, write_low_mid, write_upper_mid, write_upper, done);
signal RAM_curr_state : RAM_state := idle;
signal RAM_next_state : RAM_state := idle;
signal RAM_masks: std_logic_vector(7 downto 0);
signal RAM_timeout_counter: integer:= 0;
signal RAM_data_in: std_logic_vector(15 downto 0);
signal RAM_data_out: std_logic_vector(15 downto 0);
signal RAM_address_in: std_logic_vector(26 downto 0);
signal RAM_lb, RAM_ub: std_logic := '1';
signal s_RAM_data_out: doubleword := (others => '0'); -- The register holding the ram doubleword
signal ROM_done, RAM_done: std_logic := '0';
signal BRAM_toggle : std_logic_vector(1 downto 0) := "00";
--32 Bits acceses for ROM, either, too slow
type ROM_state is (idle, reading_lower, reading_higher, done);
signal ROM_curr_state : ROM_state := idle;
signal ROM_next_state : ROM_state := idle;
signal gated_clk: std_logic := '0';
signal s_ROM_data_out: doubleword := (others => '0'); --Register holding the rom doubleword
signal ROM_address_in : std_logic_vector(23 downto 0);
signal s_ROM_done: std_logic;
-- UART out data signal, for reading UART registers
signal ROM_Counter: integer := 0;
signal UART_out: STD_LOGIC_VECTOR(7 downto 0);
signal UART_toggle : std_logic := '0';
signal SATP_mode: std_logic_vector(63 downto 0) := (others => '0');
signal SATP_PPN: std_logic_vector(63 downto 0) := (others => '0');
signal s_internal_data : std_logic_vector(63 downto 0);
signal s_internal_address: doubleword;
signal clk_100, clk_200, clk_25, locked: std_logic;
signal page_address_in: doubleword := (others => '0');
signal uart_data_in, uart_data_out: std_logic_vector(7 downto 0);
signal uart_data_available, uart_ready: std_logic;
signal uart_reset_read, uart_send: std_logic;
signal UART_data: doubleword;
signal m_timer: integer := 0;
Type PAGE_WALK_STATE is (idle,level_i_read, level_i_decode, done);
signal PAGE_WALK_next_state, PAGE_WALK_current_state: PAGE_WALK_STATE := idle;
signal s_page_walk,page_walk_request_read, page_walk_done: std_logic := '0';
signal page_walk_address_out, page_address_final: doubleword;
signal Intermitent_Address_In: doubleword;
signal addr_in_latch: doubleword;
-- Debugging
signal s_debugging_out: std_logic_vector(5 downto 0);
signal qd: std_logic_vector(3 downto 0);
signal gated_clock, clock_gate: std_logic;
signal io_sck_gate: std_logic;
begin
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => clk_100,
clk_200MHz_o => clk_200,
clk_25MHz_o => clk_25,
locked => locked
);
myRAMController: ram_controller port map
(
clk_200 => clk_200,
clk_100 => clk_100,
rst => rst,
data_in => RAM_data_in,
data_out => RAM_data_out,
mask_lb => RAM_lb,
mask_ub => RAM_ub,
done => RAM_done,
write => w_en,
read => RAM_en,
contr_addr_in => RAM_address_in,
ddr2_addr => ddr2_addr ,
ddr2_ba => ddr2_ba ,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p ,
ddr2_ck_n => ddr2_ck_n ,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
--myROMController: ROM_controller_SPI port map(clk_25 => clk_25, rst => io_rst, read =>io_flash_en,
-- address_in => ROM_address_in, data_out => io_flash_data_out,
-- si_i =>io_SI, wp => io_WP, si_t => io_tri_si, wp_t => io_tri_wp,
-- cs_n => io_cs, qd => qd, done =>s_ROM_done);
myROMController: SPIFlashModule port map(
clk => clk_25, reset => io_rst, io_flash_en => io_flash_en, io_flash_write => io_flash_write, io_read_id => io_read_id,
io_quad_io => qd, io_flash_addr => ROM_address_in, io_flash_data_in => io_flash_data_in,
io_flash_data_out => io_flash_data_out, io_state_to_cpu => io_state_to_cpu,
io_sck_gate => io_sckgate, io_SI => io_SI, io_WP => io_WP, io_tri_si => io_tri_si, io_tri_wp => io_tri_wp, io_cs => io_cs,
io_ready => io_ready);
cs_n <= io_cs;
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => CLK,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
MMU_FSM: process(clk, rst)
-- variable s_internal_address: doubleword := (others => '0'); --Realized Physical Address
-- variable paused_state: MMU_state; -- When we find the mode from SATP, we resume from the state saved here
begin
if rst = '1' then
--curr_state <= idle;
-- ROM_curr_state <= idle;
RAM_curr_state <= idle;
PAGE_WALK_current_state <= idle;
m_timer <= 0;
instr_out <= (others => '0');
error <= (others => '0');
io_flash_write <= '0';
io_read_id <= '0';
next_state <= idle;
busy <= '0';
BRAM_toggle <= "11";
LED <= (others => '0');
UART_data <= (others => '0');
data_out <= (others => '0');
elsif(rising_edge(clk)) then
--curr_state <= next_state;
RAM_curr_state <= RAM_next_state;
-- ROM_curr_state <= ROM_next_state;
PAGE_WALK_current_state <= PAGE_WALK_next_state;
m_timer <= m_timer + 1;
busy <= '1';
--next_state <= curr_state;
case next_state is
-- Idling by like the leech you are MMU arent U
when idle =>
busy <= '1';
UART_toggle <= '0';
s_debugging_out <= "000000";
--s_internal_address <= addr_in;
uart_reset_read <= '0';
uart_send <= '0';
if(load = '1') then
next_state <= decode_state;
paused_state <= loading;
ROM_curr_state <= idle;
s_internal_address <= addr_in;
elsif(store = '1') then
next_state <= decode_state;
paused_state <= storing;
s_internal_address <= addr_in;
elsif(ready_instr = '1') then
next_state <= decode_state;
s_internal_address <= addr_instr;
paused_state <= fetching;
else
busy <= '0';
end if;
-- Figure out what state are we at
when decode_state =>
s_debugging_out <= "000001";
case satp_mode(3 downto 0) is
when x"0" => -- No translation is assumed
next_state <= paused_state;
when others =>
next_state <= page_walk; --SV39 is assumed whenever anything else is written, no SV48 shenanigans
end case;
-- Walk the thing blue page walk line
when page_walk =>
s_debugging_out <= "000010";
s_page_walk <= '1'; --We enable the page walk process
if(page_walk_done = '1') then --Page walk is done
s_internal_address <= page_walk_address_out; -- We assign the newly discovered address
next_state <= paused_state; --Resume wherever we left off matey
elsif(page_walk_request_read = '1') then
RAM_en <= '1';
end if;
-- Intermediate fetching state, just check if there is any misalignment errors
when fetching =>
busy <= '1';
s_debugging_out <= "000011";
--Fetches have to be aligned
if(unsigned(s_internal_address) mod 4 > 0) then
error(4) <= '1'; -- Misaligned error, geback geback
next_state <= idle;
elsif( s_internal_address(31 downto 16) = x"0000" ) then
next_state <= idle;
instr_out <= instr_mem(to_integer(unsigned(addr_instr(31 downto 0)))/4);
else
--s_internal_address <= std_logic_vector(unsigned(addr_instr)/2);
next_state <= loading; --Loading instructions from elsewhere
end if;
-- Loading states
when loading =>
s_debugging_out <= "000100";
if(s_internal_address(31 downto 16) = x"0000" ) then --BRAM
next_state <= idle; --Instruction already goes out here, so no need to do anything,
-- We do this to preserve the instr_out port, even though it's really not necesary.
elsif(s_internal_address(31 downto 16) = x"9801") then --UART Registers
next_state <= idle; -- By default go to idle
UART_toggle <= '1';
case s_internal_address(3 downto 0) is
when X"0" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_in;
when X"1" => data_out <= zero_word & zero_word(31 downto 1) & uart_data_available;
when X"2" => data_out <= zero_word & zero_word(31 downto 1) & uart_reset_read;
when X"3" => data_out <= zero_word & zero_word(31 downto 8) & uart_data_out;
when X"4" => data_out <= zero_word & zero_word(31 downto 1) & uart_ready;
when X"5" => data_out <= zero_word & zero_word(31 downto 1) & uart_send;
when others => NULL;
end case;
elsif(s_internal_address(31 downto 24) = x"98") then --LEDS Registers
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock Register
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"9") then --ROM
if(paused_state = fetching) then
instr_out <= ROM_mem(to_integer(unsigned(addr_instr(23 downto 0)))/4);
else
case alignment is
when "0000" =>
when "0001" => --Load byte
if(unsigned(s_internal_address(23 downto 0)) mod 4 = 0) then
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 1) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(15 downto 8);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 2) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(23 downto 16);
elsif(unsigned(s_internal_address(23 downto 0)) mod 4 = 3) then
data_out <= zero_word & zero_word(31 downto 8) & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4)(31 downto 24);
end if;
when "0010" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when "0100" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when "1000" =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
when others =>
data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
end case;
--data_out <= zero_word & ROM_mem(to_integer(unsigned(s_internal_address(23 downto 0)))/4);
ROM_curr_state <= done;
end if;
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= loading_ram;
-- ROM_counter <= 0;
else
next_state <= idle;
end if;
-- Special load cases
when loading_rom =>
s_debugging_out <= "000101";
ROM_en <= '1';
if(ROM_counter > (2 * ROM_period)) then
ROM_en <= '0';
if(paused_state = fetching) then
instr_out <= s_ROM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
when loading_ram =>
s_debugging_out <= "000110";
RAM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= s_RAM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
-- Stores and such
when storing =>
s_debugging_out <= "000111";
next_state <= idle; -- By default go back
if(addr_in(31 downto 16) = x"9801") then --UART
case addr_in(3 downto 0) is
when X"0" => NULL; -- Nothing here really, why would you write to buffer in?
when X"1" => NULL; -- Why?
when X"2" => uart_reset_read <= '1';
next_state <= done_uart_rx;
when X"3" => uart_data_out <= data_in(7 downto 0);
when X"4" => NULL; -- No no no write
when X"5" => uart_send <= '1'; -- Assuming if you are writing is to send something
next_state <= done_uart_tx; -- After writing to this register we reset it automatically
when others => UART_data <= (others => '0');
end case;
elsif(addr_in(31 downto 24) = x"98") then --LEDS
LED <= data_in(15 downto 0) OR data_in(31 downto 16);
next_state <= idle;
elsif(addr_in(31 downto 24) = x"97") then --m_clock
next_state <= idle;
-- elsif(addr_in(31 downto 28) = x"9") then --ROM
-- next_state <= idle; --Can't write to ROM, I mean you could, but hwhy? Don't write to ROM
elsif(addr_in(31 downto 28) = x"8") then --RAM
next_state <= storing_ram;
end if;
-- Special stores section
when storing_ram =>
s_debugging_out <= "001000";
w_en <= '1';
if(RAM_done = '1') then
w_en <= '0';
next_state <= idle;
end if;
-- Special done states, to reset whatever needs to be reset
when done_uart_tx =>
uart_send <= '0';
if(uart_ready = '0') then
next_state <= done_uart_tx;
else
next_state <= idle;
end if;
when done_uart_rx =>
uart_reset_read <= '0';
next_state <= idle;
when others =>
end case;
end if;
end process;
-- Walk the page
PAGE_WALK_FSM: process(clk, rst, s_page_walk)
variable level: Integer := 0;
begin
if(rst = '1') then
elsif(rising_edge(clk)) then
PAGE_WALK_next_state <= PAGE_WALK_current_state;
case PAGE_WALK_current_state is
when idle =>
if(s_page_walk = '1') then
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & addr_in(31 downto 22) & "00";--SATP PPN will give us the root page table location
PAGE_WALK_next_state <= level_i_read;
level := 0; --Start at level 0
end if;
when level_i_read =>
if(level < 3) then
page_walk_request_read <= '1';
if(RAM_done = '1') then
level := level + 1;
PAGE_WALK_next_state <= level_i_decode;
end if;
else
--Raise exception here
--More levels than 3
PAGE_WALK_next_state <= done;
end if;
when level_i_decode =>
PAGE_WALK_next_state <= idle;
if(s_RAM_data_out(0) = '0') then --Invalid PTE Raise the roof
NULL;
elsif(s_RAM_data_out(1) = '0' and s_RAM_data_out(7) = '1') then -- Not Valid and Dirty
NULL;
elsif(s_RAM_data_out(1) = '1' or s_RAM_data_out(3) = '1') then --So far this address is final
-- Check if the PTE is in user mode and we are in user mode
if(mode = "00" and s_RAM_data_out(4) = '1') then
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
-- If the PTE U bit is '0' and we are in Supervisor mode, it's still good
-- We leave this separate in case other actions need to happen in S mode
elsif(mode = "01" and s_RAM_data_out(4) = '0') then
-- If PTE A is 0 or PTE D is 0 and we are storing, then we could raise an exception
-- or set the bits to 1 ourselves
if(s_RAM_data_out(6) = '0' or (paused_state = storing and s_RAM_data_out(7) = '0')) then
-- Raise exception
end if;
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
else
page_walk_next_state <= idle;
--Raise exception when the user has no permission to access this PTE
end if;
page_walk_done <= '1';
else -- We still have to dig deeper m8
page_walk_next_state <= level_i_read;
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & s_internal_address(31 downto 22) & "00";
end if;
when done =>
PAGE_WALK_next_state <= idle;
end case;
end if;
end process;
--busy <= '0' when curr_state = idle else '1';
-- Z high impedance
dq(0) <= 'Z' when io_tri_si = '1' else io_SI;
dq(1) <= 'Z';
dq(2) <= 'Z' when io_tri_wp = '1' else io_WP;
dq(3) <= 'Z';
qd(0) <= dq(0) when io_tri_si = '1' else 'Z';
qd(1) <= dq(1);
qd(2) <= dq(2) when io_tri_wp = '1' else 'Z';
qd(3) <= dq(3);
gated_clock <= '0' when gated_clk = '1' else not(clk_25);
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 10.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => gated_clock, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);
-- ROM SPI Clock Generation
ROM_CLK: process(clk_25, rst) begin
if(rst = '1') then
gated_clk <= '1';
elsif(rising_edge(clk_25)) then
if (io_cs = '0') then
gated_clk <= '0';
else
gated_clk <= '1';
end if;
end if;
end process;
---- ROM State Machine
---- To enable rom set ROM_en high
---- Will wait for 600 cycles and give back a 64 bit word
--ROM_FSM: process(clk,rst)
-- begin
-- if(rst = '1') then
-- io_rst <= '1';
-- ROM_next_state <= idle;
-- elsif(rising_edge(clk)) then
-- ROM_next_state <= ROM_curr_state;
-- case ROM_curr_state is
-- when idle =>
-- ROM_next_state <= idle;
-- ROM_counter <= 0;
-- io_rst <= '0';
-- if(ROM_en = '1') then
-- ROM_done <= '0';
-- --io_rst <= '0';
-- ROM_address_in <= s_internal_address(23 downto 0); --24 Bits in
-- ROM_next_state <= reading_lower;
-- end if;
-- when reading_lower =>
-- ROM_next_state <= reading_lower;
-- io_flash_en <= '1';
-- ROM_counter <= ROM_counter + 1; -- Wait a good amount of time to let the device react
-- if(ROM_counter > ROM_period) then
-- s_ROM_data_out(31 downto 0) <= io_flash_data_out;
-- ROM_next_state <= reading_higher;
-- ROM_address_in <= std_logic_vector(unsigned(s_internal_address(23 downto 0)) + 4); --24 Bits in
-- end if;
-- when reading_higher =>
-- ROM_next_state <= reading_higher;
-- ROM_counter <= ROM_counter + 1; -- Wait a good amount of time to let the device react
-- if(ROM_counter > ROM_period * 2) then
-- s_ROM_data_out(63 downto 32) <= io_flash_data_out;
-- ROM_next_state <= done;
-- end if;
-- when done =>
-- ROM_done <= '1';
-- if(ROM_en <= '0') then
-- ROM_next_state <= idle;
-- end if;
-- io_rst <= '1';
-- end case;
-- end if;
--end process;
-- RAM State Machine
-- For reading from RAM, the ideal waiting time is of 230 ns
-- For writing into RAM, the ideal waiting time is of 270 ns
-- To make things easier we use 300 ns for both cases.
RAM_FSM: process(clk, RAM_en, w_en)
variable RAM_counter :integer := 0;
begin
if(rising_edge(clk)) then
if(RAM_curr_state /= idle) then
RAM_counter := RAM_counter + 1;
else
RAM_counter := 0;
end if;
RAM_next_state <= RAM_curr_state;
-- Forget about it
-- If for whatever reason we take long than
-- 1200 cycles, timeout and throw some error
if(RAM_timeout_counter >= 1200) then
RAM_next_state <= idle;
else
case RAM_curr_state is
-- Idle state, read before write
when idle =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_en = '1') then
RAM_next_state <= read_low;
elsif(w_en = '1') then
RAM_next_state <= write_low;
end if;
-- Load States
when read_low =>
if(RAM_counter > 30) then
s_RAM_data_out(15 downto 0) <= RAM_data_out;
RAM_next_state <= read_low_mid;
RAM_counter := 0;
end if;
when read_low_mid =>
if(RAM_counter > 30) then --Valid Data
s_RAM_data_out(31 downto 16) <= RAM_data_out;
RAM_next_state <= read_upper_mid;
RAM_counter := 0;
end if;
when read_upper_mid =>
if(RAM_counter > 30) then
s_RAM_data_out(47 downto 32) <= RAM_data_out;
RAM_next_state <= read_upper;
RAM_counter := 0;
end if;
when read_upper =>
if(RAM_counter > 30) then
s_RAM_data_out(63 downto 48) <= RAM_data_out;
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- Store States (LSB first)
-- Bytes 1 and 2
when write_low =>
--Alignment 0001 means Byte-wise access
if(alignment(0) = '1') then
RAM_ub <= '0'; --Disable the upper byte from controller
end if;
if(RAM_counter > 30) then
if(alignment(0) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_low_mid;
end if;
RAM_counter := 0;
-- Alignment 0100 means Upper Word access
elsif(alignment(2) = '1') then
RAM_counter := 0;
RAM_next_state <= write_upper_mid;
end if;
-- Byte 3 and 4
when write_low_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then --Valid Data
-- Alignment 0010 is Lower Word access
if(alignment(1) = '1') then
RAM_next_state <= done;
else
RAM_next_state <= write_upper_mid;
RAM_counter := 0;
end if;
end if;
-- Bytes 5 and 6
when write_upper_mid =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= write_upper;
RAM_counter := 0;
end if;
when write_upper =>
RAM_ub <= '1';
RAM_lb <= '1';
if(RAM_counter > 30) then
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- We are done here
when others =>
RAM_next_state <= idle;
end case;
end if;
end if;
end process;
-- Latches the last obtained datas (dati, datum? datae?)
--LAST_OBTAINED_DATA: process(clk,rst, UART_toggle) begin
-- if(rst = '1') then
-- data_out <= (others => '0');
-- elsif(rising_edge(clk)) then
-- if(RAM_curr_state = done) then
-- data_out <= s_RAM_data_out;
-- elsif(ROM_curr_state = done) then
-- data_out <= s_ROM_data_out;
-- elsif(UART_toggle = '1') then
-- data_out(7 downto 0) <= UART_data(7 downto 0);
-- data_out(63 downto 8) <= (others => '0');
-- end if;
-- end if;
--end process;
-- Muxes for addresses and data
-- Intermitent address is internal RAM address, whenever we need to use the RAM
-- to access something else, we will make use of this intermitent_address_in signal
Intermitent_Address_In <= addr_in when s_page_walk = '0' else page_address_in;
s_internal_data <= data_in; --For the moment this is right
-- Might change this to sequential logic if needed, I don't think it necessary
RAM_address_in <= std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 0) when RAM_curr_state = idle or RAM_curr_state = read_low or RAM_curr_state = write_low else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 2) when RAM_curr_state = read_low_mid or RAM_curr_state = write_low_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 4) when RAM_curr_state = read_upper_mid or RAM_curr_state = write_upper_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 6) when RAM_curr_state = read_upper or RAM_curr_state = write_upper
else (others => '0');
RAM_data_in <= s_internal_data(15 downto 0 ) when RAM_curr_state = idle or RAM_curr_state = write_low else
s_internal_data(31 downto 16) when RAM_curr_state = write_low_mid else
s_internal_data(47 downto 32) when RAM_curr_state = write_upper_mid else
s_internal_data(63 downto 48) when RAM_curr_state = write_upper else
(others => '0');
-- The CSR telling us where the page table start
SATP_mode(3 downto 0) <= satp(63 downto 60);
SATP_PPN(43 downto 0) <= satp(43 downto 0);
end Behavioral;
| mit | 2bec3bdc84caaf87845cf5c716039f10 | 0.555726 | 3.36045 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/controllers/score.vhd | 1 | 1,284 | LIBRARY ieee ;
USE ieee.std_logic_1164.all;
LIBRARY lib;
USE lib.general.all;
entity score is
port(
clock_i,reset_i: in std_logic;
score_o: out std_logic_vector(27 downto 0)
);
end score;
architecture Behavior of score is
signal unidade, dezena, centena, milhar: integer := 0;
begin
process(clock_i,reset_i)
begin
if reset_i = '1' then
unidade <= 0;
dezena <= 0;
centena <= 0;
milhar <= 0;
elsif rising_edge(clock_i) then
dezena <= dezena + 1;
if dezena >= 9 then
dezena <= 0;
centena <= centena + 1;
end if;
if centena >= 9 then
centena <= 0;
milhar <= milhar + 1;
end if;
end if;
end process;
disp_u: conv_7seg_int
port map (unidade,score_o(6 downto 0));
disp_d: conv_7seg_int
port map (dezena,score_o(13 downto 7));
disp_c: conv_7seg_int
port map (centena,score_o(20 downto 14));
disp_m: conv_7seg_int
port map (milhar,score_o(27 downto 21));
end Behavior;
| mit | 8026dfc68cf9cde4b6fe4e3f15bd1cee | 0.468847 | 3.926606 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/top_ROM.vhd | 1 | 6,872 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 04/21/2018 01:23:15 PM
-- Module Name: system_top - Behavioral
-- Description: System-level wrapper for processor components
--
-- Additional Comments: "Death must be so beautiful. To lie in te soft brown earth,
-- with the grasses waving above one's head, and listen to
-- silence. To have no yesterday, and no tomorrow. To forget
-- time, to forget life, to forget Vivado, to be at peace."
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.config.all;
entity top_ROM is
Port(
clk: in std_logic;
rst: in std_logic;
status: out std_logic;
DEBUG_halt: in std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM SPI signals
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end top_ROM;
architecture Behavioral of top_ROM is
--------------------------------------------------------------------------------
-- Components Forward Declarations
--------------------------------------------------------------------------------
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component shell is
Port(
clk_100: in std_logic;
clk_25: in std_logic;
rst: in std_logic;
status: out std_logic;
DEBUG_halt: in std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end component;
component stub_ram_int is
Port(
memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component;
component rom_intf is
Port(
memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk, rst : in STD_LOGIC;
-- ROM SPI signals
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end component;
-- Signals
signal s_clk: std_logic;
signal s_rst: std_logic;
signal s_status: std_logic;
signal s_DEBUG_halt: std_logic;
-- LEDS out
signal s_LED: std_logic_vector(15 downto 0);
-- UART out
signal s_UART_TXD: std_logic;
signal s_UART_RXD: std_logic;
-- ROM / RAM lines --
signal s_MEM_addr: std_logic_vector(26 downto 0);
signal s_MEM_data_in: std_logic_vector(7 downto 0);
signal s_MEM_data_out: std_logic_vector(7 downto 0);
signal s_MEM_ram: std_logic;
signal s_MEM_write: std_logic;
signal s_MEM_request: std_logic;
signal s_MEM_status: std_logic;
signal s_MEM_err: std_logic;
signal s_rom_data_out: std_logic_vector(7 downto 0);
signal s_rom_done: std_logic;
signal s_rom_chip_select: std_logic;
signal s_rom_err: std_logic;
signal s_ram_data_out: std_logic_vector(7 downto 0);
signal s_ram_done: std_logic;
signal s_ram_chip_select: std_logic;
signal s_ram_err: std_logic;
signal s_clk_100, s_clk_200, s_clk_25, locked: std_logic;
begin
s_MEM_data_out <= s_ram_data_out when ( s_MEM_ram = '1' ) else s_rom_data_out;
s_MEM_status <= s_ram_done when ( s_MEM_ram = '1' ) else s_rom_done;
s_MEM_err <= s_ram_err when ( s_MEM_ram = '1' ) else s_rom_err;
s_ram_chip_select <= s_MEM_ram;
s_rom_chip_select <= not s_MEM_ram;
s_clk <= clk;
s_rst <= rst;
status <= s_status;
s_DEBUG_halt <= DEBUG_halt;
-- LEDS out
LED <= s_LED;
-- UART out
UART_TXD <= s_UART_TXD;
s_UART_RXD <= UART_RXD;
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => s_clk_100,
clk_200MHz_o => s_clk_200,
clk_25MHz_o => s_clk_25,
locked => locked
);
my_shell: shell
port map(
clk_100 => s_clk_100,
clk_25 => s_clk_25,
rst => s_rst,
status => s_status,
DEBUG_halt => s_DEBUG_halt,
-- LEDS out
LED => s_LED,
-- UART out
UART_TXD => s_UART_TXD,
UART_RXD => s_UART_RXD,
-- ROM / RAM lines --
MEM_addr => s_MEM_addr,
MEM_data_in => s_MEM_data_in,
MEM_data_out => s_MEM_data_out,
MEM_ram => s_MEM_ram,
MEM_write => s_MEM_write,
MEM_request => s_MEM_request,
MEM_status => s_MEM_status,
MEM_err => s_MEM_err
);
my_ram: stub_ram_int
port map(
memAddress => s_MEM_addr,
dataIn => s_MEM_data_in,
dataOut => s_ram_data_out,
valid => s_MEM_request,
done => s_ram_done,
write => s_MEM_write,
chip_select => s_ram_chip_select,
err => s_ram_err,
clk => s_clk_25,
reset => s_rst
);
my_rom: rom_intf
port map(
memAddress => s_MEM_addr,
dataIn => s_MEM_data_in,
dataOut => s_rom_data_out,
valid => s_MEM_request,
done => s_rom_done,
write => s_MEM_write,
chip_select => s_rom_chip_select,
err => s_rom_err,
clk => s_clk_100,
rst => s_rst,
cs_n => cs_n,
dq => dq
);
end Behavioral;
| mit | ce557aaa46f7e6ecdbc7c072b3efa6c9 | 0.49578 | 3.365328 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/ALU.vhd | 2 | 19,558 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_BIT.ALL;
library config;
use work.config.all;
entity ALU is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end ALU;
architecture Behavioral of ALU is
-- component declaration
component Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end component;
-- Signals and constants
constant all_bits_set : doubleword := (others => '1');
signal result: doubleword;
signal feedback: std_logic_vector(2 downto 0); -- (Error, Overflow, Zero)
signal mul_reg: std_logic_vector(127 downto 0);
signal mul_reg_plus: std_logic_vector(129 downto 0); -- Special case for MULSHU
signal add_word: doubleword;
-- Shift unit signals
signal s_shift_amt: std_logic_vector(5 downto 0);
signal s_shift_arg: doubleword;
signal s_shift_result: doubleword;
begin
-- Instantiation
myShifter : Shifter
port map(
clk => clk,
rst => rst,
ctrl => ctrl,
i_a1 => s_shift_arg, -- Operand 1
i_a2 => s_shift_amt, -- Shift bits number
result => s_shift_result
);
process(clk, rst)
begin
-- shift_arg <= to_integer(unsigned(shamt));
feedback <= "000";
if(rising_edge(clk)) then
if('0' = halt) then
if('1' = rst) then
result <= (others => '0');
else
case ctrl is
-- Treat as 32-bit operands
when instr_SLL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRA =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADD =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
when instr_ADDI =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_SUB =>
result <= std_logic_vector(signed(rs1) - signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_LUI =>
-- In brief: rd = sign_extend(rsimm20 << 12)
-- Load low 20 of immediate value shifted left 12
-- sign extend to fit 64 bit system
result(31 downto 0) <= rs1(19 downto 0) & "000000000000";
result(63 downto 32) <= (others => rs1(19));
when instr_AUIPC =>
-- TODO verify that PC can easily be passed in here as arg 1
-- In brief: rd = PC + (rs << 12)
-- Load 20 MSBs of low word with low 20 of immediate value
-- sign extend (rs << 12) to fit 64 bit
-- NOTE: Here, we use a "qualified expression" to hint at how the compiler should resolve
-- the ambiguity. We give a hint as to which overloaded function should be used,
-- in this case, the one that takes in a bit vector constant and a std_logic_vector
-- and returns a std_logic_vector.
--auipc_ext(31 downto 0) := std_logic_vector'(rs2(19 downto 0) & "000000000000");
result <= std_logic_vector(signed(rs1) + signed(std_logic_vector'(rs2(19 downto 0) & "000000000000")));
when instr_XOR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_XORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_OR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_ORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_AND =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_ANDI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_SLT =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTI =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTIU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLLW =>
-- Since these are word operations instead of double
-- word operations, only use the bottom 5 bits instead of 6
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADDW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_ADDIW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_SUBW =>
add_word <= std_logic_vector(signed(rs1) - signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_MUL =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= mul_reg(63 downto 0);
when instr_MULH =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= zero_word & mul_reg(63 downto 32);
when instr_MULHU =>
mul_reg <= std_logic_vector(unsigned(rs1) * unsigned(rs2));
result <= zero_word & mul_reg(63 downto 32);
--when instr_MULHSU =>
-- TODO - verify that this multiplier does not introduce problems on the schematic/layout
--mul_reg_plus <= std_logic_vector(signed(rs1(31) & rs1) * signed('0' & rs2));
--result <= zero_word & mul_reg_plus(63 downto 32);
--
-- Special Values for Divide by Zero and Division Overflow (per 2.2 spec)
-- Situation || Special Return Values for Each Instruction
-- <condition> <Dividend> <Divisor> || <DIVU> <REMU> <DIV> <REM>
-- Divide by 0 x 0 || All bits set x -1 x
-- Overflow -(2^64 -1) -1 || N/A N/A -(2^(64-1)) 0
--
when instr_DIV =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set only MSB
mul_reg <= (63 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) / signed(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_DIVU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) / unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_REM =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) rem signed(rs2));
end if;
result(31 downto 0) <= mul_reg(31 downto 0);
result(63 downto 32) <= (others => mul_reg(31));
when instr_REMU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) rem unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_MULW =>
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) * signed(rs2(31 downto 0)));
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set only MSB
mul_reg <= (31 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) / signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) / unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) rem signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) rem unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when others =>
-- Error condition: unknown control code
feedback(0) <= '1';
result <= (others => '0');
end case;
end if; -- Reset
end if; -- Halt
end if; -- Clock
end process;
error <= feedback(0); -- TODO feedback single bit for error conditions.
overflow <= '0';--feedback(1);-- TODO check here, remove from logic above
zero <= '1' when (0 = unsigned(result)) else '0';
rout <= result;
end Behavioral; | mit | 293568585f625b4e8754c701d5616e8e | 0.390735 | 4.956412 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/sim/TxRxSim.vhd | 1 | 13,884 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:50:52 08/18/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/testBed/ethernet/TxRxSim.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EthFrameRx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TxRxSim IS
END TxRxSim;
ARCHITECTURE behavior OF TxRxSim IS
--Inputs
signal ethClk : std_logic := '0';
signal ethRst : std_logic := '0';
signal userData : std_logic_vector(7 downto 0) := (others => '0');
signal userDataValid : std_logic := '0';
signal userDataLastByte : std_logic := '0';
--signal userDataCount : std_logic_vector(10 downto 0) := (others => '0');
signal idleCount : std_logic_vector(10 downto 0) := (others => '0');
signal macData : EthMacDataType;
signal txMacAddress : MacAddrType := MAC_ADDR_DEFAULT_C;
signal rxMacAddress : MacAddrType := ( 5 => x"A1",
4 => x"B2",
3 => x"C3",
2 => x"D4",
1 => x"E5",
0 => x"F6" );
signal txEtherType : EtherType := ETH_TYPE_ARP_C;
signal txIpAddress : IpAddrType := ( 3 => conv_std_logic_vector(192,8),
2 => conv_std_logic_vector(168,8),
1 => conv_std_logic_vector(1,8),
0 => conv_std_logic_vector(2,8) );
signal rxIpAddress : IpAddrType := IP_ADDR_DEFAULT_C;
-- MAC frame TX
signal macTxData : std_logic_vector(7 downto 0) := (others => '0');
signal macTxDataValid : std_logic := '0';
signal macTxDataLastByte : std_logic := '0';
signal macTxDataReady : std_logic := '0';
-- Ethernet frame TX
signal ethTxData : std_logic_vector(7 downto 0) := (others => '0');
signal ethTxDataValid : std_logic := '0';
signal ethTxDataLastByte : std_logic := '0';
signal ethTxDataReady : std_logic := '0';
-- ARP TX interfave
signal arpReq : std_logic := '0';
signal arpAck : std_logic := '0';
-- MAC frame RX
signal macRxData : std_logic_vector(7 downto 0) := (others => '0');
signal macRxDataValid : std_logic := '0';
signal macRxDataLast : std_logic := '0';
signal macRxBadFrame : std_logic := '0';
-- Ethernet frame RX
signal ethRxEtherType : EtherType := ETH_TYPE_INIT_C;
signal ethRxSrcMac : MacAddrType := MAC_ADDR_INIT_C;
signal ethRxDestMac : MacAddrType := MAC_ADDR_INIT_C;
signal ethRxData : std_logic_vector(7 downto 0);
signal ethRxDataValid : std_logic;
signal ethRxDataLast : std_logic;
-- ARP packet RX
signal arpSenderMac : MacAddrType;
signal arpSenderIp : IpAddrType;
signal arpTargetMac : MacAddrType;
signal arpTargetIp : IpAddrType;
signal arpValid : sl;
-- Clock period definitions
constant ethClk_period : time := 8 ns;
constant GATE_DELAY_C : time := 1 ns;
BEGIN
-- Transmit data from Tx
U_MacTx : entity work.Eth1000BaseXMacTx
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- User data to be sent
userDataIn => macTxData,
userDataValid => macTxDataValid,
userDataLastByte => macTxDataLastByte,
userDataReady => macTxDataReady,
-- Data out to the GTX
macDataOut => macData
);
-- Ethernet Type II Frame Transmitter
U_EthFrameTx : entity work.EthFrameTx
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Data for the header
ethTxDestMac => rxMacAddress,
ethTxSrcMac => txMacAddress,
ethTxEtherType => txEtherType,
-- User data to be sent
ethTxDataIn => ethTxData,
ethTxDataValid => ethTxDataValid,
ethTxDataLastByte => ethTxDataLastByte,
ethTxDataReady => ethTxDataReady,
-- Data output
macTxDataOut => macTxData,
macTxDataValid => macTxDataValid,
macTxDataLastByte => macTxDataLastByte,
macTxDataReady => macTxDataReady
);
-- ARP Packet Transmitter
U_ArpPacketTx : entity work.ArpPacketTx
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Data to send
arpSenderMac => txMacAddress,
arpSenderIp => txIpAddress,
arpTargetMac => rxMacAddress,
arpTargetIp => rxIpAddress,
arpOp => ARP_OP_REQ_C,
arpReq => arpReq,
arpAck => arpAck,
-- User data to be sent
ethTxData => ethTxData,
ethTxDataValid => ethTxDataValid,
ethTxDataLastByte => ethTxDataLastByte,
ethTxDataReady => ethTxDataReady
);
------------------------------------------------------------------
-- Receive into the Rx
U_MacRx : entity work.Eth1000BaseXMacRx
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Incoming data from the 16-to-8 mux
macDataIn => macData,
-- Outgoing bytes and flags to the applications
macRxData => macRxData,
macRxDataValid => macRxDataValid,
macRxDataLast => macRxDataLast,
macRxBadFrame => macRxBadFrame,
-- Monitoring flags
macBadCrcCount => open
);
-- Ethernet Type II Frame Receiver
U_EthFrameRx : entity work.EthFrameRx
port map (
ethRxClk => ethClk,
ethRxRst => ethRst,
macAddress => rxMacAddress,
macRxData => macRxData,
macRxDataValid => macRxDataValid,
macRxDataLast => macRxDataLast,
macRxBadFrame => macRxBadFrame,
ethRxEtherType => ethRxEtherType,
ethRxSrcMac => ethRxSrcMac,
ethRxDestMac => ethRxDestMac,
ethRxData => ethRxData,
ethRxDataValid => ethRxDataValid,
ethRxDataLast => ethRxDataLast
);
-- ARP Packet Receiver
U_ArpPacketRx : entity work.ArpPacketRx
port map (
ethRxClk => ethClk,
ethRxRst => ethRst,
ethRxSrcMac => ethRxSrcMac,
ethRxDestMac => ethRxDestMac,
ethRxData => ethRxData,
ethRxDataValid => ethRxDataValid,
ethRxDataLast => ethRxDataLast,
-- Received data from ARP packet
arpSenderMac => arpSenderMac,
arpSenderIp => arpSenderIp,
arpTargetMac => arpTargetMac,
arpTargetIp => arpTargetIp,
arpValid => arpValid
);
-- Clock process definitions
ethRxClk_process :process
begin
ethClk <= '0';
wait for ethClk_period/2;
ethClk <= '1';
wait for ethClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
ethRst <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
ethRst <= '0';
wait for ethClk_period*10;
-- insert stimulus here
wait;
end process;
data_proc : process(ethClk) begin
if rising_edge(ethClk) then
if ethRst = '1' then
arpReq <= '0';
idleCount <= (others => '0') after GATE_DELAY_C;
else
if (idleCount = 10) then
arpReq <= '1';
if (arpAck = '1') then
arpReq <= '0';
-- idleCount <= (others => '0');
idleCount <= idleCount + 1;
end if;
elsif idleCount < 10 then
idleCount <= idleCount + 1;
end if;
end if;
end if;
end process;
-- data_proc : process(ethClk)
-- variable userDataCount : slv(10 downto 0) := (others => '0');
-- begin
-- if rising_edge(ethClk) then
-- if ethRst = '1' then
-- userData <= (others => '0') after GATE_DELAY_C;
-- userDataValid <= '0' after GATE_DELAY_C;
-- userDataLastByte <= '0' after GATE_DELAY_C;
-- userDataCount := (others => '0');-- after GATE_DELAY_C;
-- idleCount <= (others => '0') after GATE_DELAY_C;
-- else
-- if (userDataReady = '1') then
-- userDataCount := userDataCount + 1;
-- end if;
-- if (idleCount > 10) then
-- userDataValid <= '1' after GATE_DELAY_C;
-- userDataLastByte <= '0' after GATE_DELAY_C;
-- -- if (userDataCount = 0) then userData <= rxMacAddress(0);
-- -- elsif (userDataCount = 1) then userData <= rxMacAddress(1);
-- -- elsif (userDataCount = 2) then userData <= rxMacAddress(2);
-- -- elsif (userDataCount = 3) then userData <= rxMacAddress(3);
-- -- elsif (userDataCount = 4) then userData <= rxMacAddress(4);
-- -- elsif (userDataCount = 5) then userData <= rxMacAddress(5);
-- -- elsif (userDataCount = 6) then userData <= txMacAddress(0);
-- -- elsif (userDataCount = 7) then userData <= txMacAddress(1);
-- -- elsif (userDataCount = 8) then userData <= txMacAddress(2);
-- -- elsif (userDataCount = 9) then userData <= txMacAddress(3);
-- -- elsif (userDataCount = 10) then userData <= txMacAddress(4);
-- -- elsif (userDataCount = 11) then userData <= txMacAddress(5);
-- --elsif (userDataCount = 0) then userData <= getByte(1,ETH_TYPE_ARP_C);
-- --elsif (userDataCount = 1) then userData <= getByte(0,ETH_TYPE_ARP_C);
-- if (userDataCount = 0) then userData <= getByte(1,ARP_HTYPE_C);
-- elsif (userDataCount = 1) then userData <= getByte(0,ARP_HTYPE_C);
-- elsif (userDataCount = 2) then userData <= getByte(1,ARP_PTYPE_C);
-- elsif (userDataCount = 3) then userData <= getByte(0,ARP_PTYPE_C);
-- elsif (userDataCount = 4) then userData <= getByte(0,ARP_HLEN_C);
-- elsif (userDataCount = 5) then userData <= getByte(0,ARP_PLEN_C);
-- elsif (userDataCount = 6) then userData <= getByte(1,ARP_OP_REQ_C);
-- elsif (userDataCount = 7) then userData <= getByte(0,ARP_OP_REQ_C);
-- elsif (userDataCount = 8) then userData <= txMacAddress(5);
-- elsif (userDataCount = 9) then userData <= txMacAddress(4);
-- elsif (userDataCount = 10) then userData <= txMacAddress(3);
-- elsif (userDataCount = 11) then userData <= txMacAddress(2);
-- elsif (userDataCount = 12) then userData <= txMacAddress(1);
-- elsif (userDataCount = 13) then userData <= txMacAddress(0);
-- elsif (userDataCount = 14) then userData <= txIpAddress(3);
-- elsif (userDataCount = 15) then userData <= txIpAddress(2);
-- elsif (userDataCount = 16) then userData <= txIpAddress(1);
-- elsif (userDataCount = 17) then userData <= txIpAddress(0);
-- elsif (userDataCount = 18) then userData <= MAC_ADDR_BCAST_C(5);
-- elsif (userDataCount = 19) then userData <= MAC_ADDR_BCAST_C(4);
-- elsif (userDataCount = 20) then userData <= MAC_ADDR_BCAST_C(3);
-- elsif (userDataCount = 21) then userData <= MAC_ADDR_BCAST_C(2);
-- elsif (userDataCount = 22) then userData <= MAC_ADDR_BCAST_C(1);
-- elsif (userDataCount = 23) then userData <= MAC_ADDR_BCAST_C(0);
-- elsif (userDataCount = 24) then userData <= rxIpAddress(3);
-- elsif (userDataCount = 25) then userData <= rxIpAddress(2);
-- elsif (userDataCount = 26) then userData <= rxIpAddress(1);
-- elsif (userDataCount = 27) then userData <= rxIpAddress(0);
-- userDataLastByte <= '1';
-- else
-- userDataValid <= '0' after GATE_DELAY_C;
-- -- idleCount <= (others => '0') after GATE_DELAY_C;
-- userDataCount := (others => '0');-- after GATE_DELAY_C;
-- end if;
-- else
-- idleCount <= idleCount + 1 after GATE_DELAY_C;
-- end if;
-- end if;
-- end if;
-- end process;
END;
| lgpl-2.1 | dcf4b599f7e899d32f6348aaf40b0a9d | 0.5345 | 4.621838 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp.vhd | 1 | 9,179 | -------------------------------------------------------------------------------
--! @file onewire_idtemp.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief 1-wire ID and temperature sensor interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
--! @brief Entity declaration of onewire_idtemp
--! @details Memory: 16 bytes per device = 64 bits ID + 64 bits scratch pad
entity onewire_idtemp is
generic (
--! System clock frequency in Hz
clk_frequency_g : natural := 40e6;
--! Maximum number of devices on a bus
max_devices_g : positive := 16;
--! Invert 1-wire bus RX and TX signals
invert_bus_g : boolean := false;
--! Invert strong pull-up signal
invert_pullup_g : boolean := false);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Status and control signals
--! @{
--! Discover devices on the 1-wire bus
discover_i : in std_ulogic;
--! Convert and retrieve temperature values
get_temp_i : in std_ulogic;
--! Busy flag
busy_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! Number of detected devices
device_count_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g + 1)))) - 1 downto 0);
--! Error flag if too many devices are detected
error_too_many_o : out std_ulogic;
--! @}
--! @name Memory interface
--! @{
--! Address
rd_addr_i : in std_ulogic_vector(natural(ceil(log2(real(max_devices_g * 2)))) - 1 downto 0);
--! Read enable
rd_en_i : in std_ulogic;
--! Data output
rd_data_o : out std_ulogic_vector(63 downto 0);
--! Data output enable
rd_data_en_o : out std_ulogic;
--! Busy flag
rd_busy_o : out std_ulogic;
--! @}
--! @name Bus interface
--! @{
--! Enable strong pull-up circuit to provide more current during temperature conversion
strong_pullup_o : out std_ulogic;
--! Input
rx_i : in std_ulogic;
--! Output
tx_o : out std_ulogic);
--! @}
end entity onewire_idtemp;
--! RTL implementation of onewire_idtemp
architecture rtl of onewire_idtemp is
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal rx : std_ulogic;
signal tx : std_ulogic;
signal strong_pullup : std_ulogic;
signal if_bus_rst : std_ulogic;
signal if_send : std_ulogic;
signal if_tx_data : std_ulogic;
signal if_recv : std_ulogic;
signal if_rx_data : std_ulogic;
signal if_rx_data_en : std_ulogic;
signal if_done : std_ulogic;
signal mem_wr_addr : std_ulogic_vector(rd_addr_i'range);
signal mem_wr_en : std_ulogic;
signal mem_wr_data : std_ulogic_vector(63 downto 0);
signal mem_wr_done : std_ulogic;
signal mem_rd_addr : std_ulogic_vector(rd_addr_i'range);
signal mem_rd_en : std_ulogic;
signal mem_rd_data : std_ulogic_vector(63 downto 0);
signal mem_rd_data_en : std_ulogic;
signal mem_rd_busy : std_ulogic;
signal dcvr_start : std_ulogic;
signal dcvr_id : std_ulogic_vector(63 downto 0);
signal dcvr_id_en : std_ulogic;
signal dcvr_done : std_ulogic;
signal dcvr_bus_rst : std_ulogic;
signal dcvr_bit_send : std_ulogic;
signal dcvr_bit_tx : std_ulogic;
signal dcvr_bit_recv : std_ulogic;
signal dcvr_bit_rx : std_ulogic;
signal dcvr_bit_rx_en : std_ulogic;
signal dcvr_bit_done : std_ulogic;
signal ctrl_wr_addr : std_ulogic_vector(rd_addr_i'range);
signal ctrl_wr_en : std_ulogic;
signal ctrl_wr_data : std_ulogic_vector(63 downto 0);
signal ctrl_wr_done : std_ulogic;
signal ctrl_rd_addr : std_ulogic_vector(rd_addr_i'range);
signal ctrl_rd_en : std_ulogic;
signal ctrl_rd_data : std_ulogic_vector(63 downto 0);
signal ctrl_rd_data_en : std_ulogic;
signal ctrl_bus_rst : std_ulogic;
signal ctrl_bit_send : std_ulogic;
signal ctrl_bit_tx : std_ulogic;
signal ctrl_bit_recv : std_ulogic;
signal ctrl_bit_rx : std_ulogic;
signal ctrl_bit_rx_en : std_ulogic;
signal ctrl_bit_done : std_ulogic;
signal ctrl_busy : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
-- The 1-wire transceiver circuit might invert the signal level
tx_o <= (not tx) when invert_bus_g else tx;
strong_pullup_o <= (not strong_pullup) when invert_pullup_g else strong_pullup;
busy_o <= ctrl_busy;
rd_data_o <= mem_rd_data;
rd_data_en_o <= mem_rd_data_en and (not ctrl_busy);
rd_busy_o <= mem_rd_busy or ctrl_busy;
-----------------------------------------------------------------------------
-- Signal Assignments
-----------------------------------------------------------------------------
-- The 1-wire transceiver circuit might invert the signal level
rx <= (not rx_i) when invert_bus_g else rx_i;
if_bus_rst <= dcvr_bus_rst or ctrl_bus_rst;
if_send <= dcvr_bit_send or ctrl_bit_send;
if_tx_data <= dcvr_bit_tx or ctrl_bit_tx;
if_recv <= dcvr_bit_recv or ctrl_bit_recv;
dcvr_bit_rx <= if_rx_data;
dcvr_bit_rx_en <= if_rx_data_en;
dcvr_bit_done <= if_done;
ctrl_bit_rx <= if_rx_data;
ctrl_bit_rx_en <= if_rx_data_en;
ctrl_bit_done <= if_done;
mem_wr_addr <= ctrl_wr_addr;
mem_wr_en <= ctrl_wr_en or dcvr_id_en;
mem_wr_data <= dcvr_id when dcvr_id_en = '1' else ctrl_wr_data;
ctrl_wr_done <= mem_wr_done;
mem_rd_addr <= ctrl_rd_addr when ctrl_rd_en = '1' else rd_addr_i;
mem_rd_en <= rd_en_i or ctrl_rd_en;
ctrl_rd_data <= mem_rd_data;
ctrl_rd_data_en <= mem_rd_data_en and ctrl_busy;
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
interface_inst : entity work.onewire_interface
generic map (
clk_frequency_g => clk_frequency_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
bus_rst_i => if_bus_rst,
send_i => if_send,
data_i => if_tx_data,
recv_i => if_recv,
data_o => if_rx_data,
data_en_o => if_rx_data_en,
done_o => if_done,
rx_i => rx,
tx_o => tx);
discover_inst : entity work.onewire_discover
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
discover_i => dcvr_start,
id_o => dcvr_id,
id_en_o => dcvr_id_en,
done_o => dcvr_done,
bus_rst_o => dcvr_bus_rst,
bit_send_o => dcvr_bit_send,
bit_o => dcvr_bit_tx,
bit_recv_o => dcvr_bit_recv,
bit_i => dcvr_bit_rx,
bit_en_i => dcvr_bit_rx_en,
bit_done_i => dcvr_bit_done);
ctrl_inst : entity work.onewire_control
generic map (
clk_frequency_g => clk_frequency_g,
max_devices_g => max_devices_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
discover_i => discover_i,
get_temp_i => get_temp_i,
busy_o => ctrl_busy,
done_o => done_o,
device_count_o => device_count_o,
error_too_many_o => error_too_many_o,
strong_pullup_o => strong_pullup,
discover_o => dcvr_start,
id_en_i => dcvr_id_en,
done_i => dcvr_done,
mem_wr_addr_o => ctrl_wr_addr,
mem_wr_en_o => ctrl_wr_en,
mem_wr_data_o => ctrl_wr_data,
mem_wr_done_i => ctrl_wr_done,
mem_rd_addr_o => ctrl_rd_addr,
mem_rd_en_o => ctrl_rd_en,
mem_rd_data_i => ctrl_rd_data,
mem_rd_data_en_i => ctrl_rd_data_en,
bus_rst_o => ctrl_bus_rst,
bit_send_o => ctrl_bit_send,
bit_o => ctrl_bit_tx,
bit_recv_o => ctrl_bit_recv,
bit_i => ctrl_bit_rx,
bit_en_i => ctrl_bit_rx_en,
bit_done_i => ctrl_bit_done);
ram_inst : entity work.two_port_ram_tmr
generic map (
depth_g => 2 * max_devices_g,
width_g => rd_data_o'length)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => mem_wr_addr,
wr_en_i => mem_wr_en,
wr_data_i => mem_wr_data,
wr_done_o => mem_wr_done,
wr_busy_o => open,
rd_addr_i => mem_rd_addr,
rd_en_i => mem_rd_en,
rd_data_o => mem_rd_data,
rd_data_en_o => mem_rd_data_en,
rd_busy_o => mem_rd_busy);
end architecture rtl;
| lgpl-2.1 | 19f9d3c874901d270acbc7fe4a2c8f8e | 0.527399 | 3.250354 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/decode.vhd | 1 | 22,863 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Decode Unit
-- Determines the intruction type
-- Parses out all possible fields (whether or not they are relevant)
-- May sign extend and prepare a full immediate address, I'm not sure if
-- this is the right place to do this yet. For now, just pulls the 12 or 20 bit
-- raw immediate value based on instruction type. See config.vhd for typedefs and constants
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity decoder is
Port(
instr : in std_logic_vector(31 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20);
sext_imm12 : out std_logic_vector(63 downto 0);
sext_imm20 : out std_logic_vector(63 downto 0);
reg_A : out integer;
reg_B : out integer;
reg_C : out integer;
reg_D : out integer
);
end decoder;
architecture Behavioral of decoder is
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_instr_t: instr_t;
signal s_shamt: std_logic_vector(4 downto 0);
signal s_csr: std_logic_vector(11 downto 0);
signal s_rs1 : reg_t;
signal s_rs2 : reg_t;
signal s_rs3 : reg_t;
signal s_rd : reg_t;
begin
-- Update instruction type whenever it changes
process(instr)
begin
s_imm12 <= (others => '0');
s_imm20 <= (others => '0');
s_instr_t<= (others => '1');
s_shamt <= (others => '0');
s_csr <= (others => '0');
case instr(6 downto 0) is
when LUI_T => ----
s_instr_t <= instr_LUI;
s_imm20 <= instr(31 downto 12);
when AUIPC_T =>
s_instr_t <= instr_AUIPC;
s_imm20 <= instr(31 downto 12);
when JAL_T =>
s_instr_t <= instr_JAL;
s_imm20 <= instr(31) & instr(19 downto 12) & instr(20) & instr(30 downto 21);
when JALR_T =>
s_instr_t <= instr_JALR;
s_imm12 <= instr(31 downto 20);
when BRANCH_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_BEQ;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "001" =>
s_instr_t <= instr_BNE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "100" =>
s_instr_t <= instr_BLT;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "101" =>
s_instr_t <= instr_BGE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "110" =>
s_instr_t <= instr_BLTU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "111" =>
s_instr_t <= instr_BGEU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when others => -- error state
end case;
when LOAD_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_LB;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_LH;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_LW;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_LBU;
s_imm12 <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_LHU;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_LWU;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_LD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when STORE_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_SB;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "001" =>
s_instr_t <= instr_SH;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "010" =>
s_instr_t <= instr_SW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_SD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => -- error state
end case;
when ALUI_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDI;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_SLTI;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_SLTIU;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_XORI;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_ORI;
s_imm12 <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_ANDI;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLI;
s_shamt <= instr(24 downto 20);
when "101" =>
if (instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAI;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLI;
s_shamt <= instr(24 downto 20);
end if;
when others => -- error state
end case;
when ALU_T =>
if(instr(31 downto 25)="0000001") then
-- Case RV32M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MUL;
when "001" => s_instr_t <= instr_MULH;
when "010" => s_instr_t <= instr_MULHSU;
when "011" => s_instr_t <= instr_MULHU;
when "100" => s_instr_t <= instr_DIV;
when "101" => s_instr_t <= instr_DIVU;
when "110" => s_instr_t <= instr_REM;
when "111" => s_instr_t <= instr_REMU;
when others => -- error state
end case;
else
-- Case RV32I
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUB;
else
s_instr_t <= instr_ADD;
end if;
when "001" =>
s_instr_t <= instr_SLL;
when "010" =>
s_instr_t <= instr_SLT;
when "011" =>
s_instr_t <= instr_SLTU;
when "100" =>
s_instr_t <= instr_XOR;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRA;
else
s_instr_t <= instr_SRL;
end if;
when "110" =>
s_instr_t <= instr_OR;
when "111" =>
s_instr_t <= instr_AND;
when others => -- error state
end case;
end if;
when FENCE_T =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FENCE;
else
s_instr_t <= instr_FENCEI;
end if;
when CSR_T =>
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 20) = "000000000000") then
s_instr_t <= instr_EBREAK;
elsif(instr(31 downto 20) = "000000000001") then
s_instr_t <= instr_ECALL;
elsif(instr(31 downto 20) = "000000000010") then
s_instr_t <= instr_URET;
elsif(instr(31 downto 20) = "000100000010") then
s_instr_t <= instr_SRET;
elsif(instr(31 downto 20) = "001100000010") then
s_instr_t <= instr_MRET;
elsif(instr(31 downto 20) = "000100000101") then
s_instr_t <= instr_WFI;
elsif(instr(31 downto 25) = "0001001") then
s_instr_t <= instr_SFENCEVM;
else
end if;
when "001" =>
s_instr_t <= instr_CSRRW;
s_csr <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_CSRRS;
s_csr <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_CSRRC;
s_csr <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_CSRRWI;
s_csr <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_CSRRSI;
s_csr <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_CSRRCI;
s_csr <= instr(31 downto 20);
when others => -- error state
end case;
when ALUW_T =>
if(instr(31 downto 25) = "0000001") then
-- Case RV64M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MULW;
when "100" => s_instr_t <= instr_DIVW;
when "101" => s_instr_t <= instr_DIVUW;
when "110" => s_instr_t <= instr_REMW;
when "111" => s_instr_t <= instr_REMUW;
when others => --error state
end case;
else
-- Case 64I ALU
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUBW;
else
s_instr_t <= instr_ADDW;
end if;
when "001" =>
s_instr_t <= instr_SLLW;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAW;
else
s_instr_t <= instr_SRLW;
end if;
when others => -- error state
end case;
end if;
when ALUIW_T =>
-- case RV64I
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDIW;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLIW;
s_shamt <= instr(24 downto 20);
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAIW;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLIW;
s_shamt <= instr(24 downto 20);
end if;
when others => --error state
end case;
when ATOM_T =>
if(instr(14 downto 12)="011") then
-- case RV64A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRD;
when "00011" => s_instr_t <= instr_SCD;
when "00001" => s_instr_t <= instr_AMOSWAPD;
when "00000" => s_instr_t <= instr_AMOADDD;
when "00100" => s_instr_t <= instr_AMOXORD;
when "01100" => s_instr_t <= instr_AMOANDD;
when "01000" => s_instr_t <= instr_AMOORD;
when "10000" => s_instr_t <= instr_AMOMIND;
when "10100" => s_instr_t <= instr_AMOMAXD;
when "11000" => s_instr_t <= instr_AMOMINUD;
when "11100" => s_instr_t <= instr_AMOMAXUD;
when others => --error state
end case;
else
-- case RV32A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRW;
when "00011" => s_instr_t <= instr_SCW;
when "00001" => s_instr_t <= instr_AMOSWAPW;
when "00000" => s_instr_t <= instr_AMOADDW;
when "00100" => s_instr_t <= instr_AMOXORW;
when "01100" => s_instr_t <= instr_AMOANDW;
when "01000" => s_instr_t <= instr_AMOORW;
when "10000" => s_instr_t <= instr_AMOMINW;
when "10100" => s_instr_t <= instr_AMOMAXW;
when "11000" => s_instr_t <= instr_AMOMINUW;
when "11100" => s_instr_t <= instr_AMOMAXUW;
when others => --error state
end case;
end if;
when FLOAD_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FLW;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_FLD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when FSTORE_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FSW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_FSD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => --error state
end case;
when FMADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMADDS;
else
s_instr_t <= instr_FMADDD;
end if;
when FMSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMSUBS;
else
s_instr_t <= instr_FMSUBD;
end if;
when FNADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMADDS;
else
s_instr_t <= instr_FNMADDD;
end if;
when FNSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMSUBS;
else
s_instr_t <= instr_FNMSUBD;
end if;
when FPALU_T =>
case instr(31 downto 25) is
when "0000000" =>
s_instr_t <= instr_FADDS;
when "0000100" =>
s_instr_t <= instr_FSUBS;
when "0001000" =>
s_instr_t <= instr_FMULS;
when "0001100" =>
s_instr_t <= instr_FDIVS;
when "0101100" =>
s_instr_t <= instr_FSQRTS;
when "0010000" =>
if (instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJS;
elsif (instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJNS;
else
s_instr_t <= instr_FSGNJXS;
end if;
when "0010100" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMINS;
else
s_instr_t <= instr_FMAXS;
end if;
when "1100000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWS;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUS;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLS;
else
s_instr_t <= instr_FCVTLUS;
end if;
when "1110000" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMVXW;
else
s_instr_t <= instr_FCLASSS;
end if;
when "1010000" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQS;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTS;
else
s_instr_t <= instr_FLES;
end if;
when "1101000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTSW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTSWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTSL;
else
s_instr_t <= instr_FCVTSLU;
end if;
when "1111000" =>
s_instr_t <= instr_FMVWX;
when "0000001" =>
s_instr_t <= instr_FADDD;
when "0000101" =>
s_instr_t <= instr_FSUBD;
when "0001001" =>
s_instr_t <= instr_FMULD;
when "0001101" =>
s_instr_t <= instr_FDIVD;
when "0101101" =>
s_instr_t <= instr_FSQRTD;
when "0010001" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJND;
else
s_instr_t <= instr_FSGNJXD;
end if;
when "0010101" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMIND;
else
s_instr_t <= instr_FMAXD;
end if;
when "0100000" =>
s_instr_t <= instr_FCVTSD;
when "0100001" =>
s_instr_t <= instr_FCVTDS;
when "1010001" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTD;
else
s_instr_t <= instr_FLED;
end if;
when "1110001" =>
if(instr(14 downto 12) = "001") then
s_instr_t <= instr_FCLASSD;
else
s_instr_t <= instr_FMVXD;
end if;
when "1100001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWD;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUD;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLD;
else
s_instr_t <= instr_FCVTLUD;
end if;
when "1101001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTDW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTDWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTDL;
else
s_instr_t <= instr_FCVTDLU;
end if;
when "1111001" =>
s_instr_t <= instr_FMVDX;
when others => --error state
end case;
when others => -- error state
end case;
end process;
s_rd <= instr(11 downto 7);
s_rs1 <= instr(19 downto 15);
s_rs2 <= instr(24 downto 20);
s_rs3 <= instr(31 downto 27);
rd <= s_rd;
rs1 <= s_rs1;
rs2 <= s_rs2;
rs3 <= s_rs3;
reg_A <= to_integer(unsigned(s_rs1));
reg_B <= to_integer(unsigned(s_rs2));
reg_C <= to_integer(unsigned(s_rs3));
reg_D <= to_integer(unsigned(s_rd));
funct3 <= instr(14 downto 12);
funct6 <= instr(31 downto 26);
funct7 <= instr(31 downto 25);
opcode <= instr(6 downto 0);
imm12 <= s_imm12;
imm20 <= s_imm20;
shamt <= s_shamt;
csr <= s_csr;
instr_code <= s_instr_t;
sext_imm12(63 downto 12) <= (others => s_imm12(11));
sext_imm12(11 downto 0) <= s_imm12;
sext_imm20(63 downto 20) <= (others => s_imm20(19));
sext_imm20(19 downto 0) <= s_imm20;
end Behavioral;
| mit | b13d6f07faf729c01b35125054f096dd | 0.398329 | 4.230755 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/ps2_iobase.vhd | 1 | 6,163 | -------------------------------------------------------------------------------
-- Title : MC613
-- Project : PS2 Basic Protocol
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : ps2_base.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/04/12
-------------------------------------------------------------------------------
-- Description:
-- PS2 basic control
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity ps2_iobase is
generic(
clkfreq : integer -- This is the system clock value in kHz
);
port(
ps2_data : inout std_logic; -- PS2 data pin
ps2_clk : inout std_logic; -- PS2 clock pin
clk : in std_logic; -- system clock (same frequency as defined in
-- 'clkfreq' generic)
en : in std_logic; -- Enable
resetn : in std_logic; -- Reset when '0'
idata_rdy : in std_logic; -- Rise this to signal data is ready to be sent
-- to device
idata : in std_logic_vector(7 downto 0); -- Data to be sent to device
send_rdy : out std_logic; -- '1' if data can be sent to device (wait for
-- this before rising 'idata_rdy'
odata_rdy : out std_logic; -- '1' when data from device has arrived
odata : out std_logic_vector(7 downto 0) -- Data from device
);
end;
architecture rtl of ps2_iobase is
constant CLKSSTABLE : integer := clkfreq / 150;
signal sdata, hdata : std_logic_vector(7 downto 0);
signal sigtrigger, parchecked, sigsending,
sigsendend, sigclkreleased, sigclkheld : std_logic;
begin
-- Trigger for state change to eliminate noise
process(clk, ps2_clk, en, resetn)
variable fcount, rcount : integer range CLKSSTABLE downto 0;
begin
if(rising_edge(clk) and en = '1') then
-- Falling edge noise
if ps2_clk = '0' then
rcount := 0;
if fcount >= CLKSSTABLE then
sigtrigger <= '1';
else
fcount := fcount + 1;
end if;
-- Rising edge noise
elsif ps2_clk = '1' then
fcount := 0;
if rcount >= CLKSSTABLE then
sigtrigger <= '0';
else
rcount := rcount + 1;
end if;
end if;
end if;
if resetn = '0' then
fcount := 0;
rcount := 0;
sigtrigger <= '0';
end if;
end process;
FROMPS2:
process(sigtrigger, sigsending, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigsending = '0') then
if count > 0 and count < 9 then
sdata(count - 1) <= ps2_data;
end if;
if count = 9 then
if (not (sdata(0) xor sdata(1) xor sdata(2) xor sdata(3)
xor sdata(4) xor sdata(5) xor sdata(6) xor sdata(7))) = ps2_data then
parchecked <= '1';
else
parchecked <= '0';
end if;
end if;
count := count + 1;
if count = 11 then
count := 0;
parchecked <= '0';
end if;
end if;
if resetn = '0' or sigsending = '1' then
sdata <= (others => '0');
parchecked <= '0';
count := 0;
end if;
end process;
odata_rdy <= en and parchecked;
odata <= sdata;
-- Edge triggered send register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
sigsending <= '1';
end if;
if resetn = '0' or sigsendend = '1' then
sigsending <= '0';
end if;
end process;
-- Wait for at least 11ms before allowing to send again
process(clk, sigsending, resetn)
-- clkfreq is the number of clocks within a milisecond
variable countclk : integer range 0 to (12 * clkfreq);
begin
if(rising_edge(clk) and sigsending = '0') then
if countclk = (11 * clkfreq) then
send_rdy <= '1';
else
countclk := countclk + 1;
end if;
end if;
if sigsending = '1' then
send_rdy <= '0';
countclk := 0;
end if;
if resetn = '0' then
send_rdy <= '1';
countclk := 0;
end if;
end process;
-- Host input data register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
hdata <= idata;
end if;
if resetn = '0' or sigsendend = '1' then
hdata <= (others => '0');
end if;
end process;
-- PS2 clock control
process(clk, sigsendend, resetn)
constant US100CNT : integer := clkfreq / 10;
variable count : integer range 0 to US100CNT + 101;
begin
if(rising_edge(clk) and sigsending = '1') then
if count < US100CNT + 50 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '0';
elsif count < US100CNT + 100 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '1';
else
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
end if;
end if;
if resetn = '0' or sigsendend = '1' then
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
count := 0;
end if;
end process;
-- Sending control
TOPS2:
process(sigtrigger, sigsending, sigclkheld, sigclkreleased, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigclkreleased = '1'
and sigsending = '1') then
if count >= 0 and count < 8 then
ps2_data <= hdata(count);
sigsendend <= '0';
end if;
if count = 8 then
ps2_data <= (not (hdata(0) xor hdata(1) xor hdata(2) xor hdata(3)
xor hdata(4) xor hdata(5) xor hdata(6) xor hdata(7)));
sigsendend <= '0';
end if;
if count = 9 then
ps2_data <= 'Z';
sigsendend <= '0';
end if;
if count = 10 then
ps2_data <= 'Z';
sigsendend <= '1';
count := 0;
end if;
count := count + 1;
end if;
if sigclkheld = '1' then
ps2_data <= '0';
sigsendend <= '0';
count := 0;
end if;
if resetn = '0' or sigsending = '0' then
ps2_data <= 'Z';
sigsendend <= '0';
count := 0;
end if;
end process;
end rtl;
| mit | 942a93a1d5debd49aace759e62f56e90 | 0.547947 | 3.185013 | false | false | false | false |
gau-veldt/InsideTheBox | Ep0003/AudioEcho_ACK.vhd | 1 | 10,558 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2017 12:34:40 AM
-- Design Name:
-- Module Name: AudioEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AudioEcho is
port (
led : out std_logic_vector(3 downto 0); -- Pretty light show for debugging stuff
clk_125 : in std_logic; -- 125 MHz Zybo clock
ac_sda : inout std_logic; -- I2C data
ac_scl : inout std_logic -- I2C clock
);
end AudioEcho;
architecture Driver of AudioEcho is
signal led_st : std_logic_vector(3 downto 0) := "0000"; -- output register for leds
subtype tCount is unsigned(31 downto 0); -- type alias: 32-bit unsigned integer
constant cZero : tCount := to_unsigned(0,tCount'length); -- zero constant
constant cMod : tCount := to_unsigned(2,tCount'length); -- 2/cMod is divider period in seconds
constant cMax : tCount := to_unsigned(125000000,tCount'length); -- input clock frequency constant
signal my_clk : std_logic := '0'; -- divider output
signal r_sda_i : std_logic := '1'; -- I2C sda input register
signal r_sda_o : std_logic := '1'; -- I2C sda output register
signal r_scl_i : std_logic := '1'; -- I2C scl input register
signal r_scl_o : std_logic := '1'; -- I2C scl output register
-- enumeration of audio configuration state machine states
type ac_states is (
acsInit,
acsStart,
acsA7pre,
acsA7set,
acsA7out,
acsA6pre,
acsA6set,
acsA6out,
acsA5pre,
acsA5set,
acsA5out,
acsA4pre,
acsA4set,
acsA4out,
acsA3pre,
acsA3set,
acsA3out,
acsA2pre,
acsA2set,
acsA2out,
acsA1pre,
acsA1set,
acsA1out,
acsWpre,
acsWset,
acsWout,
acsWACKpre,
acsWACKfloat,
acsWACKclk,
acsWACKtest,
acsStop,
acsForceStop,
acsForceStop2,
acsForceStop3,
acsSpin
);
signal ac_state : ac_states := acsInit;
signal ac_good : std_logic := '0';
begin
-- clock divider
divider: process(clk_125) is
variable dCur : tCount := cZero;
begin
if (rising_edge(clk_125)) then
dCur:=dCur+cMod;
if (dCur >= cMax) then
dCur := dCur - cMax;
my_clk <= not my_clk;
end if;
end if;
end process divider;
-- state machine for I2C
audioconf : process(my_clk) is
begin
-- NB: On the Zybo board only two slaves (EEPROM and SSM2603)
-- are present on the I2C bus thus we are the only master
-- in the system thus there is no need for arbitration logic.
if (rising_edge(my_clk)) then
case ac_state is
-- Initial state
when acsInit =>
-- Use a counter to pause the minimum initialization
-- duration before transitioning to starting condition.
ac_state <= acsStart;
-- Starting condition
when acsStart =>
if (r_scl_i='1' and r_sda_i='1') then
-- signal START on the bus
r_sda_o<='0';
ac_state <= acsA7pre;
else
-- still waiting for SCL=1 and SDA=1
ac_state <= acsStart;
end if;
-- each bit sent takes three states
-- since for I2C it is required to transition SDA
-- *after* the SCL low edge and not at the same
-- time (a device might register SDA before our
-- clock in that event and misinterpret a STOP
-- signal if SDA becomes 1 on this cycle when SDA
-- was 0 on the previous cycle since we'd have
-- set SCL to 1 to transmit that bit).
when acsA7pre => -- Call SSM2603 address for write (R=1, W=0):
r_scl_o<='0'; -- 0 0 1 1 0 1 0 W
ac_state<=acsA7set;
when acsA7set =>
r_sda_o<='0'; -- 0
ac_state<=acsA7out;
when acsA7out =>
r_scl_o<='1';
ac_state <= acsA6pre;
when acsA6pre =>
r_scl_o<='0';
ac_state<=acsA6set;
when acsA6set =>
r_sda_o<='0'; -- - 0
ac_state<=acsA6out;
when acsA6out =>
r_scl_o<='1';
ac_state <= acsA5pre;
when acsA5pre =>
r_scl_o<='0';
ac_state<=acsA5set;
when acsA5set =>
r_sda_o<='1'; -- - - 1
ac_state<=acsA5out;
when acsA5out =>
r_scl_o<='1';
ac_state <= acsA4pre;
when acsA4pre =>
r_scl_o<='0';
ac_state<=acsA4set;
when acsA4set =>
r_sda_o<='1'; -- - - - 1
ac_state<=acsA4out;
when acsA4out =>
r_scl_o<='1';
ac_state <= acsA3pre;
when acsA3pre =>
r_scl_o<='0';
ac_state<=acsA3set;
when acsA3set =>
r_sda_o<='0'; -- - - - - 0
ac_state<=acsA3out;
when acsA3out =>
r_scl_o<='1';
ac_state <= acsA2pre;
when acsA2pre =>
r_scl_o<='0';
ac_state<=acsA2set;
when acsA2set =>
r_sda_o<='1'; -- - - - - - 1
ac_state<=acsA2out;
when acsA2out =>
r_scl_o<='1';
ac_state <= acsA1pre;
when acsA1pre =>
r_scl_o<='0';
ac_state<=acsA1set;
when acsA1set =>
r_sda_o<='0'; -- - - - - - - 0
ac_state<=acsA1out;
when acsA1out =>
r_scl_o<='1';
ac_state <= acsWpre;
when acsWpre =>
r_scl_o<='0';
ac_state<=acsWset;
when acsWset =>
r_sda_o<='0'; -- - - - - - - - W
ac_state<=acsWout;
when acsWout =>
r_scl_o<='1';
ac_state <= acsWACKpre;
-- On the ackknowledge there's a similar pattern
-- first we'll lower the clock THEN float SDA
-- THEN raise the clock THEN test SDA for
-- ACK/NACK. THENs mean delay is necessary
-- thus requiring a different state for each
-- step so they span different clock cycles
when acsWACKpre =>
r_scl_o<='0'; -- lower clock
ac_state<=acsWACKfloat;
when acsWACKfloat =>
r_sda_o<='1'; -- SDA floats to 1
ac_state<=acsWACKclk;
when acsWACKclk =>
r_scl_o<='1'; -- raise clock
ac_state<=acsWACKtest;
when acsWACKtest =>
-- if all is right SDA should be low at this point
if (r_sda_i='0') then
ac_good<='1';
end if;
ac_state<=acsForceStop;
-- forcibly stop:
-- lower SCL
-- lower SDA
-- raise SCL
-- raise SDA
when acsForceStop =>
r_scl_o<='0';
ac_state <= acsForceStop2;
when acsForceStop2 =>
r_sda_o<='0';
ac_state <= acsForceStop3;
when acsForceStop3 =>
r_scl_o<='1';
ac_state <= acsStop;
when acsStop =>
r_sda_o<='1';
ac_state <= acsSpin;
-- Halted (infinite loop)
when acsSpin =>
ac_state <= acsSpin;
-- Catch-all: enter halted state
when others =>
ac_state <= acsSpin;
end case;
end if;
end process audioconf;
-- i2c output registers to i2c lines
with r_sda_o select
ac_sda <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
with r_scl_o select
ac_scl <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
-- i2c lines to i2c input registers
with ac_sda select
r_sda_i <= '0' when '0',
'1' when others;
with ac_scl select
r_scl_i <= '0' when '0',
'1' when others;
-- transfer led output register to led output lines
led_st(0) <= r_sda_i;
led_st(1) <= r_scl_i;
led_st(2) <= ac_good;
led_st(3) <= my_clk;
led <= led_st;
end Driver; | gpl-3.0 | ab039a04c6cff72304c94c0557a3ba51 | 0.431237 | 4.361008 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/decode.vhd | 2 | 22,081 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Decode Unit
-- Determines the intruction type
-- Parses out all possible fields (whether or not they are relevant)
-- May sign extend and prepare a full immediate address, I'm not sure if
-- this is the right place to do this yet. For now, just pulls the 12 or 20 bit
-- raw immediate value based on instruction type. See config.vhd for typedefs and constants
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end decode;
architecture Behavioral of decode is
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_instr_t: instr_t;
signal s_shamt: std_logic_vector(4 downto 0);
signal s_csr: std_logic_vector(11 downto 0);
begin
-- Update instruction type whenever it changes
process(instr)
begin
s_imm12 <= (others => '0');
s_imm20 <= (others => '0');
s_instr_t<= (others => '1');
s_shamt <= (others => '0');
s_csr <= (others => '0');
case instr(6 downto 0) is
when LUI_T =>
s_instr_t <= instr_LUI;
s_imm20 <= instr(31 downto 12);
when AUIPC_T =>
s_instr_t <= instr_AUIPC;
s_imm20 <= instr(31 downto 12);
when JAL_T =>
s_instr_t <= instr_JAL;
s_imm20 <= instr(31) & instr(19 downto 12) & instr(20) & instr(30 downto 21);
when JALR_T =>
s_instr_t <= instr_JALR;
s_imm12 <= instr(31 downto 20);
when BRANCH_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_BEQ;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "001" =>
s_instr_t <= instr_BNE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "100" =>
s_instr_t <= instr_BLT;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "101" =>
s_instr_t <= instr_BGE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "110" =>
s_instr_t <= instr_BLTU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "111" =>
s_instr_t <= instr_BGEU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when others => -- error state
end case;
when LOAD_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_LB;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_LH;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_LW;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_LBU;
s_imm12 <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_LHU;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_LWU;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_LD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when STORE_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_SB;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "001" =>
s_instr_t <= instr_SH;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "010" =>
s_instr_t <= instr_SW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_SD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => -- error state
end case;
when ALUI_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDI;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_SLTI;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_SLTIU;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_XORI;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_ORI;
s_imm12 <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_ANDI;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLI;
s_shamt <= instr(24 downto 20);
when "101" =>
if (instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAI;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLI;
s_shamt <= instr(24 downto 20);
end if;
when others => -- error state
end case;
when ALU_T =>
if(instr(31 downto 25)="0000001") then
-- Case RV32M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MUL;
when "001" => s_instr_t <= instr_MULH;
when "010" => s_instr_t <= instr_MULHSU;
when "011" => s_instr_t <= instr_MULHU;
when "100" => s_instr_t <= instr_DIV;
when "101" => s_instr_t <= instr_DIVU;
when "110" => s_instr_t <= instr_REM;
when "111" => s_instr_t <= instr_REMU;
when others => -- error state
end case;
else
-- Case RV32I
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUB;
else
s_instr_t <= instr_ADD;
end if;
when "001" =>
s_instr_t <= instr_SLL;
when "010" =>
s_instr_t <= instr_SLT;
when "011" =>
s_instr_t <= instr_SLTU;
when "100" =>
s_instr_t <= instr_XOR;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRA;
else
s_instr_t <= instr_SRL;
end if;
when "110" =>
s_instr_t <= instr_OR;
when "111" =>
s_instr_t <= instr_AND;
when others => -- error state
end case;
end if;
when FENCE_T =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FENCE;
else
s_instr_t <= instr_FENCEI;
end if;
when CSR_T =>
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 20) = "000000000000") then
s_instr_t <= instr_EBREAK;
elsif(instr(31 downto 20) = "000000000001") then
s_instr_t <= instr_ECALL;
elsif(instr(31 downto 20) = "000000000010") then
s_instr_t <= instr_URET;
elsif(instr(31 downto 20) = "000100000010") then
s_instr_t <= instr_SRET;
elsif(instr(31 downto 20) = "001100000010") then
s_instr_t <= instr_MRET;
elsif(instr(31 downto 20) = "000100000101") then
s_instr_t <= instr_WFI;
elsif(instr(31 downto 25) = "0001001") then
s_instr_t <= instr_SFENCEVM;
else
end if;
when "001" =>
s_instr_t <= instr_CSRRW;
s_csr <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_CSRRS;
s_csr <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_CSRRC;
s_csr <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_CSRRWI;
s_csr <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_CSRRSI;
s_csr <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_CSRRCI;
s_csr <= instr(31 downto 20);
when others => -- error state
end case;
when ALUW_T =>
if(instr(31 downto 25) = "0000001") then
-- Case RV64M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MULW;
when "100" => s_instr_t <= instr_DIVW;
when "101" => s_instr_t <= instr_DIVUW;
when "110" => s_instr_t <= instr_REMW;
when "111" => s_instr_t <= instr_REMUW;
when others => --error state
end case;
else
-- Case 64I ALU
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUBW;
else
s_instr_t <= instr_ADDW;
end if;
when "001" =>
s_instr_t <= instr_SLLW;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAW;
else
s_instr_t <= instr_SRLW;
end if;
when others => -- error state
end case;
end if;
when ALUIW_T =>
-- case RV64I
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDIW;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLIW;
s_shamt <= instr(24 downto 20);
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAIW;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLIW;
s_shamt <= instr(24 downto 20);
end if;
when others => --error state
end case;
when ATOM_T =>
if(instr(14 downto 12)="011") then
-- case RV64A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRD;
when "00011" => s_instr_t <= instr_SCD;
when "00001" => s_instr_t <= instr_AMOSWAPD;
when "00000" => s_instr_t <= instr_AMOADDD;
when "00100" => s_instr_t <= instr_AMOXORD;
when "01100" => s_instr_t <= instr_AMOANDD;
when "01000" => s_instr_t <= instr_AMOORD;
when "10000" => s_instr_t <= instr_AMOMIND;
when "10100" => s_instr_t <= instr_AMOMAXD;
when "11000" => s_instr_t <= instr_AMOMINUD;
when "11100" => s_instr_t <= instr_AMOMAXUD;
when others => --error state
end case;
else
-- case RV32A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRW;
when "00011" => s_instr_t <= instr_SCW;
when "00001" => s_instr_t <= instr_AMOSWAPW;
when "00000" => s_instr_t <= instr_AMOADDW;
when "00100" => s_instr_t <= instr_AMOXORW;
when "01100" => s_instr_t <= instr_AMOANDW;
when "01000" => s_instr_t <= instr_AMOORW;
when "10000" => s_instr_t <= instr_AMOMINW;
when "10100" => s_instr_t <= instr_AMOMAXW;
when "11000" => s_instr_t <= instr_AMOMINUW;
when "11100" => s_instr_t <= instr_AMOMAXUW;
when others => --error state
end case;
end if;
when FLOAD_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FLW;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_FLD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when FSTORE_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FSW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_FSD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => --error state
end case;
when FMADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMADDS;
else
s_instr_t <= instr_FMADDD;
end if;
when FMSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMSUBS;
else
s_instr_t <= instr_FMSUBD;
end if;
when FNADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMADDS;
else
s_instr_t <= instr_FNMADDD;
end if;
when FNSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMSUBS;
else
s_instr_t <= instr_FNMSUBD;
end if;
when FPALU_T =>
case instr(31 downto 25) is
when "0000000" =>
s_instr_t <= instr_FADDS;
when "0000100" =>
s_instr_t <= instr_FSUBS;
when "0001000" =>
s_instr_t <= instr_FMULS;
when "0001100" =>
s_instr_t <= instr_FDIVS;
when "0101100" =>
s_instr_t <= instr_FSQRTS;
when "0010000" =>
if (instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJS;
elsif (instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJNS;
else
s_instr_t <= instr_FSGNJXS;
end if;
when "0010100" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMINS;
else
s_instr_t <= instr_FMAXS;
end if;
when "1100000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWS;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUS;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLS;
else
s_instr_t <= instr_FCVTLUS;
end if;
when "1110000" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMVXW;
else
s_instr_t <= instr_FCLASSS;
end if;
when "1010000" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQS;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTS;
else
s_instr_t <= instr_FLES;
end if;
when "1101000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTSW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTSWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTSL;
else
s_instr_t <= instr_FCVTSLU;
end if;
when "1111000" =>
s_instr_t <= instr_FMVWX;
when "0000001" =>
s_instr_t <= instr_FADDD;
when "0000101" =>
s_instr_t <= instr_FSUBD;
when "0001001" =>
s_instr_t <= instr_FMULD;
when "0001101" =>
s_instr_t <= instr_FDIVD;
when "0101101" =>
s_instr_t <= instr_FSQRTD;
when "0010001" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJND;
else
s_instr_t <= instr_FSGNJXD;
end if;
when "0010101" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMIND;
else
s_instr_t <= instr_FMAXD;
end if;
when "0100000" =>
s_instr_t <= instr_FCVTSD;
when "0100001" =>
s_instr_t <= instr_FCVTDS;
when "1010001" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTD;
else
s_instr_t <= instr_FLED;
end if;
when "1110001" =>
if(instr(14 downto 12) = "001") then
s_instr_t <= instr_FCLASSD;
else
s_instr_t <= instr_FMVXD;
end if;
when "1100001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWD;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUD;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLD;
else
s_instr_t <= instr_FCVTLUD;
end if;
when "1101001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTDW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTDWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTDL;
else
s_instr_t <= instr_FCVTDLU;
end if;
when "1111001" =>
s_instr_t <= instr_FMVDX;
when others => --error state
end case;
when others => -- error state
end case;
end process;
rd <= instr(11 downto 7);
rs1 <= instr(19 downto 15);
rs2 <= instr(24 downto 20);
rs3 <= instr(31 downto 27);
funct3 <= instr(14 downto 12);
funct6 <= instr(31 downto 26);
funct7 <= instr(31 downto 25);
opcode <= instr(6 downto 0);
imm12 <= s_imm12;
imm20 <= s_imm20;
shamt <= s_shamt;
csr <= s_csr;
instr_code <= s_instr_t;
end Behavioral;
| mit | ea240ca01ef02315e0cfb575510abe9b | 0.392192 | 4.33641 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/S6/rtl/S6EthTop.vhd | 1 | 13,712 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:31 07/23/2015
-- Design Name:
-- Module Name: S6EthTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity S6EthTop is
generic (
NUM_IP_G : integer := 2;
GATE_DELAY_G : time := 1 ns
);
port (
-- Direct GT connections
gtTxP : out sl;
gtTxN : out sl;
gtRxP : in sl;
gtRxN : in sl;
gtClkP : in sl;
gtClkN : in sl;
-- Alternative clock input from fabric
fabClkIn : in sl := '0';
-- SFP transceiver disable pin
txDisable : out sl;
-- Clocks out from Ethernet core
ethUsrClk62 : out sl;
ethUsrClk125 : out sl;
-- Status and diagnostics out
ethSync : out sl;
ethReady : out sl;
led : out slv(15 downto 0);
-- Core settings in
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
ipAddrs : in IpAddrArray(NUM_IP_G-1 downto 0) := (others => IP_ADDR_DEFAULT_C);
udpPorts : in Word16Array(NUM_IP_G-1 downto 0) := (others => (others => '0'));
-- User clock inputs
userClk : in sl;
userRstIn : in sl;
userRstOut : out sl;
-- User data interfaces
userTxData : in Word32Array(NUM_IP_G-1 downto 0);
userTxDataValid : in slv(NUM_IP_G-1 downto 0);
userTxDataLast : in slv(NUM_IP_G-1 downto 0);
userTxDataReady : out slv(NUM_IP_G-1 downto 0);
userRxData : out Word32Array(NUM_IP_G-1 downto 0);
userRxDataValid : out slv(NUM_IP_G-1 downto 0);
userRxDataLast : out slv(NUM_IP_G-1 downto 0);
userRxDataReady : in slv(NUM_IP_G-1 downto 0)
);
end S6EthTop;
architecture Behavioral of S6EthTop is
signal fabClk : sl;
signal fabClkRst : sl;
signal gtClk : sl;
signal ethClk62 : sl;
signal ethClk62Rst : sl;
signal ethClk125 : sl;
signal ethClk125Rst : sl;
signal dcmClkValid : sl;
signal dcmSpLocked : sl;
signal usrClkValid : sl;
signal usrClkLocked : sl;
signal pllLock0 : sl;
signal gtpResetDone0 : sl;
signal gtpReset0 : sl;
signal gtpReset1 : sl;
signal txReset0 : sl;
signal txReset1 : sl;
signal rxReset0 : sl;
signal rxReset1 : sl;
signal rxBufReset0 : sl;
signal rxBufReset1 : sl;
signal rxBufStatus0 : slv(2 downto 0);
signal rxBufStatus1 : slv(2 downto 0);
signal txBufStatus0 : slv(1 downto 0);
signal txBufStatus1 : slv(1 downto 0);
signal rxBufError0 : sl;
signal rxBufError1 : sl;
signal rxByteAligned0 : sl;
signal rxByteAligned1 : sl;
signal rxEnMCommaAlign0 : sl;
signal rxEnMCommaAlign1 : sl;
signal rxEnPCommaAlign0 : sl;
signal rxEnPCommaAlign1 : sl;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
signal phyRxLaneIn : EthRxPhyLaneInType;
signal phyTxLaneOut : EthTxPhyLaneOutType;
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl;
signal tpDataReady : sl;
signal userRst : sl;
begin
txDisable <= '0';
ethSync <= ethRxLinkSync;
ethReady <= ethAutoNegDone;
ethUsrClk62 <= ethClk62;
ethUsrClk125 <= ethClk125;
userRstOut <= userRst;
led(0) <= dcmSpLocked;
led(1) <= dcmClkValid;
led(2) <= not(gtpReset0);
led(3) <= gtpResetDone0;
led(4) <= pllLock0;
led(5) <= usrClkLocked;
led(6) <= usrClkValid;
led(7) <= ethRxLinkSync;
led(8) <= ethAutoNegDone;
led(9) <= not(ethClk62Rst);
led(10) <= not(ethClk125Rst);
led(15 downto 11) <= (others => '1');
fabClk <= fabClkIn;
U_IBUFDS : IBUFDS port map ( I => gtClkP, IB => gtClkN, O => gtClk);
U_GtpS6 : entity work.GtpS6
generic map (
-- Reference clock selection --
-- 000: CLK00/CLK01 selected
-- 001: GCLK00/GCLK01 selected
-- 010: PLLCLK00/PLLCLK01 selected
-- 011: CLKINEAST0/CLKINEAST0 selected
-- 100: CLK10/CLK11 selected
-- 101: GCLK10/GCLK11 selected
-- 110: PLLCLK10/PLLCLK11 selected
-- 111: CLKINWEST0/CLKINWEST1 selected
REF_SEL_PLL0_G => "001",
REF_SEL_PLL1_G => "001"
)
port map (
-- Clocking & reset
gtpClkIn => fabClk,
gtpReset0 => gtpReset0,
gtpReset1 => gtpReset1,
txReset0 => txReset0,
txReset1 => txReset1,
rxReset0 => rxReset0,
rxReset1 => rxReset1,
rxBufReset0 => rxBufReset0,
rxBufReset1 => rxBufReset1,
-- User clock out
usrClkOut => ethClk62,
usrClkX2Out => ethClk125,
-- DCM clocking
dcmClkValid => dcmClkValid,
dcmSpLocked => dcmSpLocked,
usrClkValid => usrClkValid,
usrClkLocked => usrClkLocked,
-- General status outputs
pllLock0 => pllLock0,
pllLock1 => open,
gtpResetDone0 => gtpResetDone0,
gtpResetDone1 => open,
-- Input signals (raw)
gtpRxP0 => gtRxP,
gtpRxN0 => gtRxN,
gtpTxP0 => gtTxP,
gtpTxN0 => gtTxN,
gtpRxP1 => '0',
gtpRxN1 => '0',
gtpTxP1 => open,
gtpTxN1 => open,
-- Data interfaces
rxDataOut0 => phyRxLaneIn.data,
rxDataOut1 => open,
txDataIn0 => phyTxLaneOut.data,
txDataIn1 => (others => '0'),
-- RX status
rxCharIsComma0 => open,
rxCharIsComma1 => open,
rxCharIsK0 => phyRxLaneIn.dataK,
rxCharIsK1 => open,
rxDispErr0 => phyRxLaneIn.dispErr, -- out slv(1 downto 0);
rxDispErr1 => open, -- out slv(1 downto 0);
rxNotInTable0 => phyRxLaneIn.decErr, -- out slv(1 downto 0);
rxNotInTable1 => open, -- out slv(1 downto 0);
rxRunDisp0 => open, -- out slv(1 downto 0);
rxRunDisp1 => open, -- out slv(1 downto 0);
rxClkCor0 => open, -- out slv(2 downto 0);
rxClkCor1 => open, -- out slv(2 downto 0);
rxByteAligned0 => rxByteAligned0, -- out std_logic;
rxByteAligned1 => rxByteAligned1, -- out std_logic;
rxEnMCommaAlign0 => rxEnMCommaAlign0, -- in std_logic;
rxEnMCommaAlign1 => rxEnMCommaAlign1, -- in std_logic;
rxEnPCommaAlign0 => rxEnPCommaAlign0, -- in std_logic;
rxEnPCommaAlign1 => rxEnPCommaAlign1, -- in std_logic;
rxBufStatus0 => rxBufStatus0, -- out slv(2 downto 0);
rxBufStatus1 => rxBufStatus1, -- out slv(2 downto 0);
-- TX status
txCharDispMode0 => "00", -- in slv(1 downto 0) := "00";
txCharDispMode1 => "00", -- in slv(1 downto 0) := "00";
txCharDispVal0 => "00", -- in slv(1 downto 0) := "00";
txCharDispVal1 => "00", -- in slv(1 downto 0) := "00";
txCharIsK0 => phyTxLaneOut.dataK, -- in slv(1 downto 0);
txCharIsK1 => "00", -- in slv(1 downto 0);
txRunDisp0 => open, -- out slv(1 downto 0);
txRunDisp1 => open, -- out slv(1 downto 0);
txBufStatus0 => txBufStatus0, -- out slv(1 downto 0);
txBufStatus1 => txBufStatus1, -- out slv(1 downto 0);
-- Loopback settings
loopbackIn0 => "000", -- : in slv(2 downto 0) := "000";
loopbackIn1 => "000" -- : in slv(2 downto 0) := "000";
);
-- Simple comma alignment
rxEnMCommaAlign0 <= not(rxByteAligned0);
rxEnPCommaAlign0 <= not(rxByteAligned0);
rxEnMCommaAlign1 <= not(rxByteAligned1);
rxEnPCommaAlign1 <= not(rxByteAligned1);
-- Reset sequencing, as per UG386, Table 2-14
-- Not all resets are implemented, only those for the functionality
-- we care about.
--
-- 1. Perform GTP reset after turning on the reference clock
U_GtpReset0 : entity work.SyncBit
port map (
clk => fabClk,
rst => not(dcmClkValid),
asyncBit => '0',
syncBit => gtpReset0
);
gtpReset1 <= gtpReset0;
-- 2. Assert rxReset and txReset when usrClk, usrClk2 is not stable
-- 3. txReset should be asserted on tx Buffer over/underflow
U_RxReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or not(dcmClkValid),
asyncBit => '0',
syncBit => rxReset0
);
rxReset1 <= rxReset0;
U_TxReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or txBufStatus0(1),
asyncBit => '0',
syncBit => txReset0
);
U_TxReset1 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => not(usrClkValid) or txBufStatus1(1),
asyncBit => '0',
syncBit => txReset1
);
-- 4. rxBufReset should be asserted on rx buffer over/underflow
rxBufError0 <= '1' when rxBufStatus0 = "101" or rxBufStatus0 = "110" else '0';
U_RxBufReset0 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => rxBufError0,
asyncBit => '0',
syncBit => rxBufReset0
);
rxBufError1 <= '1' when rxBufStatus1 = "101" or rxBufStatus1 = "110" else '0';
U_RxBufReset1 : entity work.SyncBit
generic map (
INIT_STATE_G => '1'
)
port map (
clk => fabClk,
rst => rxBufError1,
asyncBit => '0',
syncBit => rxBufReset1
);
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_Eth1000BaseXCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => NUM_IP_G,
MTU_SIZE_G => 1500,
LITTLE_ENDIAN_G => true,
EN_AUTONEG_G => true,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => macAddr,
ipAddrs => ipAddrs,
udpPorts => udpPorts,
-- Data to/from GT
phyRxData => phyRxLaneIn,
phyTxData => phyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => userClk,
userRst => userRst,
-- User data
userTxData => userTxData,
userTxDataValid => userTxDataValid,
userTxDataLast => userTxDataLast,
userTxDataReady => userTxDataReady,
userRxData => userRxData,
userRxDataValid => userRxDataValid,
userRxDataLast => userRxDataLast,
userRxDataReady => userRxDataReady
);
---------------------------------------------------------------------------
-- Resets
---------------------------------------------------------------------------
-- Generate stable reset signal
U_PwrUpRst : entity work.InitRst
generic map (
RST_CNT_G => 25000000,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => fabClk,
syncRst => fabClkRst
);
-- Synchronize the reset to the 125 MHz domain
U_RstSync125 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => ethClk125Rst
);
-- Synchronize the reset to the 62 MHz domain
U_RstSync62 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => fabClkRst,
syncBit => ethClk62Rst
);
-- User reset
U_RstSyncUser : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst or not(ethAutoNegDone) or userRstIn,
syncBit => userRst
);
end Behavioral;
| lgpl-2.1 | 14f1c07206828f4e7857a8c34b3c22cd | 0.512471 | 4.036503 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ddr_mig_sim.vhd | 1 | 79,921 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
--nBANK_MACHS : integer := 4;
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 7;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "DDR_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "DDR_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr_mig;
architecture arch_ddr_mig of ddr_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "TRUE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v4_0_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v4_0_iodelay_ctrl;
component mig_7series_v4_0_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v4_0_clk_ibuf;
component mig_7series_v4_0_infrastructure is
generic (
SIMULATION : string := "TRUE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
clk_div2 : out std_logic;
rst_div2 : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
-- auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v4_0_infrastructure;
component mig_7series_v4_0_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v4_0_tempmon;
component mig_7series_v4_0_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56;
SKIP_CALIB : string;
FPGA_VOLT_TYPE : string
);
port (
clk : in std_logic;
clk_div2 : in std_logic;
rst_div2 : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
rst : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_single_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
calib_tap_req : out std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_load : in std_logic;
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_poc : out std_logic_vector (1023 downto 0)
);
end component mig_7series_v4_0_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal clk_div2 : std_logic;
signal rst_div2 : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
signal device_temp_i : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v4_0_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v4_0_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v4_0_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v4_0_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
-- auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v4_0_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK,
SKIP_CALIB => "FALSE",
FPGA_VOLT_TYPE => "N"
)
port map (
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_ecc_single_err => app_ecc_single_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Ports to be used when SKIP_CALIB="TRUE"
calib_tap_req => open,
calib_tap_addr => (others => '0'),
calib_tap_load => '0',
calib_tap_val => (others => '0'),
calib_tap_load_done => '0',
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i,
dbg_poc => open
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_mig;
| mit | ee7a2ab5991204cdff466e54d4d0e419 | 0.439334 | 4.263135 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/pc.vhd | 1 | 3,176 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- PLAYER CONTROLLER
--------------------------------------------------------------------------------
-- TODO:
-- Remove output clock_o;
-- Define constants/generics instead of magic numbers
-- Change aux_x/aux_y to something more explanatory
--------------------------------------------------------------------------------
entity pc is
generic
(
-- screen limits (follows game resolution)
res_x : integer := 160;
res_y : integer := 120;
-- used to take into account the dimensions of the ship
aux_y : integer := 0;
aux_x : integer := 1;
-- y-position of the player ship
pos_y : integer := 5;
-- clock divider
clock_div : integer := 2
);
port
(
-- input commands for reset or movement
reset_i, enable_i : in std_logic;
-- movement direction ('0' = left, 1' = right)
right_flag_i : in std_logic;
-- clock input
clock_i : in std_logic;
-- player position output
clock_o : out std_logic; -- TODO: remove
position_x_o : buffer integer range 0 to res_x;
position_y_o : out integer range 0 to res_y
);
end entity;
architecture behavior of pc is
-- clock signal for updating x position
signal clock_s : std_logic;
begin
-- counter that generates the clock signal for updating x position
pc_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
-- register: keeps the position of the player ship
pc_movement:
process (reset_i, enable_i,clock_s)
begin
-- asynchronous reset of x coordinate
if reset_i = '1' then
position_x_o <= res_x/2 - aux_x/2;
else
-- move the ship according to right_flag_i input
if rising_edge(clock_s) and enable_i ='1' then
if right_flag_i = '1' then
position_x_o <= position_x_o + 1; -- move right
elsif right_flag_i = '0' then
position_x_o <= position_x_o - 1; -- move left
end if;
-- check boundaries
if position_x_o + aux_x > res_x-5 then
position_x_o <= res_x-aux_x-5;
end if;
if position_x_o < 5 then
position_x_o <= 5;
end if;
end if;
end if;
end process;
-- updates output position with new y-position
position_y_o <= pos_y + aux_y/2;
end architecture;
| mit | 2fe1ffdd3db8475e8d02d06ad5108b47 | 0.422859 | 4.66373 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/tb/MMU_tb.vhd | 1 | 5,060 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
entity MMU_tb is
end MMU_tb;
architecture Behavioral of MMU_tb is
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out doubleword; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
fkuck_vivado_so_much: out std_logic_vector(5 downto 0);
s_internal_address_out: out doubleword;
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end component;
signal clk, rst, store, load, busy, ready_instr: std_logic := '0'; -- 100 Mhz Clock
signal addr_in, data_in, satp, addr_instr, data_out, instr_out: doubleword := (others => '0');
signal alignment: std_logic_vector(3 downto 0) := (others => '0');
signal error: std_logic_vector(5 downto 0) := (others => '0');
signal LED: std_logic_vector(15 downto 0) := (others => '0');
-- For the moment all the rest open
signal UART_TXD: std_logic;
signal UART_RXD: std_logic;
signal s_fuck_vivado_so_fucking_much: std_logic_vector(5 downto 0);
signal ddr2_addr : STD_LOGIC_VECTOR (12 downto 0);
signal ddr2_ba : STD_LOGIC_VECTOR (2 downto 0);
signal ddr2_ras_n : STD_LOGIC;
signal ddr2_cas_n : STD_LOGIC;
signal ddr2_we_n : STD_LOGIC;
signal ddr2_ck_p : std_logic_vector(0 downto 0);
signal ddr2_ck_n : std_logic_vector(0 downto 0);
signal ddr2_cke : std_logic_vector(0 downto 0);
signal ddr2_cs_n : std_logic_vector(0 downto 0);
signal ddr2_dm : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_odt : std_logic_vector(0 downto 0);
signal ddr2_dq : STD_LOGIC_VECTOR (15 downto 0);
signal ddr2_dqs_p : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_dqs_n : STD_LOGIC_VECTOR (1 downto 0);
signal sck: std_logic; -- Special gated sck for the ROM STARTUPE2 generic
signal cs_n: STD_LOGIC;
signal dq: std_logic_vector(3 downto 0);
signal s_internal_address_out: doubleword;
signal counter: integer := 0;
begin
oom: MMU port map(clk => clk, rst => rst, store => store, load => load, busy => busy, ready_instr => ready_instr,
addr_in => addr_in, data_in => data_in, satp => satp, addr_instr => addr_instr, data_out => data_out,
instr_out => instr_out, alignment => alignment, error => error, LED => LED,
UART_TXD=>UART_TXD,
UART_RXD=>UART_RXD,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
fkuck_vivado_so_much => s_fuck_vivado_so_fucking_much,
s_internal_address_out => s_internal_address_out,
sck => sck,
cs_n => cs_n,
dq => dq);
process begin
if(counter < 5) then
rst <= '1';
elsif(counter = 5) then
rst <= '0';
elsif(counter = 8) then
load <= '1';
addr_in <= x"0000000080000000";
elsif(counter > 9) then
addr_in <= x"0000000080000000";
load <= '0';
end if;
counter <= counter + 1;
clk <= clk xor '1';
wait for 2 ns;
end process;
--pragma synthesis_off
--current_state <= current_state;
--pragma synthesis_on
end Behavioral; | mit | 74d5f30f201958e133712827a212ecd8 | 0.608893 | 3.0227 | false | false | false | false |
PsiStarPsi/firmware-ethernet | ExampleProject/projectSrc/scrodEthernetExample.vhd | 1 | 8,464 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:31 07/23/2015
-- Design Name:
-- Module Name: scrodEthernetExample - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity scrodEthernetExample is
generic (
REG_ADDR_BITS_G : integer := 16;
REG_DATA_BITS_G : integer := 16;
NUM_IP_G : integer := 2;
GATE_DELAY_G : time := 1 ns
);
port (
-- Direct GT connections
gtTxP : out sl;
gtTxN : out sl;
gtRxP : in sl;
gtRxN : in sl;
gtClkP : in sl;
gtClkN : in sl;
-- Alternative clock input
fabClkP : in sl;
fabClkN : in sl;
-- SFP transceiver disable pin
txDisable : out sl;
-- Status and diagnostics out
ethSync : out sl;
ethReady : out sl;
led : out slv(15 downto 0)
);
end scrodEthernetExample;
architecture Behavioral of scrodEthernetExample is
signal fabClk : sl;
signal ethClk62 : sl;
signal ethClk125 : sl;
signal userRst : sl;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
signal ethCoreMacAddr : MacAddrType := MAC_ADDR_DEFAULT_C;
signal ethCoreIpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal ethCoreIpAddr1 : IpAddrType := (3 => x"C0", 2 => x"A8", 1 => x"01", 0 => x"21");
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl;
signal tpDataReady : sl;
-- User Data interfaces
signal userTxDataChannels : Word32Array(NUM_IP_G-1 downto 0);
signal userTxDataValids : slv(NUM_IP_G-1 downto 0);
signal userTxDataLasts : slv(NUM_IP_G-1 downto 0);
signal userTxDataReadys : slv(NUM_IP_G-1 downto 0);
signal userRxDataChannels : Word32Array(NUM_IP_G-1 downto 0);
signal userRxDataValids : slv(NUM_IP_G-1 downto 0);
signal userRxDataLasts : slv(NUM_IP_G-1 downto 0);
signal userRxDataReadys : slv(NUM_IP_G-1 downto 0);
-- Register control interfaces
signal regAddr : slv(REG_ADDR_BITS_G-1 downto 0);
signal regWrData : slv(REG_DATA_BITS_G-1 downto 0);
signal regRdData : slv(REG_DATA_BITS_G-1 downto 0);
signal regReq : sl;
signal regOp : sl;
signal regAck : sl;
-- Test registers
-- Default is to send 1000 counter words once per second.
signal waitCyclesHigh : slv(15 downto 0) := x"0773";
signal waitCyclesLow : slv(15 downto 0) := x"5940";
signal numWords : slv(15 downto 0) := x"03E8";
begin
ethSync <= ethRxLinkSync;
ethReady <= ethAutoNegDone;
U_IBUFGDS : IBUFGDS port map ( I => fabClkP, IB => fabClkN, O => fabClk);
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_S6EthTop : entity work.S6EthTop
generic map (
NUM_IP_G => 2
)
port map (
-- Direct GT connections
gtTxP => gtTxP,
gtTxN => gtTxN,
gtRxP => gtRxP,
gtRxN => gtRxN,
gtClkP => gtClkP,
gtClkN => gtClkN,
-- Alternative clock input from fabric
fabClkIn => fabClk,
-- SFP transceiver disable pin
txDisable => txDisable,
-- Clocks out from Ethernet core
ethUsrClk62 => ethClk62,
ethUsrClk125 => ethClk125,
-- Status and diagnostics out
ethSync => ethRxLinkSync,
ethReady => ethAutoNegDone,
led => led,
-- Core settings in
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr, 1 => ethCoreIpAddr1),
udpPorts => (0 => x"07D0", 1 => x"07D1"), --x7D0 = 2000,
-- User clock inputs
userClk => ethClk125,
userRstIn => '0',
userRstOut => userRst,
-- User data interfaces
userTxData => userTxDataChannels,
userTxDataValid => userTxDataValids,
userTxDataLast => userTxDataLasts,
userTxDataReady => userTxDataReadys,
userRxData => userRxDataChannels,
userRxDataValid => userRxDataValids,
userRxDataLast => userRxDataLasts,
userRxDataReady => userRxDataReadys
);
U_TpGenTx : entity work.TpGenTx
generic map (
-- NUM_WORDS_G => 1000,
-- WAIT_CYCLES_G => 100,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- User clock and reset
userClk => ethClk125,
userRst => userRst,
-- Configuration
waitCycles => waitCyclesHigh & waitCyclesLow,
numWords => x"0000" & numWords,
-- Connection to user logic
userTxData => tpData,
userTxDataValid => tpDataValid,
userTxDataLast => tpDataLast,
userTxDataReady => tpDataReady
);
-- Channel 0 TX high speed test pattern
-- RX unused
userTxDataChannels(0) <= tpData;
userTxDataValids(0) <= tpDataValid;
userTxDataLasts(0) <= tpDataLast;
tpDataReady <= userTxDataReadys(0);
-- Note that the Channel 0 RX channels are unused here
--userRxDataChannels;
--userRxDataValids;
--userRxDataLasts;
userRxDataReadys(0) <= '1';
-- Channel 1 can be modified to a a simple loopback like this:
-- userTxDataChannels(1) <= userRxDataChannels(1);
-- userTxDataValids(1) <= userRxDataValids(1);
-- userTxDataLasts(1) <= userRxDataLasts(1);
-- userRxDataReadys(1) <= userTxDataReadys(1);
-- ...
-- Instead of this:
-- Channel 1 as a command interpreter
U_CommandInterpreter : entity work.CommandInterpreter
generic map (
REG_ADDR_BITS_G => 16,
REG_DATA_BITS_G => 16,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- User clock and reset
usrClk => ethClk125,
usrRst => userRst,
-- Incoming data
rxData => userRxDataChannels(1),
rxDataValid => userRxDataValids(1),
rxDataLast => userRxDataLasts(1),
rxDataReady => userRxDataReadys(1),
-- Outgoing response
txData => userTxDataChannels(1),
txDataValid => userTxDataValids(1),
txDataLast => userTxDataLasts(1),
txDataReady => userTxDataReadys(1),
-- This board ID
myId => x"00AB",
-- Register interfaces
regAddr => regAddr,
regWrData => regWrData,
regRdData => regRdData,
regReq => regReq,
regOp => regOp,
regAck => regAck
);
-- A few registers to toy with
process(ethClk125) begin
if rising_edge(ethClk125) then
if userRst = '1' then
regAck <= '0';
regRdData <= (others => '0');
elsif regReq = '1' then
regAck <= regReq;
case regAddr is
when x"0000" => regRdData <= numWords;
if regOp = '1' then
numWords <= regWrData;
end if;
when x"0001" => regRdData <= waitCyclesHigh;
if regOp = '1' then
waitCyclesHigh <= regWrData;
end if;
when x"0002" => regRdData <= waitCyclesLow;
if regOp = '1' then
waitCyclesLow <= regWrData;
end if;
when others =>
regRdData <= (others => '0');
end case;
else
regAck <= '0';
end if;
end if;
end process;
end Behavioral;
| lgpl-2.1 | 71b7fdd94f13d1893ae634caac553548 | 0.519731 | 4.369644 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/exception.vhd | 1 | 2,250 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 04:12:40 PM
-- Module Name: exception - Behavioral
-- Description: Helper module determines if in an exception state
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity exception is
Port(
mip: in doubleword; -- Machine interrupts pending CSR
mie: in doubleword; -- Machine interrupts enabled CSR
mstatus: in doubleword; -- Machine mode status CSR
sip: in doubleword; -- Supervisor interrupts pending CSR
sie: in doubleword; -- Supervisor interrupts enabled CSR
sstatus: in doubleword; -- Supervisor mod status CSR
mdeleg: in doubleword; -- Mask for supervisor delegated Exceptions
m_enable_interrupts:in std_logic; -- Global machine interrupt enabled
s_enable_interrupts:in std_logic; -- Global supervisor interrupt enabled
interrupt_m: out std_logic; -- Take interrupt machine mode
interrupt_s: out std_logic -- Take interrupt supervisor mode
);
end exception;
architecture Behavioral of exception is
signal s_interrupt_m: std_logic; -- Machine mode output
signal s_interrupt_s: std_logic; -- Supervisor mode output
begin
process(mip,mie,sip,sie)
variable ival_m: doubleword; -- Machine mode value
variable ival_s: doubleword; -- Supervisor mode value
begin
if('1' = m_enable_interrupts) then
ival_m := mip and mie and (not mdeleg);
if(unsigned(ival_m) > 0) then
s_interrupt_m <= '1';
else
s_interrupt_m <= '0';
end if;
end if;
if('1' = s_enable_interrupts) then
ival_s := sip and sie and mdeleg;
if(unsigned(ival_m) > 0) then
s_interrupt_m <= '1';
else
s_interrupt_m <= '0';
end if;
end if;
end process;
interrupt_m <= s_interrupt_m;
interrupt_s <= s_interrupt_s;
end Behavioral;
| mit | 103adacffeaa6df96eab2a145d73b350 | 0.570667 | 4.310345 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp_pkg.vhd | 1 | 1,368 | -------------------------------------------------------------------------------
--! @file onewire_idtemp_pkg.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Constants for the 1-wire ID and temperature sensor interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of onewire_idtemp_pkg
package onewire_idtemp_pkg is
-----------------------------------------------------------------------------
-- Types and Constants
-----------------------------------------------------------------------------
--! DS18B20 ID and temperature sensor family code
constant code_ds18b20_c : std_ulogic_vector(7 downto 0) := x"28";
--! DS2401 ID family code
constant code_ds2401_c : std_ulogic_vector(7 downto 0) := x"01";
--! Search command
constant cmd_search_c : std_ulogic_vector(7 downto 0) := x"F0";
--! Match ROM command
constant cmd_match_c : std_ulogic_vector(7 downto 0) := x"55";
--! Skip ROM command
constant cmd_skip_c : std_ulogic_vector(7 downto 0) := x"CC";
--! Convert command
constant cmd_convert_c : std_ulogic_vector(7 downto 0) := x"44";
--! Read scratchpad
constant cmd_read_sp_c : std_ulogic_vector(7 downto 0) := x"BE";
end package onewire_idtemp_pkg;
| lgpl-2.1 | 077ce432061e383830808493b0da1fa5 | 0.521199 | 4.183486 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/example_design/rtl/example_top.vhd | 1 | 34,078 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
-- generic (
-- #parameters_user_design_top_component#
-- RST_ACT_LOW : integer
-- );
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v4_0_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
MASK_SIZE : integer := 8;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
CMDS_GAP_DELAY : std_logic_vector(5 downto 0) := "000000";
SEL_VICTIM_LINE : integer := 8;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
EYE_TEST : string;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
tg_only_rst : in std_logic;
manual_clear_error : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH))-1 downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v4_0_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector((64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK))-1 downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
-- generic map (
-- #parameters_mapping_user_design_top_instance#
-- RST_ACT_LOW => RST_ACT_LOW
-- )
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst(0) or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v4_0_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error(0),
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8)-1 downto 0),
memc_wr_data => app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic(0),
vio_modify_enable => vio_modify_enable(0),
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen(0),
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w(0),
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => tg_wr_data_counts,
rd_data_counts => tg_rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done(0)
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable(0) <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen(0) <= '0';
vio_pause_traffic(0) <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error(0) <= '0';
po_win_tg_rst <= '0';
vio_tg_rst(0) <= '0';
wdt_en_w(0) <= '1';
dbg_sel_pi_incdec(0) <= '0';
dbg_sel_po_incdec(0) <= '0';
dbg_pi_f_inc(0) <= '0';
dbg_pi_f_dec(0) <= '0';
dbg_po_f_inc(0) <= '0';
dbg_po_f_dec(0) <= '0';
dbg_po_f_stg23_sel(0) <= '0';
end architecture arch_example_top;
| mit | 4b051e8af6c4bdc27ed70afd963ec557 | 0.451963 | 4.107268 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/stub_ram.vhd | 1 | 1,031 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity stub_ram is
Port (
address : in STD_LOGIC_VECTOR (13 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end stub_ram;
architecture Behavioral of stub_ram is
type RAM is array ( ( 16 * 1024 ) - 1 downto 0 ) of std_logic_vector( 7 downto 0 );
signal sys_RAM : RAM := (
others => ( others => '0')
);
signal read_address : std_logic_vector( 13 downto 0 );
begin
process ( clock )
begin
if ( rising_edge( clock ) ) then
if( we = '1' ) then
sys_RAM( to_integer( unsigned( address ))) <= dataIn;
end if;
read_address <= address;
end if;
end process;
dataOut <= sys_RAM( to_integer( unsigned( read_address )));
end Behavioral;
| mit | 3d8dbcc5f7963c1e07ffc0552bdef9be | 0.519884 | 3.980695 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Sext.vhd | 1 | 957 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 02/11/2018 03:24:43 PM
-- Module Name: sext - Behavioral
-- Description: Sign extender for immediate values
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity sext is
Port(
imm12: in std_logic_vector(11 downto 0);
imm20: in std_logic_vector(19 downto 0);
output_imm12: out std_logic_vector(63 downto 0);
output_imm20: out std_logic_vector(63 downto 0)
);
end sext;
architecture Behavioral of sext is
begin
output_imm12(63 downto 12) <= (others => imm12(11));
output_imm12(11 downto 0) <= imm12;
output_imm20(63 downto 20) <= (others => imm20(19));
output_imm20(19 downto 0) <= imm20;
end Behavioral;
| mit | 3ae962b2eca1570ba09a195e1c44890c | 0.53396 | 3.752941 | false | true | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/SSegDisp.vhd | 1 | 3,031 | ----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/22/2011
-- Design Name:
-- Module Name: SSegDisp
-- Project Name: 7-segment Display Controller
-- Target Devices:
-- Tool versions:
-- Description: This module is able to drive a common-cathode multi-digit
-- 7-segment display.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
entity SSegDisp is
generic (
CLOCKFREQ : natural := 100; -- in MHz
DIGITS : natural := 4
);
port (
CLK_I: in std_logic;
DATA_I: in std_logic_vector(DIGITS*4-1 downto 0);
DOTS_I: in std_logic_vector(DIGITS-1 downto 0);
AN_O: out std_logic_vector(DIGITS-1 downto 0);
CA_O: out std_logic_vector(7 downto 0)
);
end SSegDisp;
architecture Behavioral of SSegDisp is
constant DISP_FREQ : natural := 20 * DIGITS; --in kHz
constant DISP_FREQ_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000/DISP_FREQ)));
signal refreshCnt : natural range 0 to DISP_FREQ_CYCLES-1 := 0;
signal DisplayCLK: std_logic;
signal DigitNo: natural range 0 to DIGITS-1 := 0;
signal Digit: std_logic_vector(3 downto 0);
signal HexDigit: std_logic_vector(6 downto 0);
signal Dot: std_logic;
begin
with Digit select
HexDigit <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"0001001" when others; --H ???
Digit <= DATA_I(DigitNo*4+3 downto DigitNo*4);
-- Let's use Dots as active high and not confuse the user
Dot <= not DOTS_I(DigitNo);
CA_O <= Dot & HexDigit;
DIV_CLK_EN: process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (refreshCnt = DISP_FREQ_CYCLES-1) then
refreshCnt <= 0;
else
refreshCnt <= refreshCnt + 1;
end if;
end if;
end process;
CycleDIGITS: process(CLK_I)
begin
if Rising_Edge(CLK_I) then
if (refreshCnt = DISP_FREQ_CYCLES-1) then
if (DigitNo+1 = DIGITS) then
DigitNo <= 0;
else
DigitNo <= DigitNo+1;
end if;
end if;
end if;
end process CycleDIGITS;
SetAnodes: process(DigitNo)
begin
AN_O <= (others => '1');
AN_O(DigitNo) <= '0';
end process SetAnodes;
end Behavioral;
| gpl-3.0 | 0d17a40feeddab3d76952ae186d3beaf | 0.56582 | 3.252146 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/general/clock_counter.vhd | 1 | 668 | library ieee;
use ieee.std_logic_1164.all;
entity clock_counter is
generic
(
f: integer := 50000000
);
port
(
clock_i: in std_logic;
clock_o: out std_logic
);
end entity;
architecture behavior of clock_counter is
begin
process (clock_i)
variable counter: integer := 0;
begin
if rising_edge(clock_i) then
if counter < f/2 then
counter := counter + 1;
clock_o <= '0';
elsif counter < f then
counter := counter + 1;
clock_o <= '1';
end if;
if counter = f then
counter := 0;
end if;
end if;
end process;
end architecture;
| mit | 988dd9d2f8ba43970ba4085cd9554abe | 0.54491 | 3.67033 | false | false | false | false |
gau-veldt/InsideTheBox | Ep0001/my_vga.vhd | 1 | 6,291 | --
-- FPGA logic for simple VGA signal generator
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_vga is
port (
clk_125 : in std_logic;
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out unsigned(4 downto 0);
vga_g : out unsigned(5 downto 0);
vga_b : out unsigned(4 downto 0)
);
end my_vga;
architecture driver of my_vga is
subtype tPeriod is unsigned(17 downto 0);
constant pZero : tPeriod := to_unsigned(0,tPeriod'length);
subtype hvCount is unsigned(15 downto 0);
constant hvZero : hvCount := to_unsigned(0,hvCount'length);
--
-- VGA target is 800x600 @ 60 Hz
-- www.tinyvga.com yields:
-- pixel clock: 40 MHz (40000 kHz)
--
constant targetPeriod : tPeriod := to_unsigned(40000,tPeriod'length);
constant refPeriod : tPeriod := to_unsigned(62500,tPeriod'length);
--
-- frame timing:
-- H(pixels) : +sync=128, front=40, visible=800, back=88 (total: 1056)
-- V(lines) : +sync=4, front=1, visible=600, back=23 (total: 628)
-- NB: for 800x600 modes sync is active high hence why I write +sync
--
constant hSyncOn : std_logic := '1';
constant hSyncOff : std_logic := '0';
constant hSyncDur : hvCount := to_unsigned(128,hvCount'length);
constant hBackDur : hvCount := to_unsigned(88,hvCount'length);
constant hBegin : hvCount := to_unsigned(128+88,hvCount'length);
constant hCenterDur : hvCount := to_unsigned(800,hvCount'length);
constant hEnd : hvCount := to_unsigned(128+88+800,hvCount'length);
constant hFrontDur : hvCount := to_unsigned(40,hvCount'length);
constant hTotal : hvCount := to_unsigned(1056,hvCount'length);
constant vSyncOn : std_logic := '1';
constant vSyncOff : std_logic := '0';
constant vSyncDur : hvCount := to_unsigned(4,hvCount'length);
constant vBackDur : hvCount := to_unsigned(23,hvCount'length);
constant vBegin : hvCount := to_unsigned(4+23,hvCount'length);
constant vCenterDur : hvCount := to_unsigned(600,hvCount'length);
constant vEnd : hvCount := to_unsigned(4+23+600,hvCount'length);
constant vFrontDur : hvCount := to_unsigned(1,hvCount'length);
constant vTotal : hvCount := to_unsigned(628,hvCount'length);
signal pxClock : std_logic := '0';
signal p40count : tPeriod := pZero;
signal hPos : hvCount := hvZero;
signal vPos : hvCount := hvZero;
begin
--
-- clock divider to generate pixel clock
-- 125 Mhz (125000 kHz) input clock (Zybo 125 MHz ref clock L16)
--
-- We want to be 0 for half the period, then 1 for half the period.
-- We want the total duty cycle to match the pixel clock rate.
-- Thus we count in steps of 40000 to half the reference period
-- (62500) and whenever we are >= 62500 we subtract 62500, then
-- invert the pixel clock output signal.
--
-- This integer scaling is likely going to jitter like crazy however
-- VGA is somewhat forgiving in this regard and it will realign on
-- every LCM of the target and reference periods. The only way to
-- reduce the jitter is to reference from a faster clock (Zybo does
-- not have anything faster than 125 MHz) or use one of the 7010's
-- MMCM units.
--
pxClock_proc: process(clk_125) is
variable p40var : tPeriod := p40count;
begin
if (rising_edge(clk_125)) then
p40var := p40var + targetPeriod;
if (p40var >= refPeriod) then
p40var := p40var - refPeriod;
pxClock <= not pxClock;
end if;
p40count <= p40var;
end if;
end process pxClock_proc;
--
-- Next we need the H and V counters, which will be advanced on the
-- rising edges of the pixel clock
--
hv_proc: process(pxClock) is
variable hCnt : hvCount := hPos;
variable vCnt : hvCount := vPos;
begin
if (rising_edge(pxClock)) then
hCnt := hCnt + 1;
if (hCnt = hTotal) then
hCnt := hvZero;
vCnt := vCnt + 1;
if (vCnt = vTotal) then
vCnt := hvZero;
end if;
vPos <= vCnt;
end if;
hPos <= hCnt;
end if;
end process hv_proc;
--
-- Next we need to generate the sync pulses
--
-- Syncs pulses are first in the timing sequence thus
-- making it easy to check for sync active range
--
-- H sync:
hsync_proc: process(pxClock) is
begin
if (rising_edge(pxClock)) then
if (hPos < hSyncDur) then
vga_hs <= hSyncOn;
else
vga_hs <= hSyncOff;
end if;
end if;
end process hsync_proc;
-- V sync:
vsync_proc: process(pxClock) is
begin
if (rising_edge(pxClock)) then
if (vPos < vSyncDur) then
vga_vs <= vSyncOn;
else
vga_vs <= vSyncOff;
end if;
end if;
end process vsync_proc;
--
-- With H and V sync pulses taken care of means we could now generate pixel
-- data at the appropriate time, meaning when we are in both the horizontal
-- and vertical visible range.
--
pattern_proc: process(pxClock) is
variable pixH : hvCount := hvZero;
variable pixV : hvCount := hvZero;
variable tempR : unsigned(31 downto 0) := to_unsigned(0,32);
variable tempG : unsigned(31 downto 0) := to_unsigned(0,32);
variable tempB : unsigned(31 downto 0) := to_unsigned(0,32);
begin
if (rising_edge(pxClock)) then
if ((vPos >= vBegin) and (vPos < vEnd)) and ((hPos >= hBegin) and (hPos < hEnd)) then
pixV := vPos - vBegin;
pixH := hPos - hBegin;
-- generates a color gradation pattern
--tempR:=to_unsigned(0,32);
tempR:=(pixH*32)/hCenterDur;
tempG:=to_unsigned(0,32);
--tempG:=pixH*1;
--tempG:=(pixH*64)/hCenterDur;
--tempB:=to_unsigned(0,32);
--tempB:=pixV*1;
tempB:=(pixV*32)/vCenterDur;
vga_r <= tempR(4 downto 0);
vga_g <= tempG(5 downto 0);
vga_b <= tempB(4 downto 0);
else
-- Ensure pixels are zero outside of visible range.
-- We might get away with the porches (for a border color),
-- but NEVER have these nonzero during the sync pulses!
vga_r <= to_unsigned(0,vga_r'length);
vga_g <= to_unsigned(0,vga_g'length);
vga_b <= to_unsigned(0,vga_b'length);
end if;
end if;
end process pattern_proc;
end driver;
| gpl-3.0 | 1c92bc6967381c29f3f07718eb834338 | 0.631219 | 3.199898 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/simpler_core.vhd | 1 | 39,658 | ----------------------------------------------------------------------------------
-- Engineer: Longofono Modified by Avalos
--
-- Create Date: 02/10/2018 06:05:22 PM
-- Module Name: simpler_core - Behavioral
-- Description: Even Simpler version of the ALU pipeline for HW testing
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity simpler_core is
Port(
status: out std_logic; -- LED blinkenlites
CLK: in std_logic; -- Tied to switch V10
RST: in std_logic; -- Tied to switch J15
LED: out std_logic_vector(15 downto 0);
PC_Switch: in std_logic;
ALU_Switch: in std_logic;
-- UART Serial I/O
UART_RXD: in std_logic;
UART_TXD: out std_logic;
-- DDR2 signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- Debug Signals
--pragma synthesis_off
address_out: out std_logic_vector(63 downto 0);
instruction_out, instruction_address_out,load_wb_data : out std_logic_vector(63 downto 0);
reggie: out regfile_arr;
opcode: out opcode_t;
o_load_type: out std_logic_vector(7 downto 0);
ALU_result: out doubleword;
MMU_state: out std_logic_vector(5 downto 0);
--pragma synthesis_on
--ROM signals
dq: inout STD_LOGIC_VECTOR(3 downto 0);
cs_n: out STD_LOGIC
);
end simpler_core;
architecture Behavioral of simpler_core is
-- Component instantiation
component ALU is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end component;
component fence is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control has data to be written back
ready_output: in std_logic; -- MMU is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in doubleword; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out doubleword -- MMU destination for output data
);
end component;
component decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end component;
component regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end component;
component mux is
Port(
sel: in std_logic; -- Select from zero, one ports
zero_port: in doubleword; -- Data in, zero select port
one_port: in doubleword; -- Data in, one select port
out_port: out doubleword -- Output data
);
end component;
component sext is
Port(
imm12: in std_logic_vector(11 downto 0);
imm20: in std_logic_vector(19 downto 0);
output_imm12: out std_logic_vector(63 downto 0);
output_imm20: out std_logic_vector(63 downto 0)
);
end component;
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic;
addr_in: in doubleword;
data_in: in doubleword;
satp: in doubleword;
-- mode: in std_logic_vector(1 downto 0); -- Machine mode, user mode, hypervisor mode or machine mode
store: in std_logic;
load: in std_logic;
busy: out std_logic;
ready_instr: in std_logic;
addr_instr: in doubleword;
alignment: in std_logic_vector(3 downto 0);
data_out: out doubleword;
instr_out: out doubleword;
error: out std_logic_vector(5 downto 0);
LED: out std_logic_vector(15 downto 0);
-- debug_MEM: out doubleword; -- Dummy register that will be written to
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- UART
UART_RXD: in std_logic;
UART_TXD: out std_logic;
-- Debug Signals
--pragma synthesis_off
fkuck_vivado_so_much: out std_logic_vector(5 downto 0);
s_internal_address_out: out doubleword;
--pragma synthesis_on
-- ROM
sck: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0);
cs_n: out STD_LOGIC);
end component;
component Debug_Controller is
Port (clk,rst: in STD_LOGIC;
halt: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
uart_rxd : in STD_LOGIC;
uart_txd : out STD_LOGIC);
end component;
-- Signals and constants
-- Feedback signals
signal s_rst: std_logic; -- internal reset
signal s_halts: std_logic_vector(2 downto 0); -- IM, REG, ALU halt signals
signal s_ALU_op: ctrl_t; -- ALU operation control
signal s_request_IM_in: std_logic; -- Signal pending write to IM
signal s_request_IM_inack: std_logic; -- Acknowledge above write handled
signal s_request_IM_out: std_logic; -- Signal ready for instruction
signal s_request_IM_outack: std_logic; -- Acknowledge instruction data is fresh
signal s_wb_select: std_logic; -- Select from ALU result or MMU data to Regfile write
signal s_PC_next: doubleword; -- Next PC address
signal s_PC_curr: doubleword; -- Preserves current PC for jumps
signal s_MMU_store: std_logic; -- Signal MMU to store
signal s_MMU_load: std_logic; -- Signal MMU to load
signal s_MMU_busy: std_logic; -- MMU is loading, storing, or fetching
signal s_ATU_busy: std_logic; -- Atomic unit is doing its thing
signal s_ATU_stage:std_logic; -- After resuming, need to know what stage of atomic instruction we are in
signal s_ALU_source_select: std_logic_vector(1 downto 0); -- Switch in immediate values
-- Decoded instruction parts
signal s_instr_code: instr_t; -- Exact instruction encoding
signal s_opcode: opcode_t; -- Opcode category abstraction
signal s_rs1: reg_t; -- Regfile read address
signal s_rs2: reg_t; -- Regfile read address
signal s_rs3: reg_t; -- Regfile read address
signal s_rd: reg_t; -- Regfile write address
signal s_shamt: std_logic_vector(4 downto 0); -- Shift amount, immediate shifts
signal s_imm12: std_logic_vector(11 downto 0); -- Immediate value, 12 bit style
signal s_imm20: std_logic_vector(19 downto 0); -- Immediate value, 20 bit style
signal s_csr_bits: std_logic_vector(11 downto 0); -- CSR address for CSR instructions
signal s_functs: std_logic_vector(15 downto 0); -- Holds concatenation of funct3, funct6, funct7
-- ALU connectors
signal s_ALU_input2: doubleword;
signal s_ALU_result: doubleword;
signal s_ALU_Error: std_logic_vector(2 downto 0);
-- Instruction memory connectors
signal s_IM_input_addr: doubleword;
signal s_IM_input_data: doubleword;
signal s_IM_output_addr: doubleword;
signal s_IM_output_data: doubleword;
-- Register file connectors
signal s_REG_raddr1: reg_t;
signal s_REG_raddr2: reg_t;
signal s_REG_rdata1: doubleword;
signal s_REG_rdata2: doubleword;
signal s_REG_wdata: doubleword;
signal s_REG_waddr: reg_t;
signal s_REG_write: std_logic;
signal s_REG_error: std_logic;
signal s_REG_debug: regfile_arr;
-- MMU connectors
signal s_MMU_input_addr: doubleword := (others => '0');
signal s_MMU_input_data: doubleword;
signal s_MMU_alignment: std_logic_vector(3 downto 0); -- One-hot selection in bytes
signal s_MMU_output_data: doubleword;
signal s_MMU_output_instr: doubleword;
signal s_MMU_error: std_logic_vector(5 downto 0);
signal s_MMU_instr_out: doubleword;
signal s_MMU_fetch: std_logic;
signal s_MMU_LED: std_logic_vector(15 downto 0);
signal s_MMU_satp: doubleword := (others => '0');
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Machine mode, user mode, hypervisor mode or machine mode
signal s_MMU_UART_RXD, s_MMU_UART_TXD: std_logic;
signal d_clk: std_logic := '0';
-- Jump and branch connectors
signal s_wb_to_jal: doubleword; -- Connects output of mem/alu wb mux to input of jump mux
signal s_jump_select: std_logic; -- Select from output of mem/alu mux or jump address data
signal s_jump_wdata: doubleword; -- Data representing the jump return address or AUIPC result
--signal s_jump_target: doubleword; -- Address of the jump targer
--signal s_jump_sext: doubleword; -- Intermediate helper variable for clarity's sake
-- Others
signal s_sext_12: doubleword; -- Sign extended immediate value
signal s_sext_20: doubleword; -- Sign extended immediate value
signal privilege_mode: std_logic_vector(1 downto 0) := MACHINE_MODE;
-- Debug
signal fkuck_vivado_so_much: std_logic_vector(5 downto 0);
signal s_internal_address_out: doubleword;
-- Load/Store connectors
-- Changing these signals to variables to avoid losing time
--signal s_load_base: doubleword; -- Base address from regfile
--signal s_load_offset: doubleword; -- Offset from sext(imm12 value)
--signal s_store_base: doubleword; -- Base address from regfile
--signal s_store_offset: doubleword; -- Offset from sext(imm12 value)
signal s_load_type : std_logic_vector(7 downto 0); -- Record type so we can properly extend later
signal s_load_dest : reg_t; -- Record rd so we can access it later
signal s_load_wb_data: doubleword; -- Extended data to be written back to regfile
-- High-level states of operation (distinct from modes)
type state is (fetching, fetching_wait, regs, alus, mem, wb, done);
signal curr_state, next_state: state := fetching;
signal stupid_fucking_vivado: std_logic_vector(5 downto 0);
-- Control status registers followed by scratch
type CSR_t is array (0 to 64) of doubleword;
signal CSR: CSR_t;
signal shifterCounter: integer := 0;
-- Exception flags
-- From privilege specification: MSB 1 => asynchronous, MSB 0 => synchronous
-- Remaining bits are binary-encoded exception code
signal exceptions: std_logic_vector(4 downto 0) := (others => '0');
-- in order to act appropriately on CSr exceptions, drive and track them separately
signal csr_exceptions: std_logic := '0';
signal exception_offending_instr : instr_t := (others => '0');
signal s_decode_instruction: doubleword;
-- If in waiting state, reason determines actions on exit
signal waiting_reason: std_logic_vector(2 downto 0);
signal gated_clock: std_logic;
begin
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 10.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => gated_clock, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);
-- Component instantiations and mapping
myDecode: decode
port map(
instr => s_decode_instruction,
instr_code => s_instr_code,
funct3 => s_functs(15 downto 13),
funct6 => s_functs(12 downto 7),
funct7 => s_functs(6 downto 0),
imm12 => s_imm12,
imm20 => s_imm20,
opcode => s_opcode,
rs1 => s_rs1,
rs2 => s_rs2,
rs3 => s_rs3,
rd => s_rd,
shamt => s_shamt,
csr => s_csr_bits
);
myALU: ALU
port map(
clk => clk,
rst => s_rst,
halt => s_halts(0),
ctrl => s_instr_code,
rs1 => s_REG_rdata1,
rs2 => s_ALU_input2,
shamt => s_shamt,
rout => s_ALU_result,
error => s_ALU_error(2),
overflow => s_ALU_error(1),
zero => s_ALU_error(0)
);
myIM: fence -- MMU writes back instructions and data to core
port map(
clk => clk,
rst => s_rst,
halt => s_halts(2),
ready_input => s_request_IM_in,
ready_output => s_request_IM_out,
output_OK => s_request_IM_outack,
input_OK => s_request_IM_inack,
input_data => s_IM_input_data,
input_address => s_IM_input_addr,
output_data => s_IM_output_data,
output_address => s_IM_output_addr
);
WBMux: mux
port map(
sel => s_WB_select,
zero_port => s_ALU_result,
one_port => s_load_wb_data,
out_port => s_wb_to_jal
);
JumpReturn: mux
port map(
sel => s_jump_select,
zero_port => s_wb_to_jal,
one_port => s_jump_wdata,
out_port => s_REG_wdata
);
--ALUMux: mux
-- port map(
-- sel => s_ALU_source_select,
-- zero_port => s_REG_rdata2,
-- one_port => s_sext_12,
-- out_port => s_ALU_input2
-- );
-- Muxes
--s_REG_wdata <= s_ALU_result when s_WB_select = '0' and s_jump_select = '0' else s_load_wb_data when s_WB_select = '1' and s_jump_select = '0' else s_load_wb_data when s_WB_select = '1';
--s_wb_to_jal <= s_ALU_result when s_WB_select = '0' else s_load_wb_data;
--s_REG_wdata <= s_wb_to_jal when s_jump_select = '0' else s_jump_wdata;
s_ALU_input2 <= s_REG_rdata2 when s_ALU_source_select = "00" else s_sext_12 when s_ALU_source_select = "01" else s_sext_20;
myMMU: MMU port map
(
clk => CLK,
rst => s_rst,
addr_in => s_MMU_input_addr,
data_in => s_MMU_input_data,
satp => s_MMU_satp,
-- mode => s_MMU_mode,
store => s_MMU_store,
load => s_MMU_load,
busy => s_MMU_busy,
ready_instr => s_MMU_fetch,
addr_instr => s_PC_curr,
alignment => s_MMU_alignment,
data_out => s_MMU_output_data,
instr_out => s_MMU_instr_out,
error => s_MMU_error,
UART_RXD => s_MMU_UART_RXD,
UART_TXD => s_MMU_UART_TXD,
LED => s_MMU_LED,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
-- Debug Signals
--pragma synthesis_off
fkuck_vivado_so_much => fkuck_vivado_so_much,
s_internal_address_out => s_internal_address_out,
--pragma synthesis_on
sck => gated_clock,
cs_n => cs_n,
dq => dq
);
myDebug: Debug_Controller
port map(
clk => clk,
rst => rst,
reggie => s_REG_debug,
PC_IN => s_PC_curr,
halt => d_clk,
uart_rxd => uart_rxd,
uart_txd => uart_txd
);
myREG: regfile
port map(
clk => clk,
rst => s_rst,
read_addr_1 => s_REG_raddr1,
read_addr_2 => s_REG_raddr2,
write_addr => s_REG_waddr,
write_data => s_REG_wdata,
halt => s_halts(1),
write_en => s_REG_write,
read_data_1 => s_REG_rdata1,
read_data_2 => s_REG_rdata2,
write_error => s_REG_error,
debug_out => s_REG_debug
);
mySext: sext
port map(
imm12 => s_imm12,
imm20 => s_imm20,
output_imm12 => s_sext_12,
output_imm20 => s_sext_20
);
advance_state: process(clk,rst, next_state) begin
if(rst = '1') then
curr_state <= fetching;
if(PC_Switch = '0') then
s_PC_curr <= (others => '0');
else
s_PC_curr <= x"0000000080000000";
end if;
elsif(rising_edge(clk)) then
curr_state <= next_state;
if(curr_state = done) then
s_PC_curr <= s_PC_next;
end if;
end if;
end process;
process(clk, rst, curr_state, next_state)
variable s_store_offset, s_load_offset, s_load_base, s_store_base, s_jump_target, s_jump_sext: doubleword;
begin
if(rst = '1') then
next_state <= fetching;
s_rst <= '1';
s_REG_write <= '0';
s_MMU_fetch <= '0';
s_MMU_store <= '0';
s_MMU_load <= '0';
s_halts <= "000";
s_wb_select <= '0';
s_ALU_source_select <= "00";
elsif(rising_edge(clk)) then
case curr_state is
when fetching =>
stupid_fucking_vivado <= "000000";
s_PC_next <= std_logic_vector(unsigned(s_PC_curr) + 8);
s_MMU_fetch <= '1';
s_MMU_store <= '0';
s_MMU_load <= '0';
s_REG_write <= '0';
s_halts <= "000";
s_rst <= '0';
next_state <= fetching_wait;
-- if(d_clk = '1') then
-- next_state <= fetching_wait;
-- else
-- next_state <= fetching;
-- end if;
when fetching_wait =>
next_state <= fetching_wait;
stupid_fucking_vivado <= "000001";
s_MMU_fetch <= '0';
if(s_MMU_busy = '0') then
next_state <= regs;
end if;
when regs =>
s_decode_instruction <= s_MMU_instr_out;
stupid_fucking_vivado <= "000010";
next_state <= alus;
when alus =>
stupid_fucking_vivado <= "000011";
next_state <= mem;
case s_opcode is
when ALU_T => -- Case regular, R-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_raddr2 <= s_rs2;
s_REG_waddr <= s_rd;
-- s_REG_write <= '0';
-- Use rdata2 instead of sign extended immediate
s_ALU_source_select <= "00";
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when LUI_T =>
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
--s_REG_write <= '1';
s_ALU_source_select <= "11";
s_wb_select <= '0';
-- next_state <= wb;
when ALUI_T => -- Case regular, I-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
-- s_REG_write <= '1';
-- Use sign extended immediate instead of rdata2
s_ALU_source_select <= "01";
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when LOAD_T =>
-- Little endian byte ordering
-- Need to signal MMU: full word, half word, quarter word
-- effective address is sext(regFile[rs1]) + sext(imm12)
case s_instr_code is
when instr_LB =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LB;
when instr_LBU =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LBU;
when instr_LH =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LH;
when instr_LHU =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LHU;
when instr_LW =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LW;
when instr_LWU =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LWU;
when others =>
s_MMU_alignment <= "1000";
s_load_type <= instr_LD;
end case;
s_load_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_load_offset := zero_word & "00000000000000000000" & s_imm12;
--s_load_offset <= zero_word & "00000000000000000000" & s_imm12;
else
s_load_offset := ones_word & "11111111111111111111" & s_imm12;
--s_load_offset <= ones_word & "11111111111111111111" & s_imm12;
end if;
s_load_dest <= s_rd;
s_MMU_input_addr <= std_logic_vector(signed(s_load_base) + signed(s_load_offset));
s_MMU_load <= '1';
waiting_reason <= "001";
when STORE_T =>
-- Little endian byte ordering
s_store_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_store_offset := zero_word & "00000000000000000000" & s_imm12;
else
s_store_offset := ones_word & "11111111111111111111" & s_imm12;
end if;
--s_MMU_input_addr <= std_logic_vector(signed(s_load_base) + signed(s_load_offset));
s_MMU_input_addr <= std_logic_vector(signed(s_store_base) + signed(s_store_offset));
case s_instr_code is
when instr_SB =>
s_MMU_input_data <= byte_mask_1 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SH =>
s_MMU_input_data <= byte_mask_2 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SW =>
s_MMU_input_data <= byte_mask_4 and s_REG_debug(to_integer(unsigned(s_rs2)));
when others => -- store doubleword
s_MMU_input_data <= s_REG_debug(to_integer(unsigned(s_rs2)));
end case;
s_MMU_store <= '1';
when BRANCH_T =>
case s_instr_code is
when instr_BEQ =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) = signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
when instr_BNE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) /= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
when instr_BLT =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) < signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
when instr_BGE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) >= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
when instr_BLTU =>
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) < unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
when others => --instr_BGEU
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) >= unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "00000000000000000000" & s_imm12)));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "11111111111111111111" & s_imm12)));
end if;
end if;
end case;
when JAL_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm20(19)) then
s_jump_target := zero_word & "00000000000" & s_imm20 & "0";
else
s_jump_target := ones_word & "11111111111" & s_imm20 & "0";
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when JALR_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm12(11)) then
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext := zero_word & "00000000000000000000" & s_imm12;
s_jump_target := std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) := '0';
else
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext := ones_word & "11111111111111111111" & s_imm12;
s_jump_target := std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) := '0';
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when AUIPC_T =>
s_jump_select <= '1';
s_REG_waddr <= s_rd;
if('0' = s_imm20(19)) then
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( zero_word & s_imm20 & "000000000000" ))
);
else
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( ones_word & s_imm20 & "000000000000" ))
); end if;
when others =>
end case;
when mem =>
next_state <= mem;
stupid_fucking_vivado <= "000100";
s_REG_write <= '0';
s_MMU_store <= '0';
s_MMU_load <= '0'; --Reset these suckers
if(s_mmu_busy = '0') then
if(s_opcode = LOAD_T) then
s_wb_select <= '1';
next_state <= wb;
-- These are the special cases for the writebacks
case s_load_type is
when instr_LB =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
else
s_load_wb_data <= ones_word & "111111111111111111111111" & s_MMU_output_data(7 downto 0);
end if;
when instr_LBU =>
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
when instr_LH =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
else
s_load_wb_data <= ones_word & "1111111111111111" & s_MMU_output_data(15 downto 0);
end if;
when instr_LHU =>
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
when instr_LW =>
if('0' = s_MMU_output_data(31)) then
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
else
s_load_wb_data <= ones_word & s_MMU_output_data(31 downto 0);
end if;
when instr_LWU =>
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
when others =>
s_load_wb_data <= s_MMU_output_data;
end case;
elsif(s_opcode = ALU_T OR s_opcode = ALUI_T or s_opcode = AUIPC_T) then
next_state <= wb;
else
next_state <= done;
end if;
end if;
when wb =>
next_state <= done;
s_REG_write <= '1';
stupid_fucking_vivado <= "000101";
-- shifterCounter <= shifterCounter + 1;
-- if(shifterCounter > 2) then
-- s_REG_write <= '1';
-- next_state <= done;
-- shifterCounter <= 0;
-- end if;
when done =>
if(d_clk = '0') then
next_state <= fetching;
else
next_state <= done;
end if;
stupid_fucking_vivado <= "000110";
s_REG_write <= '0';
when others =>
stupid_fucking_vivado <= "000111";
next_state <= fetching;
end case;
end if;
end process;
s_MMU_satp <= (others => '0');
status <= s_MMU_busy;
s_IM_input_data <= s_MMU_instr_out;
--LED(15 downto 9) <= s_opcode;
--LED(8 downto 0) <= s_MMU_LED(8 downto 0);
LED <= s_MMU_instr_out(15 downto 0) or s_MMU_instr_out(31 downto 16) or s_MMU_instr_out(47 downto 32) when ALU_Switch = '1' else s_MMU_LED;
--Debug signals only
--pragma synthesis_off
address_out <= s_MMU_input_addr;
instruction_out <= s_IM_input_data;
instruction_address_out <= s_PC_curr;
reggie <= s_REG_debug;
load_wb_data <= s_load_wb_data;
opcode <= s_opcode;
MMU_state <= stupid_fucking_vivado;
--o_load_type(4 downto 0) <= s_request_IM_outack & s_request_IM_inack & s_MMU_store & s_MMU_load & s_request_IM_outack;
o_load_type(1 downto 0) <= s_MMU_fetch & s_REG_write;
ALU_result <= s_ALU_result;
--pragma synthesis_on
end Behavioral;
| mit | 10523a4eb779d3c169b16107bb24456a | 0.485652 | 3.920324 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/ROM_Controller.vhd | 1 | 6,872 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
-- so, acc, hold: in STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(31 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end ROM_controller_SPI;
architecture Behavioral of ROM_controller_SPI is
signal CFGCLK, CFGMCLK, EOS, PREQ: std_logic;
signal SCLK: std_logic := '0';
signal read_command: std_logic_vector(8 downto 0) := (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
signal address_signal: std_logic_vector(23 downto 0) := (others => '0');
signal command_ctr, address_ctr, data_1_ctr, data_2_ctr, dummy_ctr: natural := 0;
signal done_1_flag, done_2_flag: std_logic := '1';
signal data_register_1, data_register_2 : std_logic_vector(31 downto 0) := (others => '0');
type spi_states is (idle, command, address, data_out_one_low, data_out_one_high, data_out_two, dummy, deasrt);
signal curr_state, next_state : spi_states := idle;
signal sckl_o,locked : std_logic;
signal s_t_si: std_logic;
signal s_clok_wat: std_logic := '0';
signal data_counter: natural := 0;
signal stop: std_logic := '0';
signal s_done: std_logic := '0';
signal retarded_counter : integer := 0;
signal one_clock_cycle: integer := 0;
signal s_read: std_logic;
signal counter_s : std_logic;
signal counter_o : std_logic_vector(30 downto 0) := (others => '0');
begin
retarded_ctr_adder: process(clk_25, rst) begin
if(rst = '1') then
retarded_counter <= 0;
elsif(rising_edge(clk_25)) then
if(read = '1' and retarded_counter < 55) then
retarded_counter <= retarded_counter + 1;
elsif(retarded_counter > 100) then
retarded_counter <= 0;
end if;
end if;
end process;
read_proc: process(clk_25, rst, read) begin
if(rst = '1') then
one_clock_cycle <= 0;
s_read <= '0';
elsif(rising_edge(clk_25) and read = '1') then
one_clock_cycle <= one_clock_cycle + 1;
if(one_clock_cycle = 0) then
s_read <= '1';
elsif(one_clock_cycle = 1) then
s_read <= '0';
end if;
end if;
end process;
retarded_ctr_fsm: process(clk_25, rst, s_read) begin
if(rst = '1') then
cs_n <= '1';
SCLK <= '0';
si_t <= '0';
wp_t <= '1';
-- data_register_1 <= (others => '0');
elsif(rising_edge(clk_25)) then
if(retarded_counter > 0) then
sclk <= sclk xor '1';
end if;
case retarded_counter is
when 0 =>
si_t <= '0';
s_done <= '0';
si_i <= '0';
wp <= '0';
cs_n <= '1';
if(s_read = '1') then
cs_n <= '0';
end if;
wp_t <= '1';
when 1 => -- Wait for cs_n to propagate (?)
cs_n <= '0';
when 2 =>
si_i <= '0';
when 3 =>
si_i <= '0';
when 4 =>
si_i <= '0';
when 5 =>
si_i <= '0';
when 6 =>
si_i <= '0';
when 7 =>
si_i <= '0';
when 8 =>
si_i <= '1';
when 9 =>
si_i <= '1';
when 10 =>
si_i <= '0';
-- data_register_1(0) <= SO;
when 11 =>
si_i <= '0';
-- data_register_1(1) <= SO;
when 12 =>
si_i <= '0';
-- data_register_1(3) <= SO;
when 13 =>
si_i <= '0';
-- data_register_1(4) <= SO;
when 14 =>
si_i <= '0';
-- data_register_1(5) <= SO;
when 15 =>
si_i <= '0';
-- data_register_1(6) <= SO;
when 16 =>
si_i <= '0';
-- data_register_1(7) <= SO;
when 29 =>
si_i <= address_in(5);
when 30 =>
si_i <= address_in(4);
when 31 =>
si_i <= address_in(3);
when 32 =>
si_i <= address_in(2);
when 33 =>
si_i <= address_in(1);
when 34 =>
si_i <= address_in(0);
when 35 =>
data_register_1(31) <= qd(1);
when 36 =>
data_register_1(30) <= qd(1);
when 37 =>
data_register_1(29) <= qd(1);
when 38 =>
data_register_1(28) <= qd(1);
when 39 =>
data_register_1(27) <= qd(1);
when 40 =>
data_register_1(26) <= qd(1);
when 41 =>
data_register_1(25) <= qd(1);
when 42 =>
data_register_1(24) <= qd(1);
when 43 =>
data_register_1(23) <= qd(1);
when 44 =>
data_register_1(22) <= qd(1);
when 45 =>
data_register_1(21) <= qd(1);
when 46 =>
data_register_1(20) <= qd(1);
when 47 =>
data_register_1(19) <= qd(1);
when 48 =>
data_register_1(18) <= qd(1);
when 49 =>
data_register_1(17) <= qd(1);
when 50 =>
data_register_1(16) <= qd(1);
when 51 =>
data_register_1(16) <= qd(1);
when 52 =>
data_register_1(15) <= qd(1);
when 53 =>
data_register_1(14) <= qd(1);
when 54 =>
data_register_1(13) <= qd(1);
when 55 =>
data_register_1(12) <= qd(1);
when 56 =>
data_register_1(11) <= qd(1);
when 57 =>
data_register_1(10) <= qd(1);
when 58 =>
data_register_1(9) <= qd(1);
when 59 =>
data_register_1(8) <= qd(1);
when 60 =>
data_register_1(7) <= qd(1);
when 61 =>
data_register_1(6) <= qd(1);
when 62 =>
data_register_1(5) <= qd(1);
when 63 =>
data_register_1(4) <= qd(1);
when 64 =>
data_register_1(3) <= qd(1);
when 65 =>
data_register_1(2) <= qd(1);
when 66 =>
data_register_1(1) <= qd(1);
when 67 =>
data_register_1(0) <= qd(1);
when 68 =>
cs_n <= '1';
done <= '1';
when others =>
end case;
end if;
end process;
-- QUAD command if switch 2 is off, SINGLE READ if switch 2 is on
read_command <= (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
--done <= s_done;
address_signal <= address_in;
data_out <= data_register_1;
--pragma synthesis_off
counter <= retarded_counter;
--pragma synthesis_on
end Behavioral;
| mit | ded349d0b70f432ae603be54067579f0 | 0.468714 | 3.130752 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/ioport8bit.vhd | 3 | 2,362 | ----------------------------------------------------------------------------------
--
-- 8-bit I/O port
-- Contains kludge for 6510/C64 I/O port behavior
-- (in a real C64 reset sets all DDR bits to input and pullup
-- resistors on the mainboard generate 1's)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
ioi : in std_logic_vector(7 downto 0);
ioo : out std_logic_vector(7 downto 0)
);
end ioport8bit;
architecture iop8_impl of ioport8bit is
signal data : std_logic_vector(7 downto 0);
signal ddr : std_logic_vector(7 downto 0); -- 0=in, 1=out
constant d_i : std_logic := '0';
constant d_o : std_logic := '1';
signal r0w1 : std_logic;
begin
r0w1 <= not r1w0;
read: process (a,data,ddr,ioi) is
variable pos : unsigned(2 downto 0);
begin
pos := "000";
case a is
when '1' => -- ioport
for pos in 7 downto 0 loop
if (ddr(pos) = d_o) then
dout(pos) <= data(pos);
else
dout(pos) <= ioi(pos);
end if;
end loop;
when others => -- ddr
dout <= ddr;
end case;
end process read;
write: process(clk,res0,ce,r0w1,a,din) is
begin
if (res0 = '1') then
-- kludge: Setting the first three bits to one
ddr <= "00101111";
data <= "00000111";
elsif (rising_edge(clk)) then
if (r0w1 = '1' and ce = '1') then
case a is
when '0' =>
ddr <= din;
when others =>
data <= din;
end case;
end if;
end if;
end process write;
iolines: process(data,ddr) is
variable pos : unsigned(2 downto 0);
begin
for pos in 7 downto 0 loop
if (ddr(pos) = '1') then
ioo(pos) <= data(pos);
else
ioo(pos) <= 'Z';
end if;
end loop;
end process iolines;
end iop8_impl;
| gpl-3.0 | fdb5ee1ac8f03baf1d3f31e748c829c9 | 0.476715 | 3.488922 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/io.vhd | 1 | 2,368 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.io.all;
--------------------------------------------------------------------------------
-- I/O PACKAGE
--------------------------------------------------------------------------------
package io is
constant ALIENS_PER_LINE : integer := 7;
constant ALIEN_LINES : integer := 5;
type pos_arr_xt is array(ALIENS_PER_LINE*ALIEN_LINES-1 downto 0) of integer range 0 to 160;
type pos_arr_yt is array(ALIENS_PER_LINE*ALIEN_LINES-1 downto 0) of integer range 0 to 120;
type GAME_STATE is (START, PLAYING, GAME_OVER_STATE, WIN);
component kbd_input is
port
(
clock_i : in std_logic;
reset_i : in std_logic;
hold_i : in std_logic;
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
shot_o : buffer std_logic;
move_o : buffer std_logic;
control_o : buffer std_logic_vector(2 downto 0)
);
end component;
component vga_module IS
generic (
RX : INTEGER := 160; -- Number of horizontal pixels
RY : INTEGER := 120; -- Number of vertical pixels
NUM_OF_ALIENS : INTEGER := 24 -- Number of enemies
);
port (
clk27m : in std_logic;
reset : in std_logic;
game_state_i : GAME_STATE;
nave_x : INTEGER RANGE 0 TO RX;
nave_y : INTEGER RANGE 0 TO RY;
nave_d : std_logic; -- nave destroy
tiro_x : INTEGER RANGE 0 TO RX;
tiro_y : INTEGER RANGE 0 TO RY;
tiro_enemy_x : INTEGER RANGE 0 TO RX;
tiro_enemy_y : INTEGER RANGE 0 TO RY;
cpu_e : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_d : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_x : pos_arr_xt;
cpu_y : pos_arr_yt;
red, green, blue : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end component;
end package;
| mit | ec0c6d7098e7b001ff1210dde086b15e | 0.443834 | 4.169014 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/IPv4Rx.vhd | 1 | 11,473 | ---------------------------------------------------------------------------------
-- Title : IPv4 Packet RX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : IPv4Rx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to Ethernet layer, reads incoming IPv4 packets
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity IPv4Rx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Incoming data from Ethernet frame
ethRxData : in slv( 7 downto 0);
ethRxDataValid : in sl;
ethRxDataLast : in sl;
-- Data from the IPv4 header
ipLength : out slv(15 downto 0);
ipId : out slv(15 downto 0);
ipMoreFragments : out sl;
ipFragOffset : out slv(12 downto 0);
ipTtl : out slv( 7 downto 0);
ipProtocol : out slv( 7 downto 0);
ipSrcAddr : out IpAddrType;
ipDstAddr : out IpAddrType;
-- Actual data from the payload
ipData : out slv(31 downto 0);
ipDataValid : out sl;
ipDataLast : out sl
);
end IPv4Rx;
-- Define architecture
architecture rtl of IPv4Rx is
type ReadStateType is (WAIT_S, READ_S);
type StateType is (IDLE_S,
HEADER_1_S, HEADER_2_S, HEADER_3_S, HEADER_4_S,
HEADER_OPTIONS_S,
PAYLOAD_S,
DUMP_S);
type RegType is record
state : StateType;
readState : ReadStateType;
readCnt : slv( 1 downto 0);
data8 : slv( 7 downto 0);
data8Valid : sl;
data8Last : sl;
data32 : slv(31 downto 0);
data32Valid : sl;
data32Last : sl;
headerLength : slv( 3 downto 0);
packetLength : slv(15 downto 0);
packetId : slv(15 downto 0);
ipMoreFragments : sl;
ipFragOffset : slv(12 downto 0);
ipTimeToLive : slv( 7 downto 0);
ipProtocol : slv( 7 downto 0);
ipChecksum : slv(31 downto 0);
ipSrcAddr : IpAddrType;
ipDstAddr : IpAddrType;
ipData : slv(31 downto 0);
ipDataValid : sl;
ipDataLast : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
readState => WAIT_S,
readCnt => (others => '0'),
data8 => (others => '0'),
data8Valid => '0',
data8Last => '0',
data32 => (others => '0'),
data32Valid => '0',
data32Last => '0',
headerLength => (others => '0'),
packetLength => (others => '0'),
packetId => (others => '0'),
ipMoreFragments => '0',
ipFragOffset => (others => '0'),
ipTimeToLive => (others => '0'),
ipProtocol => (others => '0'),
ipChecksum => (others => '0'),
ipSrcAddr => IP_ADDR_INIT_C,
ipDstAddr => IP_ADDR_INIT_C,
ipData => (others => '0'),
ipDataValid => '0',
ipDataLast => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethRxRst,ethRxData,ethRxDataValid,ethRxDataLast) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
v.data32valid := '0';
-- Register incoming data
v.data8 := ethRxData;
v.data8Valid := ethRxDataValid;
v.data8Last := ethRxDataLast;
v.data32Valid := '0';
v.data32Last := '0';
-- State machine for 8-to-32 translation
case(r.readState) is
when WAIT_S =>
v.readCnt := (others => '1');
v.data32 := (others => '0');
v.data32Valid := '0';
v.data32Last := '0';
if ethRxDataValid = '1' then
v.readState := READ_S;
end if;
when READ_S =>
if r.data8Valid = '1' then
v.data32( (1+conv_integer(r.readCnt))*8-1 downto (conv_integer(r.readCnt))*8) := r.data8;
v.readCnt := r.readCnt - 1;
if r.readCnt = 0 then
v.data32Valid := '1';
end if;
-- Force a valid on data8Last, in case we have
-- non-4-byte divisible data.
if r.data8Last = '1' then
if r.readCnt > 0 then
v.data32(conv_integer(r.readCnt) * 8 - 1 downto 0) := (others => '0');
end if;
v.data32Valid := '1';
v.data32Last := '1';
v.readState := WAIT_S;
end if;
end if;
when others =>
v.readState := WAIT_S;
end case;
-- Reset pulsed signals
v.ipDataValid := '0';
v.ipDataLast := '0';
-- State machine for interpreting 32-bit data
case(r.state) is
-- VERSION, IHL, DSCP, ECN, LENGTH
when IDLE_S =>
v.ipChecksum := (others => '0');
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
if (r.data32(31 downto 28) /= IPV4_VERSION_C or
r.data32(23 downto 16) /= IPV4_DSCP_C & IPV4_ECN_C) then
v.state := DUMP_S;
else
v.headerLength := r.data32(27 downto 24);
v.packetLength := r.data32(15 downto 0);
v.state := HEADER_1_S;
end if;
end if;
-- ID, FLAGS, FRAGMENT OFFSET
when HEADER_1_S =>
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.ipChecksum(31 downto 16)) + conv_integer(r.ipChecksum(15 downto 0)) + conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
v.packetId := r.data32(31 downto 16);
v.ipMoreFragments := r.data32(13);
v.ipFragOffset := r.data32(12 downto 0);
v.state := HEADER_2_S;
end if;
-- TTL, PROTOCOL, HEADER CHECKSUM
when HEADER_2_S =>
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.ipChecksum(31 downto 16)) + conv_integer(r.ipChecksum(15 downto 0)) + conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
v.ipTimeToLive := r.data32(31 downto 24);
v.ipProtocol := r.data32(23 downto 16);
v.state := HEADER_3_S;
end if;
-- SOURCE IP
when HEADER_3_S =>
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.ipChecksum(31 downto 16)) + conv_integer(r.ipChecksum(15 downto 0)) + conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
v.ipSrcAddr(3) := r.data32(31 downto 24);
v.ipSrcAddr(2) := r.data32(23 downto 16);
v.ipSrcAddr(1) := r.data32(15 downto 8);
v.ipSrcAddr(0) := r.data32( 7 downto 0);
v.state := HEADER_4_S;
end if;
-- DESTINATION IP
when HEADER_4_S =>
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.ipChecksum(31 downto 16)) + conv_integer(r.ipChecksum(15 downto 0)) + conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
v.ipDstAddr(3) := r.data32(31 downto 24);
v.ipDstAddr(2) := r.data32(23 downto 16);
v.ipDstAddr(1) := r.data32(15 downto 8);
v.ipDstAddr(0) := r.data32( 7 downto 0);
if r.headerLength > 5 then
v.headerLength := r.headerLength - 5 - 1;
v.state := HEADER_OPTIONS_S;
else
if conv_std_logic_vector(conv_integer(v.ipChecksum(31 downto 16)) + conv_integer(v.ipChecksum(15 downto 0)),32)(15 downto 0) = x"FFFF" then
v.state := PAYLOAD_S;
else
v.state := DUMP_S;
end if;
end if;
end if;
-- HEADER OPTIONS
when HEADER_OPTIONS_S =>
if r.data32Valid = '1' then
v.ipChecksum := conv_std_logic_vector(conv_integer(r.ipChecksum(31 downto 16)) + conv_integer(r.ipChecksum(15 downto 0)) + conv_integer(r.data32(31 downto 16)) + conv_integer(r.data32(15 downto 0)),32);
if r.headerLength = 0 then
if conv_std_logic_vector(conv_integer(v.ipChecksum(31 downto 16)) + conv_integer(v.ipChecksum(15 downto 0)),16)(15 downto 0) = x"FFFF" then
v.state := PAYLOAD_S;
else
v.state := DUMP_S;
end if;
end if;
v.headerLength := r.headerLength - 1;
end if;
-- PAYLOAD DATA
when PAYLOAD_S =>
if r.data32Valid = '1' then
v.ipData := r.data32;
v.ipDataValid := r.data32Valid;
v.ipDataLast := r.data32Last;
if r.data32Last = '1' then
v.state := IDLE_S;
end if;
end if;
-- DUMP
when DUMP_S =>
if r.data32Last = '1' then
v.state := IDLE_S;
end if;
-- Others
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ipLength <= r.packetLength;
ipId <= r.packetId;
ipMoreFragments <= r.ipMoreFragments;
ipFragOffset <= r.ipFragOffset;
ipTtl <= r.ipTimeToLive;
ipProtocol <= r.ipProtocol;
ipSrcAddr <= r.ipSrcAddr;
ipDstAddr <= r.ipDstAddr;
ipData <= r.ipData;
ipDataValid <= r.ipDataValid;
ipDataLast <= r.ipDataLast;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 5bec973b273104bd3e54bc6fa9bbbdc4 | 0.482699 | 3.961671 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/kbdex_ctrl.vhd | 1 | 11,111 | -------------------------------------------------------------------------------
-- Title : MC613
-- Project : Keyboard Controller
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : kbdext_ctrl.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/03/29
-------------------------------------------------------------------------------
-- Description:
-- The keyboard controller receives serial data input from the device and
-- signals through 'key_on' when a key is pressed. Up to 3 keys can be pressed
-- simultaneously. The key code data is written to 'key_code':
-- First key pressed:
-- . key_code(15 downto 0) is set with data
-- . key_on(0) rises
-- First key released:
-- . key_on(0) falls
--
-- Second key pressed:
-- . key_code(31 downto 16) is set with data
-- . key_on(1) rises
-- Second key released:
-- . key_on(1) falls
--
-- Third key pressed:
-- . key_code(47 downto 32) is set with data
-- . key_on(2) rises
-- Third key released:
-- . key_on(2) falls
--
-- Remarks:
-- .clk: system clock frequency needs to be at least 10 MHz
-- .PrintScreen key signals as if two keys were pressed (E012 and E07C)
-- .Pause/Break key signals as if two keys were pressed (14 and 77), so it
-- is the same as if LCTRL (14) and NUNLOCK(77) were pressed.
-- .Currently it's not possible to write to the keyboard, turning its lights
-- on.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity kbdex_ctrl is
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
lights : in std_logic_vector(2 downto 0) := "000"; -- lights(Caps, Nun, Scroll)
key_on : out std_logic_vector(2 downto 0);
key_code : out std_logic_vector(47 downto 0)
);
end;
architecture rtl of kbdex_ctrl is
component ps2_iobase
generic(
clkfreq : integer -- This is the system clock value in kHz
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
idata_rdy : in std_logic;
idata : in std_logic_vector(7 downto 0);
send_rdy : out std_logic;
odata_rdy : out std_logic;
odata : out std_logic_vector(7 downto 0)
);
end component;
type statename is (
IDLE, FETCH, DECODE, CODE,
RELEASE, EXT0, EXT1, CLRDP
);
-- State machine signals
signal state, nstate : statename;
signal sigfetch, sigfetched, sigext0,
sigrelease, sigselect, sigclear : std_logic;
-- Datapath signals
signal newdata, selE0, relbt, selbt,
key0en, key1en, key2en,
key0clearn, key1clearn, key2clearn : std_logic;
signal ps2_code : unsigned( 7 downto 0);
signal fetchdata : unsigned( 7 downto 0);
signal upperdata : unsigned( 7 downto 0);
signal datacode : unsigned(15 downto 0);
signal key0code : unsigned(15 downto 0);
signal key1code : unsigned(15 downto 0);
signal key2code : unsigned(15 downto 0);
-- Lights control
signal hdata : std_logic_vector( 7 downto 0);
signal sigsend, sigsendrdy, sigsending,
siguplights : std_logic;
-- PS2 output signals
signal ps2_dataout : std_logic_vector(7 downto 0);
signal ps2_datardy : std_logic;
begin
ps2_ctrl : ps2_iobase generic map(clkfreq) port map(
ps2_data, ps2_clk, clk, en, resetn, sigsend, hdata,
sigsendrdy, ps2_datardy, ps2_dataout
);
ps2_code <= unsigned(ps2_dataout);
-- State cicle
process(clk, resetn, sigsending)
begin
-- Change state on falling edge of ps2_clk
if(rising_edge(clk) and en = '1') then
state <= nstate;
end if;
if resetn = '0' or sigsending = '1' then
state <= IDLE;
end if;
end process;
-- Select next state
process(state, newdata)
begin
case state is
when IDLE =>
if newdata = '1' then
nstate <= FETCH;
else
nstate <= IDLE;
end if;
when FETCH =>
nstate <= DECODE;
when DECODE =>
if fetchdata = X"F0" then
nstate <= RELEASE;
elsif fetchdata = X"E0" then
nstate <= EXT0;
elsif fetchdata = X"E1" then
nstate <= EXT1;
else
nstate <= CODE;
end if;
when CODE =>
nstate <= CLRDP;
when RELEASE | EXT0 | EXT1 | CLRDP =>
nstate <= IDLE;
end case;
end process;
-- Current state output
process(state)
begin
sigfetch <= '0';
sigfetched <= '0';
sigext0 <= '0';
sigrelease <= '0';
sigselect <= '0';
sigclear <= '0';
case state is
when IDLE | EXT1 =>
NULL;
when FETCH =>
sigfetch <= '1';
when DECODE =>
sigfetched <= '1';
when CODE =>
sigselect <= '1';
when RELEASE =>
sigrelease <= '1';
when EXT0 =>
sigext0 <= '1';
when CLRDP =>
sigclear <= '1';
end case;
end process;
-- Fetched signal register
process(clk, resetn)
begin
if(rising_edge(clk) and sigfetch = '1') then
fetchdata <= ps2_code;
end if;
if resetn = '0' then
fetchdata <= X"00";
end if;
end process;
-- EXT0 selection (SR Latch)
process(sigext0, sigclear, resetn)
begin
if sigclear = '1' or resetn = '0' then
selE0 <= '0';
elsif sigext0 = '1' then
selE0 <= '1';
end if;
end process;
-- Mux for upper value (E0 or 0)
process(selE0)
begin
if selE0 = '1' then
upperdata <= X"E0";
else
upperdata <= X"00";
end if;
end process;
-- datacode data set
datacode <= upperdata & fetchdata;
-- Keys registers
KEY0 : process(clk, key0clearn, resetn)
begin
if(rising_edge(clk) and key0en = '1') then
key0code <= datacode;
end if;
if key0clearn = '0' or resetn = '0' then
key0code <= X"0000";
end if;
end process;
KEY1 : process(clk, key1clearn, resetn)
begin
if(rising_edge(clk) and key1en = '1') then
key1code <= datacode;
end if;
if key1clearn = '0' or resetn = '0' then
key1code <= X"0000";
end if;
end process;
KEY2 : process(clk, key2clearn, resetn)
begin
if(rising_edge(clk) and key2en = '1') then
key2code <= datacode;
end if;
if key2clearn = '0' or resetn = '0' then
key2code <= X"0000";
end if;
end process;
-- Release command (SR Latch)
process(sigrelease, sigclear, resetn)
begin
if sigclear = '1' or resetn = '0' then
relbt <= '0';
elsif sigrelease = '1' then
relbt <= '1';
end if;
end process;
-- Release command (SR Latch)
process(sigselect, sigclear, resetn)
begin
if sigclear = '1' or resetn = '0' then
selbt <= '0';
elsif sigselect = '1' then
selbt <= '1';
end if;
end process;
-- Key replacement and clear selector
SELECTOR : process(relbt, selbt)
begin
key0en <= '0'; key1en <= '0'; key2en <= '0';
key0clearn <= '1'; key1clearn <= '1'; key2clearn <= '1';
-- Select an empty register to record fetched data
if relbt = '0' and selbt = '1' then
if datacode /= key0code and datacode /= key1code and
datacode /= key2code then
if key0code = X"0000" then
key0en <= '1';
elsif key1code = X"0000" then
key1en <= '1';
elsif key2code = X"0000" then
key2en <= '1';
end if;
end if;
-- Clear released key
elsif relbt = '1' and selbt = '1' then
-- Handle fake shifts
if datacode = X"0012" then
if key0code = X"E012" then
key0clearn <= '0';
elsif key1code = X"E012" then
key1clearn <= '0';
elsif key2code = X"E012" then
key2clearn <= '0';
end if;
elsif datacode = X"0059" then
if key0code = X"E059" then
key0clearn <= '0';
elsif key1code = X"E059" then
key1clearn <= '0';
elsif key2code = X"E059" then
key2clearn <= '0';
end if;
end if;
-- Handle normal release
if key0code = datacode then
key0clearn <= '0';
elsif key1code = datacode then
key1clearn <= '0';
elsif key2code = datacode then
key2clearn <= '0';
end if;
end if;
end process;
-- Out with key codes
key_code <= std_logic_vector(key2code & key1code & key0code);
-- Turn buttons on
process(clk, sigclear, resetn)
begin
if(rising_edge(clk) and sigclear = '1') then
if key0code /= X"0000" then
key_on(0) <= '1';
else
key_on(0) <= '0';
end if;
if key1code /= X"0000" then
key_on(1) <= '1';
else
key_on(1) <= '0';
end if;
if key2code /= X"0000" then
key_on(2) <= '1';
else
key_on(2) <= '0';
end if;
end if;
if resetn = '0' then
key_on <= "000";
end if;
end process;
-- Comparator for newdata signal
-- Signals on rising edge of ps2_datardy
process(ps2_datardy, sigfetched, sigsending, resetn)
begin
if(rising_edge(ps2_datardy)) then
newdata <= '1';
end if;
if resetn = '0' or sigfetched = '1' or sigsending = '1' then
newdata <= '0';
end if;
end process;
-- Keyboar lights control
-- Detect ligths state change
process(clk, lights, sigsending, resetn)
variable laststate : std_logic_vector(2 downto 0);
begin
if resetn = '0' or sigsending = '1' then
laststate := "XXX";
siguplights <= '0';
elsif(rising_edge(clk)) then
if laststate /= lights then
siguplights <= '1';
laststate := lights;
else
siguplights <= '0';
end if;
end if;
end process;
-- Send commands to keyboard
process(clk, siguplights, en, resetn)
type cmdstatename is (
SETCMD, SEND, WAITACK, SETLIGHTS, SENDVAL, WAITACK1, CLEAR
);
variable cmdstate : cmdstatename;
begin
if(rising_edge(clk)) then
sigsend <= '0';
sigsending <= '1';
case cmdstate is
when SETCMD =>
hdata <= X"ED";
if sigsendrdy = '1' then
cmdstate := SEND;
end if;
when SEND =>
sigsend <= '1';
cmdstate := WAITACK;
when WAITACK =>
if ps2_datardy = '1' then
if ps2_dataout = X"FE" then
cmdstate := SETCMD;
else
cmdstate := SETLIGHTS;
end if;
end if;
when SETLIGHTS =>
hdata <= "00000" & "000";
if sigsendrdy = '1' then
cmdstate := SENDVAL;
end if;
when SENDVAL =>
sigsend <= '1';
cmdstate := WAITACK1;
when WAITACK1 =>
if ps2_datardy = '1' then
if ps2_dataout = X"FE" then
cmdstate := SETLIGHTS;
else
cmdstate := CLEAR;
end if;
end if;
when CLEAR =>
sigsending <= '0';
end case;
end if;
if resetn = '0' or en = '0' or siguplights = '1' then
sigsending <= '1';
sigsend <= '0';
cmdstate := SETCMD;
end if;
end process;
end rtl; | mit | 7c9b7753df1100e1e7476edce9d59b27 | 0.566736 | 2.963724 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_11_19/chip6502.vhd | 1 | 43,073 | ----------------------------------------------------------------------------------
--
-- Takes all the VHDL bits and makes a 6502 out of them
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end chip6502;
architecture interaction of chip6502 is
subtype slv2 is std_logic_vector(1 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant v_nmi_l : word := x"FFFA";
constant v_nmi_h : word := x"FFFB";
constant v_res_l : word := x"FFFC";
constant v_res_h : word := x"FFFD";
constant v_irq_l : word := x"FFFE";
constant v_irq_h : word := x"FFFF";
component clockgen
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out slv2;
res0 : in std_logic
);
end component;
subtype clkstg_t is std_logic_vector(1 downto 0);
signal clkStg : clkstg_t;
signal iph0 : std_logic;
signal iph1 : std_logic;
signal iph2 : std_logic;
constant sysclk_PH2_p : clkstg_t := "00";
constant sysclk_PH2_m : clkstg_t := "01";
constant sysclk_PH1_p : clkstg_t := "10";
constant sysclk_PH1_m : clkstg_t := "11";
component ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in byte;
dout : out byte;
ioi : in byte;
ioo : out byte
);
end component;
signal io_o : byte;
signal io_i : byte;
signal io_ce : std_logic;
signal io_clk : std_logic;
component alu_8bit
port (
a_in : in byte;
b_in : in byte;
c_in : in std_logic;
d_in : in std_logic; -- the dreaded BCD mode
op_in : in unsigned(2 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
r_out : out byte
);
end component;
signal ALUcin : std_logic;
signal ALUdin : std_logic;
signal ALUain : byte;
signal ALUbin : byte;
signal ALUop : unsigned(2 downto 0);
signal ALUrout : byte;
signal ALUnout : std_logic;
signal ALUvout : std_logic;
signal ALUzout : std_logic;
signal ALUcout : std_logic;
signal regbus : byte;
signal outval : byte;
signal abus : word;
signal DBen : std_logic := '1';
signal DBrw : std_logic := '1';
signal dbRE : std_logic;
signal dbWE : std_logic;
signal nDBen : std_logic;
signal aen0 : std_logic := '1';
signal aen1 : std_logic;
alias abus_off is aen0;
subtype seqType is byte;
function countSeq(src : seqType) return seqType is
variable v : unsigned(7 downto 0);
begin
v := unsigned(src);
v := v + 1;
return seqType(v);
end countSeq;
signal seq : seqType := x"00";
subtype dbctl_t is std_logic_vector(2 downto 0);
signal DB_ctl : dbctl_t := "011";
alias dbctl_sync : std_logic is DB_ctl(2);
alias dbctl_off : std_logic is DB_ctl(1);
alias dbctl_r1w0 : std_logic is DB_ctl(0);
subtype aop_t is std_logic_vector(2 downto 0);
signal aop : aop_t := "000";
constant aop_add : aop_t := "000";
constant aop_and : aop_t := "001";
constant aop_or : aop_t := "010";
constant aop_xor : aop_t := "011";
constant aop_lsl : aop_t := "100";
constant aop_lsr : aop_t := "101";
constant aop_rol : aop_t := "110";
constant aop_ror : aop_t := "111";
signal alu_bin_mode : slv2;
constant bin_reg : slv2 := "00";
constant bin_set : slv2 := "01";
constant bin_clr : slv2 := "10";
constant bin_ireg : slv2 := "11";
signal alu_cin_mode : slv2;
constant cin_psw : slv2 := "00";
constant cin_set : slv2 := "01";
constant cin_clr : slv2 := "10";
constant cin_aux : slv2 := "11";
signal alu_din_mode : std_logic;
constant din_clr : std_logic := '0';
constant din_psw : std_logic := '1';
signal alu_bin_reg : byte;
signal alu_bin_tie : byte;
type stage_t is (
stg_reset,
stg_fetch,
stg_sub_incpc, -- pc++
--stg_sub_pc2adr, -- meml=[pc++], memh=[pc++]
stg_sub_pc2buf, -- BUF=[pc++]
stg_sub_pc2a, -- A=[pc++]
stg_sub_pc2x, -- X=[pc++]
stg_sub_pc2y, -- Y=[pc++]
stg_CLC,
stg_SEC,
stg_CLI,
stg_SEI,
stg_CLV,
stg_CLD,
stg_SED,
stg_TXS,
stg_TSX,
stg_PHA,
stg_PLA,
stg_PHP,
stg_PLP,
stg_TAX,
stg_TXA,
stg_TAY,
stg_TYA,
stg_JMP_abs,
stg_tail
);
signal seq_stage : stage_t := stg_reset;
signal ret_stage : stage_t := stg_fetch; -- return stage for sub stage
signal ir : byte := x"00";
signal reg_a : byte := x"00";
signal reg_x : byte := x"00";
signal reg_y : byte := x"00";
signal reg_pc : word := x"0000";
signal reg_sp : byte := x"00";
signal reg_p : byte := x"00";
alias psw_n is reg_p(7);
alias psw_v is reg_p(6);
alias psw_b is reg_p(4);
alias psw_d is reg_p(3);
alias psw_i is reg_p(2);
alias psw_z is reg_p(1);
alias psw_c is reg_p(0);
signal buf_data : byte := x"00";
signal buf_addr : word := x"0000";
alias reg_pcl : byte is reg_pc(7 downto 0);
alias reg_pch : byte is reg_pc(15 downto 8);
alias buf_addr_l : byte is buf_addr(7 downto 0);
alias buf_addr_h : byte is buf_addr(15 downto 8);
signal private_c : std_logic;
function isZero(src: byte) return std_logic is
begin
return ((src(0) nor src(1)) and (src(2) nor src(3))) and
((src(4) nor src(5)) and (src(6) nor src(7)));
end isZero;
begin
clock: clockgen port map(
ph4Xin => ph4Xin,
ph0 => iph0,
ph1 => iph1,
ph2 => iph2,
stg => clkStg,
res0 => res0
);
ph0 <= iph0;
ph1 <= iph1;
ph2 <= iph2;
io8bit: ioport8bit port map(
ce => io_ce,
clk => io_clk,
res0 => res0,
r1w0 => dbRW,
a => abus(0),
din => io_i,
dout => io_o,
ioi => pi,
ioo => po
);
io_clk <= (not clkStg(1)) and clkStg(0);
io_ce <= not ( (((abus(15) or abus(14)) or (abus(13) or abus(12))) or
((abus(11) or abus(10)) or (abus( 9) or abus( 8)))) or
(((abus( 7) or abus( 6)) or (abus( 5) or abus( 4))) or
((abus( 3) or abus( 2)) or abus( 1) )) );
io_i <= regbus;
alunit: alu_8bit port map(
a_in => ALUain,
b_in => ALU_bin_tie,
c_in => ALUcin,
d_in => ALUdin,
op_in => ALUop,
n_out => ALUnout,
v_out => ALUvout,
z_out => ALUzout,
c_out => ALUcout,
r_out => ALUrout
);
alu_cin_mux: process(alu_cin_mode,psw_c,private_c) is
begin
case alu_cin_mode is
when cin_set => ALUcin <= '1';
when cin_clr => ALUcin <= '0';
when cin_aux => ALUcin <= private_c;
when others => ALUcin <= psw_c;
end case;
end process alu_cin_mux;
alu_din_mux: process(alu_din_mode,psw_d) is
begin
case alu_din_mode is
when din_clr => ALUdin <= '0';
when others => ALUdin <= psw_d;
end case;
end process alu_din_mux;
alu_bin_mux: process(alu_bin_mode,alu_bin_reg) is
begin
case alu_bin_mode is
when bin_clr => alu_bin_tie <= "00000000";
when bin_set => alu_bin_tie <= "11111111";
when bin_ireg => alu_bin_tie <= not alu_bin_reg;
when others => alu_bin_tie <= alu_bin_reg;
end case;
end process alu_bin_mux;
sync <= DB_ctl(2);
DBen <= DB_ctl(1);
DBrw <= DB_ctl(0);
nDBen <= not DBen;
DBre <= DBrw;
DBwe <= not DBrw;
aen1 <= not aen0;
r1w0 <= DBrw;
ALUop <= unsigned(aop);
-- Allow connection of data bus as output during write operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_ogate: process(nDBen,DBwe,outval) iS
begin
if ((nDBen and DBwe) = '1') then
if (io_ce='1') then
do <= io_o;
else
do <= outval;
end if;
else
do <= "ZZZZZZZZ";
end if;
end process db_ogate;
-- Allow connection of data bus as input during read operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_igate: process(nDBen,DBre,di) is
begin
if ((nDBen and DBre) = '1') then
regbus <= di;
else
regbus <= "ZZZZZZZZ";
end if;
end process db_igate;
addr_gate: process(aen1,abus) is
begin
if (aen1='1') then
a <= abus;
else
a <= "ZZZZZZZZZZZZZZZZ";
end if;
end process addr_gate;
main_proc: process(res0,ph4Xin) is
begin
-- Status register stuff
reg_p(5) <= '0';
if (so0 = '0') then
psw_V <= '1';
end if;
if (res0 = '0') then
seq <= x"00";
seq_stage <= stg_reset;
ret_stage <= stg_reset;
dbctl_r1w0 <= '1';
dbctl_off <= '1';
dbctl_sync <= '0';
abus_off <= '1';
elsif (rising_edge(ph4Xin)) then
-- reset stage
if (seq_stage = stg_reset) then
if ((not (clkStg = sysclk_PH2_m)) and seq=x"00") then
else
-- we enter here at seq x00 on PH1+
case seq is
when x"00" => seq <= countSeq(seq); -- PH1+: put RES vector L on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= v_res_l;
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) write to PCL
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put RES vector H on abus
abus <= v_res_h;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
seq_stage <= stg_fetch; -- change to instruction decode
seq <= x"00";
when others => null;
end case;
end if;
end if;
-- instruction fetch/decode stage
if (seq_stage = stg_fetch) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
dbctl_sync <= '1'; -- sync on for instruction decode
abus_off <= '0';
abus <= reg_pc; -- PC on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) get instruction
ir <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: sync off
dbctl_sync <= '0';
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"05" => -- PH1-: store PCL=1+PCL
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"07" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
if (rdy = '1') then
abus_off <= '0';
dbctl_off <= '0';
seq <= x"00";
case ir is
when x"4C" =>
seq_stage <= stg_JMP_abs; -- JMP abs
when x"18" =>
seq_stage <= stg_CLC; -- CLC
when x"38" =>
seq_stage <= stg_SEC; -- SEC
when x"58" =>
seq_stage <= stg_CLI; -- CLI
when x"78" =>
seq_stage <= stg_SEI; -- SEI
when x"B8" =>
seq_stage <= stg_CLV; -- CLV
when x"D8" =>
seq_stage <= stg_CLD; -- CLD
when x"F8" =>
seq_stage <= stg_SED; -- SED
-- LDA
when x"A9" => -- imm
ret_stage <= stg_tail;
seq_stage <= stg_sub_pc2a;
-- LDX
when x"A2" => -- imm
ret_stage <= stg_tail;
seq_stage <= stg_sub_pc2x;
-- LDY
when x"A0" => -- imm
ret_stage <= stg_tail;
seq_stage <= stg_sub_pc2y;
when x"9A" => -- TXS sp=x
seq_stage <= stg_TXS;
when x"BA" => -- TSX x=sp
seq_stage <= stg_TSX;
when x"48" => -- PHA [sp--]=a
seq_stage <= stg_PHA;
when x"68" => -- PLA a=[++sp]
seq_stage <= stg_PLA;
when x"08" => -- PHP [sp--]=P
seq_stage <= stg_PHP;
when x"28" => -- PLP P=[++sp]
seq_stage <= stg_PLP;
when x"AA" => -- TAX X=A
seq_stage <= stg_TAX;
when x"8A" => -- TXA A=X
seq_stage <= stg_TXA;
when x"A8" => -- TAY Y=A
seq_stage <= stg_TAY;
when x"98" => -- TYA A=Y
seq_stage <= stg_TYA;
when others =>
seq_stage <= stg_tail; -- NOP
end case;
else
abus_off <= '1'; -- burn a full PH1/PH2 cycle if RDY=0
dbctl_off <= '1';
seq <= x"08";
end if;
when x"08" => seq <= countSeq(seq); -- PH1+: burn
when x"09" => seq <= countSeq(seq); -- PH1-: burn
when x"0A" => seq <= x"07"; -- PH2+: will check RDY again on PH2-
when others => null;
end case;
end if;
-- epilogue stage (also handles NOP)
-- checks for interrupts, and RDY
if (seq_stage = stg_tail) then
case seq is
when x"00" => -- PH1+: burn
abus_off <= '0'; -- abus enabled
dbctl_off <= '0'; -- dbus enabled
dbctl_r1w0 <= '1'; -- dbus to read
seq <= countSeq(seq);
when x"01" => -- PH1-: burn
seq <= countSeq(seq);
when x"02" => -- PH2+: burn
seq <= countSeq(seq);
when x"03" =>
seq_stage <= stg_fetch; -- PH2-: return to fetch (on PH1+)
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_incpc) then
case seq is
when x"00" => -- PH1+:
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+1
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
seq <= x"00";
seq_stage <= ret_stage; -- PH2+: set return-to stage (on PH1+)
when others => null;
end case;
end if;
if (seq_stage = stg_sub_pc2buf) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_pc2a) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to A
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq <= x"00";
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_pc2x) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to X
reg_x <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq <= x"00";
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_pc2y) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to Y
reg_y <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq <= x"00";
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- JMP abs
if (seq_stage = stg_JMP_abs) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
reg_pcl <= buf_addr_l; -- copy buffered lobyte to PCL
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLC
if (seq_stage = stg_CLC) then
case seq is
when x"00" => -- PH1+: C=0
psw_c <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEC
if (seq_stage = stg_SEC) then
case seq is
when x"00" => -- PH1+: C=1
psw_c <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLI
if (seq_stage = stg_CLI) then
case seq is
when x"00" => -- PH1+: I=0
psw_i <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEI
if (seq_stage = stg_SEI) then
case seq is
when x"00" => -- PH1+: I=1
psw_i <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLV
if (seq_stage = stg_CLV) then
case seq is
when x"00" => -- PH1+: V=0
psw_v <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLD
if (seq_stage = stg_CLD) then
case seq is
when x"00" => -- PH1+: D=0
psw_d <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SED
if (seq_stage = stg_SED) then
case seq is
when x"00" => -- PH1+: D=1
psw_d <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXS
if (seq_stage = stg_TXS) then
case seq is
when x"00" => -- PH1+:
reg_sp <= reg_x; -- store SP=X
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TSX
if (seq_stage = stg_TSX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_sp; -- store X=SP
psw_z <= isZero(reg_sp); -- Z flag
psw_n <= reg_sp(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- PHA
if (seq_stage = stg_PHA) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= reg_a;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PHP
if (seq_stage = stg_PHP) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= (reg_p(7 downto 6) & "01" &
reg_p(3 downto 0)); -- 6502 quirk: B always set on pushed psw
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLA
if (seq_stage = stg_PLA) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLP
if (seq_stage = stg_PLP) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_p <= (regbus(7 downto 6) & "0" &
regbus(4 downto 0)); -- store status value (unused bit forced to 0)
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- TAX
if (seq_stage = stg_TAX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_a; -- store X=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXA
if (seq_stage = stg_TXA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_x; -- store A=X
psw_z <= isZero(reg_x); -- Z flag
psw_n <= reg_x(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TAY
if (seq_stage = stg_TAY) then
case seq is
when x"00" => -- PH1+:
reg_y <= reg_a; -- store Y=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TYA
if (seq_stage = stg_TYA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_y; -- store A=Y
psw_z <= isZero(reg_y); -- Z flag
psw_n <= reg_y(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
end if;
end process main_proc;
end interaction;
| gpl-3.0 | 512b846185308e73b676dfac933ba18a | 0.337102 | 4.511207 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/sim/CoreTwoIpDataSim.vhd | 1 | 8,869 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:36:20 08/28/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Google Drive/mTC/svn/src/Ethernet/General/sim/IPv4Test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4Tx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
use work.Eth1000BaseXPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CoreTwoIpDataSim IS
END CoreTwoIpDataSim;
ARCHITECTURE behavior OF CoreTwoIpDataSim IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4Tx
PORT(
ethTxClk : IN std_logic;
ethTxRst : IN std_logic;
ipPacketLength : IN std_logic_vector(15 downto 0);
ipPacketId : IN std_logic_vector(15 downto 0);
ipMoreFragments : IN std_logic;
ipFragOffset : IN std_logic_vector(12 downto 0);
ipProtocol : IN std_logic_vector(7 downto 0);
ipSrcAddr : IN IpAddrType;
ipDstAddr : IN IpAddrType;
ipData : IN std_logic_vector(31 downto 0);
ipDataValid : IN std_logic;
ipDataReady : OUT std_logic;
ethTxDataIn : OUT std_logic_vector(7 downto 0);
ethTxDataValid : OUT std_logic;
ethTxDataLastByte : OUT std_logic;
ethTxDataReady : IN std_logic
);
END COMPONENT;
--Inputs
signal ethClk125 : std_logic := '0';
signal ethClk125Rst : std_logic := '0';
signal ethClk62 : std_logic := '0';
signal ethClk62Rst : std_logic := '0';
signal ethCoreMacAddr : MacAddrType := MAC_ADDR_DEFAULT_C;
signal ethCoreIpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal ch2IpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal phyRxLaneIn : EthRxPhyLaneInType;
signal phyTxLaneOut : EthTxPhyLaneOutType;
signal dummyPhyRxLaneIn : EthRxPhyLaneInType;
signal dummyPhyTxLaneOut : EthTxPhyLaneOutType;
signal ethRxLinkSync : sl;
signal ethAutoNegDone : sl;
-- User Data signals
signal tpData : slv(31 downto 0);
signal tpDataValid : sl;
signal tpDataLast : sl := '0';
signal tpDataReady : sl;
signal tpData1 : slv(31 downto 0);
signal tpDataValid1 : sl;
signal tpDataLast1 : sl := '0';
signal tpDataReady1 : sl;
-- Clock period definitions
constant ethClk125_period : time := 8 ns;
constant ethClk62_period : time := 16 ns;
constant GATE_DELAY_C : time := 1 ns;
BEGIN
ch2IpAddr(0) <= x"15";
--------------------------------
-- Gigabit Ethernet Interface --
--------------------------------
U_Eth1000BaseXCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 2,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr, 1 => ch2IpAddr),
udpPorts => (0 => x"08D0", 1 => x"08D1"), --x7D0 = 2000
-- Data to/from GT
phyRxData => phyRxLaneIn,
phyTxData => phyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData, 1 => tpData1),
userTxDataValid => (0 => tpDataValid, 1 => tpDataValid1),
userTxDataLast => (0 => tpDataLast, 1 => tpDataLast1),
userTxDataReady(1) => tpDataReady1,
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
U_TpGenTx : entity work.TpGenTx
generic map (
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst or not(ethAutoNegDone),
-- Configuration
waitCycles => conv_std_logic_vector(1000,32),
numWords => conv_std_logic_vector(100,32),
-- Connection to user logic
userTxData => tpData,
userTxDataValid => tpDataValid,
userTxDataLast => tpDataLast,
userTxDataReady => tpDataReady
);
U_TpGenTx1 : entity work.TpGenTx
generic map (
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst or not(ethAutoNegDone),
-- Configuration
waitCycles => conv_std_logic_vector(100,32),
numWords => conv_std_logic_vector(2500,32),
-- Connection to user logic
userTxData => tpData1,
userTxDataValid => tpDataValid1,
userTxDataLast => tpDataLast1,
userTxDataReady => tpDataReady1
);
--------------------------------
-- DummyCore Ethernet Interface --
--------------------------------
U_DummyCore : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => ethClk125,
eth125Rst => ethClk125Rst,
-- 62 MHz clock and reset
eth62Clk => ethClk62,
eth62Rst => ethClk62Rst,
-- Addressing
macAddr => ethCoreMacAddr,
ipAddrs => (0 => ethCoreIpAddr),
udpPorts => (0 => x"07D0"), --x7D0 = 2000
-- Data to/from GT
phyRxData => dummyPhyRxLaneIn,
phyTxData => dummyPhyTxLaneOut,
-- Status signals
statusSync => ethRxLinkSync,
statusAutoNeg => ethAutoNegDone,
-- User clock and reset
userClk => ethClk125,
userRst => ethClk125Rst,
-- User data
userTxData => (0 => tpData),
userTxDataValid => (0 => tpDataValid),
userTxDataLast => (0 => tpDataLast),
userTxDataReady(0) => tpDataReady,
userRxData => open,
userRxDataValid => open,
userRxDataLast => open,
userRxDataReady => (others => '1')
);
-- Match up B TX to A RX
phyRxLaneIn.data <= dummyPhyTxLaneOut.data;
phyRxLaneIn.dataK <= dummyPhyTxLaneOut.dataK;
phyRxLaneIn.dispErr <= (others => '0');
phyRxLaneIn.decErr <= (others => '0');
-- Match up A TX to B RX
dummyPhyRxLaneIn.data <= phyTxLaneOut.data;
dummyPhyRxLaneIn.dataK <= phyTxLaneOut.dataK;
dummyPhyRxLaneIn.dispErr <= (others => '0');
dummyPhyRxLaneIn.decErr <= (others => '0');
-- Clock process definitions
ethClk125_process : process
begin
ethClk125 <= '0';
wait for ethClk125_period/2;
ethClk125 <= '1';
wait for ethClk125_period/2;
end process;
ethClk62_process : process
begin
ethClk62 <= '0';
wait for ethClk62_period/2;
ethClk62 <= '1';
wait for ethClk62_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ethClk125Rst <= '1';
ethClk62Rst <= '1';
wait for 100 ns;
ethClk125Rst <= '0';
ethClk62Rst <= '0';
wait for ethClk125_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-2.1 | d61d29f17cdaa32c4d2a5a1ebb5a8f90 | 0.551922 | 4.423441 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/top_system_simulation.vhd | 1 | 10,080 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/28/2018 05:30:29 PM
-- Design Name:
-- Module Name: top_system_simulation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_system_simulation is
-- Port ( );
end top_system_simulation;
architecture Behavioral of top_system_simulation is
component simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
reggie: out regfile_arr;
pc_curr: out doubleword;
DEBUG_halt: in std_logic;
MMU_addr_in: out doubleword; -- 64-bits address for load/store
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_store: out std_logic; -- High to toggle store
MMU_load: out std_logic; -- High to toggle load
MMU_busy: in std_logic; -- High when busy
MMU_ready_instr: out std_logic; -- Ready for a new instruction (initiates fetch)
MMU_addr_instr: out doubleword; -- Instruction Address (AKA PC)
MMU_alignment: out std_logic_vector(3 downto 0);-- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_instr_out: in word; -- 64-Bits instruction out for fetch
MMU_error: in std_logic_vector(5 downto 0) -- Error bits from MMU
);
end component;
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out word; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end component;
component debug_controller is
port (clk,RST: in STD_LOGIC;
HALT: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
INSTRUCTION_IN: in word;
UART_RXD: in STD_LOGIC;
UART_TXD : out STD_LOGIC);
end component;
signal s_MMU_addr_in: doubleword; -- 64-bits address for load/store
signal s_MMU_data_in: doubleword; -- 64-bits data for store
signal s_MMU_satp: doubleword := (others => '0'); -- Signals address translation privilege
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
signal s_MMU_store: std_logic; -- High to toggle store
signal s_MMU_load: std_logic; -- High to toggle load
signal s_MMU_busy: std_logic; -- High when busy
signal s_MMU_ready_instr: std_logic; -- Ready for a new instruction (initiates fetch)
signal s_MMU_addr_instr: doubleword; -- Instruction Address (AKA PC)
signal s_MMU_alignment: std_logic_vector(3 downto 0); -- alignment in bytes
signal s_MMU_data_out: doubleword; -- 64-Bits data out for load
signal s_MMU_instr_out: word; -- 64-Bits instruction out for fetch
signal s_MMU_error: std_logic_vector(5 downto 0); -- Error bits from MMU
signal s_MMU_txd : std_logic;
signal status, clk: std_logic := '0';
signal rst: std_logic := '1';
signal LED: std_logic_vector(15 downto 0);
signal UART_TXD: std_logic;
signal UART_RXD: std_logic;
signal ddr2_addr : STD_LOGIC_VECTOR (12 downto 0);
signal ddr2_ba : STD_LOGIC_VECTOR (2 downto 0);
signal ddr2_ras_n : STD_LOGIC;
signal ddr2_cas_n : STD_LOGIC;
signal ddr2_we_n : STD_LOGIC;
signal ddr2_ck_p : std_logic_vector(0 downto 0);
signal ddr2_ck_n : std_logic_vector(0 downto 0);
signal ddr2_cke : std_logic_vector(0 downto 0);
signal ddr2_cs_n : std_logic_vector(0 downto 0);
signal ddr2_dm : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_odt : std_logic_vector(0 downto 0);
signal ddr2_dq : STD_LOGIC_VECTOR (15 downto 0);
signal ddr2_dqs_p : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_dqs_n : STD_LOGIC_VECTOR (1 downto 0);
signal sck: std_logic; -- Special gated sck for the ROM STARTUPE2 generic
signal cs_n: STD_LOGIC;
signal dq: std_logic_vector(3 downto 0);
signal s_DEBUG_halt: std_logic; -- Halt signal from Debugger
signal s_DEBUG_pc_in: doubleword;
signal s_DEBUG_reggie: regfile_arr;
signal s_DEBUG_txd: std_logic;
signal counter: integer := 0;
begin
bestCore: simple_core
port map(
status => status,
clk => clk,
rst => rst,
reggie => s_DEBUG_reggie,
pc_curr => s_DEBUG_pc_in,
DEBUG_halt => s_DEBUG_halt,
MMU_addr_in => s_MMU_addr_in,
MMU_data_in => s_MMU_data_in,
MMU_satp => s_MMU_satp,
MMU_mode => s_MMU_mode,
MMU_store => s_MMU_store,
MMU_load => s_MMU_load,
MMU_busy => s_MMU_busy,
MMU_ready_instr => s_MMU_ready_instr,
MMU_addr_instr => s_MMU_addr_instr,
MMU_alignment => s_MMU_alignment,
MMU_data_out => s_MMU_data_out,
MMU_instr_out => s_MMU_instr_out,
MMU_error => s_MMU_error
);
memmy: MMU
port map(
clk => clk,
rst => rst,
addr_in => s_MMU_addr_in,
data_in => s_MMU_data_in,
satp => s_MMU_satp,
mode => s_MMU_mode,
store => s_MMU_store,
load => s_MMU_load,
busy => s_MMU_busy,
ready_instr => s_MMU_ready_instr,
addr_instr => s_MMU_addr_instr,
alignment => s_MMU_alignment,
data_out => s_MMU_data_out,
instr_out => s_MMU_instr_out,
error => s_MMU_error,
LED => LED,
UART_TXD => s_MMU_txd,
UART_RXD => UART_RXD,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
sck => sck,
cs_n => cs_n,
dq => dq
);
debugger: debug_controller port map(
clk => clk,
rst => rst,
halt => s_DEBUG_halt,
reggie => s_DEBUG_reggie,
pc_in => s_DEBUG_pc_in,
INSTRUCTION_IN => s_MMU_instr_out,
UART_RXD => UART_RXD,
UART_TXD => s_DEBUG_txd);
process begin
counter <= counter + 1;
if(counter > 2) then
rst <= '0';
end if;
clk <= clk xor '1';
wait for 10 ns;
end process;
end Behavioral;
| mit | 2a2de180cc2ba9264f02af2817c1339f | 0.527778 | 3.652174 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXAutoNeg.vhd | 1 | 9,333 | ---------------------------------------------------------------------------------
-- Title : 1000 BASE X link autonegotiation
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXAutoNeg.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Autonegotiation for 1000 BASE-X.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
entity Eth1000BaseXAutoNeg is
generic (
GATE_DELAY_G : time := 1 ns;
PIPE_STAGES_G : integer range 1 to 8 := 2;
SIM_SPEEDUP_G : boolean := false
);
port (
-- GT user clock and reset (62.5 MHz)
ethRx62Clk : in sl;
ethRx62Rst : in sl;
-- Autonegotiation is done
autonegDone : out sl;
-- Link is synchronized
rxLinkSync : in sl;
-- Physical Interface Signals
phyRxData : in EthRxPhyLaneInType;
phyTxData : out EthTxPhyLaneOutType
);
end Eth1000BaseXAutoNeg;
architecture rtl of Eth1000BaseXAutoNeg is
type AutoNegStateType is (S_IDLE, S_AUTONEG_RESTART, S_ABILITY_DETECT,
S_ACK_DETECT, S_COMPLETE_ACK, S_FIRST_IDLE,
S_IDLE_DETECT, S_LINK_UP);
type PhyRxDataArray is array (PIPE_STAGES_G-1 downto 0) of EthRxPhyLaneInType;
type RegType is record
autoNegState : AutoNegStateType;
rxDataPipe : PhyRxDataArray;
txData : slv(15 downto 0);
toggleC1C2 : sl;
toggleWord : sl;
timerCnt : slv(19 downto 0);
sendIdle : sl;
useI1 : sl;
linkUp : sl;
newState : sl;
end record RegType;
constant REG_INIT_C : RegType := (
autoNegState => S_IDLE,
rxDataPipe => (others => ETH_RX_PHY_LANE_IN_INIT_C),
txData => (others => '0'),
toggleC1C2 => '0',
toggleWord => '0',
timerCnt => (others => '0'),
sendIdle => '0',
useI1 => '0',
linkUp => '0',
newState => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- Signals for outputs from the match unit
signal abilityMatch : sl;
signal acknowledgeMatch : sl;
signal consistencyMatch : sl;
signal idleMatch : sl;
signal ability : slv(15 downto 0);
constant LINK_TIMER_SIM_C : natural := 625; -- 10 us at 62.5 MHz
constant THIS_LINK_TIMER_C : natural := sel(SIM_SPEEDUP_G,LINK_TIMER_SIM_C,LINK_TIMER_C);
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- Match unit
U_AbMatch : entity work.Eth1000BaseXAbilityMatch
generic map (
GATE_DELAY_G => GATE_DELAY_G)
port map (
ethRx62Clk => ethRx62Clk,
ethRx62Rst => ethRx62Rst,
rxLinkSync => rxLinkSync,
newState => r.newState,
abilityMatch => abilityMatch,
ability => ability,
acknowledgeMatch => acknowledgeMatch,
consistencyMatch => consistencyMatch,
idleMatch => idleMatch,
phyRxData => r.rxDataPipe(PIPE_STAGES_G-1)
);
comb : process(r,phyRxData,ethRx62Rst,rxLinkSync,abilityMatch,
acknowledgeMatch,consistencyMatch,idleMatch,ability) is
variable v : RegType;
begin
v := r;
-- Pipeline for incoming data
for i in PIPE_STAGES_G-1 downto 0 loop
if (i /= 0) then
v.rxDataPipe(i) := v.rxDataPipe(i-1);
else
v.rxDataPipe(0) := phyRxData;
end if;
end loop;
-- Toggle the configuration bit if toggleWord is 1
if (r.toggleWord = '1') then
v.toggleC1C2 := not(r.toggleC1C2);
end if;
-- Always switch between /C(1,2)/ and ConfigReg
v.toggleWord := not(r.toggleWord);
-- Choose what to send here (idle or configuration)
if (r.sendIdle = '0') then
if (r.toggleWord = '0') then
if (r.toggleC1C2 = '0') then
phyTxData.data <= OS_C1_C;
phyTxData.dataK <= "01";
else
phyTxData.data <= OS_C2_C;
phyTxData.dataK <= "01";
end if;
else
phyTxData.data <= r.txData;
phyTxData.dataK <= "00";
end if;
else
phyTxData.dataK <= "01";
if (r.useI1 = '1') then
phyTxData.data <= OS_I1_C;
else
phyTxData.data <= OS_I2_C;
end if;
end if;
-- Regardless of what you're sending, the data is valid
phyTxData.valid <= '1';
-- Combinatorial state logic
case(r.autoNegState) is
-- Just transmit breaklink until you get a restart
when S_IDLE =>
v.txData := OS_BL_C;
v.sendIdle := '0';
v.timerCnt := (others => '0');
v.linkUp := '0';
if (rxLinkSync = '1') then
v.autoNegState := S_AUTONEG_RESTART;
end if;
-- Transmit breaklink for 10 ms
when S_AUTONEG_RESTART =>
v.sendIdle := '0';
v.txData := OS_BL_C;
v.timerCnt := r.timerCnt + 1;
if (r.timerCnt > THIS_LINK_TIMER_C) then
v.timerCnt := (others => '0');
v.autoNegState := S_ABILITY_DETECT;
end if;
-- Transmit own configuration with no ack
-- Exit when we see 3 consistent non-breaklink configs
when S_ABILITY_DETECT =>
v.sendIdle := '0';
v.txData := OS_CN_C;
if (abilityMatch = '1' and ability /= 0) then
v.autoNegState := S_ACK_DETECT;
end if;
-- Send configuration with ack bit
-- Back to start on ackMatch and not(consistMatch)
-- Success if we get ackMatch and consistencyMatch
when S_ACK_DETECT =>
v.sendIdle := '0';
v.txData := OS_CA_C;
if ( (acknowledgeMatch = '1' and consistencyMatch = '0') or
(abilityMatch = '1' and ability = 0) ) then
v.autoNegState := S_IDLE;
elsif (acknowledgeMatch = '1' and consistencyMatch = '1') then
v.autoNegState := S_COMPLETE_ACK;
end if;
-- Just send configuration with ack bit for timeout period
-- (we're not trying to do next pages [yet])
when S_COMPLETE_ACK =>
v.sendIdle := '0';
v.txData := OS_CA_C;
if (abilityMatch = '1' and ability = 0) then
v.autoNegState := S_IDLE;
end if;
if (r.timerCnt < THIS_LINK_TIMER_C) then
v.timerCnt := r.timerCnt + 1;
elsif (abilityMatch = '0' or ability /= 0) then
v.timerCnt := (others => '0');
--v.autoNegState := S_FIRST_IDLE;
v.autoNegState := S_IDLE_DETECT;
end if;
-- Send one I1 to flip disparity
when S_FIRST_IDLE =>
v.sendIdle := '1';
v.useI1 := '1';
v.autoNegState := S_IDLE_DETECT;
-- Send idles
when S_IDLE_DETECT =>
v.sendIdle := '1';
v.useI1 := '0';
if (abilityMatch = '1' and ability = 0) then
v.autoNegState := S_IDLE;
end if;
if (r.timerCnt < THIS_LINK_TIMER_C) then
v.timerCnt := r.timerCnt + 1;
elsif (idleMatch = '1') then
v.timerCnt := (others => '0');
v.autoNegState := S_LINK_UP;
end if;
when S_LINK_UP =>
v.sendIdle := '1';
v.linkUp := '1';
if (abilityMatch = '1') then
v.autoNegState := S_IDLE;
end if;
when others =>
end case;
-- If we lose sync, always go back to the start
if (rxLinkSync = '0') then
v.autoNegState := S_IDLE;
end if;
-- Check for new state condition
if (v.autoNegState /= r.autoNegState) then
v.newState := '1';
else
v.newState := '0';
end if;
-- Reset logic
if (ethRx62Rst = '1') then
v := REG_INIT_C;
end if;
-- Connections to output ports
autonegDone <= r.linkUp;
rin <= v;
end process;
seq : process (ethRx62Clk) is
begin
if (rising_edge(ethRx62Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | be76ec422b1730df48ca62fe7b4bf0e8 | 0.496196 | 4.104222 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/debug_controller.vhd | 1 | 18,399 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity Debug_Controller is
port (clk,RST: in STD_LOGIC;
HALT: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
UART_RXD: in STD_LOGIC;
UART_TXD : out STD_LOGIC);
end Debug_Controller;
architecture Behavioral of Debug_Controller is
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Types
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
type UART_STATE_TYPE is (IDLE, RECEIVE, UNPAUSE, DECODE, REGISTERS, PC, STEP, STEP_HI, STEP_LO, SEND_CHAR, REGFILE, SEND_CHAR_2, SEND_CHAR_3, SEND_CHAR_4, WAIT_CHAR, KEEP_WAITING_CHAR, LD_REGISTERS_STR, RESET_LO, RESET_HI);
type BOUNDS is array (integer range<>) of integer;
-- Constants
constant MAX_STR_LEN : integer := 750;
constant MAX_REGISTER_LEN : integer := 23;
constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
-- Signals
signal uart_curr_state, uart_next_state : UART_STATE_TYPE := idle;
signal uartRdy, uartSend ,uartTX: std_logic;
signal uartData: std_logic_vector(7 downto 0);
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1)) := ( others => (others => '0'));
signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
-- String counters
signal reggie_counter : integer := 0;
signal reggie_str_counter : integer := 12;
signal reggie_counter_counter : integer := 0;
signal strEnd, strIndex: natural := 0;
signal strConcatCtr: integer := 0;
signal pc_str_counter: integer := 0;
signal pc_reg: doubleword := (others => '0');
-- CPU halt interface
signal halt_l : std_logic := '1';
-- UART RX and TX signals
signal uart_data_in: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal data_available, reset_read: STD_LOGIC;
signal rx_str : CHAR_ARRAY(30 DOWNTO 0);
signal rx_str_ctr : integer := 0;
signal d_clk: std_logic := '0';
begin
DEBUG_UART_TX: UART_TX_CTRL port map(SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => UART_TXD );
DEBUG_UART_RX: UART_RX_CTRL
port map(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => data_available,
RESET_READ => reset_read
);
--State Machine transition
DEBUG_FSM: process(clk, rst) begin
if(rst = '1') then
uart_curr_state <= IDLE;
elsif(rising_edge(clk)) then
uart_curr_state <= uart_next_state;
end if;
end process;
HALT <= halt_l;
-- Generate the debug clock d_clk
D_CLK_GEN: process(clk) begin
if(rising_edge(clk)) then
if(halt_l = '0') then
d_clk <= d_clk xor '1';
end if;
end if;
end process;
DEBUG_FSM_TRANSITION: process(clk, rst) begin
if(rst = '1') then
strConcatCtr <= 0;
reggie_str_counter <= 0;
reset_read <= '1';
uart_next_state <= IDLE;
strIndex <= 0;
halt_l <= '1';
elsif(rising_edge(clk)) then
case uart_curr_state is
-- State IDLE: Nothing happening
when IDLE =>
reggie_counter_counter <= 0;
reggie_str_counter <= 0;
strConcatCtr <= 0;
strEnd <= 735;
uartSend <= '0';
strIndex <= 0;
reset_read <= '0';
reggie_counter <= 0;
pc_str_counter <= 0;
uart_next_state <= IDLE;
-- Default go to IDLE
if(data_available = '1' AND uartRdy = '1' ) then -- If we have data and not outputing anything
rx_str(0) <= uart_data_in; -- Save the data
uart_next_state <= DECODE;
end if;
-- State DECODE: Decode what function the user is accessing
when DECODE =>
if(rx_str(0) = X"72") then
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"73") then
uart_next_state <= STEP;
elsif(rx_str(0) = X"75") then
uart_next_state <= UNPAUSE;
elsif(rx_str(0) = X"70") then
uart_next_state <= PC;
strEnd <= 23;
pc_reg <= PC_IN;
else
uart_next_state <= IDLE;
end if;
-- State REGFILE: Print out the entire register file
-- TODO: change this to make it less crappy
-- reggie_counter indicates how many registers should be printed
-- reggie_counter_counter is the length of the string printed per register
when REGFILE =>
uart_next_state <= REGFILE;
if( reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_counter >= 31) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 1 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(reggie_counter, 4)));
reggie_counter_counter <= 1;
when 2 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when PC =>
uart_next_state <= PC;
if(pc_str_counter > 21) then
uart_next_state <= SEND_CHAR;
else
pc_str_counter <= pc_str_counter + 1;
case pc_str_counter is
when 1 => sendStr(pc_str_counter) <= X"50";
when 2 => sendStr(pc_str_counter) <= X"43";
when 3 => sendStr(pc_str_counter) <= X"3A";
when 4 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(63 downto 60));
when 5 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(59 downto 56));
when 6 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(55 downto 52));
when 7 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(51 downto 48));
when 8 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(47 downto 44));
when 9 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(43 downto 40));
when 10 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(39 downto 36));
when 11 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(35 downto 32));
when 12 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(31 downto 28));
when 13 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(27 downto 24));
when 14 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(23 downto 20));
when 15 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(19 downto 16));
when 16 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(15 downto 12));
when 17 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(11 downto 8));
when 18 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(7 downto 4));
when 19 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(3 downto 0));
when 20 => sendStr(pc_str_counter) <= X"20";
when 21 => sendStr(pc_str_counter) <= X"0A";
when 22 => sendStr(pc_str_counter) <= X"0A";
when 23 => sendStr(pc_str_counter) <= X"0A";
when 24 => sendStr(pc_str_counter) <= X"0A";
when others => sendStr(24) <= X"20";
end case;
end if;
-- State STEP: Step one clock cycle
-- halt_l is 0, allows the CPU to continue for one clock cycle
when STEP =>
halt_l <= '0';
uart_next_state <= STEP_HI;
-- State STEP_HI: One step done
-- halt_l is 1, halts the processor
when STEP_HI =>
halt_l <= '1';
uart_next_state <= STEP_LO;
-- State STEP_LO: One step done
-- If the user wants to skip 2 clock cycles instead of one,
-- STEP_HI can set halt_l to 0 and STEP_LO can be set to 1
-- This can be
when STEP_LO =>
halt_l <= '1';
uart_next_state <= RESET_LO;
-- State REGISTERS: Once the strings are prepared, send the characters
when REGISTERS =>
uart_next_state <= SEND_CHAR;
-- State SEND_CHAR: Tell the UART controller to print things
when SEND_CHAR =>
strIndex <= strIndex + 1;
uartSend <= '1';
uartData <= sendStr(strIndex);
uart_next_state <= WAIT_CHAR;
-- State WAIT_CHAR: Checks if the entirety of the string
-- has been sent
when WAIT_CHAR =>
uart_next_state <= WAIT_CHAR;
if(strEnd <= strIndex) then
uart_next_state <= RESET_LO;
elsif(uartRdy = '1') then
uart_next_state <= SEND_CHAR;
end if;
-- State RESET_LO: Resets the RX_UART to flush whatever it
-- had as an input to prepare for the next function
when RESET_LO =>
reset_read <= '1';
uart_next_state <= RESET_HI;
-- State RESET_HI:
when RESET_HI =>
reset_read <= '0';
uart_next_state <= IDLE;
-- State UNPAUSE: Lifts the halt_l, allowing the CPU to run normally
when UNPAUSE =>
halt_l <= '0';
uart_next_state <= RESET_LO;
when OTHERS =>
uart_next_state <= IDLE;
end case;
end if;
end process;
end Behavioral;
| mit | 6ab137bfd5156fe68513ffb90eb1008a | 0.454318 | 4.547454 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/EthTx.vhd | 1 | 6,095 | -------------------------------------------------------------------------------
-- Title : Ethernet Lane
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : EthTx.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Ethernet interface TX
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity EthTx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz clock and reset
ethClk : in sl;
ethRst : in sl;
-- Addressing
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
-- Connection to GT
macData : out EthMacDataType;
-- Connection to upper level ARP
arpTxSenderMac : in MacAddrType;
arpTxSenderIp : in IpAddrType;
arpTxTargetMac : in MacAddrType;
arpTxTargetIp : in IpAddrType;
arpTxOp : in slv(15 downto 0);
arpTxReq : in sl;
arpTxAck : out sl;
-- Connection to IPv4 interface
ipTxDestMac : in MacAddrType;
ipTxData : in slv(7 downto 0);
ipTxDataValid : in sl;
ipTxDataLastByte : in sl;
ipTxDataReady : out sl
);
end EthTx;
architecture Behavioral of EthTx is
-- Communication between MAC and Ethernet framer
signal macTxData : slv(7 downto 0);
signal macTxDataValid : sl;
signal macTxDataLastByte : sl;
signal macTxDataReady : sl;
-- Communication between Ethernet framer and higher level protocols
signal ethTxEtherType : EtherType;
signal ethTxData : slv(7 downto 0);
signal ethTxDataValid : sl;
signal ethTxDataLastByte : sl;
signal ethTxDataReady : sl;
-- Local connection to ARP interface
signal arpTxData : slv(7 downto 0);
signal arpTxDataValid : sl;
signal arpTxDataLastByte : sl;
signal arpTxDataReady : sl;
signal iArpTxAck : sl;
--
signal ethTxDestMac : MacAddrType;
begin
-- Transmit data from Tx
U_MacTx : entity work.Eth1000BaseXMacTx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- User data to be sent
userDataIn => macTxData,
userDataValid => macTxDataValid,
userDataLastByte => macTxDataLastByte,
userDataReady => macTxDataReady,
-- Data out to the GT
macDataOut => macData
);
-- Ethernet Type II Frame Transmitter
U_EthFrameTx : entity work.EthFrameTx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Data for the header
ethTxDestMac => ethTxDestMac,
ethTxSrcMac => macAddr,
ethTxEtherType => ethTxEtherType,
-- User data to be sent
ethTxDataIn => ethTxData,
ethTxDataValid => ethTxDataValid,
ethTxDataLastByte => ethTxDataLastByte,
ethTxDataReady => ethTxDataReady,
-- Data output
macTxDataOut => macTxData,
macTxDataValid => macTxDataValid,
macTxDataLastByte => macTxDataLastByte,
macTxDataReady => macTxDataReady
);
-- ARP Packet Transmitter
U_ArpPacketTx : entity work.ArpPacketTx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Data to send
arpSenderMac => arpTxSenderMac,
arpSenderIp => arpTxSenderIp,
arpTargetMac => arpTxTargetMac,
arpTargetIp => arpTxTargetIp,
arpOp => arpTxOp,
arpReq => arpTxReq,
arpAck => iArpTxAck,
-- User data to be sent
ethTxData => arpTxData,
ethTxDataValid => arpTxDataValid,
ethTxDataLastByte => arpTxDataLastByte,
ethTxDataReady => arpTxDataReady
);
-- Arbiter to MUX between ARP requests and IP data
U_ArpIpArbiter : entity work.ArpIpArbiter
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- ARP request/ack, data interface
arpTxReq => arpTxReq,
arpTxAck => iArpTxAck,
arpTxData => arpTxData,
arpTxDataValid => arpTxDataValid,
arpTxDataLastByte => arpTxDataLastByte,
arpTxDataReady => arpTxDataReady,
-- IPv4 data interface
ipTxData => ipTxData,
ipTxDataValid => ipTxDataValid,
ipTxDataLastByte => ipTxDataLastByte,
ipTxDataReady => ipTxDataReady,
-- Output MUXed data
ethTxEtherType => ethTxEtherType,
ethTxData => ethTxData,
ethTxDataValid => ethTxDataValid,
ethTxDataLastByte => ethTxDataLastByte,
ethTxDataReady => ethTxDataReady
);
arpTxAck <= iArpTxAck;
process(ethClk) begin
if rising_edge(ethClk) then
if ethRst = '1' then
ethTxDestMac <= MAC_ADDR_INIT_C;
elsif arpTxDataValid = '1' then
ethTxDestMac <= arpTxTargetMac;
elsif ipTxDestMac /= MAC_ADDR_INIT_C then
ethTxDestMac <= ipTxDestMac;
end if;
end if;
end process;
end Behavioral;
| lgpl-2.1 | 34cacf215f7b50b454d8614274f11eb9 | 0.529943 | 5.389036 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXCore.vhd | 1 | 6,933 | -------------------------------------------------------------------------------
-- Title : Ethernet Interface
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : Eth1000BaseXCore.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Ethernet interface
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity Eth1000BaseXCore is
generic (
NUM_IP_G : integer := 1;
MTU_SIZE_G : integer := 1500;
LITTLE_ENDIAN_G : boolean := true;
EN_AUTONEG_G : boolean := true;
SIM_SPEEDUP_G : boolean := false;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz clock and reset
eth125Clk : in sl;
eth125Rst : in sl;
-- 62 MHz clock and reset
eth62Clk : in sl;
eth62Rst : in sl;
-- Addressing
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
ipAddrs : in IpAddrArray(NUM_IP_G-1 downto 0) := (others => IP_ADDR_DEFAULT_C);
udpPorts : in Word16Array(NUM_IP_G-1 downto 0) := (others => (others => '0'));
-- Data to/from GT
phyRxData : in EthRxPhyLaneInType;
phyTxData : out EthTxPhyLaneOutType;
-- Status signals
statusSync : out sl;
statusAutoNeg : out sl;
statusArpDone : out slv(NUM_IP_G-1 downto 0);
-- User clock and reset
userClk : in sl;
userRst : in sl;
-- User data interfaces
userTxData : in Word32Array(NUM_IP_G-1 downto 0);
userTxDataValid : in slv(NUM_IP_G-1 downto 0);
userTxDataLast : in slv(NUM_IP_G-1 downto 0);
userTxDataReady : out slv(NUM_IP_G-1 downto 0);
userRxData : out Word32Array(NUM_IP_G-1 downto 0);
userRxDataValid : out slv(NUM_IP_G-1 downto 0);
userRxDataLast : out slv(NUM_IP_G-1 downto 0);
userRxDataReady : in slv(NUM_IP_G-1 downto 0)
);
end Eth1000BaseXCore;
architecture Behavioral of Eth1000BaseXCore is
signal macTxData : EthMacDataType;
signal macRxData : EthMacDataType;
signal anPhyTxData : EthTxPhyLaneOutType;
signal ethPhyTxData : EthTxPhyLaneOutType;
signal autonegDone : sl;
signal linkSynced : sl;
begin
statusSync <= linkSynced;
statusAutoNeg <= autonegDone when EN_AUTONEG_G = true else '1';
-----------------------------
-- Core Ethernet Interface --
-----------------------------
U_EthCore : entity work.EthCore
generic map (
NUM_IP_G => NUM_IP_G,
MTU_SIZE_G => MTU_SIZE_G,
LITTLE_ENDIAN_G => LITTLE_ENDIAN_G,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz clock and reset
ethClk => eth125Clk,
ethRst => eth125Rst,
-- Addressing
macAddr => macAddr,
ipAddrs => ipAddrs,
udpPorts => udpPorts,
-- Connection to physical interface (GT or otherwise)
macTxData => macTxData,
macRxData => macRxData,
-- User clock and reset
userClk => userClk,
userRst => userRst,
-- Connection to user logic
userTxData => userTxData,
userTxDataValid => userTxDataValid,
userTxDataLast => userTxDataLast,
userTxDataReady => userTxDataReady,
userRxData => userRxData,
userRxDataValid => userRxDataValid,
userRxDataLast => userRxDataLast,
userRxDataReady => userRxDataReady
);
-----------------------------
-- Width translation --
-----------------------------
-- TX data width translation
U_Mux8to16 : entity work.Eth1000BaseX8To16Mux
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- Clocking to deal with the GT data out (62.5 MHz)
eth62Clk => eth62Clk,
eth62Rst => eth62Rst,
-- 125 MHz clock for 8 bit inputs
eth125Clk => eth125Clk,
eth125Rst => eth125Rst,
-- PHY (16 bit) data interface out
ethPhyDataOut => ethPhyTxData,
-- MAC (8 bit) data interface out
ethMacDataIn => macTxData
);
-- RX data width translation
U_Mux16to8 : entity work.Eth1000BaseX16To8Mux
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- Clocking to deal with the GT data out (62.5 MHz)
eth62Clk => eth62Clk,
eth62Rst => eth62Rst,
-- 125 MHz clock for 8 bit inputs
eth125Clk => eth125Clk,
eth125Rst => eth125Rst,
-- PHY (16 bit) data interface
ethPhyDataIn => phyRxData,
-- MAC (8 bit) data interface
ethMacDataOut => macRxData
);
--------------------------
-- Link synchronization --
--------------------------
U_LinkSync : entity work.Eth1000BaseXRxSync
generic map (
GATE_DELAY_G => GATE_DELAY_G,
PIPE_STAGES_G => 2
)
port map (
-- GT user clock and reset (62.5 MHz)
ethRx62Clk => eth62Clk,
ethRx62Rst => eth62Rst,
-- Local side has synchronization
rxLinkSync => linkSynced,
-- Incoming data from GT
phyRxData => phyRxData
);
---------------------
-- Autonegotiation --
---------------------
U_AutoNeg : entity work.Eth1000BaseXAutoNeg
generic map (
GATE_DELAY_G => GATE_DELAY_G,
PIPE_STAGES_G => 2,
SIM_SPEEDUP_G => SIM_SPEEDUP_G
)
port map (
-- GT user clock and reset (62.5 MHz)
ethRx62Clk => eth62Clk,
ethRx62Rst => eth62Rst,
-- Autonegotiation is done
autonegDone => autonegDone,
-- Link is synchronized
rxLinkSync => linkSynced,
-- Physical Interface Signals
phyRxData => phyRxData,
phyTxData => anPhyTxData
);
----------------------------------------------------------------
-- Multiplex data source between autonegotiation and MAC data --
----------------------------------------------------------------
process(eth62Clk)
begin
if rising_edge(eth62Clk) then
if (autonegDone = '1' and ethPhyTxData.valid = '1') or (EN_AUTONEG_G = false) then
phyTxData <= ethPhyTxData after GATE_DELAY_G;
else
phyTxData <= anPhyTxData after GATE_DELAY_G;
end if;
end if;
end process;
end Behavioral;
| lgpl-2.1 | f74239195ea3d2fe1fe6ad6b02aecaa8 | 0.504255 | 4.555191 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/trace_cntrl_1_2/hdl/vhdl/trace_cntrl_trace_cntrl_s_axi.vhd | 4 | 15,361 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity trace_cntrl_trace_cntrl_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
data_compare_V :out STD_LOGIC_VECTOR(63 downto 0);
length_r :out STD_LOGIC_VECTOR(31 downto 0);
sample_rate :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity trace_cntrl_trace_cntrl_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of data_compare_V
-- bit 31~0 - data_compare_V[31:0] (Read/Write)
-- 0x14 : Data signal of data_compare_V
-- bit 31~0 - data_compare_V[63:32] (Read/Write)
-- 0x18 : reserved
-- 0x1c : Data signal of length_r
-- bit 31~0 - length_r[31:0] (Read/Write)
-- 0x20 : reserved
-- 0x24 : Data signal of sample_rate
-- bit 31~0 - sample_rate[31:0] (Read/Write)
-- 0x28 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of trace_cntrl_trace_cntrl_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_DATA_COMPARE_V_DATA_0 : INTEGER := 16#10#;
constant ADDR_DATA_COMPARE_V_DATA_1 : INTEGER := 16#14#;
constant ADDR_DATA_COMPARE_V_CTRL : INTEGER := 16#18#;
constant ADDR_LENGTH_R_DATA_0 : INTEGER := 16#1c#;
constant ADDR_LENGTH_R_CTRL : INTEGER := 16#20#;
constant ADDR_SAMPLE_RATE_DATA_0 : INTEGER := 16#24#;
constant ADDR_SAMPLE_RATE_CTRL : INTEGER := 16#28#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_data_compare_V : UNSIGNED(63 downto 0);
signal int_length_r : UNSIGNED(31 downto 0);
signal int_sample_rate : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_DATA_COMPARE_V_DATA_0 =>
rdata_data <= RESIZE(int_data_compare_V(31 downto 0), 32);
when ADDR_DATA_COMPARE_V_DATA_1 =>
rdata_data <= RESIZE(int_data_compare_V(63 downto 32), 32);
when ADDR_LENGTH_R_DATA_0 =>
rdata_data <= RESIZE(int_length_r(31 downto 0), 32);
when ADDR_SAMPLE_RATE_DATA_0 =>
rdata_data <= RESIZE(int_sample_rate(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
data_compare_V <= STD_LOGIC_VECTOR(int_data_compare_V);
length_r <= STD_LOGIC_VECTOR(int_length_r);
sample_rate <= STD_LOGIC_VECTOR(int_sample_rate);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_DATA_COMPARE_V_DATA_0) then
int_data_compare_V(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_data_compare_V(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_DATA_COMPARE_V_DATA_1) then
int_data_compare_V(63 downto 32) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_data_compare_V(63 downto 32));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_LENGTH_R_DATA_0) then
int_length_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_length_r(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_SAMPLE_RATE_DATA_0) then
int_sample_rate(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_sample_rate(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| bsd-3-clause | c6532b21250696bbe24e662e084891e1 | 0.46553 | 3.754828 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_dongle_top.vhd | 1 | 9,240 | -------------------------------------------------------------------------------
--! @file onewire_dongle_top.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief 1-wire ID and temperature sensor USB dongle.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proasic3;
use proasic3.all;
--! @brief Entity declaration of onewire_dongle_top
--! @details
--! When push-button is pressed, read 1-wire bus and transmit all values over
--! UART at 115200 baud.
entity onewire_dongle_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_pad_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! @}
--! @name Push-button and LEDs
--! @{
--! Push-button (active-low)
pb_n_i : in std_ulogic;
--! LEDs
leds_o : out std_ulogic_vector(2 downto 0);
--! @}
--! @name UART
--! @{
--! Receive signal
uart_rx_i : in std_ulogic;
--! Transmit signal
uart_tx_o : out std_ulogic;
--! @}
--! @name 1-wire bus
--! @{
--! Receive signal
ow_rx_i : in std_ulogic;
--! Transmit signal
ow_tx_o : out std_ulogic;
--! Strong pull-up
ow_spup_o : out std_ulogic);
--! @}
end entity onewire_dongle_top;
--! RTL implementation of onewire_dongle_top
architecture rtl of onewire_dongle_top is
-----------------------------------------------------------------------------
--! @name Components
-----------------------------------------------------------------------------
--! @{
-- Input buffer to force INBUF on clock (can't use pin 10 otherwise)
component INBUF_LVCMOS33
port (
PAD : in std_logic;
Y : out std_logic);
end component;
--! @}
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
type state_t is (IDLE, FULL_RUN, GET_DATA, DATA);
type reg_t is record
state : state_t;
rd : std_ulogic;
addr : unsigned(4 downto 0);
end record;
constant init_c : reg_t := (
state => IDLE,
rd => '0',
addr => "00000");
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal clk_i : std_ulogic;
signal rst_n : std_ulogic;
signal pb_n : std_ulogic;
signal ow_rx : std_ulogic;
signal uart_rx : std_ulogic;
signal ow_discover : std_ulogic;
signal ow_get_temp : std_ulogic;
signal ow_busy : std_ulogic;
signal ow_done : std_ulogic;
signal ow_device_count : std_ulogic_vector(4 downto 0);
signal ow_error_too_many : std_ulogic;
signal ow_rd_addr : std_ulogic_vector(4 downto 0);
signal ow_rd_en : std_ulogic;
signal ow_rd_data : std_ulogic_vector(63 downto 0);
signal ow_rd_data_en : std_ulogic;
signal tx_done : std_ulogic;
signal uart_data : std_ulogic_vector(7 downto 0);
signal uart_data_en : std_ulogic;
signal uart_done : std_ulogic;
signal uart_cmd : std_ulogic_vector(7 downto 0);
signal uart_cmd_en : std_ulogic;
signal trigger_discover : std_ulogic;
signal trigger_get_temp : std_ulogic;
signal nxt_reg : reg_t;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
leds_o(0) <= ow_busy;
leds_o(1) <= '0' when ow_device_count = "00000" else '1';
leds_o(2) <= ow_error_too_many;
-----------------------------------------------------------------------------
-- Signal Assignments
-----------------------------------------------------------------------------
trigger_discover <= '1' when uart_cmd = x"01" and uart_cmd_en = '1' else '0';
trigger_get_temp <= '1' when uart_cmd = x"10" and uart_cmd_en = '1' else '0';
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
-- Input buffer to force INBUF on clock (can't use pin 10 otherwise)
INBUF_inst : INBUF_LVCMOS33
port map (
PAD => clk_pad_i,
Y => clk_i);
reset_gen_inst : entity work.reset_generator
port map (
clk_i => clk_i,
rst_asy_i => rst_asy_n_i,
rst_o => rst_n);
ext_inputs_inst : entity work.external_inputs
generic map (
init_value_g => '1',
num_inputs_g => 3,
filter_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i(0) => pb_n_i,
sig_i(1) => ow_rx_i,
sig_i(2) => uart_rx_i,
sig_o(0) => pb_n,
sig_o(1) => ow_rx,
sig_o(2) => uart_rx);
onewire_idtemp_inst : entity work.onewire_idtemp
generic map (
clk_frequency_g => 40e6,
max_devices_g => 16,
invert_bus_g => true,
invert_pullup_g => true)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
discover_i => ow_discover,
get_temp_i => ow_get_temp,
busy_o => ow_busy,
done_o => ow_done,
device_count_o => ow_device_count,
error_too_many_o => ow_error_too_many,
rd_addr_i => ow_rd_addr,
rd_en_i => ow_rd_en,
rd_data_o => ow_rd_data,
rd_data_en_o => ow_rd_data_en,
rd_busy_o => open,
strong_pullup_o => ow_spup_o,
rx_i => ow_rx,
tx_o => ow_tx_o);
array_tx_inst : entity work.array_tx
generic map (
data_count_g => 8,
data_width_g => 8)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
data_i => ow_rd_data,
data_en_i => ow_rd_data_en,
busy_o => open,
done_o => tx_done,
tx_data_o => uart_data,
tx_data_en_o => uart_data_en,
tx_done_i => uart_done);
uart_tx_inst : entity work.uart_tx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 347)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
data_i => uart_data,
data_en_i => uart_data_en,
busy_o => open,
done_o => uart_done,
tx_o => uart_tx_o);
uart_rx_inst : entity work.uart_rx
generic map (
data_width_g => 8,
parity_g => 0,
stop_bits_g => 1,
num_ticks_g => 347)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
rx_i => uart_rx,
data_o => uart_cmd,
data_en_o => uart_cmd_en,
error_o => open);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_n) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_n = '0' then
reset;
elsif rising_edge(clk_i) then
reg <= nxt_reg;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, pb_n, ow_busy, ow_done, tx_done, trigger_discover,
trigger_get_temp) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.rd <= '0';
ow_discover <= '0';
ow_get_temp <= '0';
ow_rd_addr <= std_ulogic_vector(reg.addr);
ow_rd_en <= reg.rd;
case reg.state is
when IDLE =>
if pb_n = '0' and ow_busy = '0' then
ow_discover <= '1';
nxt_reg.state <= FULL_RUN;
elsif trigger_discover = '1' and ow_busy = '0' then
ow_discover <= '1';
nxt_reg.state <= GET_DATA;
elsif trigger_get_temp = '1' and ow_busy = '0' then
ow_get_temp <= '1';
nxt_reg.state <= GET_DATA;
end if;
when FULL_RUN =>
if ow_done = '1' then
ow_get_temp <= '1';
nxt_reg.state <= GET_DATA;
end if;
when GET_DATA =>
if ow_done = '1' then
nxt_reg.rd <= '1';
nxt_reg.state <= DATA;
end if;
when DATA =>
if tx_done = '1' then
if reg.addr = "11111" then
nxt_reg <= init_c;
else
nxt_reg.addr <= reg.addr + 1;
nxt_reg.rd <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | 448092e52d3a936ade6a735f6ecf7020 | 0.432792 | 3.666667 | false | false | false | false |
satputeaditya/vernier-ring-oscillator-tdc | counter.vhd | 1 | 1,589 | -- counter.vhd
--**********************************************************************
-- Program to detect if STOP pulse is leading and lagging edge wrt START
--**********************************************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity counter is
port (
rst : in std_logic;
slow_clk : in std_logic;
fast_clk : in std_logic;
latch : in std_logic;
count : out std_logic_Vector(15 downto 0):=x"0000"
);
end entity;
architecture behave of counter is
signal slow_counter: std_logic_vector(15 downto 0):=x"0000";
signal fast_counter: std_logic_vector(15 downto 0):=x"0000";
begin
process(rst,slow_clk,fast_clk,latch)
begin
-- PROCESS 1 : SLOW COUNTER
if rst = '1' then
slow_counter <= (others =>'0');
elsif slow_clk'event and slow_clk = '1' then
if latch = '0' then
slow_counter <= slow_counter + '1';
else
slow_counter <= slow_counter;
end if;
end if;
-- PROCESS 2 : FAST COUNTER
if rst = '1' then
fast_counter <= (others =>'0');
elsif fast_clk'event and fast_clk = '1' then
if latch = '0' then
fast_counter <= fast_counter + '1';
else
fast_counter <= fast_counter;
end if;
end if;
-- PROCESS 3 : COUNTER LATCHING
if rst = '1' then
count <= (others =>'0');
elsif latch'event and latch = '1' then
count <= (slow_counter-fast_counter);
end if;
end process;
end behave; | mit | 7a14549e54fe4ac591d0ad92cb78fd80 | 0.539333 | 3.317328 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/testbench/tb_decoder.vhd | 1 | 9,447 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/13/2017 11:22:26 AM
-- Module Name: tb_decoder - Behavioral
-- Description: Test bench for decoder
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity tb_decoder is
-- Port ( );
end tb_decoder;
architecture Behavioral of tb_decoder is
-- Components
component decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end component;
-- Types for input
type test_input is array (0 to 163) of std_logic_vector(31 downto 0);
constant t_per: time := 1ns;
constant z_vec: std_logic_vector(31 downto 0) := (others => '0');
-- Signals
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal bin: std_logic_vector(63 downto 0) := (others => '0');
signal bin32: std_logic_vector(31 downto 0);
signal s_instr: instr_t;
signal s_funct3 : funct3_t;
signal s_funct6 : funct6_t;
signal s_funct7 : funct7_t;
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_opcode : opcode_t;
signal s_rs1 : reg_t;
signal s_rs2 : reg_t;
signal s_rs3 : reg_t;
signal s_rd : reg_t;
signal s_shamt : std_logic_vector(4 downto 0);
signal s_csr : std_logic_vector(31 downto 20);
signal inputs : test_input :=
(
"00000000000000000000000000110111",
"00000000000000000000000000010111",
"00000000000000000000000001101111",
"00000000000000000000000001100111",
"00000000000000000000000001100011",
"00000000000000000001000001100011",
"00000000000000000100000001100011",
"00000000000000000101000001100011",
"00000000000000000110000001100011",
"00000000000000000111000001100011",
"00000000000000000000000000000011",
"00000000000000000001000000000011",
"00000000000000000010000000000011",
"00000000000000000100000000000011",
"00000000000000000101000000000011",
"00000000000000000000000000100011",
"00000000000000000001000000100011",
"00000000000000000010000000100011",
"00000000000000000000000000010011",
"00000000000000000010000000010011",
"00000000000000000011000000010011",
"00000000000000000100000000010011",
"00000000000000000110000000010011",
"00000000000000000111000000010011",
"00000000000000000001000000010011",
"00000000000000000101000000010011",
"01000000000000000101000000010011",
"00000000000000000000000000110011",
"01000000000000000000000000110011",
"00000000000000000001000000110011",
"00000000000000000010000000110011",
"00000000000000000011000000110011",
"00000000000000000100000000110011",
"00000000000000000101000000110011",
"01000000000000000101000000110011",
"00000000000000000110000000110011",
"00000000000000000111000000110011",
"00000000000000000000000000001111",
"00000000000000000001000000001111",
"00000000000000000000000001110011",
"00000000000100000000000001110011",
"00000000000000000001000001110011",
"00000000000000000010000001110011",
"00000000000000000011000001110011",
"00000000000000000101000001110011",
"00000000000000000110000001110011",
"00000000000000000111000001110011",
"00000000000000000110000000000011",
"00000000000000000011000000000011",
"00000000000000000011000000100011",
"00000000000000000001000000010011",
"00000000000000000101000000010011",
"01000000000000000101000000010011",
"00000000000000000000000000011011",
"00000000000000000001000000011011",
"00000000000000000101000000011011",
"01000000000000000101000000011011",
"00000000000000000000000000111011",
"01000000000000000000000000111011",
"00000000000000000001000000111011",
"00000000000000000101000000111011",
"01000000000000000101000000111011",
"00000010000000000000000000110011",
"00000010000000000001000000110011",
"00000010000000000010000000110011",
"00000010000000000011000000110011",
"00000010000000000100000000110011",
"00000010000000000101000000110011",
"00000010000000000110000000110011",
"00000010000000000111000000110011",
"00000010000000000000000000111011",
"00000010000000000100000000111011",
"00000010000000000101000000111011",
"00000010000000000110000000111011",
"00000010000000000111000000111011",
"00010000000000000010000000101111",
"00011000000000000010000000101111",
"00001000000000000010000000101111",
"00000000000000000010000000101111",
"00100000000000000010000000101111",
"01100000000000000010000000101111",
"01000000000000000010000000101111",
"10000000000000000010000000101111",
"10100000000000000010000000101111",
"11000000000000000010000000101111",
"11100000000000000010000000101111",
"00010000000000000011000000101111",
"00011000000000000011000000101111",
"00001000000000000011000000101111",
"00000000000000000011000000101111",
"00100000000000000011000000101111",
"01100000000000000011000000101111",
"01000000000000000011000000101111",
"10000000000000000011000000101111",
"10100000000000000011000000101111",
"11000000000000000011000000101111",
"11100000000000000011000000101111",
"00000000000000000010000000000111",
"00000000000000000010000000100111",
"00000000000000000000000001000011",
"00000000000000000000000001000111",
"00000000000000000000000001001011",
"00000000000000000000000001001111",
"00000000000000000000000001010011",
"00001000000000000000000001010011",
"00010000000000000000000001010011",
"00011000000000000000000001010011",
"01011000000000000000000001010011",
"00100000000000000000000001010011",
"00100000000000000001000001010011",
"00100000000000000010000001010011",
"00101000000000000000000001010011",
"00101000000000000001000001010011",
"11000000000000000000000001010011",
"11000000000100000000000001010011",
"11100000000000000000000001010011",
"10100000000000000010000001010011",
"10100000000000000001000001010011",
"10100000000000000000000001010011",
"11100000000000000001000001010011",
"11010000000000000000000001010011",
"11010000000100000000000001010011",
"11110000000000000000000001010011",
"11000000001000000000000001010011",
"11000000001100000000000001010011",
"11010000001000000000000001010011",
"11010000001100000000000001010011",
"00000000000000000011000000000111",
"00000000000000000011000000100111",
"00000010000000000000000001000011",
"00000010000000000000000001000111",
"00000010000000000000000001001011",
"00000010000000000000000001001111",
"00000010000000000000000001010011",
"00001010000000000000000001010011",
"00010010000000000000000001010011",
"00011010000000000000000001010011",
"01011010000000000000000001010011",
"00100010000000000000000001010011",
"00100010000000000001000001010011",
"00100010000000000010000001010011",
"00101010000000000000000001010011",
"00101010000000000001000001010011",
"01000000000100000000000001010011",
"01000010000000000000000001010011",
"10100010000000000010000001010011",
"10100010000000000001000001010011",
"10100010000000000000000001010011",
"11100010000000000001000001010011",
"11000010000000000000000001010011",
"11000010000100000000000001010011",
"11010010000000000000000001010011",
"11010010000100000000000001010011",
"11000010001000000000000001010011",
"11000010001100000000000001010011",
"11100010000000000000000001010011",
"11010010001000000000000001010011",
"11010010001100000000000001010011",
"11110010000000000000000001010011",
"00000000001000000000000001110011",
"00010000001000000000000001110011",
"00110000001000000000000001110011",
"00010000010100000000000001110011",
"00010010000000000000000001110011"
);
begin
-- Declare components
dcode: decode
port map(
instr => bin,
instr_code => s_instr,
funct3 => s_funct3,
funct6 => s_funct6,
funct7 => s_funct7,
imm12 => s_imm12,
imm20 => s_imm20,
opcode => s_opcode,
rs1 => s_rs1,
rs2 => s_rs2,
rs3 => s_rs3,
rd => s_rd,
shamt => s_shamt,
csr => s_csr
);
-- Clock generation
tiktok: process
begin
wait for t_per/2;
clk <= '0';
wait for t_per/2;
clk <= '1';
end process; -- end tiktok
main: process
begin
bin32 <= bin(31 downto 0);
wait for t_per;
rst <= '0';
for I in 0 to 163 loop
bin <= z_vec & inputs(I);
wait for t_per;
end loop;
wait;
end process; --end main
end Behavioral;
| mit | 2487d95381d60a91f623a73cb1fca953 | 0.719064 | 5.145425 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp/onewire_discover.vhd | 1 | 9,439 | -------------------------------------------------------------------------------
--! @file onewire_discover.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Perform a search algorithm to discover devices on the bus.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
use work.onewire_idtemp_pkg.all;
--! @brief Entity declaration of onewire_discover
entity onewire_discover is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Start search algorithm
discover_i : in std_ulogic;
--! Discovered device ID
id_o : out std_ulogic_vector(63 downto 0);
--! Discovered device ID enable
id_en_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name Bus interface signals
--! @{
--! Send a bus reset command
bus_rst_o : out std_ulogic;
--! Send data bit
bit_send_o : out std_ulogic;
--! The data bit to be sent
bit_o : out std_ulogic;
--! Receive data bit
bit_recv_o : out std_ulogic;
--! The received data bit
bit_i : in std_ulogic;
--! The received data bit enable
bit_en_i : in std_ulogic;
--! Done flag
bit_done_i : in std_ulogic);
--! @}
end entity onewire_discover;
--! RTL implementation of onewire_discover
architecture rtl of onewire_discover is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
constant lfsr_len_c : natural := lfsr_length(cmd_search_c'length);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant lfsr_max_c : lfsr_t := lfsr_shift(lfsr_seed_c, cmd_search_c'length - 1);
type state_t is (IDLE, RESET_DONE, SEARCH_COMMAND, READ_ID_BIT,
READ_CMP_ID_BIT, COMPARE, CHECK);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
done : std_ulogic;
id : std_ulogic_vector(id_o'high + 1 downto id_o'low + 1);
id_en : std_ulogic;
cmd : std_ulogic_vector(7 downto 0);
bus_rst : std_ulogic;
bit_send : std_ulogic;
bit_recv : std_ulogic;
crc_reset : std_ulogic;
id_bit : std_ulogic;
cmp_id_bit : std_ulogic;
search : std_ulogic;
id_bit_number : unsigned(6 downto 0);
marker : unsigned(6 downto 0);
last_discrepancy : unsigned(6 downto 0);
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
done => '0',
id => (others => '0'),
id_en => '0',
cmd => cmd_search_c,
bus_rst => '0',
bit_send => '0',
bit_recv => '0',
crc_reset => '0',
id_bit => '0',
cmp_id_bit => '0',
search => '0',
id_bit_number => to_unsigned(1, 7),
marker => to_unsigned(0, 7),
last_discrepancy => to_unsigned(0, 7));
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
signal crc_valid : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
id_o <= reg.id;
id_en_o <= reg.id_en;
done_o <= reg.done;
bus_rst_o <= reg.bus_rst;
bit_send_o <= reg.bit_send;
bit_recv_o <= reg.bit_recv;
bit_o <= reg.search;
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
crc_inst : entity work.onewire_crc
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
reset_i => reg.crc_reset,
data_i => reg.search,
data_en_i => reg.bit_send,
valid_o => crc_valid);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, discover_i, bit_i, bit_en_i, bit_done_i, crc_valid) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.id_en <= init_c.id_en;
nxt_reg.bus_rst <= init_c.bus_rst;
nxt_reg.bit_send <= init_c.bit_send;
nxt_reg.bit_recv <= init_c.bit_recv;
nxt_reg.crc_reset <= init_c.crc_reset;
case reg.state is
when IDLE =>
if discover_i = '1' then
nxt_reg.bus_rst <= '1';
nxt_reg.state <= RESET_DONE;
end if;
when RESET_DONE =>
if bit_done_i = '1' then
if bit_i = '1' then
nxt_reg <= init_c;
nxt_reg.done <= '1';
else
nxt_reg.bit_send <= '1';
nxt_reg.search <= reg.cmd(reg.cmd'low);
nxt_reg.cmd <= '0' & reg.cmd(reg.cmd'high downto reg.cmd'low + 1);
nxt_reg.state <= SEARCH_COMMAND;
end if;
end if;
when SEARCH_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = lfsr_max_c then
nxt_reg.bit_recv <= '1';
nxt_reg.crc_reset <= '1';
nxt_reg.state <= READ_ID_BIT;
else
nxt_reg.bit_send <= '1';
nxt_reg.search <= reg.cmd(reg.cmd'low);
nxt_reg.cmd <= '0' & reg.cmd(reg.cmd'high downto reg.cmd'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when READ_ID_BIT =>
if bit_en_i = '1' then
nxt_reg.id_bit <= bit_i;
nxt_reg.bit_recv <= '1';
nxt_reg.state <= READ_CMP_ID_BIT;
end if;
when READ_CMP_ID_BIT =>
if bit_en_i = '1' then
nxt_reg.cmp_id_bit <= bit_i;
nxt_reg.state <= COMPARE;
end if;
when COMPARE =>
nxt_reg.state <= CHECK;
nxt_reg.bit_send <= '1';
if reg.id_bit = '1' and reg.cmp_id_bit = '1' then
nxt_reg <= init_c;
nxt_reg.done <= '1';
elsif reg.id_bit = '0' and reg.cmp_id_bit = '0' then
if reg.id_bit_number = reg.last_discrepancy then
nxt_reg.id(to_integer(reg.id_bit_number)) <= '1';
nxt_reg.search <= '1';
elsif reg.id_bit_number > reg.last_discrepancy then
nxt_reg.id(to_integer(reg.id_bit_number)) <= '0';
nxt_reg.search <= '0';
nxt_reg.marker <= reg.id_bit_number;
else
nxt_reg.search <= reg.id(to_integer(reg.id_bit_number));
if reg.id(to_integer(reg.id_bit_number)) = '0' then
nxt_reg.marker <= reg.id_bit_number;
end if;
end if;
else
nxt_reg.id(to_integer(reg.id_bit_number)) <= reg.id_bit;
nxt_reg.search <= reg.id_bit;
end if;
when CHECK =>
if bit_done_i = '1' then
if to_integer(reg.id_bit_number) < reg.id'length then
nxt_reg.id_bit_number <= reg.id_bit_number + 1;
nxt_reg.bit_recv <= '1';
nxt_reg.state <= READ_ID_BIT;
else
if to_integer(reg.marker) = 0 then
nxt_reg <= init_c;
nxt_reg.done <= '1';
else
nxt_reg <= init_c;
nxt_reg.last_discrepancy <= reg.marker;
nxt_reg.bus_rst <= '1';
nxt_reg.state <= RESET_DONE;
end if;
if crc_valid = '0' then
nxt_reg.id <= (others => '1');
else
nxt_reg.id <= reg.id;
end if;
nxt_reg.id_en <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | cf62ed192599dcae48b59a25da72a93e | 0.43119 | 3.741181 | false | false | false | false |
Subsets and Splits