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Kalugy/Procesadorarquitectura | Terceryfullprocesador/TbEFNEW.vhd | 2 | 3,635 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:25:10 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Segundoprocesador/TbEFNEW.vhd
-- Project Name: Segundoprocesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RF
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbEFNEW IS
END TbEFNEW;
ARCHITECTURE behavior OF TbEFNEW IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
dwr : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
crs1 : OUT std_logic_vector(31 downto 0);
crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal dwr : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal crs1 : std_logic_vector(31 downto 0);
signal crs2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
dwr => dwr,
rst => rst,
crs1 => crs1,
crs2 => crs2
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rs1<="000001";
rs2<="000000";
rd<="000010";
dwr<="00010000000000011100000000000000";
rst<='1';
wait for 200 ns;
rs1<="000010";
rs2<="000000";
rd<="000001";
dwr<="00010000000000000000000000000111";
rst<='0';
wait for 200 ns;
rs1<="000001";
rs2<="000000";
rd<="010000";
dwr<="00010000000000000000000000000000";
rst<='0';
wait for 200 ns;
rs1<="000000";
rs2<="000100";
rd<="000100";
dwr<="00010000000000000000000000000000";
rst<='0';
wait for 200 ns;
rs1<="000001";
rs2<="000100";
rd<="000011";
dwr<="00010000000000000000000000000001";
rst<='0';
wait for 200 ns;
rs1<="000001";
rs2<="000100";
rd<="000011";
dwr<="00010000000000000000000000000001";
rst<='1';
wait for 200 ns;
rs1<="000001";
rs2<="010000";
rd<="000011";
dwr<="00010000000000000000000000000001";
rst<='0';
wait for 200 ns;
rs1<="000100";
rs2<="000011";
rd<="000000";
dwr<="00010000000000000000000000000001";
rst<='0';
-- insert stimulus here
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 75e70aff73d03c276443a41aaa88e767 | 0.589821 | 3.656942 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TB2_MultiByte_4ByteAligned.vhd | 1 | 9,420 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TB2_MultiByte_4ByteAligned - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB2_MultiByte_4ByteAligned is
end TB2_MultiByte_4ByteAligned;
architecture Behavioral of TB2_MultiByte_4ByteAligned is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
type input_2e is array (0 to 1) of std_logic_vector(31 downto 0);
type input_3e is array (0 to 2) of std_logic_vector(31 downto 0);
constant entrada1 : input_2e := ( x"2362f9de", x"fbf1402a" );
constant entrada2 : input_3e := ( x"2362f9de", x"fbf1402a", x"3412cdab" );
constant resultsBank : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
-- if( rising_edge(clk) ) then
-- if( resultsBankCounter = resultReference'length ) then
-- errorDetected <= '0';
-- else
-- if (resultReady = '1') then
-- if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
-- errorDetected <= '1';
-- else
-- errorDetected <= '0';
-- end if;
-- resultsBankCounter <= resultsBankCounter+1;
-- else
-- errorDetected <= '0';
-- end if;
-- end if;
-- end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "11";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= entrada1(0);
start <= '1';
finalBlock <= '0';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
inputBlock <= entrada1(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
readInput <= '1';
wait for clk_period;
readInput <= '0';
finalBlock <= '0';
start <= '0';
wait for 3*clk_period;
--SEGUNDA PRUEBA
readInput <= '1';
start <= '1';
finalBlock <= '0';
inputBlock <= entrada2(0);
readInput <= '1';
wait for clk_period;
inputBlock <= entrada2(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
inputBlock <= entrada2(2);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
wait for clk_period;
readInput <= '0';
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
--TERCERA PRUEBA, los mismos datos de la segunda, pero con espaciados
readInput <= '1';
start <= '1';
finalBlock <= '0';
inputBlock <= entrada2(0);
readInput <= '1';
wait for clk_period;
inputBlock <= entrada2(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '1';
inputBlock <= entrada2(2);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
wait for clk_period;
readInput <= '0';
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
| bsd-3-clause | 0e4430132ee37567590d14bf6ba714fb | 0.54034 | 4.008511 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/CU.vhd | 2 | 3,088 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:09:48 10/04/2017
-- Design Name:
-- Module Name: CU - ArqCU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CU is
Port ( op3 : in STD_LOGIC_VECTOR (5 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end CU;
architecture ArqCU of CU is
begin
process(op, op3) begin
case(op) is
when "10" =>
if(op3="000001") then--AND
ALUOP <= "000001";
end if;
if(op3="000010") then-- OR
ALUOP <= "000010";
end if;
if(op3="000011") then-- XOR
ALUOP <= "000011";
end if;
if(op3="000111") then-- XNOR
ALUOP <= "000111";
end if;
if(op3="000000") then-- ADD
ALUOP <= "000000";
end if;
if(op3="000100") then-- SUB
ALUOP <= "000100";
end if;
if(op3="000101") then-- ANDN
ALUOP <= "000101";
end if;
if(op3="000110") then-- ORN
ALUOP <= "000110";
end if;
--instrucciones con Conditional Codes
if(op3="010100") then--SUBcc
ALUOP <= "010100";
end if;
if(op3="010000") then--ADDcc
ALUOP <= "010000";
end if;
if(op3="010001") then--ANDcc
ALUOP <= "010001";
end if;
if(op3="010010") then--ORcc
ALUOP <= "010010";
end if;
if(op3="010101") then--ANDNcc
ALUOP <= "010101";
end if;
if(op3="010110") then--ORNcc
ALUOP <= "010110";
end if;
if(op3="010011") then--XORcc
ALUOP <= "010011";
end if;
if(op3="010111") then--XNORcc
ALUOP <= "010111";
end if;
--instrucciones con Carry
if(op3="001100") then--SUBX
ALUOP <= "001100";
end if;
if(op3="001000") then--ADDX
ALUOP <= "001000";
end if;
--instrucciones con carry y Conditional Codes
if(op3="011000") then--ADDxcc
ALUOP <= "011000";
end if;
if(op3="011100") then--SUBxcc
ALUOP <= "011100";
end if;
--instrucciones con
if(op3="100101") then--sll
ALUOP <= "100101";
end if;
if(op3="100110") then--slr
ALUOP <= "100110";
end if;
--- instrucciones save y restore
if(op3="111100") then--save
ALUOP <= "111100";
end if;
if(op3="111101") then--restore
ALUOP <= "111101";
end if;
--when "11" =>
when others => ALUOP<= "111111";
end case;
end process;
end ArqCU;
| gpl-3.0 | 40984d6a076897f9b682bdf57254b295 | 0.535622 | 3.253952 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/EthFrameAnalizer.vhd | 1 | 9,683 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2014 13:25:44
-- Design Name:
-- Module Name: Eth_GMII_RXTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Modulo ue analiza la recepción de
-- paquetes ethernet y analiza sus estadìsticas.
-- Las señales que utiliza son las recibidas de una interfaz GMII.
-- No valdia preambulo, delimitador de inicio de trama ni checksum.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity EthFrameAnalizer is
Port (
gmii_rx_clk : in STD_LOGIC;
gmii_rx_data : in STD_LOGIC_VECTOR (7 downto 0);
gmii_rx_dataValid : in STD_LOGIC;
gmii_rx_col : in STD_LOGIC;
gmii_rx_err : in STD_LOGIC;
--Caracteristicas extraidas
--Se actualizan de forma simultanea al momento que se termina la recepcion del paquete
--Solo son validos durante un cicl ode reloj, cuando packet_evaluationFinished es '1'
packet_evaluationFinished : out std_logic;
packet_actualByte : out std_logic_vector(15 downto 0);
packet_MACDstAddrBroadcast : out std_logic;
packet_PHYSignaledError : out std_logic;
packet_Valid : out std_logic;-- Si el paquete es valida, comprueba, PHYSignaledError y Len
packet_EthTypeOrLen : out std_logic;
packet_EtherType_Len : out std_logic_vector(15 downto 0);
packet_IPV4 : out std_logic;
packet_IPV6 : out std_logic;
packet_ARP : out std_logic
);
end EthFrameAnalizer;
architecture Behavioral of EthFrameAnalizer is
signal packet_MACDstAddrBroadcast_newValue : std_logic;
signal packet_IPV4_newValue : std_logic;
signal packet_IPV6_newValue : std_logic;
signal packet_ARP_newValue : std_logic;
signal eth_rx_frameEnded : boolean;-- Señal que indica que se ha terminado la captura de un frame ethernet
--Con esta señal las caracterísitcas del frame recibido deben guardarse y reniciarse para
--estar listas para el sgte
signal eth_rx_MACDstAddrBroadcast : boolean := false;
signal eth_rx_PHYErr : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_Type_Len_Byte1 : std_logic_vector(7 downto 0); --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_Type_Len_Byte2 : std_logic_vector(7 downto 0); --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_TypeIPV4 : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_TypeIPV6 : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_isARP : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_payloadLen : std_logic_vector(15 downto 0) := x"002E"; --Cuando el chip PHY ha indicado error durante la recepciòn del frame
signal eth_rx_lenOK : boolean := false;
signal eth_rx_EthTypeOrLen : boolean := false; --EtherType='1', Len= '0'
signal thisLenOK : boolean := true;
signal eth_rx_payloadLen_newValue : std_logic_vector(15 downto 0);
signal oldDataValid : std_logic;
signal bytesCounter : std_logic_vector(15 downto 0) := x"0000";
signal MACDst_Byte_IsFF : std_logic_vector(5 downto 0) := "000000";
signal MACDst_Byte_IsFF_Registered : std_logic_vector(5 downto 0) := "000000";
signal MACDst_IsFF : std_logic := '0';
signal evaluateMACBcst : boolean;
signal EtherTypeByte1IsIPV4 : boolean := false;
signal EtherTypeByte1IsIPV6 : boolean := false;
signal EtherTypeByte1IsARP : boolean := false;
signal EtherTypeByte2IsIPV4 : boolean := false;
signal EtherTypeByte2IsIPV6 : boolean := false;
signal EtherTypeByte2IsARP : boolean := false;
begin
--tratar eth_rx_frameEnd
eth_rx_frameEnded <= (gmii_rx_dataValid='0') and (oldDataValid='1');
packet_evaluationFinished<= '1' when eth_rx_frameEnded else '0';
detectEndOfFrame: process(gmii_rx_clk, gmii_rx_dataValid, oldDataValid)
begin
if ( rising_edge(gmii_rx_clk) ) then
oldDataValid<=gmii_rx_dataValid;
end if;
end process detectEndOfFrame;
bytesCounterUdpate: process (gmii_rx_clk, gmii_rx_dataValid, eth_rx_frameEnded)
begin
if( rising_edge(gmii_rx_clk) ) then
if ( eth_rx_frameEnded ) then
bytesCounter <= ( others => '0');
else
if ( gmii_rx_dataValid = '1') then
bytesCounter <= (bytesCounter+1);
end if;
end if;
end if;
end process bytesCounterUdpate;
--detectar MAC es broadcast
evaluateMACBcst <= ((gmii_rx_data = x"FF") and (gmii_rx_dataValid='1') );
evaluateDstMACIsBroadcast : for macOffset in 0 to 5 generate
MACDst_Byte_IsFF(macOffset) <= '1' when ( (bytesCounter = (x"0008"+macOffset)) and evaluateMACBcst ) else '0';
end generate evaluateDstMACIsBroadcast;
detectMACIsBroadcast: process(gmii_rx_clk, gmii_rx_dataValid, oldDataValid, gmii_rx_data, eth_rx_frameEnded, bytesCounter, MACDst_Byte_IsFF)
begin
if( rising_edge(gmii_rx_clk) ) then
if (eth_rx_frameEnded) then
MACDst_Byte_IsFF_Registered <= "000000";
else
registerActualByteMACIsBroadcast : for macOffset in 0 to 5 loop
if (bytesCounter = (x"0008"+macOffset)) then
MACDst_Byte_IsFF_Registered(macOffset) <= MACDst_Byte_IsFF(macOffset);
end if;
end loop;
end if;
end if;
end process detectMACIsBroadcast;
eth_rx_MACDstAddrBroadcast <= true when ( MACDst_Byte_IsFF_Registered = (MACDst_Byte_IsFF_Registered'range => '1') ) else false;--haciendo un AND de todos los valores del vector
-- detect PHY error
detectPHYError: process (gmii_rx_clk, gmii_rx_col, gmii_rx_err, eth_rx_frameEnded, eth_rx_PHYErr )
begin
if( rising_edge(gmii_rx_clk) ) then
if(eth_rx_frameEnded)then
eth_rx_PHYErr <= false;
else
if( (gmii_rx_err='1') or (gmii_rx_col='1') ) then
eth_rx_PHYErr <= true;
end if;
end if;
end if;
end process;
--detectar paquetes TypeIPV4, TypeIPV6 ó ARP
thisLenOK <= ((eth_rx_Type_Len_Byte1 & gmii_rx_data)>x"002E");
eth_rx_payloadLen_newValue <= (eth_rx_Type_Len_Byte1 & gmii_rx_data) when thisLenOK else x"002E";
detectTypeOrLen: process (gmii_rx_clk , eth_rx_frameEnded, eth_rx_PHYErr, bytesCounter, gmii_rx_data, gmii_rx_dataValid )
begin
if( rising_edge(gmii_rx_clk) ) then
if( (bytesCounter=20) and (gmii_rx_dataValid='1') ) then
eth_rx_Type_Len_Byte1 <= gmii_rx_data;
end if;
if( (bytesCounter=21) and (gmii_rx_dataValid='1') ) then
eth_rx_Type_Len_Byte2 <= gmii_rx_data;
eth_rx_EthTypeOrLen <= ((eth_rx_Type_Len_Byte1 & gmii_rx_data)>x"05DC");
eth_rx_lenOK <= thisLenOK;
eth_rx_payloadLen <= eth_rx_payloadLen_newValue;
end if;
end if;
end process;
eth_rx_TypeIPV4 <= (eth_rx_Type_Len_Byte1 = x"08") and (eth_rx_Type_Len_Byte2 = x"00");
eth_rx_TypeIPV6 <= (eth_rx_Type_Len_Byte1 = x"86") and (eth_rx_Type_Len_Byte2 = x"DD");
eth_rx_isARP <= (eth_rx_Type_Len_Byte1 = x"08") and (eth_rx_Type_Len_Byte2 = x"06") and eth_rx_MACDstAddrBroadcast;
--eth_rx_EthTypeOrLen <= eth_rx_payloadLen>
--Registrar las señales a la salida
packet_evaluationFinished <= '1' when (eth_rx_frameEnded) else '0';
packet_actualByte <= bytesCounter;
packet_PHYSignaledError <= '1' when eth_rx_PHYErr else '0';
packet_Valid <= '1' when (not(eth_rx_PHYErr) and eth_rx_lenOK) else '0';
packet_EthTypeOrLen <= '1' when eth_rx_EthTypeOrLen else '0';
packet_EtherType_Len <= eth_rx_payloadLen;
packet_MACDstAddrBroadcast_newValue <= '1' when eth_rx_MACDstAddrBroadcast else '0';
packet_IPV4_newValue <= '1' when eth_rx_TypeIPV4 else '0';
packet_IPV6_newValue <= '1' when eth_rx_TypeIPV6 else '0';
packet_ARP_newValue <= '1' when eth_rx_isARP else '0';
registerResults: process (gmii_rx_clk, eth_rx_frameEnded, eth_rx_PHYErr, bytesCounter, gmii_rx_data, gmii_rx_dataValid )
begin
if( rising_edge(gmii_rx_clk) ) then
packet_MACDstAddrBroadcast <= packet_MACDstAddrBroadcast_newValue;
packet_IPV4 <= packet_IPV4_newValue;
packet_IPV6 <= packet_IPV6_newValue;
packet_ARP <= packet_ARP_newValue;
end if;
end process registerResults;
end Behavioral ;
| bsd-3-clause | d2f147bf8b0922b372f63b0307e9f0a1 | 0.60302 | 3.756022 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/sim/tri_intersect_ap_fsub_7_full_dsp_32.vhd | 1 | 10,722 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fsub_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fsub_7_full_dsp_32_arch;
| mit | e4b2f9d17e1fbf046a75c48cd669247e | 0.632625 | 3.216922 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/componant_2_tb.vhd | 2 | 1,748 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:21:57 01/15/2015
-- Design Name:
-- Module Name: componant_2_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2_tb is
end componant_2_tb;
architecture Behavioral of componant_2_tb is
signal entree1, entree2, entree3, sortie1, sortie2 : std_logic;
component componant_2
port (a1,b1,rin : in std_logic;
s1,rout : out std_logic);
end component;
begin
uut: componant_2 port map (a1 => entree1, b1 => entree2, rin => entree3, rout => sortie1, s1 => sortie2);
stimuli:process
begin
entree1<='0';
entree2<='0';
entree3<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
entree2<='1';
wait for 30 ns;
entree1<='0';
entree2<='0';
entree3<='1';
wait for 30 ns;
entree1<='1';
entree3<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
entree3<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end Behavioral;
| gpl-2.0 | 5e04dcd7ed02fc24ed9ae4dfb75911f0 | 0.561213 | 3.342256 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/WindowsManager.vhd | 1 | 2,629 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
else cwpout<='0';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; | gpl-3.0 | e08b5ce584798690c33fd48546f6449d | 0.590719 | 2.848321 | false | false | false | false |
alemedeiros/flappy_vhdl | modules/obstacles_pack.vhd | 1 | 2,315 | -- file: modules/obstacles_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package obstacles is
-- Set of n registers to save the obstacles positions (2 integers for each
-- obstacle), when an obstacle reaches the horizontal position 0, it is
-- automatically discarded and a new one is read from in_{low,high}
component obst_regbank
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- New obstacles input
in_low : in integer range 0 to V_RES - 1 ;
in_high : in integer range 0 to V_RES - 1 ;
up_clk : in std_logic ;
-- Read current values
id : in integer range 0 to N_OBST - 1 ;
low : out integer range 0 to V_RES - 1 ;
high : out integer range 0 to V_RES - 1 ;
pos : out integer range 0 to H_RES / N_OBST - 1 ;
f_low : out integer range 0 to V_RES - 1 ;
f_high : out integer range 0 to V_RES - 1 ;
-- Control signal
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic ;
obst_rem : out std_logic
) ;
end component ;
-- Update and generate new obstacles for game.
component update_obstacles
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
new_obst : in std_logic ;
obst_count : buffer integer range -2 to 255 ;
low_obst : out integer range 0 to V_RES - 1 ;
high_obst : out integer range 0 to V_RES - 1 ;
obst_rem : out std_logic ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
-- Random number module.
component generate_random
generic (
V_RES : integer := 96 -- Vertical Resolution
) ;
port (
seed : in std_logic_vector (4 downto 0) ;
rand : out integer range 0 to (V_RES/2 - 1) ;
clock : in std_logic
) ;
end component ;
end obstacles ;
| bsd-3-clause | bc4f14051e5c291270233118a3b46caf | 0.587473 | 3.507576 | false | false | false | false |
nickdesaulniers/Omicron | clk_blk/clk_blk.vhd | 1 | 2,675 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 12.3
-- \ \ Application : xaw2vhdl
-- / / Filename : clk_blk.vhd
-- /___/ /\ Timestamp : 04/07/2011 10:39:11
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st X:\\DSD\clk_blk\ipcore_dir\.\clk_blk.xaw X:\\DSD\clk_blk\ipcore_dir\.\clk_blk
--Design Name: clk_blk
--Device: xc3s500e-4fg320
--
-- Module clk_blk
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clk_blk is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK180_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clk_blk;
architecture BEHAVIORAL of clk_blk is
signal CLKFB_IN : std_logic;
signal CLK0_BUF : std_logic;
signal CLK180_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLK0_OUT <= CLKFB_IN;
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK180_BUFG_INST : BUFG
port map (I=>CLK180_BUF,
O=>CLK180_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>CLK180_BUF,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | d7083738cf97102f286d37cb61c7169c | 0.459065 | 3.689655 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TbPC.vhd | 3 | 2,951 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:44:25 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TbPC.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PC
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbPC IS
END TbPC;
ARCHITECTURE behavior OF TbPC IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PC
PORT(
inPC : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Clk : IN std_logic;
outPC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal inPC : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
signal Clk : std_logic := '0';
--Outputs
signal outPC : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PC PORT MAP (
inPC => inPC,
Reset => Reset,
Clk => Clk,
outPC => outPC
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Reset <= '0';
inPC <= "00000000000000000000000000000000";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000000001";
wait for 100 ns;
Reset <= '1';
inPC <= "00000000000000000000000000000000";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000000001";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000000011";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000000111";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000001111";
wait for 100 ns;
Reset <= '0';
inPC <= "00000000000000000000000000000001";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 4f1f0747bd6d73e942d8abbd8dc63d43 | 0.583531 | 4.191761 | false | false | false | false |
loetlab-jena/das-atv | hdl/src/nco.vhd | 1 | 1,812 | -- title: Numeric Controlled Oscillator
-- author: Sebastian Weiss <[email protected]>
-- last change: 14.09.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nco is
generic
(
A : positive; -- amplitude resolution
F : positive; -- frequency resolution
P : positive; -- phase resolution
N : positive; -- number of stages
FCW : positive -- frequency control word
);
port
(
clk : in std_logic; -- signal processing clock
sin : out signed(A-1 downto 0); -- sine output
cos : out signed(A-1 downto 0) -- cosine output
);
end entity;
architecture behavioral of nco is
type q_vector is array(natural range <>) of std_logic_vector(1 downto 0);
signal cordic_phi : unsigned(P-3 downto 0);
signal cordic_sin : signed(A-1 downto 0);
signal cordic_cos : signed(A-1 downto 0);
signal phi : unsigned(P-1 downto 0) := (others => '0');
signal phase : unsigned(P-2 downto 0);
signal q : q_vector(N+1 downto 0) := (others => (others => '0'));
begin
cordic : entity work.cordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
phi => cordic_phi,
sin => cordic_sin,
cos => cordic_cos
);
process
begin
wait until rising_edge(clk);
phi <= phi + FCW;
if phi(P-2) = '1' then
phase <= 0 - phi(P-2 downto 0);
else
phase <= phi(P-2 downto 0);
end if;
q(0) <= phi(P-1) & phi(P-2);
for i in 1 to N+1 loop
q(i) <= q(i-1);
end loop;
if q(N+1) = "00" then
sin <= cordic_sin;
cos <= cordic_cos;
elsif q(N+1) = "01" then
sin <= cordic_sin;
cos <= -cordic_cos;
elsif q(N+1) = "10" then
sin <= -cordic_sin;
cos <= -cordic_cos;
elsif q(N+1) = "11" then
sin <= -cordic_sin;
cos <= cordic_cos;
end if;
end process;
cordic_phi <= phase(P-3 downto 0);
end behavioral;
| gpl-2.0 | 123de2499f27407b6552a1030bd3d92d | 0.605408 | 2.599713 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd | 1 | 81,357 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_cdc_v1_0;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
| mit | 72f5497bf15eab8875e8da105b4b41dd | 0.438168 | 4.446224 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd | 1 | 39,563 | -- *************************************************************************
--
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--
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-- of Xilinx, Inc. and is protected under U.S. and
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-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
-- ch2_updt_curdesc_wren : out std_logic ; --
-- ch2_updt_curdesc : out std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_INCLUDE_MM2S => C_INCLUDE_CH1 ,
C_INCLUDE_S2MM => C_INCLUDE_CH2 ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
-- updt2_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt2_curdesc => ch2_updt_curdesc ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch1_updt_tready ,
-- S2MM Stream Out To DataMover
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_NO_QUEUE;
-- Channel 1 NOT included therefore tie ch1 outputs off
--GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
--begin
-- ch1_updt_curdesc_wren <= '0';
-- ch1_updt_curdesc <= (others => '0');
-- ch1_updt_queue_empty <= '1';
-- ch1_updt_ioc <= '0';
-- ch1_dma_interr <= '0';
-- ch1_dma_slverr <= '0';
-- ch1_dma_decerr <= '0';
-- m_axis_ch1_updt_tdata <= (others => '0');
-- m_axis_ch1_updt_tlast <= '0';
-- m_axis_ch1_updt_tvalid <= '0';
-- s_axis_ch1_updtptr_tready <= '0';
-- s_axis_ch1_updtsts_tready <= '0';
--end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
--GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
--
--begin
--
-- --*************************************************************************
-- --** CHANNEL 2 - DESCRIPTOR QUEUE **
-- --*************************************************************************
-- -- If Descriptor Update queueing enabled then instantiate Queue Logic
-- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
-- begin
-- ---------------------------------------------------------------------------
-- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
-- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
-- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_QUEUE;
--
--
-- --*****************************************************************************
-- --** CHANNEL 2 - NO DESCRIPTOR QUEUE **
-- --*****************************************************************************
--
-- -- No update queue enabled, therefore map internal stream logic
-- -- directly to channel port.
-- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
-- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_NO_QUEUE;
--
--end generate GEN_CH2_UPDATE_Q_IF;
--
---- Channel 2 NOT included therefore tie ch2 outputs off
--GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
--begin
-- ch2_updt_curdesc_wren <= '0';
-- ch2_updt_curdesc <= (others => '0');
-- ch2_updt_queue_empty <= '1';
--
-- ch2_updt_ioc <= '0';
-- ch2_dma_interr <= '0';
-- ch2_dma_slverr <= '0';
-- ch2_dma_decerr <= '0';
--
-- m_axis_ch2_updt_tdata <= (others => '0');
-- m_axis_ch2_updt_tlast <= '0';
-- m_axis_ch2_updt_tvalid <= '0';
--
-- s_axis_ch2_updtptr_tready <= '0';
-- s_axis_ch2_updtsts_tready <= '0';
--
--end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
--TO_DATAMVR_MUX : process(ch1_updt_active,
-- ch2_updt_active,
-- m_axis_ch1_updt_tdata,
-- m_axis_ch1_updt_tlast,
-- m_axis_ch1_updt_tvalid,
-- m_axis_ch2_updt_tdata,
-- m_axis_ch2_updt_tlast,
-- m_axis_ch2_updt_tvalid)
-- begin
-- if(ch1_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
-- elsif(ch2_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
-- else
-- s_axis_s2mm_tdata <= (others => '0');
-- s_axis_s2mm_tlast <= '0';
-- s_axis_s2mm_tvalid <= '0';
-- end if;
-- end process TO_DATAMVR_MUX;
--
--m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
--m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
--
end implementation;
| mit | 6d931ece9fb7f0f8760c3afaaaf4bec3 | 0.351996 | 4.668751 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_register_s2mm.vhd | 1 | 174,353 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register_s2mm.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register_s2mm is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
tdest_in : in std_logic_vector (5 downto 0) ;
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register_s2mm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant SGCTL_INDEX : integer := 0;
constant DMACR_INDEX : integer := 1; -- DMACR Register index
constant DMASR_INDEX : integer := 2; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index
constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index
constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index
constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index
constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index
constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index
constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index
constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index
constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index
constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index
constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index
constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index
constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index
constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index
constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index
constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index
constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index
constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index
constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index
constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index
constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index
constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index
constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index
constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index
constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index
constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index
constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index
constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index
constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index
constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index
constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index
constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index
constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index
constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index
constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index
constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index
constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index
constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index
constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index
constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index
constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index
constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index
constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index
constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index
constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index
constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index
constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index
constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index
constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index
constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index
constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index
constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index
constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index
constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index
constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index
constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index
constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index
constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index
constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index
constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index
constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 7;
constant BUFF_ADDRESS_MSB_INDEX : integer := 8;
constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_64_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal update_curdesc1 : std_logic := '0';
signal update_curdesc2 : std_logic := '0';
signal update_curdesc3 : std_logic := '0';
signal update_curdesc4 : std_logic := '0';
signal update_curdesc5 : std_logic := '0';
signal update_curdesc6 : std_logic := '0';
signal update_curdesc7 : std_logic := '0';
signal update_curdesc8 : std_logic := '0';
signal update_curdesc9 : std_logic := '0';
signal update_curdesc10 : std_logic := '0';
signal update_curdesc11 : std_logic := '0';
signal update_curdesc12 : std_logic := '0';
signal update_curdesc13 : std_logic := '0';
signal update_curdesc14 : std_logic := '0';
signal update_curdesc15 : std_logic := '0';
signal dest0 : std_logic := '0';
signal dest1 : std_logic := '0';
signal dest2 : std_logic := '0';
signal dest3 : std_logic := '0';
signal dest4 : std_logic := '0';
signal dest5 : std_logic := '0';
signal dest6 : std_logic := '0';
signal dest7 : std_logic := '0';
signal dest8 : std_logic := '0';
signal dest9 : std_logic := '0';
signal dest10 : std_logic := '0';
signal dest11 : std_logic := '0';
signal dest12 : std_logic := '0';
signal dest13 : std_logic := '0';
signal dest14 : std_logic := '0';
signal dest15 : std_logic := '0';
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal error_pointer_set1 : std_logic := '0';
signal error_pointer_set2 : std_logic := '0';
signal error_pointer_set3 : std_logic := '0';
signal error_pointer_set4 : std_logic := '0';
signal error_pointer_set5 : std_logic := '0';
signal error_pointer_set6 : std_logic := '0';
signal error_pointer_set7 : std_logic := '0';
signal error_pointer_set8 : std_logic := '0';
signal error_pointer_set9 : std_logic := '0';
signal error_pointer_set10 : std_logic := '0';
signal error_pointer_set11 : std_logic := '0';
signal error_pointer_set12 : std_logic := '0';
signal error_pointer_set13 : std_logic := '0';
signal error_pointer_set14 : std_logic := '0';
signal error_pointer_set15 : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal tail_update_lsb : std_logic := '0';
signal tail_update_msb : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal halt_free : std_logic := '0';
signal tmp11 : std_logic := '0';
signal sig_cur_updated : std_logic := '0';
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
halt_free <= '1';
end generate GEN_MULTI_CH;
GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
halt_free <= dmasr_i(DMASR_HALTED_BIT);
end generate GEN_NOMULTI_CH;
GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate
begin
update_curdesc1 <= '0';
update_curdesc2 <= '0';
update_curdesc3 <= '0';
update_curdesc4 <= '0';
update_curdesc5 <= '0';
update_curdesc6 <= '0';
update_curdesc7 <= '0';
update_curdesc8 <= '0';
update_curdesc9 <= '0';
update_curdesc10 <= '0';
update_curdesc11 <= '0';
update_curdesc12 <= '0';
update_curdesc13 <= '0';
update_curdesc14 <= '0';
update_curdesc15 <= '0';
end generate GEN_DESC_UPDATE_FOR_SG;
dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0';
dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0';
dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0';
dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0';
dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0';
dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0';
dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0';
dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0';
dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0';
dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0';
dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0';
dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0';
dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0';
dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0';
dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0';
dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0';
GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate
update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0';
update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0';
update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0';
update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0';
update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0';
update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0';
update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0';
update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0';
update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0';
update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0';
update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0';
update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0';
update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0';
update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0';
update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0';
end generate GEN_DESC_UPDATE_FOR_SG_CH;
GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_64_i & buffer_address_i ;
end generate GEN_DA_ADDR_EQL64;
GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate GEN_DA_ADDR_EQL32;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_length <= buffer_length_i ;
curdesc1_lsb <= curdesc1_lsb_i ;
curdesc1_msb <= curdesc1_msb_i ;
taildesc1_lsb <= taildesc1_lsb_i ;
taildesc1_msb <= taildesc1_msb_i ;
curdesc2_lsb <= curdesc2_lsb_i ;
curdesc2_msb <= curdesc2_msb_i ;
taildesc2_lsb <= taildesc2_lsb_i ;
taildesc2_msb <= taildesc2_msb_i ;
curdesc3_lsb <= curdesc3_lsb_i ;
curdesc3_msb <= curdesc3_msb_i ;
taildesc3_lsb <= taildesc3_lsb_i ;
taildesc3_msb <= taildesc3_msb_i ;
curdesc4_lsb <= curdesc4_lsb_i ;
curdesc4_msb <= curdesc4_msb_i ;
taildesc4_lsb <= taildesc4_lsb_i ;
taildesc4_msb <= taildesc4_msb_i ;
curdesc5_lsb <= curdesc5_lsb_i ;
curdesc5_msb <= curdesc5_msb_i ;
taildesc5_lsb <= taildesc5_lsb_i ;
taildesc5_msb <= taildesc5_msb_i ;
curdesc6_lsb <= curdesc6_lsb_i ;
curdesc6_msb <= curdesc6_msb_i ;
taildesc6_lsb <= taildesc6_lsb_i ;
taildesc6_msb <= taildesc6_msb_i ;
curdesc7_lsb <= curdesc7_lsb_i ;
curdesc7_msb <= curdesc7_msb_i ;
taildesc7_lsb <= taildesc7_lsb_i ;
taildesc7_msb <= taildesc7_msb_i ;
curdesc8_lsb <= curdesc8_lsb_i ;
curdesc8_msb <= curdesc8_msb_i ;
taildesc8_lsb <= taildesc8_lsb_i ;
taildesc8_msb <= taildesc8_msb_i ;
curdesc9_lsb <= curdesc9_lsb_i ;
curdesc9_msb <= curdesc9_msb_i ;
taildesc9_lsb <= taildesc9_lsb_i ;
taildesc9_msb <= taildesc9_msb_i ;
curdesc10_lsb <= curdesc10_lsb_i ;
curdesc10_msb <= curdesc10_msb_i ;
taildesc10_lsb <= taildesc10_lsb_i ;
taildesc10_msb <= taildesc10_msb_i ;
curdesc11_lsb <= curdesc11_lsb_i ;
curdesc11_msb <= curdesc11_msb_i ;
taildesc11_lsb <= taildesc11_lsb_i ;
taildesc11_msb <= taildesc11_msb_i ;
curdesc12_lsb <= curdesc12_lsb_i ;
curdesc12_msb <= curdesc12_msb_i ;
taildesc12_lsb <= taildesc12_lsb_i ;
taildesc12_msb <= taildesc12_msb_i ;
curdesc13_lsb <= curdesc13_lsb_i ;
curdesc13_msb <= curdesc13_msb_i ;
taildesc13_lsb <= taildesc13_lsb_i ;
taildesc13_msb <= taildesc13_msb_i ;
curdesc14_lsb <= curdesc14_lsb_i ;
curdesc14_msb <= curdesc14_msb_i ;
taildesc14_lsb <= taildesc14_lsb_i ;
taildesc14_msb <= taildesc14_msb_i ;
curdesc15_lsb <= curdesc15_lsb_i ;
curdesc15_msb <= curdesc15_msb_i ;
taildesc15_lsb <= taildesc15_lsb_i ;
taildesc15_msb <= taildesc15_msb_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Key Hole write bit (3)
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest0 = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_lsb_i <= (others => '0');
error_pointer_set1 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set1 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then
curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set1 <= '0';
end if;
end if;
end if;
end process CURDESC1_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then
taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC1_LSB_REGISTER;
end generate GEN_DESC1_REG_FOR_SG;
GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_lsb_i <= (others => '0');
error_pointer_set2 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set2 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then
curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set2 <= '0';
end if;
end if;
end if;
end process CURDESC2_LSB_REGISTER;
TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then
taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC2_LSB_REGISTER;
end generate GEN_DESC2_REG_FOR_SG;
GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_lsb_i <= (others => '0');
error_pointer_set3 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set3 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then
curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set3 <= '0';
end if;
end if;
end if;
end process CURDESC3_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then
taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC3_LSB_REGISTER;
end generate GEN_DESC3_REG_FOR_SG;
GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_lsb_i <= (others => '0');
error_pointer_set4 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set4 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then
curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set4 <= '0';
end if;
end if;
end if;
end process CURDESC4_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then
taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC4_LSB_REGISTER;
end generate GEN_DESC4_REG_FOR_SG;
GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_lsb_i <= (others => '0');
error_pointer_set5 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set5 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then
curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set5 <= '0';
end if;
end if;
end if;
end process CURDESC5_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then
taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC5_LSB_REGISTER;
end generate GEN_DESC5_REG_FOR_SG;
GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_lsb_i <= (others => '0');
error_pointer_set6 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set6 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then
curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set6 <= '0';
end if;
end if;
end if;
end process CURDESC6_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then
taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC6_LSB_REGISTER;
end generate GEN_DESC6_REG_FOR_SG;
GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_lsb_i <= (others => '0');
error_pointer_set7 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set7 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then
curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set7 <= '0';
end if;
end if;
end if;
end process CURDESC7_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then
taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC7_LSB_REGISTER;
end generate GEN_DESC7_REG_FOR_SG;
GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_lsb_i <= (others => '0');
error_pointer_set8 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set8 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then
curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set8 <= '0';
end if;
end if;
end if;
end process CURDESC8_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then
taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC8_LSB_REGISTER;
end generate GEN_DESC8_REG_FOR_SG;
GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_lsb_i <= (others => '0');
error_pointer_set9 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set9 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then
curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set9 <= '0';
end if;
end if;
end if;
end process CURDESC9_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then
taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC9_LSB_REGISTER;
end generate GEN_DESC9_REG_FOR_SG;
GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_lsb_i <= (others => '0');
error_pointer_set10 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set10 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then
curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set10 <= '0';
end if;
end if;
end if;
end process CURDESC10_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then
taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC10_LSB_REGISTER;
end generate GEN_DESC10_REG_FOR_SG;
GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_lsb_i <= (others => '0');
error_pointer_set11 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set11 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then
curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set11 <= '0';
end if;
end if;
end if;
end process CURDESC11_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then
taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC11_LSB_REGISTER;
end generate GEN_DESC11_REG_FOR_SG;
GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_lsb_i <= (others => '0');
error_pointer_set12 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set12 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then
curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set12 <= '0';
end if;
end if;
end if;
end process CURDESC12_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then
taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC12_LSB_REGISTER;
end generate GEN_DESC12_REG_FOR_SG;
GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_lsb_i <= (others => '0');
error_pointer_set13 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set13 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then
curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set13 <= '0';
end if;
end if;
end if;
end process CURDESC13_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then
taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC13_LSB_REGISTER;
end generate GEN_DESC13_REG_FOR_SG;
GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_lsb_i <= (others => '0');
error_pointer_set14 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set14 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then
curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set14 <= '0';
end if;
end if;
end if;
end process CURDESC14_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then
taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC14_LSB_REGISTER;
end generate GEN_DESC14_REG_FOR_SG;
GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_lsb_i <= (others => '0');
error_pointer_set15 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set15 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then
curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set15 <= '0';
end if;
end if;
end if;
end process CURDESC15_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then
taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC15_LSB_REGISTER;
end generate GEN_DESC15_REG_FOR_SG;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
elsif(sg_updt_error = '1' and dest0 = '1')then
curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_msb_i <= (others => '0');
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then
curdesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC1_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then
taildesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC1_MSB_REGISTER;
end generate GEN_DESC1_MSB_FOR_SG;
GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_msb_i <= (others => '0');
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then
curdesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC2_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then
taildesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC2_MSB_REGISTER;
end generate GEN_DESC2_MSB_FOR_SG;
GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_msb_i <= (others => '0');
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then
curdesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC3_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then
taildesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC3_MSB_REGISTER;
end generate GEN_DESC3_MSB_FOR_SG;
GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_msb_i <= (others => '0');
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then
curdesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC4_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then
taildesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC4_MSB_REGISTER;
end generate GEN_DESC4_MSB_FOR_SG;
GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_msb_i <= (others => '0');
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then
curdesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC5_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then
taildesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC5_MSB_REGISTER;
end generate GEN_DESC5_MSB_FOR_SG;
GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_msb_i <= (others => '0');
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then
curdesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC6_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then
taildesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC6_MSB_REGISTER;
end generate GEN_DESC6_MSB_FOR_SG;
GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_msb_i <= (others => '0');
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then
curdesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC7_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then
taildesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC7_MSB_REGISTER;
end generate GEN_DESC7_MSB_FOR_SG;
GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_msb_i <= (others => '0');
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then
curdesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC8_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then
taildesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC8_MSB_REGISTER;
end generate GEN_DESC8_MSB_FOR_SG;
GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_msb_i <= (others => '0');
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then
curdesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC9_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then
taildesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC9_MSB_REGISTER;
end generate GEN_DESC9_MSB_FOR_SG;
GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_msb_i <= (others => '0');
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then
curdesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC10_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then
taildesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC10_MSB_REGISTER;
end generate GEN_DESC10_MSB_FOR_SG;
GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_msb_i <= (others => '0');
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then
curdesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC11_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then
taildesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC11_MSB_REGISTER;
end generate GEN_DESC11_MSB_FOR_SG;
GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_msb_i <= (others => '0');
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then
curdesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC12_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then
taildesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC12_MSB_REGISTER;
end generate GEN_DESC12_MSB_FOR_SG;
GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_msb_i <= (others => '0');
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then
curdesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC13_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then
taildesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC13_MSB_REGISTER;
end generate GEN_DESC13_MSB_FOR_SG;
GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_msb_i <= (others => '0');
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then
curdesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC14_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then
taildesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC14_MSB_REGISTER;
end generate GEN_DESC14_MSB_FOR_SG;
GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_msb_i <= (others => '0');
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then
curdesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC15_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then
taildesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC15_MSB_REGISTER;
end generate GEN_DESC15_MSB_FOR_SG;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to the extra registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15);
end generate GENERATE_MULTI_CH;
GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15);
end generate GENERATE_NO_MULTI_CH1;
GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH2;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_msb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to new registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
curdesc1_lsb_i <= (others => '0');
taildesc1_lsb_i <= (others => '0');
curdesc2_lsb_i <= (others => '0');
taildesc2_lsb_i <= (others => '0');
curdesc3_lsb_i <= (others => '0');
taildesc3_lsb_i <= (others => '0');
curdesc4_lsb_i <= (others => '0');
taildesc4_lsb_i <= (others => '0');
curdesc5_lsb_i <= (others => '0');
taildesc5_lsb_i <= (others => '0');
curdesc6_lsb_i <= (others => '0');
taildesc6_lsb_i <= (others => '0');
curdesc7_lsb_i <= (others => '0');
taildesc7_lsb_i <= (others => '0');
curdesc8_lsb_i <= (others => '0');
taildesc8_lsb_i <= (others => '0');
curdesc9_lsb_i <= (others => '0');
taildesc9_lsb_i <= (others => '0');
curdesc10_lsb_i <= (others => '0');
taildesc10_lsb_i <= (others => '0');
curdesc11_lsb_i <= (others => '0');
taildesc11_lsb_i <= (others => '0');
curdesc12_lsb_i <= (others => '0');
taildesc12_lsb_i <= (others => '0');
curdesc13_lsb_i <= (others => '0');
taildesc13_lsb_i <= (others => '0');
curdesc14_lsb_i <= (others => '0');
taildesc14_lsb_i <= (others => '0');
curdesc15_lsb_i <= (others => '0');
taildesc15_lsb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_64_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_64_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then
buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| mit | 95ce792b4d942f0db05f2cfa798bafd2 | 0.445315 | 4.182933 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover.vhd | 1 | 74,512 | -------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
| mit | 08e3fcd5308de0605b2b3c84fa2792d7 | 0.402754 | 4.16967 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/MurmurHashUtils.vhdl | 1 | 37,855 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.ALL;
package MurmurHashUtils is
constant C1 : std_logic_vector(31 downto 0) := x"cc9e2d51";
constant C2 : std_logic_vector(31 downto 0) := x"1b873593";
constant M : std_logic_vector(31 downto 0) := x"00000005";
constant N : std_logic_vector(31 downto 0) := x"e6546b64";
constant FinalShift1 : integer := 16;
constant FinalC1 : std_logic_vector(31 downto 0) := x"85ebca6b";
constant FinalShift2 : integer := 13;
constant FinalC2 : std_logic_vector(31 downto 0) := x"c2b2ae35";
constant FinalShift3 : integer := 16;
type Step1_Capture is record
dataValid : boolean; --! Indica que los datos capturados en este datoa ctual son validos
data : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
dataLength : std_logic_vector(1 downto 0);
isFirst : boolean;
isLast : boolean;
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
seed : std_logic_vector(31 downto 0);
end record Step1_Capture;
type Step2_C1Mult is record
dataValid : boolean; --! Indica que los datos capturados en este datoa ctual son validos
data : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
dataLength : std_logic_vector(1 downto 0);
isFirst : boolean;
isLast : boolean;
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
seed : std_logic_vector(31 downto 0);
end record Step2_C1Mult;
type Step3_R1 is record
dataValid : boolean; --! Indica que los datos capturados en este datoa ctual son validos
data : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
dataLength : std_logic_vector(1 downto 0);
isFirst : boolean;
isLast : boolean;
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
seed : std_logic_vector(31 downto 0);
end record Step3_R1;
type Step4_C2Mult is record
dataValid : boolean; --! Indica que los datos capturados en este datoa ctual son validos
data : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
dataLength : std_logic_vector(1 downto 0);
isFirst : boolean;
isLast : boolean;
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
seed : std_logic_vector(31 downto 0);
end record Step4_C2Mult;
type Step5_HashResult is record
hash : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
dataLength : std_logic_vector(1 downto 0);
resultReady : boolean;
isFirst : boolean;
isLast : boolean;
end record Step5_HashResult;
--PASOS PARA LA ETAPA FINAL EN CASO LA LONGITUD NO SEA MULTIPLO de 4
type Step1_EndianSwap is record
dataValid : boolean; --! Indica que los datos capturados en este datoa ctual son validos
data : std_logic_vector(31 downto 0); --! Guarda los datos recibidos
dataLength : std_logic_vector(1 downto 0);
isFirst : boolean;
isLast : boolean;
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
seed : std_logic_vector(31 downto 0);
end record Step1_EndianSwap;
--PASOS DE LA ETAPA FINAL DEL CALCULO DEl HASH
type FinalStep is record
hash : std_logic_vector(31 downto 0); --! Hash
totalLen : std_logic_vector(31 downto 0); --! Longitud de todos los datos recibidos
operationID : std_logic_vector(31 downto 0); --31 es el 'size' maximo del opID
resultReady : boolean;
isFirst : boolean;
isLast : boolean;
end record FinalStep;
function funcionFinalHashOperation_4B(
hash:std_logic_vector(31 downto 0);
k:std_logic_vector(31 downto 0)
) return std_logic_vector is
variable xorResult : std_logic_vector(31 downto 0);
variable rotR2Result : std_logic_vector(31 downto 0);
variable multMResult_temp : std_logic_vector(63 downto 0);
variable multMResult : std_logic_vector(31 downto 0);
variable additionNResult : std_logic_vector(31 downto 0);
begin
xorResult := hash xor k;
rotR2Result(31 downto 13) := xorResult(18 downto 0);
rotR2Result(12 downto 0) := xorResult(31 downto 19);
multMResult_temp := rotR2Result*M;
multMResult := multMResult_temp(31 downto 0);
additionNResult := multMResult+N;
return additionNResult;
end function funcionFinalHashOperation_4B;
function mh3_boolean_to_std_logic(a: boolean) return std_logic is
begin
if a then
return('1');
else
return('0');
end if;
end function mh3_boolean_to_std_logic;
function ClampedMult(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
variable fullMultResult : std_logic_vector( (a'length*2-1) downto 0);
begin
fullMultResult := a*b;
return fullMultResult( (a'length-1) downto 0);
end function ClampedMult;
function xor_with_shiftRight(data: std_logic_vector; constant count:integer) return std_logic_vector is
variable value : std_logic_vector( (data'length-1) downto 0 );
variable shifted : std_logic_vector( (data'length-1) downto 0 );
--variable returnValue : std_logic_vector( data'length downto 0 );
begin
shifted((data'length-1-count) downto 0 ) := data((data'length-1) downto count);
shifted((data'length-1) downto (data'length-count) ) := ( others=>'0' );
return (data xor shifted);
--return (data );
end function xor_with_shiftRight;
function MH_ShiftRight(data: std_logic_vector; constant count:integer) return std_logic_vector is
variable shifted : std_logic_vector( (data'length-1) downto 0 );
begin
shifted((data'length-1-count) downto 0 ) := data((data'length-1) downto count);
shifted((data'length-1) downto (data'length-count) ) := ( others=>'0' );
return shifted;
end function MH_ShiftRight;
function char_to_slv8(inputByte: character) return std_logic_vector is
begin
return (std_logic_vector(to_unsigned(character'pos(inputByte), 8 )));
--return (data );
end function char_to_slv8;
--! En caso de recibir datos cuya lingitud no es multiplo de 4
--! estos deben de alinearse empezando por inputBlock(7 downto 0)
--! hasta inputBlock(23 downto 16)
component MurmurHash32Generator is
generic (
ID_PRESENT: boolean := true;
ID_LENGTH: integer := 31
);
port(
--ENTRADAS
inputBlock : in std_logic_vector(31 downto 0);
readInput : in std_logic;
blockLength : in std_logic_vector(1 downto 0);
finalBlock : in std_logic;
start : in std_logic;
operationID : in std_logic_vector(ID_LENGTH downto 0);
seed : in std_logic_vector(31 downto 0);
--SALIDAS
canAccept : out std_logic;
resultReady : out std_logic;
result : out std_logic_vector(31 downto 0);
resultID : out std_logic_vector(ID_LENGTH downto 0);
--RELOJ
clk : in std_logic;
--Salidas de depuracion
dataStep1_dbg : out std_logic_vector(31 downto 0);
dataStep2_dbg : out std_logic_vector(31 downto 0);
dataStep3_dbg : out std_logic_vector(31 downto 0);
dataStep4_dbg : out std_logic_vector(31 downto 0);
dataStep5_dbg : out std_logic_vector(31 downto 0);
dataStep1_ID_dbg : out std_logic_vector(31 downto 0);
dataStep2_ID_dbg : out std_logic_vector(31 downto 0);
dataStep3_ID_dbg : out std_logic_vector(31 downto 0);
dataStep4_ID_dbg : out std_logic_vector(31 downto 0);
dataStep5_ID_dbg : out std_logic_vector(31 downto 0);
dataStepA_dbg : out std_logic_vector(31 downto 0);
dataStepB_dbg : out std_logic_vector(31 downto 0);
dataStepC_dbg : out std_logic_vector(31 downto 0);
dataStepD_dbg : out std_logic_vector(31 downto 0);
dataStepA_ID_dbg : out std_logic_vector(31 downto 0);
dataStepB_ID_dbg : out std_logic_vector(31 downto 0);
dataStepC_ID_dbg : out std_logic_vector(31 downto 0);
dataStepD_ID_dbg : out std_logic_vector(31 downto 0);
finalStep1_dbg : out std_logic_vector(31 downto 0);
finalStep2_dbg : out std_logic_vector(31 downto 0);
finalStep3_dbg : out std_logic_vector(31 downto 0);
finalStep4_dbg : out std_logic_vector(31 downto 0);
finalStep5_dbg : out std_logic_vector(31 downto 0);
finalStep1_ID_dbg : out std_logic_vector(31 downto 0);
finalStep2_ID_dbg : out std_logic_vector(31 downto 0);
finalStep3_ID_dbg : out std_logic_vector(31 downto 0);
finalStep4_ID_dbg : out std_logic_vector(31 downto 0);
finalStep5_ID_dbg : out std_logic_vector(31 downto 0)
);
end component MurmurHash32Generator;
constant simulationSeed : std_logic_vector(31 downto 0) := x"7538c68c";
constant nTuplas : std_logic_vector(31 downto 0) := x"000000bd";
type referencesArray_t is array (0 to 188) of std_logic_vector(31 downto 0);
constant resultsBank : referencesArray_t := ( x"0005e4fe",x"0120548c",x"012b30f2",x"01de0324",x"0383146b",x"03b4f753",x"03e134b3",x"0465f7d0",x"04bec7f6",x"0527cba1",x"0557f965",x"0559b317",x"0753af24",x"0754e422",x"08892d9b",x"08da5d8b",x"0ce5afa5",x"0d23c3d5",x"0d3b5299",x"0d78e716",x"0f46b237",x"1012888a",x"10ea1f74",x"11bab0a2",x"11f6f69e",x"152b9cac",x"16704ec4",x"1755cafa",x"17baa90b",x"181b6936",x"1d419388",x"1e2711ac",x"1f6579b0",x"1fc0e894",x"22f16379",x"234d74e2",x"23925899",x"29b89cd6",x"2adc8800",x"2da45cda",x"2ee16629",x"30270ec9",x"30d416d3",x"31487f79",x"31ae4b6f",x"31defc3c",x"326743fe",x"32a4fa78",x"33e04691",x"385ed0da",x"393d1f2e",x"3a089667",x"3a8f1665",x"3fae4162",x"42d46789",x"43df45e8",x"43e3df86",x"45e24bd2",x"481a4139",x"48f27c34",x"49707b17",x"4adf0df5",x"4b33bd8f",x"4b7e2041",x"4c2ecfad",x"4ce2e62c",x"4d3f080d",x"4e12afb6",x"50d66947",x"5194e696",x"52acb891",x"52ec1964",x"53427a11",x"54413217",x"564f8e54",x"59ad4a13",x"59d2efd2",x"5a66d0f0",x"5d0ba789",x"5fd8b078",x"630298b3",x"6335ee99",x"640f09c0",x"6474be5b",x"65a9646b",x"6616c671",x"663ccfea",x"692e950d",x"6a7d612d",x"6b837fd0",x"6ca874cb",x"6e45ef50",x"6ec2d543",x"6fb48b5f",x"70011e03",x"723308ed",x"747fa6a1",x"7516216f",x"756936a1",x"75734302",x"75f13f94",x"76441924",x"7859e6de",x"787395fa",x"7ab00815",x"7b8869a3",x"7c276640",x"7eaac05f",x"82a02ebc",x"87699861",x"8857cd8a",x"89796081",x"8d68443f",x"8d6c037c",x"931cc510",x"940d2551",x"94885205",x"94d5dbb3",x"961afcaa",x"97049e47",x"99bc16bb",x"9a1a403b",x"9db585a3",x"9e6a33a5",x"9edead29",x"9f203b78",x"9fc6f3d2",x"a0787910",x"a2a1d04f",x"a529eb09",x"a5aefdc2",x"a5ed9e3e",x"a952bdf1",x"aa8b0ff0",x"aca5c7b0",x"ae14470f",x"af197f39",x"afd0b0ac",x"b3a1a6ec",x"b4e9d9f8",x"b6cdcad7",x"b7c75d78",x"ba17837d",x"bc3d33b8",x"bce01814",x"bd607bc0",x"c10ca292",x"c195cc20",x"c1e56cba",x"c2e6bf3f",x"c32a6539",x"c3cba9aa",x"c5aaeb93",x"c82e2bf7",x"ca0cd23c",x"cd88ee27",x"cfcd9af0",x"d0b348aa",x"d0de6981",x"d55e74fb",x"d73ce098",x"d995505a",x"d9d7bc36",x"dbdbdaba",x"dc543f2d",x"dc962921",x"de427b73",x"e02bd14c",x"e1716b85",x"e22bb836",x"e38da496",x"e4d793bc",x"e7fd97fc",x"e9868af1",x"ec2862f7",x"ec453692",x"ed5f28c0",x"eec1db61",x"eef77cee",x"f00f04fb",x"f29f7946",x"f2cf2c51",x"f5706b91",x"f5a4af48",x"f73fc385",x"f852f16b",x"fbcf6333",x"fca34145",x"ff94311f");
constant entrysLengths : referencesArray_t := ( x"00000015",x"00000019",x"0000001d",x"00000010",x"0000000d",x"00000019",x"00000019",x"0000000b",x"0000000e",x"0000000d",x"00000008",x"0000000b",x"00000009",x"0000001b",x"00000010",x"0000000a",x"0000000f",x"00000012",x"00000014",x"0000000b",x"0000000f",x"0000001a",x"0000000b",x"0000001b",x"00000010",x"00000015",x"00000016",x"00000016",x"0000000a",x"0000000c",x"00000018",x"00000017",x"00000010",x"0000000b",x"0000000e",x"0000001a",x"0000000f",x"00000010",x"0000000c",x"0000000f",x"0000001e",x"00000029",x"0000001d",x"0000000c",x"0000000f",x"0000000c",x"0000000b",x"0000001e",x"0000001e",x"00000010",x"0000001a",x"00000020",x"00000011",x"0000001d",x"0000001f",x"0000000c",x"00000009",x"0000000a",x"0000002a",x"0000000d",x"0000000f",x"0000000f",x"00000001",x"00000015",x"00000012",x"0000001b",x"0000001a",x"0000000d",x"0000000b",x"00000011",x"0000001a",x"00000016",x"00000010",x"0000000b",x"0000000a",x"0000001d",x"0000000e",x"00000019",x"0000000a",x"0000000e",x"0000000b",x"0000000b",x"0000001e",x"0000002a",x"0000000c",x"0000001a",x"00000016",x"0000000e",x"00000012",x"0000000e",x"00000013",x"00000019",x"00000010",x"0000000a",x"00000016",x"0000001a",x"0000001b",x"00000019",x"0000000d",x"00000019",x"0000000c",x"00000011",x"00000015",x"0000000f",x"0000000a",x"00000010",x"0000001d",x"0000000a",x"0000000f",x"00000013",x"0000001c",x"0000000f",x"00000010",x"00000010",x"00000016",x"00000011",x"0000001a",x"00000012",x"0000000a",x"00000009",x"0000000e",x"0000000d",x"00000013",x"00000010",x"00000015",x"0000001b",x"00000021",x"0000001a",x"00000010",x"0000002b",x"0000000d",x"00000011",x"0000000a",x"00000010",x"0000000d",x"0000000b",x"0000000a",x"00000015",x"0000001a",x"0000000b",x"0000001b",x"00000019",x"0000001a",x"0000001b",x"0000001a",x"0000000e",x"00000017",x"0000001b",x"00000009",x"0000000f",x"00000019",x"00000018",x"0000001e",x"0000000f",x"00000010",x"0000001a",x"00000020",x"0000001a",x"0000000f",x"0000000c",x"00000017",x"0000000a",x"0000000f",x"0000000c",x"0000000b",x"0000000a",x"0000000f",x"0000000f",x"00000019",x"0000000d",x"0000000d",x"0000000f",x"0000000a",x"0000000a",x"00000010",x"00000016",x"0000000b",x"00000016",x"0000000c",x"0000000f",x"00000010",x"0000000b",x"0000001d",x"0000000e",x"0000000c",x"0000001e",x"0000001a",x"0000000b",x"0000000b");
type referencesDataArray_t is array (0 to 3498) of std_logic_vector(7 downto 0);
constant dataBank : referencesDataArray_t := ( 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--component BinarySearchBRAM is
--generic(
-- DATA_WIDTH : integer := 32;
-- ADDR_WIDTH : integer := 10
--);
--port(
-- clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
-- --Puerto de escritura en el cual se vana grabar los datos en la tabla
-- porta_wr : in std_logic;
-- porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
-- porta_rd : in std_logic;
-- porta_raddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- porta_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0);
-- --puerto de lectura, desde el cual se van a leer los 0
-- --datos para la comparación
-- portb_rd : in std_logic;
-- portb_addr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- portb_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0)
--);
--end component BinarySearchBRAM;
--component BinarySearch_ComparingRow is
-- generic (
-- DATA_WIDTH: integer := 32;
-- ADDR_WIDTH: integer := 10;
-- RADIO: std_logic_vector
-- );
-- port(
-- clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
-- dataToCompare : in std_logic_vector((DATA_WIDTH-1) downto 0);
-- operationID : in std_logic_vector((DATA_WIDTH-1) downto 0);
-- previousIndex : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- compare : in std_logic;--El dato actual se debe comparar
-- previousResult : in std_logic;--El resultado es encontrado'1' o no
-- porta_wr : in std_logic;
-- porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
-- --valores de saldia de esta columna
-- result : out std_logic;--El resultado es encontrado'1' o no
-- nextIndex : out std_logic_vector( (ADDR_WIDTH-1) downto 0);
-- compareFinished : out std_logic--Resultado de una comparación listo
-- );
--end component BinarySearch_ComparingRow;
end MurmurHashUtils;
| bsd-3-clause | 7177872a0eb6193d0d8f61ef62e44b95 | 0.566296 | 1.792282 | false | false | false | false |
loetlab-jena/das-atv | hdl/src/cordic.vhd | 1 | 1,716 | -- title: Coordinate Rotator
-- author: Sebastian Weiss <[email protected]>
-- last change: 22.10.13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity cordic is
generic
(
A : natural; -- amplitude resolution
P : natural; -- phase resolution
N : natural -- number of stages
);
port
(
clk : in std_logic; -- signal processing clock
phi : in unsigned(P-3 downto 0); -- phase input (0° - 90°)
sin : out signed(A-1 downto 0); -- sine output
cos : out signed(A-1 downto 0) -- cosine output
);
end entity;
architecture behavioral of cordic is
type alpha_t is array(0 to N-1) of signed(P downto 0);
type xy_vector is array(natural range <>) of signed(A-1 downto 0);
type z_vector is array(natural range <>) of signed(P downto 0);
constant init : signed(A-1 downto 0) := to_signed(integer(0.60725*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( arctan(1.0/real(2**i)) / (2.0*math_pi) * real(2**P) ),P+1);
end generate;
process begin
wait until rising_edge(clk);
x(0) <= init;
y(0) <= (others => '0');
z(0) <= signed("000" & phi); -- 0..90° -> +- 0..360*
for i in 1 to N loop
if z(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
end if;
end loop;
end process;
sin <= y(N);
cos <= x(N);
end behavioral;
| gpl-2.0 | 8ec76d9794ad48273d9c14d01a035e86 | 0.575598 | 2.346575 | false | false | false | false |
Kalugy/Procesadorarquitectura | Primerprocesador17octubre/tb_RF.vhd | 1 | 2,768 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_RF IS
END tb_RF;
ARCHITECTURE behavior OF tb_RF IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
dwr : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
crs1 : OUT std_logic_vector(31 downto 0);
crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal dwr : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal crs1 : std_logic_vector(31 downto 0);
signal crs2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
dwr => dwr,
rst => rst,
crs1 => crs1,
crs2 => crs2
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rs1<="00001";
rs2<="00000";
rd<="00010";
dwr<="00010000000000011100000000000000";
rst<='1';
wait for 200 ns;
rs1<="00010";
rs2<="00000";
rd<="00001";
dwr<="00010000000000000000000000000111";
rst<='0';
wait for 200 ns;
rs1<="00001";
rs2<="00000";
rd<="10000";
dwr<="00010000000000000000000000000000";
rst<='0';
wait for 200 ns;
rs1<="00000";
rs2<="00100";
rd<="00100";
dwr<="00010000000000000000000000000000";
rst<='0';
wait for 200 ns;
rs1<="00001";
rs2<="00100";
rd<="00011";
dwr<="00010000000000000000000000000001";
rst<='0';
wait for 200 ns;
rs1<="00001";
rs2<="00100";
rd<="00011";
dwr<="00010000000000000000000000000001";
rst<='1';
wait for 200 ns;
rs1<="00001";
rs2<="10000";
rd<="00011";
dwr<="00010000000000000000000000000001";
rst<='0';
wait for 200 ns;
rs1<="00100";
rs2<="00011";
rd<="00000";
dwr<="00010000000000000000000000000001";
rst<='0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 4034d4af28cb27bceae03ed46379c351 | 0.553107 | 3.59948 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_register.vhd | 1 | 49,414 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| mit | 5f9bfe82ceca6a9d7cf253df2c26cad4 | 0.433824 | 4.423022 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_cmd_split.vhd | 1 | 22,804 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| mit | c3bb987f36b90fddc74e503d457c7c35 | 0.504429 | 3.727971 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_mm2s_sm.vhd | 1 | 28,362 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
attribute mark_debug of mm2s_cmnd_wr_i : signal is "true";
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| mit | d8c03ee1586c9f08c36dc837156defba | 0.400677 | 4.600487 | false | false | false | false |
1995parham/AlteraDE2-RS232 | src/main.vhd | 1 | 2,386 | library ieee;
use ieee.std_logic_1164.all;
entity serial is port (
rxd : in std_logic := '1';
txd : out std_logic := '1';
clk : in std_logic
);
end entity;
architecture main_arch of serial is
component async_transmitter is port (
clk : in std_logic;
TxD_start : in std_logic;
TxD_data : in std_logic_vector(7 downto 0);
TxD : out std_logic;
TxD_busy : out std_logic
);
end component;
type state is (recv, bsend1, send1, bsend2, send2, bsend3, send3, bsend4, send4, s1, s2, s3, s4, s5, s6);
signal present_state : state := s3;
signal next_state : state := s3;
signal player_color : std_logic_vector(15 downto 0);
signal input : std_logic_vector (7 downto 0);
-- sender ports
signal snd_data : std_logic_vector (7 downto 0) := "00000000";
signal snd_start : std_logic := '0';
signal snd_busy : std_logic;
begin
-- set senders port
snd: async_transmitter port map (clk, snd_start, snd_data, txd, snd_busy);
process(clk) begin
if (rising_edge(clk)) then
present_state <= next_state;
end if;
end process;
process(present_state, snd_busy) begin
case present_state is
when s1 =>
-- nothing
null;
when recv =>
-- nothing
null;
when s2 =>
-- nothing
null;
when s3 =>
-- start send @
snd_data <= "01000000";
next_state <= bsend1;
when bsend1 =>
snd_start <= '1';
next_state <= send1;
when send1 =>
snd_start <= '0';
if (snd_busy = '0') then
next_state <= s4;
end if;
when s4 =>
-- start send 0
snd_data <= "00110000";
next_state <= bsend2;
when bsend2 =>
snd_start <= '1';
next_state <= send2;
when send2 =>
snd_start <= '0';
if (snd_busy = '0') then
next_state <= s5;
end if;
when s5 =>
-- start send /
snd_data <= "00101111";
next_state <= bsend3;
when bsend3 =>
snd_start <= '1';
next_state <= send3;
when send3 =>
snd_start <= '0';
if (snd_busy = '0') then
next_state <= s6;
end if;
when s6 =>
-- start send \n
snd_data <= "00001010";
next_state <= bsend4;
when bsend4 =>
snd_start <= '1';
next_state <= send4;
when send4 =>
snd_start <= '0';
if (snd_busy = '0') then
next_state <= s3;
end if;
end case;
end process;
end main_arch;
| gpl-2.0 | 178b9f11585d703de12c8e5652204bce | 0.560352 | 2.854067 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_updt_queue.vhd | 1 | 53,685 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
attribute mark_debug of updt_tvalid : signal is "true";
attribute mark_debug of updt2_tvalid : signal is "true";
attribute mark_debug of updt_tlast : signal is "true";
attribute mark_debug of updt2_tlast : signal is "true";
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_mm2s : signal is "true";
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_s2mm : signal is "true";
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
-- updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= ptr_queue_dout_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
-- updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
-- updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
| mit | 221fa51d41270a79da3fbbfa7768a371 | 0.432728 | 4.269864 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_cmdsts_if.vhd | 1 | 22,870 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
| mit | 6d10179c81043b8a21f957e356e03a8f | 0.451946 | 4.292417 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/synth/tri_intersect_ap_fadd_7_full_dsp_32.vhd | 1 | 12,685 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fadd_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fadd_7_full_dsp_32_arch;
| mit | 6551e6f75eb313460ccebc424ccc379d | 0.65203 | 3.023838 | false | false | false | false |
alemedeiros/flappy_vhdl | output/draw_frame.vhd | 1 | 5,487 | -- file: output/draw_frame.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Draw game images from current game state (player position and current
-- obstacles) using vgacon.
library ieee ;
use ieee.std_logic_1164.all ;
library module ;
use module.output.vgacon ;
use module.output.pixel_counter ;
use module.output.frame_builder ;
use module.input.clock_divider ;
entity draw_frame is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- Input data
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
-- VGA output
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic ;
-- Control signals
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end draw_frame ;
architecture behavior of draw_frame is
-- State type
type state_t is (start, clear, update_frame) ;
signal state : state_t := start ;
signal next_state : state_t := start ;
signal finish_write : std_logic ;
-- Local control signals
signal we : std_logic := '1' ; -- VGA controller write enable
signal lin : integer range 0 to V_RES - 1 ;
signal col : integer range 0 to H_RES - 1 ;
signal colour : std_logic_vector(2 downto 0) ;
-- Pixel counter signals
signal pxl_count_rst : std_logic ;
signal pxl_count_en : std_logic ;
-- Frame builder signals
signal pxl_col_en : std_logic ;
signal pxl_colour : std_logic_vector(2 downto 0) ;
-- Timer signals
signal timer : std_logic ;
signal timer_en : std_logic ;
signal timer_rst : std_logic ;
begin
-- VGA controller
vga_controller: vgacon
generic map (
NUM_HORZ_PIXELS => H_RES,
NUM_VERT_PIXELS => V_RES
)
port map (
clk27M => clock,
rstn => not reset,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vsync,
write_clk => clock,
write_enable => we,
write_addr => col + (128 * lin),
data_in => colour
) ;
-- Pixel counter, sweeps through each pixel of vga
count_pixel: pixel_counter
generic map (
H_RES => H_RES,
V_RES => V_RES
)
port map (
lin => lin,
col => col,
clock => clock,
reset => pxl_count_rst,
enable => pxl_count_en
) ;
-- Using the game state information, build a frame.
build_frame: frame_builder
generic map (
H_RES => H_RES,
V_RES => V_RES,
N_OBST => N_OBST
)
port map (
player => player,
obst_low => obst_low,
obst_high => obst_high,
obst_pos => obst_pos,
obst_id => obst_id,
lin => lin,
col => col,
enable => pxl_col_en,
colour => pxl_colour
) ;
frame_timer : clock_divider
generic map (
RATE => 270000
)
port map (
clk_in => clock,
clk_out => timer,
enable => timer_en,
reset => timer_rst
) ;
-- Signal end of frame write
finish_write <= '1' when (lin = V_RES - 1) and (col = H_RES - 1) else '0' ;
-- Finite State Machine for drawing frame.
fsm: process(state, finish_write, timer, enable)
begin
if enable = '0' then
next_state <= state ;
timer_en <= '0' ;
timer_rst <= '0' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
else
case state is
when start =>
if timer = '1' then
next_state <= update_frame ;
else
next_state <= start ;
end if ;
timer_en <= '1' ;
timer_rst <= '0' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '1' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
when clear =>
if finish_write = '1' then
next_state <= start ;
else
next_state <= clear ;
end if ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '1' ;
we <= '1' ;
colour <= "000" ;
when update_frame =>
if finish_write = '1' then
next_state <= start ;
else
next_state <= update_frame ;
end if ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '1' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '1' ;
we <= '1' ;
colour <= pxl_colour ;
when others =>
next_state <= start ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '1' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
end case ;
end if ;
end process ;
-- Update state process.
update_state: process(clock, reset)
begin
if reset = '1' then
state <= clear ;
elsif rising_edge(clock) then
state <= next_state ;
end if ;
end process ;
end behavior ;
| bsd-3-clause | f4f36324b1cb191606dfc8a587887afc | 0.528157 | 3.080853 | false | false | false | false |
dhesant/elec4320 | Lab2/ipcore_dir/bram_decoder/example_design/bmg_wrapper.vhd | 1 | 9,890 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : bram_decoder.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 13
-- C_READ_WIDTH_A : 13
-- C_WRITE_DEPTH_A : 22
-- C_READ_DEPTH_A : 22
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 13
-- C_READ_WIDTH_B : 13
-- C_WRITE_DEPTH_B : 22
-- C_READ_DEPTH_B : 22
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT bram_decoder_top IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : bram_decoder_top
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | c0f2f5f83ca6dad83db3ff89d5fd174e | 0.494843 | 3.830364 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng.vhd | 4 | 3,998 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-3-clause | 285a312168bceb3ff9992e576d2a7d07 | 0.642071 | 4.26226 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_updt_noqueue.vhd | 1 | 30,464 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
| mit | 19a72664f2dce411c0ffac2b918e27e8 | 0.402672 | 4.911172 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.vhd | 3 | 11,912 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
| bsd-3-clause | c82436e863b1146f1f0d785d31d2f818 | 0.513684 | 3.881395 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TBSEU.vhd | 3 | 2,304 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:59:22 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBSEU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SEU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBSEU IS
END TBSEU;
ARCHITECTURE behavior OF TBSEU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
Instruction : IN std_logic_vector(31 downto 0);
OUTSEU : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal OUTSEU : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEU PORT MAP (
Instruction => Instruction,
OUTSEU => OUTSEU
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "00000000000000000000000000000111";
wait for 100 ns;
Instruction <= "00001000000000000000000000011100";
wait for 100 ns;
Instruction <= "00000000100000000011111111111111";
wait for 100 ns;
Instruction <= "00001111100000000000000000000000";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | d2d389a1226a03a1b65ac81ab6a97c04 | 0.621094 | 4.45648 | false | true | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/sim/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 1 | 10,720 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit | 64b3a4277b68664f2e2ccd6a114cbebe | 0.632556 | 3.215357 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segundoprocesador19oct/firstrpart.vhd | 1 | 6,617 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity firstrpart is
Port ( Resetext : in STD_LOGIC;
Clkinext : in STD_LOGIC;
Adressext : out STD_LOGIC_VECTOR (31 downto 0));
end firstrpart;
architecture arqfirstrpart of firstrpart is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT NPC
PORT(
inNPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outNPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c :in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Windowsmanager
PORT(
cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0')
);
END COMPONENT;
COMPONENT PSR
PORT(
nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC ;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
c : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
signal aux1,aux2,aux3,aux4,aux6,aux7,aux8,aux9,aux10: std_logic_vector(31 downto 0);
signal aux5: std_logic_vector(5 downto 0);
signal aux13,aux14,aux15: std_logic_vector(5 downto 0);
signal aux11,aux12: STD_LOGIC;
signal aux16: STD_LOGIC_VECTOR (3 downto 0);
signal aux17: STD_LOGIC;
begin
U0: NPC PORT MAP(
inNPC => aux1,
Reset => Resetext,
Clk => Clkinext,
outNPC => aux2
);
U1: PC PORT MAP(
inPC => aux2,
Reset => Resetext,
Clk => Clkinext,
outPC => aux3
);
U2: Sumador32bit PORT MAP(
Oper1 => aux3,
Result => aux1
);
U3: IM PORT MAP(
Address => aux3,
Reset => Resetext,
Instruction => aux4
);
U4: CU PORT MAP(
op =>aux4(31 downto 30),
op3 =>aux4(24 downto 19),
ALUOP => aux5
);
U5: SEU PORT MAP(
Instruction =>aux4,
OUTSEU =>aux6
);
U6: MUX32 PORT MAP(
SEUIMM => aux6,
CRS2 => aux7,
OPER2 => aux9,
Instruction => aux4
);
U7: ALU PORT MAP(
OPER1 => aux8,
OPER2 => aux9,
c =>aux17,
ALURESULT => aux10,
ALUOP => aux5
);
U8: RF PORT MAP(
rs1 => aux13,
rs2 => aux14,
rd => aux15,
dwr => aux10,
rst => Resetext,
crs1 => aux8,
crs2 => aux7
);
U9: Windowsmanager PORT MAP(
cwp =>aux12,
rs1 =>aux4(18 downto 14),
rs2 =>aux4(4 downto 0),
rd =>aux4(29 downto 25),
op =>aux4(31 downto 30),
op3 =>aux4(24 downto 19),
cwpout=> aux11,
rs1out=>aux13,
rs2out=> aux14,
rdout=> aux15
);
U10: PSR PORT MAP(
nzvc => aux16,
clk => Clkinext,
cwp => aux12,
rest => Resetext,
ncwp => aux11,
c => aux17
);
U11: PSR_Modifier PORT MAP(
oper1 => aux8,
oper2 => aux9,
aluop => aux5,
aluResult => aux10,
conditionalCodes => aux16
);
Adressext<=aux10;
end arqfirstrpart;
| gpl-3.0 | 70b3d59d6298be61195dc457bc0e8b20 | 0.517908 | 3.607961 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/sim/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 1 | 10,717 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit | 33312b8d4ad69ae3b62459a8dec84152 | 0.632453 | 3.215422 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl.vhd | 3 | 15,657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-3-clause | 92abafa813cce0d1b9bfe86f48f277a8 | 0.525133 | 3.364926 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fmul_32ns_32ns_32_5_max_dsp.vhd | 4 | 3,386 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fmul_32ns_32ns_32_5_max_dsp is
generic (
ID : integer := 23;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fmul_32ns_32ns_32_5_max_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fmul_3_max_dsp_32_u : component tri_intersect_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | e9233fd86f3734cbac75384591e557a2 | 0.489959 | 3.487127 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/SearchModuleTB.vhd | 1 | 5,915 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.SearchModule_pkg.ALL;
entity SearchModuleTB is
end SearchModuleTB;
architecture Behavioral of SearchModuleTB is
constant DATA_WIDTH_A_USAR: integer := 32;
constant ADDR_WIDTH_A_USAR: integer := 10;
--type arrayOfADDR_WIDTH is array ((ADDR_WIDTH_A_USAR-1) downto 0) of std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0);
signal clk : std_logic;
signal search : std_logic;
signal dataToCompare : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
signal operationID : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
signal porta_wr : std_logic;
signal porta_waddr : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal porta_din : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0);
signal searchFinished : std_logic;
signal searchresult : std_logic;
signal resultIndex : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal result_operationID : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0);
signal internalResultFinished_dbg : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal resultIndexs_dbg : arrayOfADDR_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0);
signal dataFound_dbg : arrayUOfDATA_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0);
signal errorDetected : std_logic := '0';
constant clk_period : time := 10 ns;
begin
uut: entity work.SearchModule
generic map (
DATA_WIDTH => DATA_WIDTH_A_USAR,
ADDR_WIDTH => ADDR_WIDTH_A_USAR
)
port map (
clk => clk,
search => search,
dataToCompare => dataToCompare,
operationID => operationID,
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
searchFinished => searchFinished,
searchresult => searchresult,
resultIndex => resultIndex,
result_operationID => result_operationID,
internalResultFinished_dbg => internalResultFinished_dbg,
resultIndexs_dbg => resultIndexs_dbg,
dataFound_dbg => dataFound_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test : process
variable readWriteCounter : integer := 0;
variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := ( others => '0');
variable addrToWrite : std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0) := ( others => '0');
begin
-- Primero grabar los datos en la memoria
search <= '0';
dataToCompare <= (others => '0');
operationID <= (others => '0');
dataToWrite := x"10000000";
porta_wr <= '0';
porta_waddr <= (others => '0');
porta_din <= (others => '0');
wait for 10*clk_period;
porta_wr <= '0';
porta_waddr <= addrToWrite;
porta_din <= dataToWrite;
wait for clk_period;
while readWriteCounter < (2**ADDR_WIDTH_A_USAR) loop
porta_wr <= '1';
porta_waddr <= addrToWrite;
porta_din <= dataToWrite;
wait for clk_period;
porta_wr <= '0';
wait for clk_period;
dataToWrite := dataToWrite+1;
addrToWrite := addrToWrite+1;
readWriteCounter := readWriteCounter+1;
end loop;
porta_wr <= '0';
wait for clk_period;
search <= '0';
dataToWrite := x"10000005";
wait for clk_period;
wait for clk_period;
dataToCompare <= dataToWrite;
search <= '0';
wait for clk_period;
dataToWrite := x"10000006";
dataToCompare <= dataToWrite;
wait for clk_period;
search <= '0';
wait for clk_period;
readWriteCounter := 0;
dataToWrite := x"10000000";
addrToWrite := ( others => '0' );
while readWriteCounter < (2**ADDR_WIDTH_A_USAR) loop
dataToCompare <= dataToWrite;
search <= '1';
wait for clk_period;
search <= '0';
wait for clk_period;
dataToWrite := dataToWrite+1;
addrToWrite := addrToWrite+1;
readWriteCounter := readWriteCounter+1;
end loop;
search <= '0';
wait for clk_period;
wait;
end process;
verification: process
variable verifCounter : integer := 0;
variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := x"10000000";
variable verifDataCounter : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := (others => '0');
begin
errorDetected <= '0';
if( rising_edge(clk) ) then
if( verifCounter >= (2**ADDR_WIDTH_A_USAR) ) then
errorDetected <= '0';
else
if (searchFinished = '1') then
if( (verifDataCounter/=resultIndex) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
verifCounter := verifCounter+1;
dataToWrite := dataToWrite+1;
verifDataCounter := verifDataCounter+1;
else
errorDetected <= '0';
end if;
end if;
end if;
wait;
end process verification;
end Behavioral;
| bsd-3-clause | 589502e898dacde308b0ff5906141cc2 | 0.526458 | 4.280029 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/Eth_GMII_RXTest.vhd | 1 | 4,597 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2014 13:25:44
-- Design Name:
-- Module Name: Eth_GMII_RXTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Eth_GMII_RXTest is
Port (
botones : in STD_LOGIC_VECTOR (3 downto 0);
leds : out STD_LOGIC_VECTOR (3 downto 0);
gmii_int : in STD_LOGIC;
gmii_reset : out STD_LOGIC;
--Interfaz hacia el PHY
gmii_mdc : out STD_LOGIC;
gmii_mdio : inout STD_LOGIC;
gmii_tx_clk : out STD_LOGIC;
gmii_tx_en : out STD_LOGIC;
gmii_tx_data : out STD_LOGIC_VECTOR (7 downto 0);
gmii_tx_err : out STD_LOGIC;
gmii_rx_clk : in STD_LOGIC;
gmii_rx_crs : in STD_LOGIC;
gmii_rx_col : in STD_LOGIC;
gmii_rx_data : in STD_LOGIC_VECTOR (7 downto 0);
gmii_rx_dataValid : in STD_LOGIC;
gmii_rx_err : in STD_LOGIC;
sysclk_n : in std_logic;
sysclk_p : in std_logic
);
end Eth_GMII_RXTest;
architecture Behavioral of Eth_GMII_RXTest is
signal packetCounter : std_logic_vector(3 downto 0) := "0000";
signal gmii_rx_dataValid_previous : std_logic;
signal tx_clk : std_logic;
signal packetAlreadyReaded : std_logic := '0';
signal porta_wr : std_logic;
signal porta_waddr : std_logic_vector(9 downto 0);
signal porta_din : std_logic_vector(7 downto 0) := ( others => '0');
signal porta_rd : std_logic;
signal porta_raddr : std_logic_vector(9 downto 0);
signal porta_dout : std_logic_vector(7 downto 0);
signal portb_rd : std_logic;
signal portb_addr : std_logic_vector(9 downto 0);
signal portb_dout : std_logic_vector(7 downto 0);
signal storeCounter : std_logic_vector(9 downto 0) := ( others => '0');
begin
memory: entity work.BinarySearchBRAM
generic map( DATA_WIDTH => 8, ADDR_WIDTH => 10 )
port map (
clk => gmii_rx_clk,
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
porta_rd => porta_rd,
porta_raddr => porta_raddr,
porta_dout => open,
portb_rd => portb_rd,
portb_addr => portb_addr,
portb_dout => portb_dout
);
porta_wr <= (gmii_rx_dataValid and not(packetAlreadyReaded));
porta_waddr <= storeCounter;
porta_din <= gmii_rx_data(7 downto 0);
porta_rd <= '0';
porta_raddr <= ( others => '0');
portb_rd <= '0';
portb_addr <= ( others => '0');
RXClocking: process (gmii_rx_clk, gmii_rx_dataValid, gmii_rx_data, storeCounter, gmii_rx_dataValid_previous, packetCounter) begin
if ( rising_edge(gmii_rx_clk) ) then
if(gmii_rx_dataValid = '1') then
--leds(3 downto 0) <= gmii_rx_data(3 downto 0);
storeCounter <= storeCounter+1;
end if;
gmii_rx_dataValid_previous <= gmii_rx_dataValid;
if( (gmii_rx_dataValid = '1') and (gmii_rx_dataValid_previous = '0') ) then
packetCounter <= packetCounter+1;
elsif ( (gmii_rx_dataValid = '0') and (gmii_rx_dataValid_previous = '1') ) then
packetAlreadyReaded <= '1';
end if;
end if;
end process RXClocking;
leds <= packetCounter;
gmii_reset <= '1';
gmii_tx_en <= '0';
gmii_tx_data <= (others => '0');
gmii_tx_err <= '0';
gmii_mdc <= '0';
gmii_mdio <= 'Z';
txClkGenerator: entity work.clk_wiz_v3_6_0
port map
(-- Clock in ports
CLK_IN1_P => sysclk_p,
CLK_IN1_N => sysclk_n,
-- Clock out ports
CLK_OUT1 => tx_clk
);
gmii_tx_clk_ddr_iob : ODDR2
port map(
D0 => '0',
D1 => '1',
C0 => tx_clk,
C1 => '0',
CE => '1',
R => '0',
S => '0',
Q => gmii_tx_clk
);
end Behavioral;
| bsd-3-clause | 097bbd1ef5238f7901629cacfe0a57e8 | 0.551229 | 3.461596 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/sim/tri_intersect_ap_fmul_3_max_dsp_32.vhd | 1 | 10,719 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
| mit | cd93b6e8094b37187867da6626fe512d | 0.632522 | 3.215057 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl.vhd | 3 | 15,657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-3-clause | 119bd467f0d5bc67d39a4531a9190490 | 0.525133 | 3.364926 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/hdl/system_axi_dispctrl_0_wrapper.vhd | 3 | 6,408 | -------------------------------------------------------------------------------
-- system_axi_dispctrl_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.all;
entity system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end system_axi_dispctrl_0_wrapper;
architecture STRUCTURE of system_axi_dispctrl_0_wrapper is
component axi_dispctrl is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER;
C_USE_BUFR_DIV5 : INTEGER;
C_RED_WIDTH : INTEGER;
C_GREEN_WIDTH : INTEGER;
C_BLUE_WIDTH : INTEGER;
C_S_AXIS_MM2S_TDATA_WIDTH : INTEGER
);
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector((C_RED_WIDTH-1) downto 0);
GREEN_O : out std_logic_vector((C_GREEN_WIDTH-1) downto 0);
BLUE_O : out std_logic_vector((C_BLUE_WIDTH-1) downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH-1) downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0)
);
end component;
begin
axi_dispctrl_0 : axi_dispctrl
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"75c00000",
C_HIGHADDR => X"75c0ffff",
C_FAMILY => "zynq",
C_NUM_REG => 1,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32,
C_USE_BUFR_DIV5 => 1,
C_RED_WIDTH => 8,
C_GREEN_WIDTH => 8,
C_BLUE_WIDTH => 8,
C_S_AXIS_MM2S_TDATA_WIDTH => 32
)
port map (
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
DEBUG_O => DEBUG_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TSTRB => S_AXIS_TSTRB
);
end architecture STRUCTURE;
| bsd-3-clause | cee1b98ce0f274daea606a99339e647a | 0.573658 | 2.899548 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/DataMemory.vhd | 2 | 1,298 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:25 10/20/2017
-- Design Name:
-- Module Name: DataMemory - tbDataMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity DataMemory is
Port ( cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
Reset : in STD_LOGIC;
DataMem : out STD_LOGIC_VECTOR (31 downto 0));
end DataMemory;
architecture Behavioral of DataMemory is
type reg is array (0 to 31) of std_logic_vector (31 downto 0);
signal myReg : reg := (others => x"00000000");
begin
process(cRD,AluResult,Reset,WRENMEM)
begin
if (Reset='1') then
DataMem <= x"00000000";
else
if (WRENMEM='1') then
myReg(conv_integer(AluResult(4 downto 0))) <= cRD;
else
DataMem <= myReg(conv_integer(AluResult(4 downto 0)));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 747cfed0fe80c0f7a6f4864f733b31b6 | 0.568567 | 3.585635 | false | false | false | false |
quicky2000/top_wireworld | top_wireworld.vhd | 1 | 2,956 | --
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_wireworld is
port(
clk : in std_logic;
w1a : inout std_logic_vector(15 downto 0);
w1b : inout std_logic_vector(15 downto 0);
w2c : inout std_logic_vector(15 downto 0);
rx : in std_logic;
tx : inout std_logic
);
end top_wireworld;
architecture Behavioral of top_wireworld is
-- component wireworld_cell is
-- generic (
-- init_state : state_type := t_copper
-- );
-- Port ( clk : in STD_LOGIC;
-- reset : in STD_LOGIC;
-- neighbours : in STD_LOGIC_VECTOR (7 downto 0);
-- electron_head : out STD_LOGIC;
-- electron_queue : out STD_LOGIC);
-- end component;
signal reset : std_logic;
signal to_0 : std_logic_vector (7 downto 0);
signal to_1 : std_logic_vector (7 downto 0);
signal to_2 : std_logic_vector (7 downto 0);
signal from_0 : std_logic;
signal from_1 : std_logic;
signal from_2 : std_logic;
begin
-- to_0 <= (0 => from_1,others => '0');
-- to_1 <= (0 => from_0,others => '0');
to_0 <= (0=> from_2, others => '0');
to_1 <= (0=> from_0, others => '0');
to_2 <= (0=> from_1, others => '0');
cell_0 : entity work.wireworld_cell
generic map( init_state => t_electron_head )
port map (
clk => clk,
reset => reset,
neighbours => to_0,
electron_head => from_0,
electron_queue => w1a(2)
);
cell_1 : entity work.wireworld_cell
port map (
clk => clk,
reset => reset,
neighbours => to_1,
electron_head => from_1,
electron_queue => w1a(6)
);
cell_2 : entity work.wireworld_cell
port map (
clk => clk,
reset => reset,
neighbours => to_2,
electron_head => from_2,
electron_queue => w1a(10)
);
w1a(0) <= from_0;
w1a(4) <= from_1;
w1a(8) <= from_2;
reset <= '0';
end Behavioral;
| gpl-3.0 | 1810e07410d66a910a6e30593d629c16 | 0.646482 | 3.111579 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd | 1 | 70,811 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_pcc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1.axi_datamover_rd_sf;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| mit | 36acafb788f4f42214b117f722ec1cad | 0.438985 | 4.208427 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serportlib.vhd | 1 | 14,493 | -- $Id: serportlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: serportlib
-- Description: serial port interface components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-25 752 1.3.2 add serport_2clock2
-- 2015-04-11 666 1.3.1 add serport_master
-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud
-- 2013-01-26 476 1.2.6 renamed package to serportlib
-- 2011-12-09 437 1.2.5 rename stat->moni port
-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts
-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
-- 2011-10-14 416 1.2.2 add c_serport defs
-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
-- 2010-04-10 276 1.2 add clock divider constant defs
-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of many serport_* entities, with -tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package serportlib is
constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
component serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rx is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end component;
component serport_uart_tx is -- serial port uart: transmit part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end component;
component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting
ABCLKDIV_F : out slv3 -- autobaud clock divider fraction
);
end component;
component serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
CLKDIV_F: out slv3; -- clock divider fractional part
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end component;
component serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end component;
component serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end component;
type serport_moni_type is record -- serport monitor port
rxerr : slbit; -- receiver data error (frame error)
rxovr : slbit; -- receiver data overrun
rxact : slbit; -- receiver active
txact : slbit; -- transceiver active
abact : slbit; -- autobauder active;if 1 clkdiv invalid
abdone : slbit; -- autobauder resync done
abclkdiv : slv16; -- autobauder clock divider
abclkdiv_f : slv3; -- autobauder clock divider fraction
rxok : slbit; -- rx channel ok
txok : slbit; -- tx channel ok
end record serport_moni_type;
constant serport_moni_init : serport_moni_type := (
'0','0', -- rxerr,rxovr
'0','0', -- rxact,txact
'0','0', -- abact,abdone
(others=>'0'), -- abclkdiv
(others=>'0'), -- abclkdiv_f
'0','0' -- rxok,txok
);
component serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end component;
component serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end component;
component serport_2clock2 is -- serial port module, 2 clock dom. (v2)
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- U|clock (backend:user)
RESET : in slbit; -- U|reset
CLKS : in slbit; -- S|clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end component;
component serport_master is -- serial port module, master side
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
ENAXON : in slbit := '0'; -- enable xon/xoff handling
ENAESC : in slbit := '0'; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXOK : in slbit := '1'; -- rx channel ok
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit :='0' -- transmit cts (uart view, act.low)
);
end component;
end package serportlib;
| gpl-3.0 | 622c8f0ef887b289e3e67fcd27aff168 | 0.504312 | 4.498138 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04900_bad.vhd | 1 | 2,910 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-17 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04900_bad.vhd
-- File Creation date : 2015-04-17
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of clock signal: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity CNE_04900_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_04900_bad;
--CODE
architecture Behavioral of CNE_04900_bad is
signal Gated_Clock : std_logic; -- Gated clock signal
begin
Gated_Clock <= i_Clock and i_Enable;
DFF:DFlipFlop
port map (
i_Clock => Gated_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 | ce6953e69ff89554d36d6ad5134337d3 | 0.479725 | 4.442748 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/tb_cmoda7.vhd | 1 | 4,633 | -- $Id: tb_cmoda7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cmoda7 - sim
-- Description: Test bench for cmoda7 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_basys3_core
-- serport/tb/serport_master_tb
-- cmoda7_aif [UUT]
--
-- To test: generic, any cmoda7_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.4-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-06-04 906 1.0 Initial version (derived from tb_arty)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.cmoda7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_cmoda7 is
end tb_cmoda7;
architecture sim of tb_cmoda7 is
signal CLKOSC : slbit := '0'; -- board clock (12 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_BTN : slv2 := (others=>'0');
signal O_LED : slv2 := (others=>'0');
signal O_RGBLED0_N : slv3 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 83.333 ns;
constant clock_offset : Delay_length := 2000 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
C7CORE : entity work.tb_cmoda7_core
port map (
I_BTN => I_BTN
);
UUT : cmoda7_aif
port map (
I_CLK12 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0_N => O_RGBLED0_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most cmoda7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | cdf9a18facf3f479384904822d4a3201 | 0.54414 | 3.473013 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_maxisys.vhd | 1 | 21,873 | -- $Id: ibdr_maxisys.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_maxisys - syn
-- Description: ibus(rem) devices for full system
--
-- Dependencies: ib_rlim_gen
-- ibd_iist
-- ibd_kw11l
-- ibd_kw11p
-- ibdr_deuna
-- ibdr_rhrp
-- ibdr_rl11
-- ibdr_rk11
-- ibdr_tm11
-- ibdr_dl11
-- ibdr_dl11_buf
-- ibdr_dz11
-- ibdr_pc11
-- ibdr_pc11_buf
-- ibdr_lp11
-- ibdr_lp11_buf
-- ibd_m9312
-- ibdr_sdreg
-- ib_sres_or_4
-- ib_sres_or_3
-- ib_intmap24
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
--
-- Synthesized:
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-10-13 1055 14.7 131013 xc6slx16-2 774 1720 30 584 s 8.5 +KW11P
-- 2017-01-29 847 14.7 131013 xc6slx16-2 712 1628 30 599 s 8.5 +DEUNA
-- 2017-01-28 846 14.7 131013 xc6slx16-2 668 1562 30 577 s 8.5 intmap24
-- 2017-01-28 683 viv 2016.4 xc7a100t-1 683 1684 48 - -
-- 2017-01-28 683 14.7 131013 xc6slx16-2 668 1557 30 576 s 8.5 +TM11
-- 2015-04-06 664 14.7 131013 xc6slx16-2 559 1068 29 410 s 9.1 +RHRP
-- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11
-- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1
-- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3
-- 2010-10-17 314 12.1 M53d xc3s1000-4 300 1094 16 626 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-04 1146 1.6.9 add ibdr_dz11
-- 2019-04-28 1142 1.6.8 add ibd_m9312
-- 2019-04-26 1139 1.6.7 add ibdr_dl11_buf
-- 2019-04-23 1136 1.6.6 add CLK port to ib_intmap24
-- 2019-04-14 1131 1.6.5 ib_rlim_gen has CPUSUSP port; RLIM_CEV now slv8
-- 2019-04-07 1129 1.6.4 add ibdr_pc11_buf
-- 2019-04-07 1127 1.6.3 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2019-03-17 1123 1.6.2 add ib_rlim_gen, use with ibdr_lp11_buf
-- 2019-03-09 1121 1.6.1 add ibdr_lp11_buf
-- 2019-02-10 1111 1.6 use typ for DL,PC,LP
-- 2019-01-29 1108 1.5.1 move IIST signals into generate
-- 2018-10-13 1055 1.5 add IDEC port, connect to EXTEVT of KW11P
-- 2018-09-08 1043 1.4.2 add KW11P;
-- 2017-01-29 847 1.4.1 add DEUNA; rename generic labels
-- 2017-01-28 846 1.4 use ib_intmap24
-- 2015-05-15 683 1.3.1 add TM11
-- 2015-05-10 678 1.3 start/stop/suspend overhaul
-- 2015-04-06 664 1.2.3 rename RPRM to RHRP
-- 2015-03-14 658 1.2.2 add RPRM; rearrange intmap (+rhrp,tm11,-kw11-p)
-- use sys_conf, make most devices configurable
-- 2015-01-04 630 1.2.1 RL11 back in
-- 2014-06-27 565 1.2.1 temporarily hide RL11
-- 2014-06-08 561 1.2 add RL11
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
-- 2009-06-20 227 1.0.3 rename generate labels
-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces
-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist
-- 2009-05-24 219 1.0 Initial version
------------------------------------------------------------------------------
--
--
-- full system setup
--
-- ibbase vec pri slot attn sror device name
--
-- 172540 104 6 17 - 1/1 KW11-P
-- 177500 260 6 15 16 - 1/2 IIST
-- 177546 100 6 14 15 - 1/3 KW11-L
-- 174510 120 5 14 9 1/4 DEUNA
-- 176700 254 5 13 13 6 2/1 RHRP
-- 174400 160 5 12 12 5 2/2 RL11
-- 177400 220 5 11 11 4 2/3 RK11
-- 172520 224 5 10 10 7 2/4 TM11
-- 160100 310 5 9 9 3 3/1 DZ11-RX
-- 314 5 8 8 ^ DZ11-TX
-- 177560 060 4 7 7 1 3/2 DL11-RX 1st
-- 064 4 6 6 ^ DL11-TX 1st
-- 176500 300 4 5 5 2 3/3 DL11-RX 2nd
-- 304 4 4 4 ^ DL11-TX 2nd
-- 177550 070 4 3 3 10 4/1 PC11/PTR
-- 074 4 2 2 ^ PC11/PTP
-- 177514 200 4 1 1 8 4/2 LP11
-- 177570 - - - - 4/3 sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity ibdr_maxisys is -- ibus(rem) full system
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
IDEC : in slbit; -- instruction decode
CPUSUSP : in slbit; -- cpu suspended
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_maxisys;
architecture syn of ibdr_maxisys is
constant ibaddr_dl11_1 : slv16 := slv(to_unsigned(8#176500#,16));
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
constant conf_intmap24 : intmap24_array_type :=
(intmap_init, -- line 23 (unused)
intmap_init, -- line 22 (unused)
intmap_init, -- line 21 (unused)
intmap_init, -- line 20 (unused)
intmap_init, -- line 19 (unused)
intmap_init, -- line 18 (unused)
(8#104#,6), -- line 17 KW11-P
(8#260#,6), -- line 16 IIST
(8#100#,6), -- line 15 KW11-L
(8#120#,5), -- line 14 DENUA
(8#254#,5), -- line 13 RHRP
(8#160#,5), -- line 12 RL11
(8#220#,5), -- line 11 RK11
(8#224#,5), -- line 10 TM11
(8#310#,5), -- line 9 DZ11-RX
(8#314#,5), -- line 8 DZ11-TX
(8#060#,4), -- line 7 DL11-RX 1st
(8#064#,4), -- line 6 DL11-TX 1st
(8#300#,4), -- line 5 DL11-RX 2nd
(8#304#,4), -- line 4 DL11-TX 2nd
(8#070#,4), -- line 3 PC11-PTR
(8#074#,4), -- line 2 PC11-PTP
(8#200#,4), -- line 1 LP11
intmap_init -- line 0 (must be unused!)
);
signal RB_LAM_DEUNA : slbit := '0';
signal RB_LAM_RHRP : slbit := '0';
signal RB_LAM_RL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal RB_LAM_TM11 : slbit := '0';
signal RB_LAM_DL11_0 : slbit := '0';
signal RB_LAM_DL11_1 : slbit := '0';
signal RB_LAM_DZ11 : slbit := '0';
signal RB_LAM_PC11 : slbit := '0';
signal RB_LAM_LP11 : slbit := '0';
signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init;
signal IB_SRES_RHRP : ib_sres_type := ib_sres_init;
signal IB_SRES_RL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal IB_SRES_TM11 : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11_0 : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11_1 : ib_sres_type := ib_sres_init;
signal IB_SRES_DZ11 : ib_sres_type := ib_sres_init;
signal IB_SRES_PC11 : ib_sres_type := ib_sres_init;
signal IB_SRES_LP11 : ib_sres_type := ib_sres_init;
signal IB_SRES_M9312 : ib_sres_type := ib_sres_init;
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_1 : ib_sres_type := ib_sres_init;
signal IB_SRES_2 : ib_sres_type := ib_sres_init;
signal IB_SRES_3 : ib_sres_type := ib_sres_init;
signal IB_SRES_4 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv24_1 := (others=>'0');
signal EI_ACK : slv24_1 := (others=>'0');
signal EI_REQ_IIST : slbit := '0';
signal EI_REQ_KW11P : slbit := '0';
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DEUNA : slbit := '0';
signal EI_REQ_RHRP : slbit := '0';
signal EI_REQ_RL11 : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_REQ_TM11 : slbit := '0';
signal EI_REQ_DL11RX_0 : slbit := '0';
signal EI_REQ_DL11TX_0 : slbit := '0';
signal EI_REQ_DL11RX_1 : slbit := '0';
signal EI_REQ_DL11TX_1 : slbit := '0';
signal EI_REQ_DZ11RX : slbit := '0';
signal EI_REQ_DZ11TX : slbit := '0';
signal EI_REQ_PC11PTR : slbit := '0';
signal EI_REQ_PC11PTP : slbit := '0';
signal EI_REQ_LP11 : slbit := '0';
signal EI_ACK_IIST : slbit := '0';
signal EI_ACK_KW11P : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DEUNA : slbit := '0';
signal EI_ACK_RHRP : slbit := '0';
signal EI_ACK_RL11 : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
signal EI_ACK_TM11 : slbit := '0';
signal EI_ACK_DL11RX_0 : slbit := '0';
signal EI_ACK_DL11TX_0 : slbit := '0';
signal EI_ACK_DL11RX_1 : slbit := '0';
signal EI_ACK_DL11TX_1 : slbit := '0';
signal EI_ACK_DZ11RX : slbit := '0';
signal EI_ACK_DZ11TX : slbit := '0';
signal EI_ACK_PC11PTR : slbit := '0';
signal EI_ACK_PC11PTP : slbit := '0';
signal EI_ACK_LP11 : slbit := '0';
signal RLIM_CEV : slv8 := (others=>'0');
begin
RLIM : ib_rlim_gen
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0',
CPUSUSP => CPUSUSP,
RLIM_CEV => RLIM_CEV
);
IIST: if sys_conf_ibd_iist generate
signal IIST_BUS : iist_bus_type := iist_bus_init;
signal IIST_OUT_0 : iist_line_type := iist_line_init;
signal IIST_MREQ : iist_mreq_type := iist_mreq_init;
signal IIST_SRES : iist_sres_type := iist_sres_init;
begin
I0 : ibd_iist
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IIST,
EI_REQ => EI_REQ_IIST,
EI_ACK => EI_ACK_IIST,
IIST_BUS => IIST_BUS,
IIST_OUT => IIST_OUT_0,
IIST_MREQ => IIST_MREQ,
IIST_SRES => IIST_SRES
);
IIST_BUS(0) <= IIST_OUT_0;
IIST_BUS(1) <= iist_line_init;
IIST_BUS(2) <= iist_line_init;
IIST_BUS(3) <= iist_line_init;
end generate IIST;
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
CPUSUSP => CPUSUSP,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
KW11P: if sys_conf_ibd_kw11p generate
begin
I0 : ibd_kw11p
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
EXTEVT => IDEC,
CPUSUSP => CPUSUSP,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11P,
EI_REQ => EI_REQ_KW11P,
EI_ACK => EI_ACK_KW11P
);
end generate KW11P;
DEUNA: if sys_conf_ibd_deuna generate
begin
XUA : ibdr_deuna
port map (
CLK => CLK,
BRESET => BRESET,
RB_LAM => RB_LAM_DEUNA,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DEUNA,
EI_REQ => EI_REQ_DEUNA,
EI_ACK => EI_ACK_DEUNA
);
end generate DEUNA;
RHRP: if sys_conf_ibd_rhrp generate
begin
RPA : ibdr_rhrp
port map (
CLK => CLK,
CE_USEC => CE_USEC,
BRESET => BRESET,
ITIMER => ITIMER,
RB_LAM => RB_LAM_RHRP,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RHRP,
EI_REQ => EI_REQ_RHRP,
EI_ACK => EI_ACK_RHRP
);
end generate RHRP;
RL11: if sys_conf_ibd_rl11 generate
begin
RLA : ibdr_rl11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RL11,
EI_REQ => EI_REQ_RL11,
EI_ACK => EI_ACK_RL11
);
end generate RL11;
RK11: if sys_conf_ibd_rk11 generate
begin
RKA : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
end generate RK11;
TM11: if sys_conf_ibd_tm11 generate
begin
TMA : ibdr_tm11
port map (
CLK => CLK,
BRESET => BRESET,
RB_LAM => RB_LAM_TM11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_TM11,
EI_REQ => EI_REQ_TM11,
EI_ACK => EI_ACK_TM11
);
end generate TM11;
DL11_0: if sys_conf_ibd_dl11_0 = 0 generate
TTA : ibdr_dl11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_0,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_0,
EI_REQ_RX => EI_REQ_DL11RX_0,
EI_REQ_TX => EI_REQ_DL11TX_0,
EI_ACK_RX => EI_ACK_DL11RX_0,
EI_ACK_TX => EI_ACK_DL11TX_0
);
end generate DL11_0;
DL11_0BUF: if sys_conf_ibd_dl11_0 > 0 generate
TTA : ibdr_dl11_buf
generic map (
AWIDTH => sys_conf_ibd_dl11_0)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_0,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_0,
EI_REQ_RX => EI_REQ_DL11RX_0,
EI_REQ_TX => EI_REQ_DL11TX_0,
EI_ACK_RX => EI_ACK_DL11RX_0,
EI_ACK_TX => EI_ACK_DL11TX_0
);
end generate DL11_0BUF;
DL11_1: if sys_conf_ibd_dl11_1 = 0 generate
begin
TTB : ibdr_dl11
generic map (
IB_ADDR => ibaddr_dl11_1)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_1,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_1,
EI_REQ_RX => EI_REQ_DL11RX_1,
EI_REQ_TX => EI_REQ_DL11TX_1,
EI_ACK_RX => EI_ACK_DL11RX_1,
EI_ACK_TX => EI_ACK_DL11TX_1
);
end generate DL11_1;
DL11_1BUF: if sys_conf_ibd_dl11_1 > 0 generate
begin
TTB : ibdr_dl11_buf
generic map (
IB_ADDR => ibaddr_dl11_1,
AWIDTH => sys_conf_ibd_dl11_1)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_1,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_1,
EI_REQ_RX => EI_REQ_DL11RX_1,
EI_REQ_TX => EI_REQ_DL11TX_1,
EI_ACK_RX => EI_ACK_DL11RX_1,
EI_ACK_TX => EI_ACK_DL11TX_1
);
end generate DL11_1BUF;
DZ11: if sys_conf_ibd_dz11 > 0 generate
DZA : ibdr_dz11
generic map (
IB_ADDR => ibaddr_dz11,
AWIDTH => sys_conf_ibd_dz11)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DZ11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DZ11,
EI_REQ_RX => EI_REQ_DZ11RX,
EI_REQ_TX => EI_REQ_DZ11TX,
EI_ACK_RX => EI_ACK_DZ11RX,
EI_ACK_TX => EI_ACK_DZ11TX
);
end generate DZ11;
PC11: if sys_conf_ibd_pc11 = 0 generate
begin
PCA : ibdr_pc11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_PC11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PC11,
EI_REQ_PTR => EI_REQ_PC11PTR,
EI_REQ_PTP => EI_REQ_PC11PTP,
EI_ACK_PTR => EI_ACK_PC11PTR,
EI_ACK_PTP => EI_ACK_PC11PTP
);
end generate PC11;
PC11BUF: if sys_conf_ibd_pc11 > 0 generate
begin
PCA : ibdr_pc11_buf
generic map (
AWIDTH => sys_conf_ibd_pc11)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_PC11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PC11,
EI_REQ_PTR => EI_REQ_PC11PTR,
EI_REQ_PTP => EI_REQ_PC11PTP,
EI_ACK_PTR => EI_ACK_PC11PTR,
EI_ACK_PTP => EI_ACK_PC11PTP
);
end generate PC11BUF;
LP11: if sys_conf_ibd_lp11 = 0 generate
begin
LPA : ibdr_lp11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_LP11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_LP11,
EI_REQ => EI_REQ_LP11,
EI_ACK => EI_ACK_LP11
);
end generate LP11;
LP11BUF: if sys_conf_ibd_lp11 > 0 generate
begin
LPA : ibdr_lp11_buf
generic map (
AWIDTH => sys_conf_ibd_lp11)
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_LP11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_LP11,
EI_REQ => EI_REQ_LP11,
EI_ACK => EI_ACK_LP11
);
end generate LP11BUF;
M9312: if sys_conf_ibd_m9312 generate
begin
ROM : ibd_m9312
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_M9312
);
end generate M9312;
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
SRES_OR_1 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_KW11P,
IB_SRES_2 => IB_SRES_IIST,
IB_SRES_3 => IB_SRES_KW11L,
IB_SRES_4 => IB_SRES_DEUNA,
IB_SRES_OR => IB_SRES_1
);
SRES_OR_2 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_RHRP,
IB_SRES_2 => IB_SRES_RL11,
IB_SRES_3 => IB_SRES_RK11,
IB_SRES_4 => IB_SRES_TM11,
IB_SRES_OR => IB_SRES_2
);
SRES_OR_3 : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_DL11_0,
IB_SRES_2 => IB_SRES_DL11_1,
IB_SRES_3 => IB_SRES_DZ11,
IB_SRES_OR => IB_SRES_3
);
SRES_OR_4 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_PC11,
IB_SRES_2 => IB_SRES_LP11,
IB_SRES_3 => IB_SRES_M9312,
IB_SRES_4 => IB_SRES_SDREG,
IB_SRES_OR => IB_SRES_4
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap24
generic map (
INTMAP => conf_intmap24)
port map (
CLK => CLK,
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(23 downto 18) <= (others=>'0');
EI_REQ(17) <= EI_REQ_KW11P;
EI_REQ(16) <= EI_REQ_IIST;
EI_REQ(15) <= EI_REQ_KW11L;
EI_REQ(14) <= EI_REQ_DEUNA;
EI_REQ(13) <= EI_REQ_RHRP;
EI_REQ(12) <= EI_REQ_RL11;
EI_REQ(11) <= EI_REQ_RK11;
EI_REQ(10) <= EI_REQ_TM11;
EI_REQ( 9) <= EI_REQ_DZ11RX;
EI_REQ( 8) <= EI_REQ_DZ11TX;
EI_REQ( 7) <= EI_REQ_DL11RX_0;
EI_REQ( 6) <= EI_REQ_DL11TX_0;
EI_REQ( 5) <= EI_REQ_DL11RX_1;
EI_REQ( 4) <= EI_REQ_DL11TX_1;
EI_REQ( 3) <= EI_REQ_PC11PTR;
EI_REQ( 2) <= EI_REQ_PC11PTP;
EI_REQ( 1) <= EI_REQ_LP11;
EI_ACK_KW11P <= EI_ACK(17);
EI_ACK_IIST <= EI_ACK(16);
EI_ACK_KW11L <= EI_ACK(15);
EI_ACK_DEUNA <= EI_ACK(14);
EI_ACK_RHRP <= EI_ACK(13);
EI_ACK_RL11 <= EI_ACK(12);
EI_ACK_RK11 <= EI_ACK(11);
EI_ACK_TM11 <= EI_ACK(10);
EI_ACK_DZ11RX <= EI_ACK( 9);
EI_ACK_DZ11TX <= EI_ACK( 8);
EI_ACK_DL11RX_0 <= EI_ACK( 7);
EI_ACK_DL11TX_0 <= EI_ACK( 6);
EI_ACK_DL11RX_1 <= EI_ACK( 5);
EI_ACK_DL11TX_1 <= EI_ACK( 4);
EI_ACK_PC11PTR <= EI_ACK( 3);
EI_ACK_PC11PTP <= EI_ACK( 2);
EI_ACK_LP11 <= EI_ACK( 1);
RB_LAM(15 downto 11) <= (others=>'0');
RB_LAM(10) <= RB_LAM_PC11;
RB_LAM( 9) <= RB_LAM_DEUNA;
RB_LAM( 8) <= RB_LAM_LP11;
RB_LAM( 7) <= RB_LAM_TM11;
RB_LAM( 6) <= RB_LAM_RHRP;
RB_LAM( 5) <= RB_LAM_RL11;
RB_LAM( 4) <= RB_LAM_RK11;
RB_LAM( 3) <= RB_LAM_DZ11;
RB_LAM( 2) <= RB_LAM_DL11_1;
RB_LAM( 1) <= RB_LAM_DL11_0;
end syn;
| gpl-3.0 | af71b8c9c33a8e1e013c4ad5da39375c | 0.49536 | 2.83109 | false | false | false | false |
kb3gtn/fpga_edc | src/mojo_top.vhd | 1 | 12,735 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mojo_top is
Port (
clk50m : in STD_LOGIC;
rst_n : in STD_LOGIC;
cclk : in STD_LOGIC; -- spi/fpga programming clock (not used).
led : out STD_LOGIC_VECTOR (7 downto 0); -- board LEDs
-- spi interface shared with AVR and SPI flash chip (not used here)
--spi_mosi : in STD_LOGIC;
--spi_miso : out STD_LOGIC;
--spi_ss : in STD_LOGIC;
--spi_sck : in STD_LOGIC;
--spi_channel : in STD_LOGIC_VECTOR (3 downto 0); ( not used here)
-- avr rs232 interface (ttl levels) ( not used here )
-- avr_tx : in STD_LOGIC;
-- avr_rx : in STD_LOGIC;
-- avr_rx_busy : in STD_LOGIC
-- RS232
serial_tx : out STD_LOGIC; -- 3rd pin up from uC outside.
serial_rx : in STD_LOGIC; -- 4th pin up from uC outside.
-- SPI1 signals
spi1_miso : in STD_LOGIC;
spi1_mosi : out STD_LOGIC;
spi1_sclk : out STD_LOGIC;
spi1_cs_n : out STD_LOGIC_VECTOR( 3 downto 0)
);
end mojo_top;
architecture Behavioral of mojo_top is
--#########################################################
--# Component Definitions
--#########################################################
component uart is
port (
i_clk : in std_logic; -- system clock
i_srst : in std_logic; -- synchronious reset, 1 - active
i_baud_div : in std_logic_vector(15 downto 0); -- clk divider to get to baud rate
-- uart interface
o_uart_tx : out std_logic; -- tx bit stream
i_uart_rx : in std_logic; -- uart rx bit stream input
-- fpga side
i_tx_send : in std_logic_vector(7 downto 0); -- data byte in
i_tx_send_we : in std_logic; -- write enable
o_tx_send_busy : out std_logic; -- tx is busy, writes are ignored.
o_rx_read : out std_logic_vector(7 downto 0); -- data byte out
o_rx_read_valid : out std_logic; -- read data valid this clock cycle
i_rx_read_rd : in std_logic -- read request, get next byte..
);
end component uart;
component uart_db_interface is
port (
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- uart interface
i_rx_data : in std_logic_vector( 7 downto 0); -- data from uart
i_rx_data_valid : in std_logic; -- valid data from uart
o_rx_read_ack : out std_logic; -- tell uart we have read byte.
o_tx_send : out std_logic_vector( 7 downto 0); -- tx_send data
o_tx_send_wstrb : out std_logic; -- write data strobe
i_tx_send_busy : in std_logic; -- uart is busy tx, don't write anything.. (stall)
-- databus master interface
o_db_cmd_wstrb : out std_logic; -- write command strobe
o_db_cmd_out : out std_logic_vector( 7 downto 0); -- cmd to databus master
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- write data to databus master
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- read data from databus master
i_db_cmd_rdy : in std_logic -- db is ready to process a cmd / previous cmd is complete.
);
end component;
component databus_master is
generic (
slave_latency_max : integer := 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
);
port (
-- clock and resets
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- db master cmd interface
i_db_cmd_in : in std_logic_vector( 7 downto 0); -- input cmd byte
i_db_cmd_wstrb : in std_logic; -- write strobe for cmd byte
o_db_cmd_rdy : out std_logic; -- '1' rdy to process next cmd, '0' busy
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- input byte if cmd is a write (with wstrb)
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- output byte if cmd was a read
-- data bus interface
o_db_addr : out std_logic_vector( 6 downto 0); -- 6 -> 0 bit address bus (7 bits)
o_db_write_data : out std_logic_vector( 7 downto 0); -- write data
i_db_read_data : in std_logic_vector( 7 downto 0); -- read data
o_db_read_strb : out std_logic; -- db_read_strobe
o_db_write_strb : out std_logic -- db_write_strobe
);
end component;
component spi_master is
generic (
-- default address for this module to use..
data_reg_addr : std_logic_vector( 6 downto 0) := "0000000"; -- address 0
conf_reg_addr : std_logic_vector( 6 downto 0) := "0000001"; -- address 1
baud_reg_addr : std_logic_vector( 6 downto 0) := "0000010" -- address 2
);
port (
i_clk : in std_logic; -- input system clock (50 MHz)
i_srst : in std_logic; -- input sync reset to i_clk
-- spi interface
o_spi_sclk : out std_logic; -- spi clock signal
o_spi_mosi : out std_logic; -- spi master data output
i_spi_miso : in std_logic; -- spi master data input
o_spi_cs_n : out std_logic_vector( 3 downto 0); -- chip select signals. (active low)
-- data bus interface
i_db_addr : in std_logic_vector( 6 downto 0);
i_db_wr_strb : in std_logic;
i_db_rd_strb : in std_logic;
i_db_wr_data : in std_logic_vector( 7 downto 0 );
o_db_rd_data : out std_logic_vector( 7 downto 0 )
);
end component;
--###########################################################
--# Signal Definitions
--###########################################################
-- uart signals
signal baud_div : std_logic_vector( 15 downto 0);
signal tx_byte : std_logic_vector( 7 downto 0);
signal tx_byte_we : std_logic;
signal tx_byte_busy : std_logic;
signal rx_byte : std_logic_vector( 7 downto 0);
signal rx_byte_valid : std_logic;
signal rx_byte_rd : std_logic;
-- data bus master signals
signal db_cmd : std_logic_vector( 7 downto 0 );
signal db_cmd_wstrb : std_logic;
signal db_cmd_rdy : std_logic;
signal db_cmd_wr_data : std_logic_vector( 7 downto 0 );
signal db_cmd_rd_data : std_logic_vector( 7 downto 0 );
-- data bus interface to slaves
signal db_addr : std_logic_vector(6 downto 0);
signal db_wr_data : std_logic_vector(7 downto 0);
signal db_rd_data : std_logic_vector(7 downto 0);
signal db_wr_strb : std_logic;
signal db_rd_strb : std_logic;
-- output register for driving the LEDs
signal led_reg : std_logic_vector(7 downto 0);
-- sync reset signal to 50 MHz clk
signal srst : std_logic;
begin
led <= led_reg;
-- led <= rx_byte;
baud_div <= x"01B2"; -- 115200
uart_1 : uart
port map (
i_clk => clk50m,
i_srst => srst,
i_baud_div => baud_div,
-- uart interface
o_uart_tx => serial_tx,
i_uart_rx => serial_rx,
-- fpga side
i_tx_send => tx_byte,
i_tx_send_we => tx_byte_we,
o_tx_send_busy => tx_byte_busy,
o_rx_read => rx_byte,
o_rx_read_valid => rx_byte_valid,
i_rx_read_rd => rx_byte_rd
);
udbi_1 : uart_db_interface
port map (
i_clk => clk50m,
i_srst => srst,
-- uart interface
i_rx_data => rx_byte,
i_rx_data_valid => rx_byte_valid,
o_rx_read_ack => rx_byte_rd,
o_tx_send => tx_byte,
o_tx_send_wstrb => tx_byte_we,
i_tx_send_busy => tx_byte_busy,
-- databus master interface
o_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_out => db_cmd,
o_db_cmd_data_out => db_cmd_wr_data,
i_db_cmd_data_in => db_cmd_rd_data,
i_db_cmd_rdy => db_cmd_rdy
);
db_master_1 : databus_master
generic map (
slave_latency_max => 3 -- latency from read/write strb to when the
-- operation is complete in number of i_clk cycles.
-- 3 would give a slave 3 clock cycles to perform
-- the needed operation.
)
port map (
-- clock and resets
i_clk => clk50m,
i_srst => srst,
-- db master cmd interface
i_db_cmd_in => db_cmd,
i_db_cmd_wstrb => db_cmd_wstrb,
o_db_cmd_rdy => db_cmd_rdy,
i_db_cmd_data_in => db_cmd_wr_data,
o_db_cmd_data_out => db_cmd_rd_data,
-- data bus interface
o_db_addr => db_addr,
o_db_write_data => db_wr_data,
i_db_read_data => db_rd_data,
o_db_read_strb => db_rd_strb,
o_db_write_strb => db_wr_strb
);
-- generate synchronious reset signal for
-- synchronious blocks
rst_sync : process( clk50m )
begin
if ( rising_edge(clk50m) ) then
if ( rst_n = '0' ) then
-- reset active
srst <= '1';
-- for now, just hardcode the nco rate at startup
-- 0x1AE ~= 10 Hz rate.. (10.0117176818 Hz)
-- freq = (nco_ftw / 2^31-1)*50e6
-- nco_ftw = ( Freq / 50e6 ) * (2^31-1)
-- nco_ftw <= x"000001AE";
else
srst <= '0';
end if;
end if;
end process;
spi_master_1 : spi_master
generic map (
-- default address for this module to use..
data_reg_addr => "0000000", -- address 0
conf_reg_addr => "0000001", -- address 1
baud_reg_addr => "0000010" -- address 2
)
port map (
i_clk => clk50m,
i_srst => srst,
-- spi interface
o_spi_sclk => spi1_sclk,
o_spi_mosi => spi1_mosi,
i_spi_miso => spi1_miso,
o_spi_cs_n => spi1_cs_n,
-- data bus interface
i_db_addr => db_addr,
i_db_wr_strb => db_wr_strb,
i_db_rd_strb => db_rd_strb,
i_db_wr_data => db_wr_data,
o_db_rd_data => db_rd_data
);
-- simple data bus slave to control LEDs on address 3
led_ctrl : process( clk50m )
begin
if ( rising_edge( clk50m ) ) then
if ( srst = '1' ) then
led_reg <= (others=>'0');
else
if ( db_wr_strb = '1' ) then
-- if address 0x03
if ( db_addr = "0000011" ) then
led_reg <= db_wr_data;
end if;
end if;
if ( db_rd_strb = '1' ) then
if ( db_addr = "0000011" ) then
db_rd_data <= led_reg;
end if;
else
db_rd_data <= (others=>'Z');
end if;
end if;
end if;
end process;
end architecture;
| apache-2.0 | d37c80d3c5269f04da797177d679b4b7 | 0.456851 | 3.798091 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/nexys4d/sys_conf.vhd | 1 | 2,008 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_nexys4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | de9b4d2fa24ccf5766aa241c69af4318 | 0.616534 | 3.684404 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_sres_or_4.vhd | 1 | 2,362 | -- $Id: ib_sres_or_4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_4 - syn
-- Description: ibus: result or, 4 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_4;
architecture syn of ib_sres_or_4 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack or
IB_SRES_4.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy or
IB_SRES_4.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout or
IB_SRES_4.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 85a77387515b2167d0711d5f64e20a29 | 0.49619 | 3.136786 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/tb_artys7.vhd | 1 | 4,799 | -- $Id: tb_artys7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_artys7 - sim
-- Description: Test bench for artys7 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_basys3_core
-- serport/tb/serport_master_tb
-- artys7_aif [UUT]
--
-- To test: generic, any artys7_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2018-08-05 1038 1.0 Initial version (derived from tb_artya7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artys7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_artys7 is
end tb_artys7;
architecture sim of tb_artys7 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYS7CORE : entity work.tb_artys7_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : artys7_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most artys7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 1a11eba92b36b02387d3358ece13c2a5 | 0.541154 | 3.455004 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dmpcnt.vhd | 1 | 12,206 | -- $Id: pdp11_dmpcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmpcnt - syn
-- Description: pdp11: debug&moni: performance counters
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2-2019.1; ghdl 0.34-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-09-23 1050 14.7 131013 xc6slx16-2 250 337 20 121 s 6.5
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2018-09-29 1051 1.0 Initial version
-- 2018-09-23 1050 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 cntl -/w/f Control register
-- 15 ainc -/w/- enable address autoinc
-- 13:09 caddr -/w/- counter address
-- 07:00 vers r/-/- counter layout version
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start
-- 110 clr clear
-- 111 loa load caddr
-- 01 stat r/-/- Status register
-- 15 ainc r/-/- enable address autoinc
-- 13:09 caddr r/-/- counter address
-- 08 waddr r/-/- word address
-- 00 run r/-/- running
-- 10 data r/-/- Data register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmpcnt_precnt is -- pre-counter
port (
CLK : in slbit; -- clock
CLR : in slbit; -- clear
ENA : in slbit; -- count
DOUT : out slv5 -- data
);
end pdp11_dmpcnt_precnt;
architecture syn of pdp11_dmpcnt_precnt is
signal R_CNT : slv5 := (others=>'0');
begin
proc_cnt: process (CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
R_CNT <= (others=>'0');
else
if ENA = '1' then
R_CNT <= slv(unsigned(R_CNT) + 1);
end if;
end if;
end if;
end process proc_cnt;
DOUT <= R_CNT;
end syn;
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
entity pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(1, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
PERFSIG : in slv32 -- signals to count
);
end pdp11_dmpcnt;
architecture syn of pdp11_dmpcnt is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_stat : slv2 := "01"; -- stat address offset
constant rbaddr_data : slv2 := "10"; -- data address offset
constant cntl_rbf_ainc : integer := 15;
subtype cntl_rbf_caddr is integer range 13 downto 9;
subtype cntl_rbf_vers is integer range 7 downto 0;
subtype cntl_rbf_func is integer range 2 downto 0;
constant stat_rbf_ainc : integer := 15;
subtype stat_rbf_caddr is integer range 13 downto 9;
constant stat_rbf_waddr : integer := 8;
constant stat_rbf_run : integer := 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_clr : slv3 := "110"; -- func: clear
constant func_loa : slv3 := "111"; -- func: load
type regs_type is record
rbsel : slbit; -- rbus select
run : slbit; -- run flag
saddr : slv5; -- scan address
raddr : slv5; -- read address (counter)
waddr : slbit; -- read address (word)
ainc : slbit; -- enable ddress autoinc
zbusy : slbit; -- clear in progress
dval : slbit; -- data valid
dout : slv32; -- read data (valid if dval=1)
psig : slv32; -- signals, floped
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- rbsel,run
(others=>'0'), -- saddr
(others=>'0'), -- raddr
'0','0','0','0', -- waddr,ainc,zbusy,dval
(others=>'0'), -- dout
(others=>'0') -- psig
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
type pre_do_type is array (31 downto 0) of slv5;
signal PRE_CLR : slv32 := (others=>'0');
signal PRE_DO : pre_do_type := (others=> (others => '0'));
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
begin
MEM : ram_1swar_gen
generic map (
AWIDTH => 5,
DWIDTH => 32)
port map (
CLK => CLK,
WE => '1',
ADDR => R_REGS.saddr,
DI => MEM_DI,
DO => MEM_DO
);
PRE: for i in 31 downto 0 generate
ENA: if CENA(i)='1' generate
CNT : entity work.pdp11_dmpcnt_precnt
port map (
CLK => CLK,
CLR => PRE_CLR(i),
ENA => R_REGS.psig(i),
DOUT => PRE_DO(i)
);
end generate ENA;
end generate PRE;
proc_cnt: process (R_REGS, PRE_DO, MEM_DO)
variable iclr : slv32 := (others=>'0');
variable ipdo : slv32 := (others=>'0');
variable icnt : slv32 := (others=>'0');
variable imdi : slv32 := (others=>'0');
constant ipdo_pad : slv(31 downto 5) := (others=>'0');
constant icnt_pad : slv(31 downto 1) := (others=>'0');
begin
iclr := (others=>'0');
iclr(to_integer(unsigned(R_REGS.saddr))) := '1';
ipdo := ipdo_pad & PRE_DO(to_integer(unsigned(R_REGS.saddr)));
icnt := icnt_pad & R_REGS.psig(to_integer(unsigned(R_REGS.saddr)));
PRE_CLR <= iclr;
if R_REGS.zbusy = '0' then
imdi := slv(unsigned(MEM_DO) + unsigned(ipdo) + unsigned(icnt));
else
imdi := (others=>'0');
end if;
MEM_DI <= imdi;
end process proc_cnt;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, PERFSIG, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
end if;
if r.run = '1' then -- if running
n.psig := PERFSIG; -- capture performance signals
else
n.psig := (others=>'0'); -- otherwise ignore them
end if;
n.saddr := slv(unsigned(r.saddr) + 1); -- scan counter (always running)
-- capture data in dout buffer if scan=read address and looking at lsb and
-- if either data not valid or no rbus cycle active. this ensures that
-- dval waits end, and also that data isn't changing during rbus active.
if r.saddr = r.raddr and r.waddr = '0' and
(r.dval='0' or r.rbsel='0') then
n.dout := MEM_DO; -- capture data
n.dval := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.run := '0';
when func_sta => -- func: start -----------
n.run := '1';
when func_clr => -- func: clear -----------
n.run := '0';
if r.zbusy = '0' then
n.zbusy := '1';
n.saddr := (others=>'0');
n.raddr := (others=>'0');
n.waddr := '0';
n.ainc := '0';
irb_busy := '1';
else
if r.saddr = "11111" then
n.zbusy := '0';
n.dval := '0';
else
irb_busy := '1';
end if;
end if;
when func_loa => -- func: load ------------
n.ainc := RB_MREQ.din(cntl_rbf_ainc);
n.raddr := RB_MREQ.din(cntl_rbf_caddr);
n.waddr := '0';
n.dval := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => -- stat ------------------
irb_err := RB_MREQ.we;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1'; -- error
end if;
if RB_MREQ.re = '1' then
if r.dval = '0' then
irb_busy := '1';
else
n.waddr := not r.waddr;
if r.ainc='1' and r.waddr = '1' then -- autoinc and wrap ?
n.raddr := slv(unsigned(r.raddr) + 1);
n.dval := '0';
end if;
end if;
end if;
when others => irb_err := '1'; -- <> --------------------
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => null; -- cntl ------------------
irb_dout(cntl_rbf_vers) := VERS;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_ainc) := r.ainc;
irb_dout(stat_rbf_caddr) := r.raddr;
irb_dout(stat_rbf_waddr) := r.waddr;
irb_dout(stat_rbf_run) := r.run;
when rbaddr_data => -- data ------------------
if r.waddr = '0' then
irb_dout := r.dout(15 downto 0);
else
irb_dout := r.dout(31 downto 16);
end if;
when others => null;
end case;
end if;
N_REGS <= n;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 21345f9ebf553e2b8e340549d10eaa59 | 0.449697 | 3.76496 | false | false | false | false |
nsensfel/tabellion | data/test/combinational_processes/valid_unsupported.vhd | 1 | 1,492 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of valid is
signal s0, s1, s2, s3 : std_logic;
begin
-- Add some vectors.
-- Add some enums.
s0 <= s1;
s0 <= (s1 and s2);
process (s0, s1)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
process (s0, s1)
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
process (s0, s1)
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
process (s0, s1, s2)
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op0 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
with ip0 select
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
end;
| apache-2.0 | 9aa75063872ea1c27f127a6041313b01 | 0.396113 | 3.167728 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02000_good.vhd | 1 | 4,706 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02000_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of Finite State Machine: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_02000_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_02000_good;
architecture Behavioral of CNE_02000_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
--CODE
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
--CODE
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
sm_State <= init;
elsif (rising_edge(i_Clock)) then
case sm_State is
when init =>
-- Set the length value
Length <= c_Length;
sm_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
sm_State <= Enabled;
else
Enable <= '0';
sm_State <= finished;
end if;
when others =>
sm_State <= init;
end case;
end if;
end process;
end Behavioral; | gpl-3.0 | f9e51438c2a4aa4a5a955b8d685f3325 | 0.474713 | 4.797146 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bpgenrbuslib.vhd | 1 | 6,141 | -- $Id: bpgenrbuslib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: bpgenrbuslib
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4-2019.1; ghdl 0.26-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.3.2 add sn_humanio_emu_rbus
-- 2017-06-05 907 1.3.1 rgbdrv_analog_rbus: add ACTLOW generic
-- 2016-02-20 734 1.3 add rgbdrv_analog_rbus
-- 2015-01-25 637 1.2 add generics to sn_humanio_rbus
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package bpgenrbuslib is
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component sn_humanio_emu_rbus is -- sn_humanio rbus emulator
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points
);
end component;
component rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'; -- invert output polarity
RB_ADDR : slv16 := x"0000");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
end package bpgenrbuslib;
| gpl-3.0 | 1956ed9c963b2659b87a244de0eab182 | 0.529718 | 3.699398 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vhd | 1 | 5,784 | -- $Id: pdp11_hio70_artys7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_hio70_artys7 - syn
-- Description: pdp11: hio led and rgb for sys70 for artys7
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2018-08-05 1038 1.0 Initial version (cloned from pdp11_hio70_artya7)
------------------------------------------------------------------------------
--
-- collects the output for LED and RGB leds
-- MODE = 00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with y=1)
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with y=1)
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with x=1)
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- MODE = 0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
-- MODE = 1xyy (show lsb or msb of 16 bit register)
-- LED show bit 7:4, RGB_G bit 1:0; x=0 shows lsb and x=1 shows msb
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_hio70_artys7 is -- hio led+rgb for sys70 for artys7
port (
CLK : in slbit; -- clock
MODE : in slv4; -- mode select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
LED : out slv4; -- hio leds
RGB_R : out slv2; -- hio rgb leds - red
RGB_G : out slv2; -- hio rgb leds - green
RGB_B : out slv2 -- hio rgb leds - blue
);
end pdp11_hio70_artys7;
architecture syn of pdp11_hio70_artys7 is
signal R_LED : slv4 := (others=>'0');
signal R_RGB_R : slv2 := (others=>'0');
signal R_RGB_G : slv2 := (others=>'0');
signal R_RGB_B : slv2 := (others=>'0');
begin
proc_regs : process (CLK)
variable idat16 : slv16 := (others=>'0');
variable idat8 : slv8 := (others=>'0');
variable iled : slv4 := (others=>'0');
variable irgb_r : slv2 := (others=>'0');
variable irgb_g : slv2 := (others=>'0');
variable irgb_b : slv2 := (others=>'0');
begin
if rising_edge(CLK) then
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
if MODE(2) = '0' then
idat8 := idat16( 7 downto 0);
else
idat8 := idat16(15 downto 8);
end if;
iled := (others=>'0');
irgb_r := (others=>'0');
irgb_g := (others=>'0');
irgb_b := (others=>'0');
if MODE(3) = '0' then
if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM
iled := IOLEDS;
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
irgb_g(1) := '1';
end if;
when c_psw_smode =>
irgb_g(0) := '1';
when c_psw_umode =>
irgb_g(0) := '1';
when others => null;
end case;
else
irgb_r(1 downto 0) := CP_STAT.cpurust(1 downto 0);
end if;
end if; -- MODE(0) = '1'
if MODE(1) = '1' then
irgb_b(1) := CP_STAT.cmdbusy;
irgb_b(0) := not CP_STAT.cpugo;
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc( 9 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 5 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 1 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs
iled := idat8(7 downto 4);
irgb_g := idat8(1 downto 0);
end if; -- MODE(3) = '0'
R_LED <= iled;
R_RGB_R <= irgb_r;
R_RGB_G <= irgb_g;
R_RGB_B <= irgb_b;
end if;
end process proc_regs;
LED <= R_LED;
RGB_R <= R_RGB_R;
RGB_G <= R_RGB_G;
RGB_B <= R_RGB_B;
end syn;
| gpl-3.0 | 58195e0fe7f501bfd0c38e469bca6825 | 0.46473 | 3.386417 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/fifo_simple_dram.vhd | 1 | 5,533 | -- $Id: fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_simple_dram - syn
-- Description: FIFO, CE/WE interface, distributed RAM based
--
-- Dependencies: ram_1swar_gen
--
-- Test bench: tb/tb_fifo_simple_dram
-- Target Devices: generic Spartan, Artix
-- Tool versions: ise 14.7; viv 2017.2-2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end fifo_simple_dram;
architecture syn of fifo_simple_dram is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
signal RAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
RAM : ram_1swar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDR => RAM_ADDR,
DI => DI,
DO => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CE, WE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iram_we : slbit := '0';
variable iram_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iram_we := '0';
if WE = '1' then -- select RAM address
iram_addr := r.waddr; -- for write
else
iram_addr := r.raddr; -- for read
end if;
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
if CE = '1' then -- do read or write
if WE = '1' then -- do write
if r.full = '0' then -- only if not full
iram_we := '1'; -- assert write enable
n.waddr := slv(unsigned(r.waddr) + 1); -- advance address
n.empty := '0'; -- can't be empty after write
if unsigned(isize) = memsize-2 then -- check for full
n.full := '1';
end if;
end if;
else -- do read
if r.empty = '0' then -- only if not empty
n.raddr := slv(unsigned(r.raddr) + 1); -- advance address
n.full := '0'; -- can't be full after read
if unsigned(isize) = 1 then -- check for empty
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_ADDR <= iram_addr;
RAM_WE <= iram_we;
EMPTY <= r.empty;
FULL <= r.full;
SIZE <= isize;
end process proc_next;
-- synthesis translate_off
proc_moni: process (CLK)
variable oline : line;
begin
if rising_edge(CLK) then
if RESET='0' and CE='1' then -- not in reset and active
if WE = '0' then
if R_REGS.empty='1' then -- read on empty fifo
write(oline, now, right, 12);
write(oline, string'(" read on empty fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
else
if R_REGS.full='1' then -- write on full fifo
write(oline, now, right, 12);
write(oline, string'(" write on full fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
end if;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;
| gpl-3.0 | 9e71dee1a75c7013a47f01800ac75618 | 0.495391 | 3.815862 | false | false | false | false |
marcoep/LogicAnalyzerNano | LogicAnalyzerTLD.vhd | 1 | 2,097 | -------------------------------------------------------------------------------
-- Title : LogicAnalyzer Top Level Design
-- Project :
-------------------------------------------------------------------------------
-- File : LogicAnalyzer.vhd
-- Author : <Marco@JUDI>
-- Company :
-- Created : 2014-11-27
-- Last update: 2014-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top Level Design for a Logic Analyzer in VHDL for the DE0nano
-- Board from Terasic.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-27 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LogicAnalyzerTLD is
port (
CLOCK_50 : in std_logic;
LED : out std_logic_vector(7 downto 0);
KEY : in std_logic_vector(1 downto 0);
GPIO : in std_logic_vector(33 downto 0);
GPIO_IN : in std_logic_vector(1 downto 0));
end entity LogicAnalyzerTLD;
architecture Behavioral of LogicAnalyzerTLD is
component LogicAnalyzer is
port (
Clk_CI : in std_logic;
Reset_RBI : in std_logic;
BusDI_DI : in std_logic;
BusDO_DI : in std_logic;
BusCS_DI : in std_logic;
BusClk_SI : in std_logic;
Led_SO : out std_logic;
Btn_SI : in std_logic);
end component LogicAnalyzer;
begin -- architecture Behavioral
LogicAnalyzer_1: entity work.LogicAnalyzer
port map (
Clk_CI => CLOCK_50,
Reset_RBI => KEY(0),
BusDI_DI => GPIO(4),
BusDO_DI => GPIO(2),
BusCS_DI => GPIO_IN(1),
BusClk_SI => GPIO_IN(0),
Led_SO => LED(0),
Btn_SI => not KEY(1));
LED(7 downto 1) <= "0000000";
end architecture Behavioral;
| mit | 75dd71f5930475ece7d928ea6cd3a86c | 0.460181 | 4.127953 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_lunit.vhd | 1 | 6,384 | -- $Id: pdp11_lunit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_lunit - syn
-- Description: pdp11: logic unit for data (lunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-10 581 1.1.2 use c_cc_f_*
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from lbox
-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_lunit;
architecture syn of pdp11_lunit is
-- --------------------------------------
begin
process (DSRC, DDST, CCIN, FUNC, BYTOP)
variable iout : slv16 := (others=>'0');
variable inzstd : slbit := '0';
variable ino : slbit := '0';
variable izo : slbit := '0';
variable ivo : slbit := '0';
variable ico : slbit := '0';
alias DSRC_L : slv8 is DSRC(7 downto 0);
alias DSRC_H : slv8 is DSRC(15 downto 8);
alias DDST_L : slv8 is DDST(7 downto 0);
alias DDST_H : slv8 is DDST(15 downto 8);
alias NI : slbit is CCIN(c_cc_f_n);
alias ZI : slbit is CCIN(c_cc_f_z);
alias VI : slbit is CCIN(c_cc_f_v);
alias CI : slbit is CCIN(c_cc_f_c);
alias iout_l : slv8 is iout(7 downto 0);
alias iout_h : slv8 is iout(15 downto 8);
begin
iout := (others=>'0');
inzstd := '1'; -- use standard logic by default
ino := '0';
izo := '0';
ivo := '0';
ico := '0';
--
-- the decoding of FUNC is done "manually" to get a structure based on
-- a 8->1 pattern. This matches the opcode structure and seems most
-- efficient.
--
if FUNC(3) = '0' then
if BYTOP = '0' then
case FUNC(2 downto 0) is
when "000" => -- ASR
iout := DDST(15) & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "001" => -- ASL
iout := DDST(14 downto 0) & '0';
ico := DDST(15);
ivo := iout(15) xor ico;
when "010" => -- ROR
iout := CI & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
when "011" => -- ROL
iout := DDST(14 downto 0) & CI;
ico := DDST(15);
ivo := iout(15) xor ico;
when "100" => -- BIS
iout := DDST or DSRC;
ico := CI;
when "101" => -- BIC
iout := DDST and not DSRC;
ico := CI;
when "110" => -- BIT
iout := DDST and DSRC;
ico := CI;
when "111" => -- MOV
iout := DSRC;
ico := CI;
when others => null;
end case;
else
case FUNC(2 downto 0) is
when "000" => -- ASRB
iout_l := DDST_L(7) & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "001" => -- ASLB
iout_l := DDST(6 downto 0) & '0';
ico := DDST(7);
ivo := iout_l(7) xor ico;
when "010" => -- RORB
iout_l := CI & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
when "011" => -- ROLB
iout_l := DDST_L(6 downto 0) & CI;
ico := DDST_L(7);
ivo := iout_l(7) xor ico;
when "100" => -- BISB
iout_l := DDST_L or DSRC_L;
ico := CI;
when "101" => -- BICB
iout_l := DDST_L and not DSRC_L;
ico := CI;
when "110" => -- BITB
iout_l := DDST_L and DSRC_L;
ico := CI;
when "111" => -- MOVB
iout_l := DSRC_L;
iout_h := (others=>DSRC_L(7));
ico := CI;
when others => null;
end case;
end if;
else
case FUNC(2 downto 0) is
when "000" => -- SXT
iout := (others=>NI);
inzstd := '0';
ino := NI;
izo := not NI;
ivo := '0';
ico := CI;
when "001" => -- SWAP
iout := DDST_L & DDST_H;
inzstd := '0';
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
when "010" => -- XOR
iout := DDST xor DSRC;
ico := CI;
when others => null;
end case;
end if;
DOUT <= iout;
if inzstd = '1' then
if BYTOP = '1' then
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
else
ino := iout(15);
if unsigned(iout) = 0 then
izo := '1';
else
izo := '0';
end if;
end if;
end if;
CCOUT(3) <= ino;
CCOUT(2) <= izo;
CCOUT(1) <= ivo;
CCOUT(0) <= ico;
end process;
end syn;
| gpl-3.0 | bff69450e2ebb3121efdc9bdc981ce7f | 0.411654 | 3.753086 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | memData_inst.vhd | 1 | 165 | --memData_inst : memData PORT MAP (
-- address => address_sig,
-- clock => clock_sig,
-- data => data_sig,
-- wren => wren_sig,
-- q => q_sig
-- );
| mit | ae7d67c10c42e30db391203d388955f7 | 0.49697 | 2.2 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd | 1 | 2,498 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2013-09-28 535 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- single clock design, clkser = clksys
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide;
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply;
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide;
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | b424ca84bbdfeeac826d87b0c95116a9 | 0.594876 | 3.921507 | false | true | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd | 1 | 12,029 | -- $Id: sys_tst_rlink_cuff_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n2 - syn
-- Description: rlink tester design for nexys2 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 1023 2160 192 1486 p 16.0 ic2/ 50
-- 2013-01-04 469 13.3 O76d xc3s1200e-4 846 1798 160 1215 p 16.3 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50
-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-25 638 1.1.2 retire fx2_2fifoctl_as
-- 2014-12-24 620 1.1.1 relocate hio rbus address
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2
-- the now obsoleted sys_tst_rlink_n2_cuff design
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (1) timer 1 busy
-- (0) timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back pressure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n2;
architecture syn of sys_tst_rlink_cuff_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 08479318618947eb7bdb1ba282316920 | 0.491895 | 3.053821 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_1clock.vhd | 1 | 8,176 | -- $Id: serport_1clock.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR
-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud;
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.memlib.all;
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal ABCLKDIV_F : slv3 := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV,
ABCLKDIV_F => ABCLKDIV_F
);
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back pressure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV, ABCLKDIV_F)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
MONI.abclkdiv_f <= ABCLKDIV_F;
end process proc_abclkdiv;
-- synthesis translate_off
proc_check: process (CLK)
begin
if rising_edge(CLK) then
assert RXOVR = '0'
report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) &
"; data loss in receive fifo"
severity warning;
assert RXERR = '0'
report "serport_1clock-W: RXERR = " & slbit'image(RXERR) &
"; spurious receive error"
severity warning;
end if;
end process proc_check;
-- synthesis translate_on
end syn;
| gpl-3.0 | 1d943f0ceb01ea99edd988007044aa1c | 0.534736 | 3.689531 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_basic_soc_xtea_tb.vhd | 1 | 11,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 15;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
signal ext_periph, ext_periph_dly, ready: std_logic;
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
signal data_read_xtea, data_read_xtea_s: std_logic_vector(31 downto 0);
signal control: std_logic_vector(1 downto 0);
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 100 us;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
ext_periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
ext_periph_dly <= ext_periph;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 24) = x"e1" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
data_read_xtea <= data_read_xtea_s(7 downto 0) & data_read_xtea_s(15 downto 8) & data_read_xtea_s(23 downto 16) & data_read_xtea_s(31 downto 24);
ext_periph <= '1' when address(31 downto 24) = x"e7" else '0';
process (clock_in, reset, address, key, input, output)
begin
if reset = '1' then
data_read_xtea_s <= (others => '0');
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1') then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea_s <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xe7000010
data_read_xtea_s <= key(127 downto 96);
when "0010" => -- key[1] 0xe7000020
data_read_xtea_s <= key(95 downto 64);
when "0011" => -- key[2] 0xe7000030
data_read_xtea_s <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea_s <= key(31 downto 0);
when "0101" => -- input[0] 0xe7000050
data_read_xtea_s <= input(63 downto 32);
when "0110" => -- input[1] 0xe7000060
data_read_xtea_s <= input(31 downto 0);
when "0111" => -- output[0] 0xe7000070
data_read_xtea_s <= output(63 downto 32);
when "1000" => -- output[1] 0xe7000080
data_read_xtea_s <= output(31 downto 0);
when others =>
data_read_xtea_s <= (others => '0');
end case;
end if;
end if;
end process;
process (clock_in, reset, address, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
input <= (others => '0');
control <= "00";
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write_periph(1 downto 0);
when "0001" => -- key[0] 0xe7000010
key(127 downto 96) <= data_write_periph;
when "0010" => -- key[1] 0xe7000020
key(95 downto 64) <= data_write_periph;
when "0011" => -- key[2] 0xe7000030
key(63 downto 32) <= data_write_periph;
when "0100" => -- key[3] 0xe7000040
key(31 downto 0) <= data_write_periph;
when "0101" => -- input[0] 0xe7000050
input(63 downto 32) <= data_write_periph;
when "0110" => -- input[1] 0xe7000060
input(31 downto 0) <= data_write_periph;
when others =>
end case;
end if;
end if;
end process;
-- XTEA core
crypto_core: entity work.xtea
port map( clock => clock_in,
reset => reset,
start => control(0),
encrypt => control(1),
key => key,
input => input,
output => output,
ready => ready
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | d4734cd6532b098974f647a168dd82ae | 0.590905 | 2.727744 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2_basic_soc_xtea.vhd | 1 | 8,138 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal ext_periph, ext_periph_dly, ready: std_logic;
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
signal data_read_xtea, data_read_xtea_s: std_logic_vector(31 downto 0);
signal control: std_logic_vector(1 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
ext_periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
ext_periph_dly <= ext_periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 24) = x"e1" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
data_read_xtea <= data_read_xtea_s(7 downto 0) & data_read_xtea_s(15 downto 8) & data_read_xtea_s(23 downto 16) & data_read_xtea_s(31 downto 24);
ext_periph <= '1' when address(31 downto 24) = x"e7" else '0';
process (clock, reset, address, key, input, output)
begin
if reset = '1' then
data_read_xtea_s <= (others => '0');
elsif clock'event and clock = '1' then
if (ext_periph = '1') then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea_s <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xe7000010
data_read_xtea_s <= key(127 downto 96);
when "0010" => -- key[1] 0xe7000020
data_read_xtea_s <= key(95 downto 64);
when "0011" => -- key[2] 0xe7000030
data_read_xtea_s <= key(63 downto 32);
when "0100" => -- key[3] 0xe7000040
data_read_xtea_s <= key(31 downto 0);
when "0101" => -- input[0] 0xe7000050
data_read_xtea_s <= input(63 downto 32);
when "0110" => -- input[1] 0xe7000060
data_read_xtea_s <= input(31 downto 0);
when "0111" => -- output[0] 0xe7000070
data_read_xtea_s <= output(63 downto 32);
when "1000" => -- output[1] 0xe7000080
data_read_xtea_s <= output(31 downto 0);
when others =>
data_read_xtea_s <= (others => '0');
end case;
end if;
end if;
end process;
process (clock, reset, address, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
input <= (others => '0');
control <= "00";
elsif clock'event and clock = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write_periph(1 downto 0);
when "0001" => -- key[0] 0xe7000010
key(127 downto 96) <= data_write_periph;
when "0010" => -- key[1] 0xe7000020
key(95 downto 64) <= data_write_periph;
when "0011" => -- key[2] 0xe7000030
key(63 downto 32) <= data_write_periph;
when "0100" => -- key[3] 0xe7000040
key(31 downto 0) <= data_write_periph;
when "0101" => -- input[0] 0xe7000050
input(63 downto 32) <= data_write_periph;
when "0110" => -- input[1] 0xe7000060
input(31 downto 0) <= data_write_periph;
when others =>
end case;
end if;
end if;
end process;
-- XTEA core
crypto_core: entity work.xtea
port map( clock => clock,
reset => reset,
start => control(0),
encrypt => control(1),
key => key,
input => input,
output => output,
ready => ready
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | a8d473ac6eb7fb0706e20b5c6d4cef5f | 0.617965 | 2.650814 | false | false | false | false |
wfjm/w11 | rtl/bplib/micron/mt45w8mw16b.vhd | 1 | 11,995 | -- $Id: mt45w8mw16b.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: mt45w8mw16b - sim
-- Description: Micron MT45W8MW16B CellularRAM model
-- Currently a much simplified model
-- - only async accesses
-- - ignores CLK
-- - simple model for response of DATA lines, but no
-- check for timing violations of control lines
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.4.1 remove 'assert false' from report statements
-- 2016-07-10 786 1.4 add RCR handling; page mode by default now off !!
-- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
-- 2010-05-21 293 1.1 add BCR (only read of default so far)
-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Asynchronous Mode (BCR(15)=1)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Read L L L L H L L act data-out
-- Write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- CRE write L L L H L H X act 'z'
-- CRE read L L L L H H L act conf-out
--
-- Burst Mode (BCR(15)=0)
-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
-- Async read L L L L H L L act data-out
-- Async write L L L X L L L act data-in
-- Standby L X H X X L X 'z' 'z'
-- Initial burst read 0-1 L L X H L L act X
-- Initial burst write 0-1 L L H L L X act X
-- Burst continue 0-1 H L X X X X act data-in/out
-- CRE write 0-1 L L H L H X act 'z'
-- CRE read 0-1 L L L H H L act conf-out
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model
port (
CLK : in slbit; -- clock for synchonous operation
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADV_N : in slbit; -- address valid (act.low)
CRE : in slbit; -- control register enable
MWAIT : out slbit; -- wait (for burst read/write)
ADDR : in slv23; -- address lines
DATA : inout slv16 -- data lines
);
end mt45w8mw16b;
architecture sim of mt45w8mw16b is
-- timing constants for -701 speed grade (70 ns; 104 MHz)
constant T_aa : Delay_length := 70 ns; -- address access time (max)
constant T_apa : Delay_length := 20 ns; -- page access time (max)
constant T_oh : Delay_length := 5 ns; -- output hold from addr change (max)
constant T_oe : Delay_length := 20 ns; -- output enable to valid output (max)
constant T_ohz : Delay_length := 8 ns; -- output disable to high-z out (max)
constant T_olz : Delay_length := 3 ns; -- output enable to low-z output (min)
constant T_lz : Delay_length := 10 ns; -- chip enable to low-z output (min)
constant T_hz : Delay_length := 8 ns; -- chip disable to high-z output (max)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
subtype xcr_f_sel is integer range 19 downto 18; -- cre register select
constant xcr_sel_rcr : slv2 := "00";
constant xcr_sel_bcr : slv2 := "10";
constant bcr_f_mode : integer := 15; -- operating mode
constant bcr_f_ilat : integer := 14; -- initial latency
subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
constant bcr_f_wp : integer := 10; -- wait polarity
constant bcr_f_wc : integer := 8; -- wait configuration
subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
constant bcr_f_bw : integer := 3; -- burst wrap
subtype bcr_f_bl is integer range 2 downto 0; -- burst length
subtype rcr_f_res3 is integer range 22 downto 20; -- reserved - MBZ
subtype rcr_f_res2 is integer range 17 downto 8; -- reserved - MBZ
constant rcr_f_pmode : integer := 7; -- page mode (1=ena)
subtype rcr_f_res1 is integer range 6 downto 5; -- reserved - MBZ
constant rcr_f_dpd : integer := 4; -- dpd mode (1=dis)
constant rcr_f_res0 : integer := 3; -- reserved - MBZ
subtype rcr_f_par is integer range 2 downto 0; -- array conf (000=all)
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
signal ADV : slbit := '0';
signal WE_L_EFF : slbit := '0';
signal WE_U_EFF : slbit := '0';
signal WE_C_EFF : slbit := '0';
signal R_BCR_MODE : slbit := '1'; -- mode: def: async
signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
signal R_BCR_WP : slbit := '1'; -- wp: def: active high
signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
signal R_RCR_PMODE : slbit := '0'; -- pmode:def: disabled (ena=1 !)
signal R_RCR_DPD : slbit := '1'; -- dpd: def: disabled (ena=0 !)
signal R_RCR_PAR : slv3 := "000"; -- par: def: full array
signal R_T_APA_EFF : Delay_length := T_aa; -- page mode disabled by default
signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access
signal DOUT_VAL_EN : slbit := '0';
signal DOUT_VAL_AA : slbit := '0';
signal DOUT_VAL_PA : slbit := '0';
signal DOUT_VAL_OE : slbit := '0';
signal DOUT_LZ_CE : slbit := '0';
signal DOUT_LZ_OE : slbit := '0';
signal OEWE : slbit := '0';
signal DOUT : slv16 := (others=>'0');
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
ADV <= not ADV_N;
WE_L_EFF <= CE and WE and BE_L and (not CRE);
WE_U_EFF <= CE and WE and BE_U and (not CRE);
WE_C_EFF <= CE and WE and CRE;
-- address valid logic, latch ADDR when ADV true
proc_adv: process (ADV, ADDR)
begin
if ADV = '1' then
L_ADDR <= ADDR;
end if;
end process proc_adv;
-- Notes:
-- 1. the row change (t_aa) and column change (t_apa) timing depends on the
-- recognition of address changes and of page changes. To keep the logic
-- simple L_ADDR and addr_last are initialized with all '1'. This gives
-- proper behaviour unless the very first access uses the very last
-- address. In w11a systems, with use only 4 MB, this can't happen, in
-- most other use cases this is very unlikely.
proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
variable addr_last : slv23 := (others=>'1');-- all '1' for propper 1st access
begin
if (CE'event and CE='1') or
(BE_L'event and BE_L='1') or
(BE_U'event and BE_U='1') or
(WE'event and WE='0') or
(ADV'event and ADV='1') then
DOUT_VAL_EN <= '0', '1' after T_aa;
end if;
if L_ADDR'event then
DOUT_VAL_PA <= '0', '1' after R_T_APA_EFF;
if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
DOUT_VAL_AA <= '0', '1' after T_aa;
end if;
addr_last := L_ADDR;
end if;
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
-- to simplify things assume that OE and (not WE) have same effect on output
-- drivers. The timing rules are very similar indeed...
OEWE <= OE and (not WE);
proc_dout_lz: process (CE, OEWE)
begin
if (CE'event) then
if CE = '1' then
DOUT_LZ_CE <= '1' after T_lz;
else
DOUT_LZ_CE <= '0' after T_hz;
end if;
end if;
if (OEwe'event) then
if OEWE = '1' then
DOUT_LZ_OE <= '1' after T_olz;
else
DOUT_LZ_OE <= '0' after T_ohz;
end if;
end if;
end process proc_dout_lz;
proc_cram: process (WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;
proc_cr: process (WE_C_EFF, L_ADDR)
begin
if falling_edge(WE_C_EFF) then
case L_ADDR(xcr_f_sel) is
when xcr_sel_rcr =>
R_RCR_PMODE <= L_ADDR(rcr_f_pmode);
if L_ADDR(rcr_f_pmode) = '1' then
R_T_APA_EFF <= T_apa;
else
R_T_APA_EFF <= T_aa;
end if;
assert L_ADDR(rcr_f_res3) = "000"
report "bad rcr write: 22:20 not zero" severity error;
assert L_ADDR(rcr_f_res2) = "0000000000"
report "bad rcr write: 17: 8 not zero" severity error;
assert L_ADDR(rcr_f_res1) = "00"
report "bad rcr write: 6: 5 not zero" severity error;
assert L_ADDR(rcr_f_dpd) = '1'
report "bad rcr write: dpd not '1'" severity error;
assert L_ADDR(rcr_f_res0) = '0'
report "bad rcr write: 3: 3 not zero" severity error;
assert L_ADDR(rcr_f_par) = "000"
report "bad rcr write: par not '000'" severity error;
when xcr_sel_bcr =>
report "bcr written - not supported" severity error;
when others =>
report "bad select field" severity error;
end case;
end if;
end process proc_cr;
proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
DOUT_LZ_CE, DOUT_LZ_OE)
variable idout : slv16 := (others=>'0');
begin
idout := DOUT;
if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or
DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then
idout := (others=>'X');
end if;
if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then
idout := (others=>'Z');
end if;
DATA <= idout;
end process proc_data;
proc_mwait: process (CE)
begin
-- WT driver (just a dummy)
if CE = '1' then
MWAIT <= '1';
else
MWAIT <= 'Z';
end if;
end process proc_mwait;
end sim;
| gpl-3.0 | bc02f0152c7ced102fd61293d03b2f90 | 0.539892 | 3.184231 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/tb_artys7_dram.vhd | 1 | 5,382 | -- $Id: tb_artys7_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_artys7_dram - sim
-- Description: Test bench for artys7 (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_artys7_core
-- serport/tb/serport_master_tb
-- artys7_dram_aif [UUT]
--
-- To test: generic, any artys7_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (derived from tb_artya7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artys7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_artys7_dram is
end tb_artys7_dram;
architecture sim of tb_artys7_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal IO_DDR3_DQ : slv16 := (others=>'Z');
signal IO_DDR3_DQS_P : slv2 := (others=>'Z');
signal IO_DDR3_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYS7CORE : entity work.tb_artys7_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : artys7_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
DDR3_DQ => IO_DDR3_DQ,
DDR3_DQS_P => IO_DDR3_DQS_P,
DDR3_DQS_N => IO_DDR3_DQS_N,
DDR3_ADDR => open,
DDR3_BA => open,
DDR3_RAS_N => open,
DDR3_CAS_N => open,
DDR3_WE_N => open,
DDR3_RESET_N => open,
DDR3_CK_P => open,
DDR3_CK_N => open,
DDR3_CKE => open,
DDR3_CS_N => open,
DDR3_DM => open,
DDR3_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most artys7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 34de272ff6d306df40ca8e524c3e8407 | 0.53233 | 3.347015 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/virtex4_ml403/virtex4ml403.vhd | 1 | 4,854 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '0') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | 93d9be2e1efc0f87a78ff86ca15697e5 | 0.629584 | 2.611081 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd | 1 | 19,892 | -- $Id: sys_w11a_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_s3 - syn
-- Description: w11a test design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- vlib/rlink/rlink_sp1c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/s3board/s3_sram_memctl
-- vlib/rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2019-05-19 1150 14.7 131013 xc3s1000-4 3019 8764 574 5558 OK: +dz11 72%
-- 2019-04-27 1140 14.7 131013 xc3s1000-4 2890 8306 524 5252 OK: +*buf 68%
-- 2019-03-02 1116 14.7 131013 xc3s1000-4 2830 8045 462 5086 OK: +ibtst 66%
-- 2019-01-27 1108 14.7 131013 xc3s1000-4 2782 7873 446 4942 OK: -iist 64%
-- 2018-10-13 1055 14.7 131013 xc3s1000-4 2890 8217 446 5177 OK: +dmpcnt 67%
-- 2018-09-15 1045 14.7 131013 xc3s1000-4 2670 7721 382 4851 OK: +KP11P 63%
-- 2017-03-04 858 14.7 131013 xc3s1000-4 2576 7471 382 4716 OK: +DEUNA 61%
-- 2017-01-29 846 14.7 131013 xc3s1000-4 2538 7355 382 4635 OK: +int24 60%
-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51%
-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51%
-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11
-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon
-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4
-- 2014-06-08 561 14.7 131013 xc3s1000-4 1374 4580 286 2776 OK: +RL11
-- 2014-06-01 558 14.7 131013 xc3s1000-4 1301 4306 270 2614 OK:
-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-16 1112 2.2.1 set BTOWIDTH 7 (was 6, must > vmbox atowidth (6))
-- 2018-10-13 1055 2.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
-- 2015-04-11 666 1.7.1 rearrange XON handling
-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
-- 2014-08-28 588 1.6 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- add pm1 rs232 (usp) support
-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
-- 2008-02-23 118 1.3.1 add _mem70
-- 2008-02-17 117 1.3 use ext. memory interface of _core;
-- use _cache + memctl or _bram (configurable)
-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
-- add _ib_mux2
-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
-- instanciate all parts directly
-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
--
-- w11a test design for s3board
-- w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
-- SWI(7:6): no function (only connected to sn_humanio_rbus)
-- (5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LEDs if SWI(3) = 1
-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_s3;
architecture syn of sys_w11a_s3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"01"; -- s3board
constant sysid_vers : slv8 := x"00";
begin
CLK <= I_CLK50; -- use 50MHz as system clock
CLKDIV : clkdivce -- usec/msec clock divider -----------
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLINK : rlink_sp1c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
SRAMCTL: s3_sram_memctl -- memory controller -----------------
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR(17 downto 0),
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | 5bddc4ec73b9bca4beac342e34867331 | 0.523477 | 2.879977 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/arty/tb/sys_conf_sim.vhd | 1 | 1,909 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 21e286bce347ff1aa6fe0f81f8fa969b | 0.608172 | 3.706796 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_sdreg.vhd | 1 | 4,396 | -- $Id: ibdr_sdreg.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_sdreg - syn
-- Description: ibus dev(rem): Switch/Display register
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 34 40 0 30 s 4.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.1 now numeric_std clean
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2008-08-22 161 1.0.4 use iblib
-- 2008-04-18 136 1.0.3 use RESET. Switch/Display not cleared by console
-- reset or reset instruction, only by cpu_reset
-- 2008-01-20 112 1.0.2 use BRESET
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- reorganize code, all in state_type/proc_next
-- 2007-12-31 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DISPREG : out slv16 -- display register
);
end ibdr_sdreg;
architecture syn of ibdr_sdreg is
constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16));
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
sreg : slv16; -- switch register
dreg : slv16; -- display register
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- sreg
(others=>'0') -- dreg
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
if IB_MREQ.racc = '0' then
idout := r.sreg; -- cpu will read switch register
else
idout := r.dreg; -- rri will read display register
end if;
end if;
-- ibus write transactions
if r.ibsel='1' and IB_MREQ.we='1' then
if IB_MREQ.racc = '0' then -- cpu will write display register
if IB_MREQ.be1 = '1' then
n.dreg(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.dreg(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
else -- rri will write switch register
n.sreg := IB_MREQ.din; -- byte write not supported
end if;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
DISPREG <= r.dreg;
end process proc_next;
end syn;
| gpl-3.0 | 80ecde0651aa33a68d75d8fdefb2cedd | 0.506369 | 3.513989 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_keeper_gen.vhd | 1 | 1,622 | -- $Id: iob_keeper_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_keeper_gen - sim
-- Description: keeper for IOB, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 299 1.1 add explicit R_KEEP and driver
-- 2008-05-22 148 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_keeper_gen;
-- Is't possible to directly use 'PAD<='H' in proc_pad. Introduced R_KEEP and
-- the explicit driver 'PAD<=R_KEEP' to state the keeper function more clearly.
architecture sim of iob_keeper_gen is
signal R_KEEP : slv(DWIDTH-1 downto 0) := (others=>'W');
begin
proc_keep: process (PAD)
begin
for i in PAD'range loop
if PAD(i) = '1' then
R_KEEP(i) <= 'H';
elsif PAD(i) = '0' then
R_KEEP(i) <= 'L';
elsif PAD(i)='X' or PAD(i)='U' then
R_KEEP(i) <= 'W';
end if;
end loop;
PAD <= R_KEEP;
end process proc_keep;
end sim;
| gpl-3.0 | 4c2bdce1bc72d418b82cb9ad76de444d | 0.546239 | 3.32377 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2_standard_soc.vhd | 1 | 4,997 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable_n, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable_n <= '0' when address(31 downto 28) = "0000" else '1';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable_n,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | a07965686208b18a3561b8cde96476fa | 0.630378 | 2.60396 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd | 1 | 5,966 | -- $Id: s7_cmt_sfs_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs - syn
-- Description: Series-7 CMT for simple frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-09-28 535 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs;
architecture syn of s7_cmt_sfs is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "MMCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
pure function bool2string (val : boolean) return string is
begin
if val then
return "TRUE";
else
return "FALSE";
end if;
end function bool2string;
begin
PLL : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => bool2string(STARTUP_WAIT))
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT : BUFG
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEPLL;
USEMMCM: if GEN_TYPE = "MMCM" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKFBOUTB_UNUSED : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT0B_UNUSED : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT1B_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT2B_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT3B_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
begin
MMCM : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT_F => real(VCO_MULTIPLY),
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => real(OUT_DIVIDE),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKFBOUT => CLKFBOUT,
CLKFBOUTB => CLKFBOUTB_UNUSED,
CLKOUT0 => CLKOUT0,
CLKOUT0B => CLKOUT0B_UNUSED,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT1B => CLKOUT1B_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT2B => CLKOUT2B_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT3B => CLKOUT3B_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT : BUFG
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEMMCM;
end syn;
| gpl-3.0 | 44b4640bde1bee7537545b61582298e1 | 0.506872 | 4.058503 | false | false | false | false |
abcsds/Micros | RS232Read_16/regserpar.vhd | 4 | 736 | library IEEE;
use IEEE.std_logic_1164.all;
entity RegSerPar is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
LDx : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end RegSerPar;
architecture simple of RegSerPar is
signal Qp, Qn: std_logic_vector(7 downto 0);
begin
COMB: process(Rx,LDx,Qp)
begin
if(LDx='0')then
Qn<= Qp;
else
Qn(7)<= Rx;
for i in 6 downto 0 loop
Qn(i)<= Qp(i+1);
end loop;
end if;
Q<= Qp;
end process COMB;
SEC: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp<= (others=>'0');
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process SEC;
end simple;
| gpl-3.0 | 0f52748fefaae3db6fe5754675747b8d | 0.554348 | 2.52921 | false | false | false | false |
sjohann81/hf-risc | mips/sim/hf-risc_basic_standard_soc_tb.vhd | 1 | 7,594 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 15;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 3 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISC core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | bc5976d6b56014a57b10da7f93b1b327 | 0.591125 | 2.70153 | false | false | false | false |
jasonpeng/cg3207-proj | DataMemory.vhd | 1 | 2,151 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity DataMemory is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- state registers
IN_EX_MM_MemWrite : in STD_LOGIC;
IN_EX_MM_MemRead : in STD_LOGIC;
-- alu related
IN_EX_MM_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_MM_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- for Writing Data to RAM
OUT_MM_WB_Data : out STD_LOGIC_VECTOR(31 downto 0)
);
end DataMemory;
architecture Behavioral of DataMemory is
type ram_type is array(0 to 31) of STD_LOGIC_VECTOR(7 downto 0);
signal ram : ram_type := (
x"00", x"00", x"00", x"00",
x"01", x"00", x"00", x"00",
x"02", x"00", x"00", x"00",
x"03", x"00", x"00", x"00",
x"04", x"00", x"00", x"00",
x"05", x"00", x"00", x"00",
x"06", x"00", x"00", x"00",
x"07", x"00", x"00", x"00" );
begin
process(CLK)
variable address : integer;
variable data : STD_LOGIC_VECTOR(31 downto 0);
variable rw : STD_LOGIC_VECTOR(1 downto 0);
begin
rw := IN_EX_MM_MemRead & IN_EX_MM_MemWrite;
address := to_integer(unsigned(IN_EX_MM_ALU_Result(4 downto 0)));
case rw is
when "01" => -- write
ram(address+3) <= IN_EX_MM_Data2(31 downto 24);
ram(address+2) <= IN_EX_MM_Data2(23 downto 16);
ram(address+1) <= IN_EX_MM_Data2(15 downto 8);
ram(address) <= IN_EX_MM_Data2(7 downto 0);
data := (others => 'Z');
when "10" => -- read
data := ram(address+3) & ram(address+2) & ram(address+1) & ram(address);
when others =>
data := (others => 'Z');
end case;
OUT_MM_WB_Data <= data;
end process;
end Behavioral; | gpl-2.0 | e251641f24435d784ef3f0d898d52db0 | 0.496048 | 3.452648 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd | 1 | 9,038 | -- $Id: sys_tst_serloop2_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n3 - syn
-- Description: Tester serial link for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-27 433 13.1 O40d xc6slx16-2 486 652 59 237 t 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0.2 add dcm monitor hack; use with ser=usr=100 MHz
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop2_n3;
architecture syn of sys_tst_serloop2_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal LED_OUT : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
-- some signals for dcm monitor hack
signal LOCKED_DCMU : slbit := '0';
signal LOCKED_DCMS : slbit := '0';
signal R_MSECU_CNT : slv10 := (others=>'0');
signal R_MSECS_CNT : slv10 := (others=>'0');
begin
DCM_U : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 2
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => LOCKED_DCMU
);
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 150 sim: 30
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 5
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLKS,
LOCKED => LOCKED_DCMS
);
CLKDIV_S : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED_OUT,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLKS,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_2clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
-- this is a hack to monitor the two dcm's
proc_msecu: process (CLK)
begin
if rising_edge(CLK) then
if CE_MSEC = '1' then
R_MSECU_CNT <= slv(unsigned(R_MSECU_CNT) + 1);
end if;
end if;
end process proc_msecu;
proc_msecs: process (CLKS)
begin
if rising_edge(CLKS) then
if CES_MSEC = '1' then
R_MSECS_CNT <= slv(unsigned(R_MSECS_CNT) + 1);
end if;
end if;
end process proc_msecs;
LED_OUT(7) <= R_MSECU_CNT(9) or (not LOCKED_DCMU);
LED_OUT(6) <= R_MSECS_CNT(9) or (not LOCKED_DCMS);
LED_OUT(5 downto 0) <= LED(5 downto 0);
end syn;
| gpl-3.0 | 0c20479c86bd3d9bc63d69d207fbf7eb | 0.483846 | 3.239427 | false | false | false | false |
sjohann81/hf-risc | devices/peripherals/standard_soc.vhd | 1 | 20,380 | -- file: standard_soc.vhd
-- description: standard SoC with peripherals
-- date: 08/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Standard SoC configuration template for prototyping. Dual GPIO ports,
-- a counter, a timer, dual UARTs and dual SPIs are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal s0cause: std_logic_vector(4 downto 0);
signal gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(15 downto 0);
signal pbddr, pbout, pbin, pbin_inv, pbin_mask: std_logic_vector(15 downto 0);
signal paaltcfg0: std_logic_vector(31 downto 0);
signal paalt: std_logic_vector(15 downto 0);
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_gpiob, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_uart: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
signal uart1_tx, uart1_rx, uart1_enable_w, uart1_enable_r, uart1_write_busy, uart1_data_avail: std_logic;
signal uart1_data_read, uart1_data_write: std_logic_vector(7 downto 0);
signal uart1_divisor: std_logic_vector(15 downto 0);
signal int_spi: std_logic;
signal spicause, spicause_inv, spimask: std_logic_vector(3 downto 0);
signal spi0_data_write, spi0_data_read: std_logic_vector(7 downto 0);
signal spi0_clk_div: std_logic_vector(8 downto 0);
signal spi0_data_valid, spi0_data_xfer, spi0_ssn, spi0_clk_i, spi0_clk_o, spi0_do, spi0_di: std_logic;
signal spi1_data_write, spi1_data_read: std_logic_vector(7 downto 0);
signal spi1_clk_div: std_logic_vector(8 downto 0);
signal spi1_data_valid, spi1_data_xfer, spi1_ssn, spi1_clk_i, spi1_clk_o, spi1_do, spi1_di: std_logic;
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "00000" else '0';
s0cause <= int_spi & int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "00" & int_gpiob & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_gpiob <= '1' when ((pbin xor pbin_inv) and pbin_mask) /= "0000" else '0';
pain <= gpioa_in(15 downto 0);
gpioa_out <= paalt;
gpioa_ddr <= paddr;
pbin <= gpiob_in(15 downto 0);
gpiob_out <= pbout;
gpiob_ddr <= pbddr;
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= uart1_write_busy & uart1_data_avail & uart0_write_busy & uart0_data_avail;
int_spi <= '1' when ((spicause xor spicause_inv) and spimask) /= "0000" else '0';
spicause <= "00" & spi1_data_valid & spi0_data_valid;
-- PORT A alternate config MUXes for outputs
paalt(0) <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt(1) <= spi1_clk_o when paaltcfg0(3 downto 2) = "11" else paout(1);
paalt(2) <= uart0_tx when paaltcfg0(5 downto 4) = "01" else spi1_do when paaltcfg0(5 downto 4) = "11" else paout(2);
paalt(3) <= spi1_do when paaltcfg0(7 downto 6) = "11" else paout(3);
paalt(4) <= uart1_tx when paaltcfg0(9 downto 8) = "01" else paout(4);
paalt(5) <= spi0_clk_o when paaltcfg0(11 downto 10) = "10" else paout(5);
paalt(6) <= spi0_do when paaltcfg0(13 downto 12) = "10" else paout(6);
paalt(7) <= spi0_do when paaltcfg0(15 downto 14) = "10" else paout(7);
paalt(8) <= int_timer1_ctc when paaltcfg0(17 downto 16) = "01" else int_timer1_ocr when paaltcfg0(17 downto 16) = "10" else paout(8);
paalt(9) <= spi1_clk_o when paaltcfg0(19 downto 18) = "11" else paout(9);
paalt(10) <= uart0_tx when paaltcfg0(21 downto 20) = "01" else spi1_do when paaltcfg0(21 downto 20) = "11" else paout(10);
paalt(11) <= spi1_do when paaltcfg0(23 downto 22) = "11" else paout(11);
paalt(12) <= uart1_tx when paaltcfg0(25 downto 24) = "01" else paout(12);
paalt(13) <= spi0_clk_o when paaltcfg0(27 downto 26) = "10" else paout(13);
paalt(14) <= spi0_do when paaltcfg0(29 downto 28) = "10" else paout(14);
paalt(15) <= spi0_do when paaltcfg0(31 downto 30) = "10" else paout(15);
-- PORT A alternate config MUXes for inputs
uart0_rx <= pain(3) when paaltcfg0(7 downto 6) = "01" else pain(11) when paaltcfg0(23 downto 22) = "01" else '1';
uart1_rx <= pain(5) when paaltcfg0(11 downto 10) = "01" else pain(13) when paaltcfg0(27 downto 26) = "01" else '1';
spi0_ssn <= pain(4) when paaltcfg0(9 downto 8) = "10" else pain(12) when paaltcfg0(25 downto 24) = "10" else '1';
spi0_clk_i <= pain(5) when paaltcfg0(11 downto 10) = "10" else pain(13) when paaltcfg0(27 downto 26) = "10" else '0';
spi0_di <= pain(6) when paaltcfg0(13 downto 12) = "10" else pain(14) when paaltcfg0(29 downto 28) = "10" else
pain(7) when paaltcfg0(15 downto 14) = "10" else pain(15) when paaltcfg0(31 downto 30) = "10" else '0';
spi1_ssn <= pain(0) when paaltcfg0(1 downto 0) = "11" else pain(8) when paaltcfg0(17 downto 16) = "11" else '1';
spi1_clk_i <= pain(1) when paaltcfg0(3 downto 2) = "11" else pain(9) when paaltcfg0(19 downto 18) = "11" else '0';
spi1_di <= pain(2) when paaltcfg0(5 downto 4) = "11" else pain(10) when paaltcfg0(21 downto 20) = "11" else
pain(3) when paaltcfg0(7 downto 6) = "11" else pain(11) when paaltcfg0(23 downto 22) = "11" else '0';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
uart1_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"000000" & "000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"0000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"0000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"0000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"0000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"0000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
data_o <= x"0000" & pbddr;
when "0001" => -- PBOUT (RW)
data_o <= x"0000" & pbout;
when "0010" => -- PBIN (RO)
data_o <= x"0000" & pbin;
when "0011" => -- PBIN_INV (RW)
data_o <= x"0000" & pbin_inv;
when "0100" => -- PBIN_MASK (RW)
data_o <= x"0000" & pbin_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
data_o <= x"000000" & uart1_data_read;
uart1_enable_r <= '1';
when "0001" => -- UART1DIV (RW)
data_o <= x"0000" & uart1_divisor;
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000001" => -- SPICAUSE (RO)
data_o <= x"0000000" & spicause;
when "000010" => -- SPICAUSE_INV (RW)
data_o <= x"0000000" & spicause_inv;
when "000011" => -- SPIMASK (RW)
data_o <= x"0000000" & spimask;
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
data_o <= x"000000" & spi0_data_read;
when "0001" => -- SPI0CTRL (RW)
data_o <= x"0000" & "0000" & spi0_clk_div & "0" & spi0_data_valid & spi0_data_xfer;
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
data_o <= x"000000" & spi1_data_read;
when "0001" => -- SPI1CTRL (RW)
data_o <= x"0000" & "0000" & spi1_clk_div & "0" & spi1_data_valid & spi1_data_xfer;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
uart1_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
pbout <= (others => '0');
pbin_inv <= (others => '0');
pbin_mask <= (others => '0');
pbddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
uart1_enable_w <= '0';
uart1_data_write <= (others => '0');
uart1_divisor <= (others => '0');
spicause_inv <= (others => '0');
spimask <= (others => '0');
spi0_data_write <= (others => '0');
spi0_data_xfer <= '0';
spi0_clk_div <= (others => '0');
spi1_data_write <= (others => '0');
spi1_data_xfer <= '0';
spi1_clk_div <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(31 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(15 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(15 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(15 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
pbddr <= data_i(15 downto 0);
when "0001" => -- PBOUT (RW)
pbout <= data_i(15 downto 0);
when "0011" => -- PBIN_INV (RW)
pbin_inv <= data_i(15 downto 0);
when "0100" => -- PBIN_MASK (RW)
pbin_mask <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
uart1_data_write <= data_i(7 downto 0);
uart1_enable_w <= '1';
when "0001" => -- UART1DIV (RW)
uart1_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000010" => -- SPICAUSE_INV (RW)
spicause_inv <= data_i(3 downto 0);
when "000011" => -- SPIMASK (RW)
spimask <= data_i(3 downto 0);
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
spi0_data_write <= data_i(7 downto 0);
spi0_data_xfer <= '1';
when "0001" => -- SPI0CTRL (RW)
spi0_data_xfer <= data_i(0);
spi0_clk_div <= data_i(11 downto 3);
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
spi1_data_write <= data_i(7 downto 0);
spi1_data_xfer <= '1';
when "0001" => -- SPI1CTRL (RW)
spi1_data_xfer <= data_i(0);
spi1_clk_div <= data_i(11 downto 3);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
uart1_enable_w <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
uart1: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart1_divisor(11 downto 0),
enable_read => uart1_enable_r,
enable_write => uart1_enable_w,
data_in => uart1_data_write,
data_out => uart1_data_read,
uart_read => uart1_rx,
uart_write => uart1_tx,
busy_write => uart1_write_busy,
data_avail => uart1_data_avail
);
spi0: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi0_data_write,
data_o => spi0_data_read,
data_valid_o => spi0_data_valid,
wren_i => spi0_data_xfer,
clk_div_i => spi0_clk_div,
spi_ssn_i => spi0_ssn,
spi_clk_i => spi0_clk_i,
spi_clk_o => spi0_clk_o,
spi_do_o => spi0_do,
spi_di_i => spi0_di
);
spi1: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi1_data_write,
data_o => spi1_data_read,
data_valid_o => spi1_data_valid,
wren_i => spi1_data_xfer,
clk_div_i => spi1_clk_div,
spi_ssn_i => spi1_ssn,
spi_clk_i => spi1_clk_i,
spi_clk_o => spi1_clk_o,
spi_do_o => spi1_do,
spi_di_i => spi1_di
);
end peripherals_arch;
| gpl-2.0 | ef8b20da6d8f463eab8952b4275b2884 | 0.555545 | 2.716247 | false | false | false | false |
wfjm/w11 | rtl/vlib/simlib/simlib.vhd | 1 | 40,809 | -- $Id: simlib.vhd 1210 2021-08-26 13:27:26Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simlib - sim
-- Description: Support routines for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-13 1202 2.1.5 write{oct,hex}: fix for ghdl V0.36 -Whide warnings
-- 2016-09-03 805 2.1.4 simclk(v): CLK_STOP,CLK_HOLD now optional ports
-- 2016-07-16 787 2.1.3 add simbididly component
-- 2016-06-12 774 2.1.2 add writetimens()
-- 2014-10-25 599 2.1.1 add wait_* procedures; writeoptint: no dat clear
-- 2014-10-18 597 2.1 add simfifo_*, writetrace procedures
-- 2014-09-06 591 2.0.1 add readint_ea() with range check
-- 2011-12-23 444 2.0 drop CLK_CYCLE from simclk,simclkv; use integer for
-- simclkcnt(CLK_CYCLE),writetimestamp(clkcyc);
-- 2011-11-18 427 1.3.8 now numeric_std clean
-- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
-- 2007-12-27 106 1.3.3 added simclk2v
-- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic)
-- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-28 76 1.3 added writehex and writegen
-- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source
-- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg
-- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea,
-- readoptchar, writetimestamp
-- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen
-- use readgen in readtagval() and readtagval2()
-- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2
-- 2007-06-30 62 1.0.1 remove clock_period ect constant defs
-- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
package simlib is
constant null_char : character := character'val(0); -- '\0'
constant null_string : string(1 to 1) := (others=>null_char); -- "\0"
procedure readwhite( -- read over white space
L: inout line); -- line
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean); -- success flag
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer:= 2); -- default base
procedure readcomment(
L: inout line;
good: out boolean);
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean);
procedure readword(
L: inout line;
name: out string;
good: out boolean);
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean);
procedure readempty(
L: inout line);
procedure testempty(
L: inout line;
good: out boolean);
procedure testempty_ea(
L: inout line);
procedure read_ea(
L: inout line;
value: out integer);
procedure read_ea(
L: inout line;
value: out time);
procedure readint_ea(
L: inout line;
value: out integer;
imin : in integer := integer'low;
imax : in integer := integer'high);
procedure read_ea(
L: inout line;
value: out std_logic);
procedure read_ea(
L: inout line;
value: out std_logic_vector);
procedure readoct_ea(
L: inout line;
value: out std_logic_vector);
procedure readhex_ea(
L: inout line;
value: out std_logic_vector);
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer:= 2);
procedure readword_ea(
L: inout line;
name: out string);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2);
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean);
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic);
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2);
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2);
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0); -- field width
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:= 2); -- default base
procedure writetimens( -- write time as fractional ns
L: inout line; -- line
t : in time; -- time
field : in width:=0); -- number of ns digits
procedure writetimestamp( -- write time stamp
L: inout line; -- line
str : in string := null_string); -- 1st string field
procedure writetimestamp( -- write time stamp w/ clk cycle
L: inout line; -- line
clkcyc: in integer; -- cycle number
str : in string := null_string); -- 1st string field
procedure writeoptint( -- write int if > 0
L: inout line; -- line
str : in string; -- string
dat : in integer; -- int value
field: in width:=0); -- field width
procedure writetrace( -- debug trace - plain
str : in string); -- string
procedure writetrace( -- debug trace - int
str : in string; -- string
dat : in integer); -- value
procedure writetrace( -- debug trace - slbit
str : in string; -- string
dat : in slbit); -- value
procedure writetrace( -- debug trace - slv
str : in string; -- string
dat : in slv); -- value
type clock_dsc is record -- clock descriptor
period : Delay_length; -- clock period
hold : Delay_length; -- hold time = clock yo stim time
setup : Delay_length; -- setup time = moni to clock time
end record;
procedure wait_nextstim( -- wait for next stim time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
constant cnt : in positive := 1); -- number of cycles to wait
procedure wait_nextmoni( -- wait for next moni time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
constant cnt : in positive := 1); -- number of cycles to wait
procedure wait_stim2moni( -- wait from stim to moni time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc); -- clock descriptor
procedure wait_untilsignal( -- wait until signal
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
signal sig : in slbit; -- signal
constant val : in slbit; -- value
variable cnt : out natural); -- cycle count
type simfifo_type is array (natural range <>, natural range<>) of std_logic;
procedure simfifo_put( -- add item to simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
din : in std_logic_vector; -- element to add
val : in slbit := '1'); -- valid flag
procedure simfifo_get( -- get item from simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
dout: out std_logic_vector); -- element retrieved
procedure simfifo_writetest( -- test value against simfifo and write
L: inout line; -- line
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
dat : in std_logic_vector); -- data to test
procedure simfifo_dump( -- dump simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
str : in string := null_string); -- header text
-- ----------------------------------------------------------------------------
component simclk is -- test bench clock generator
generic (
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
component simclkv is -- test bench clock generator
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_PERIOD : in Delay_length; -- clock period
CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out integer -- clock cycle number
);
end component;
component simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end component;
end package simlib;
-- ----------------------------------------------------------------------------
package body simlib is
procedure readwhite( -- read over white space
L: inout line) is -- line
variable ch : character;
begin
while L'length>0 loop
ch := L(L'left);
exit when (ch/=' ' and ch/=HT);
read(L,ch);
end loop;
end procedure readwhite;
-- -------------------------------------
procedure readoct( -- read slv in octal base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(2 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readoct called with ascending range"
severity failure;
assert value'length<=32
report "readoct called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "000";
when '1' => nibble := "001";
when '2' => nibble := "010";
when '3' => nibble := "011";
when '4' => nibble := "100";
when '5' => nibble := "101";
when '6' => nibble := "110";
when '7' => nibble := "111";
when 'u'|'U' => nibble := "UUU";
when 'x'|'X' => nibble := "XXX";
when 'z'|'Z' => nibble := "ZZZ";
when '-' => nibble := "---";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 3) := sum(sum'left-3 downto 0);
sum(2 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readoct;
-- -------------------------------------
procedure readhex( -- read slv in hex base (arb. length)
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean) is -- success flag
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable ndig : integer; -- number of digits
variable ok : boolean;
variable ichar : character;
begin
assert not value'ascending(1)
report "readhex called with ascending range"
severity failure;
assert value'length<=32
report "readhex called with value'length > 32"
severity failure;
readwhite(L);
ndig := 0;
sum := (others=>'U');
while L'length>0 loop
ok := true;
case L(L'left) is
when '0' => nibble := "0000";
when '1' => nibble := "0001";
when '2' => nibble := "0010";
when '3' => nibble := "0011";
when '4' => nibble := "0100";
when '5' => nibble := "0101";
when '6' => nibble := "0110";
when '7' => nibble := "0111";
when '8' => nibble := "1000";
when '9' => nibble := "1001";
when 'a'|'A' => nibble := "1010";
when 'b'|'B' => nibble := "1011";
when 'c'|'C' => nibble := "1100";
when 'd'|'D' => nibble := "1101";
when 'e'|'E' => nibble := "1110";
when 'f'|'F' => nibble := "1111";
when 'u'|'U' => nibble := "UUUU";
when 'x'|'X' => nibble := "XXXX";
when 'z'|'Z' => nibble := "ZZZZ";
when '-' => nibble := "----";
when others => ok := false;
end case;
exit when not ok;
read(L,ichar);
ndig := ndig + 1;
sum(sum'left downto 4) := sum(sum'left-4 downto 0);
sum(3 downto 0) := nibble;
end loop;
ok := ndig>0;
value := sum(value'range);
good := ok;
end procedure readhex;
-- -------------------------------------
procedure readgen( -- read slv generic base
L: inout line; -- line
value: out std_logic_vector; -- value to be read
good: out boolean; -- success flag
base: in integer := 2) is -- default base
variable nibble : std_logic_vector(3 downto 0);
variable sum : std_logic_vector(31 downto 0);
variable lbase : integer; -- local base
variable cbase : integer; -- current base
variable ok : boolean;
variable ivalue : integer;
variable ichar : character;
begin
assert not value'ascending(1)
report "readgen called with ascending range"
severity failure;
assert value'length<=32
report "readgen called with value'length > 32"
severity failure;
assert base=2 or base=8 or base=10 or base=16
report "readgen base not 2,8,10, or 16"
severity failure;
readwhite(L);
cbase := base;
lbase := 0;
ok := true;
if L'length >= 2 then
if L(L'left+1) = '"' then
case L(L'left) is
when 'b'|'B' => lbase := 2;
when 'o'|'O' => lbase := 8;
when 'd'|'D' => lbase := 10;
when 'x'|'X' => lbase := 16;
when others => ok := false;
end case;
end if;
if lbase /= 0 then
read(L, ichar);
read(L, ichar);
cbase := lbase;
end if;
end if;
if ok then
case cbase is
when 2 => read(L, value, ok);
when 8 => readoct(L, value, ok);
when 16 => readhex(L, value, ok);
when 10 =>
read(L, ivalue, ok);
-- the following if allows to enter negative integers, e.g. -1 for all-1
if ivalue >= 0 then
value := slv(to_unsigned(ivalue, value'length));
else
value := slv(to_signed(ivalue, value'length));
end if;
when others => null;
end case;
end if;
if ok and lbase/=0 then
if L'length>0 and L(L'left)='"' then
read(L, ichar);
else
ok := false;
end if;
end if;
good := ok;
end procedure readgen;
-- -------------------------------------
procedure readcomment(
L: inout line;
good: out boolean) is
variable ichar : character;
begin
readwhite(L);
good := true;
if L'length > 0 then
good := false;
if L(L'left) = '#' then
good := true;
elsif L(L'left) = 'C' then
good := true;
writeline(output, L);
end if;
end if;
end procedure readcomment;
-- -------------------------------------
procedure readdotcomm(
L: inout line;
name: out string;
good: out boolean) is
begin
for i in name'range loop
name(i) := ' ';
end loop;
good := false;
if L'length>0 and L(L'left)='.' then
readword(L, name, good);
end if;
end procedure readdotcomm;
-- -------------------------------------
procedure readword(
L: inout line;
name: out string;
good: out boolean) is
variable ichar : character;
variable ind : integer;
begin
assert name'ascending(1)
report "readword called with descending range for name"
severity failure;
readwhite(L);
for i in name'range loop
name(i) := ' ';
end loop;
ind := name'left;
while L'length>0 and ind<=name'right loop
ichar := L(L'left);
exit when ichar=' ' or ichar=',' or ichar='|';
read(L,ichar);
name(ind) := ichar;
ind := ind + 1;
end loop;
good := ind /= name'left; -- ok if one non-blank found
end procedure readword;
-- -------------------------------------
procedure readoptchar(
L: inout line;
char: in character;
good: out boolean) is
variable ichar : character;
begin
good := false;
if L'length > 0 then
if L(L'left) = char then
read(L, ichar);
good := true;
end if;
end if;
end procedure readoptchar;
-- -------------------------------------
procedure readempty(
L: inout line) is
variable ch : character;
begin
while L'length>0 loop -- anything left ?
read(L,ch); -- read and discard it
end loop;
end procedure readempty;
-- -------------------------------------
procedure testempty(
L: inout line;
good: out boolean) is
begin
readwhite(L); -- discard white space
good := true; -- good if now empty
if L'length > 0 then -- anything left ?
good := false; -- assume bad
if L'length >= 2 and -- check for "--"
L(L'left)='-' and L(L'left+1)='-' then
good := true; -- in that case comment -> good
end if;
end if;
end procedure testempty;
-- -------------------------------------
procedure testempty_ea(
L: inout line) is
variable ok : boolean := false;
begin
testempty(L, ok);
assert ok report "extra chars in """ & L.all & """" severity failure;
end procedure testempty_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out integer) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(integer) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out time) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(time) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure readint_ea(
L: inout line;
value: out integer;
imin : in integer := integer'low;
imax : in integer := integer'high) is
variable dat : integer := 0;
begin
read_ea(L, dat);
assert dat>=imin and dat<=imax
report "readint_ea range check: " &
integer'image(dat) & " not in " &
integer'image(imin) & ":" & integer'image(imax)
severity failure;
value := dat;
end procedure readint_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure read_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
read(L, value, ok);
assert ok report "read(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure read_ea;
-- -------------------------------------
procedure readoct_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readoct(L, value, ok);
assert ok report "readoct() conversion error in """ &
L.all & """" severity failure;
end procedure readoct_ea;
-- -------------------------------------
procedure readhex_ea(
L: inout line;
value: out std_logic_vector) is
variable ok : boolean := false;
begin
readhex(L, value, ok);
assert ok report "readhex() conversion error in """ &
L.all & """" severity failure;
end procedure readhex_ea;
-- -------------------------------------
procedure readgen_ea(
L: inout line;
value: out std_logic_vector;
base: in integer := 2) is
variable ok : boolean := false;
begin
readgen(L, value, ok, base);
assert ok report "readgen() conversion error in """ &
L.all & """" severity failure;
end procedure readgen_ea;
-- -------------------------------------
procedure readword_ea(
L: inout line;
name: out string) is
variable ok : boolean := false;
begin
readword(L, name, ok);
assert ok report "readword() read error in """ &
L.all & """" severity failure;
end procedure readword_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
for i in val'range loop
val(i) := '0';
end loop;
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
readgen(L, val, good, base);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok, base);
assert ok report "readtagval(std_logic_vector) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic;
good: out boolean) is
variable itag : string(tag'range);
variable ichar : character;
variable imatch : boolean;
begin
readwhite(L);
val := '0';
good := true;
imatch := false;
if L'length > tag'length then
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then
read(L, itag);
read(L, ichar);
read(L, val, good);
end if;
end if;
match := imatch;
end procedure readtagval;
-- -------------------------------------
procedure readtagval_ea(
L: inout line;
tag: in string;
match: out boolean;
val: out std_logic) is
variable ok : boolean := false;
begin
readtagval(L, tag, match, val, ok);
assert ok report "readtagval(std_logic) conversion error in """ &
L.all & """" severity failure;
end procedure readtagval_ea;
-- -------------------------------------
procedure readtagval2(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
good: out boolean;
base: in integer:= 2) is
variable itag : string(tag'range);
variable imatch : boolean;
variable igood : boolean;
variable ichar : character;
variable ok : boolean;
begin
readwhite(L);
for i in val1'range loop -- zero val1
val1(i) := '0';
end loop;
for i in val2'range loop -- zero val2
val2(i) := '0';
end loop;
igood := true;
imatch := false;
if L'length > tag'length then -- check for tag
imatch := L(L'left to L'left+tag'length-1) = tag and
L(L'left+tag'length) = '=';
if imatch then -- if found
read(L, itag); -- remove tag
read(L, ichar); -- remove =
igood := false;
readoptchar(L, '-', ok); -- check for tag=-
if ok then
for i in val2'range loop -- set mask to all 1 (ignore)
val2(i) := '1';
end loop;
igood := true;
else -- here if tag=bit[,bit]
readgen(L, val1, igood, base); -- read val1
if igood then
readoptchar(L, ',', ok); -- check(and remove) ,
if ok then
readgen(L, val2, igood, base); -- and read val2
end if;
end if;
end if;
end if;
end if;
match := imatch;
good := igood;
end procedure readtagval2;
-- -------------------------------------
procedure readtagval2_ea(
L: inout line;
tag: in string;
match: out boolean;
val1: out std_logic_vector;
val2: out std_logic_vector;
base: in integer:= 2) is
variable ok : boolean := false;
begin
readtagval2(L, tag, match, val1, val2, ok, base);
assert ok report "readtagval2() conversion error in """ &
L.all & """" severity failure;
end procedure readtagval2_ea;
-- -------------------------------------
procedure writeoct( -- write slv in octal base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(2 downto 0);
variable ochar : character;
begin
assert not value'ascending(1)
report "writeoct called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+2)/3;
iwidth := nbit mod 3;
if iwidth = 0 then
iwidth := 3;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for j in nibble'range loop
case nibble(j) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- j
if ochar = ' ' then
write(L,to_integer(unsigned(nibble)));
else
write(L,ochar);
end if;
iwidth := 3;
ioffset := ioffset - 3;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writeoct;
-- -------------------------------------
procedure writehex( -- write slv in hex base (arb. length)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0) is -- field width
variable nbit : integer; -- number of bits
variable ndig : integer; -- number of digits
variable iwidth : integer;
variable ioffset : integer;
variable nibble : std_logic_vector(3 downto 0);
variable ochar : character;
variable hextab : string(1 to 16) := "0123456789abcdef";
begin
assert not value'ascending(1)
report "writehex called with ascending range"
severity failure;
nbit := value'length(1);
ndig := (nbit+3)/4;
iwidth := nbit mod 4;
if iwidth = 0 then
iwidth := 4;
end if;
ioffset := value'left(1) - iwidth+1;
if justified=right and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
for i in 0 to ndig-1 loop
nibble := "0000";
nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
ochar := ' ';
for j in nibble'range loop
case nibble(j) is
when 'U' => ochar := 'U';
when 'X' => ochar := 'X';
when 'Z' => ochar := 'Z';
when '-' => ochar := '-';
when others => null;
end case;
end loop; -- j
if ochar = ' ' then
write(L,hextab(to_integer(unsigned(nibble))+1));
else
write(L,ochar);
end if;
iwidth := 4;
ioffset := ioffset - 4;
end loop; -- i
if justified=left and field>ndig then
for i in ndig+1 to field loop
write(L,' ');
end loop; -- i
end if;
end procedure writehex;
-- -------------------------------------
procedure writegen( -- write slv in generic base (arb. lth)
L: inout line; -- line
value: in std_logic_vector; -- value to be written
justified: in side:=right; -- justification (left/right)
field: in width:=0; -- field width
base: in integer:=2) is -- default base
begin
case base is
when 2 => write(L, value, justified, field);
when 8 => writeoct(L, value, justified, field);
when 16 => writehex(L, value, justified, field);
when others => report "writegen base not 2,8, or 16"
severity failure;
end case;
end procedure writegen;
-- -------------------------------------
procedure writetimens( -- write time as fractional ns
L: inout line; -- line
t : in time; -- time
field : in width:=0) is -- number of ns digits
variable t_nsec : integer := 0;
variable t_psec : integer := 0;
variable t_dnsec : integer := 0;
begin
t_nsec := t / 1 ns;
t_psec := (t - t_nsec * 1 ns) / 1 ps;
t_dnsec := t_psec/100;
write(L, t_nsec, right, field);
write(L,'.');
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
end procedure writetimens;
-- -------------------------------------
procedure writetimestamp(
L: inout line;
str : in string := null_string) is
begin
writetimens(L, now, 8);
if str /= null_string then
write(L, str);
end if;
end procedure writetimestamp;
-- -------------------------------------
procedure writetimestamp(
L: inout line;
clkcyc: in integer;
str: in string := null_string) is
begin
writetimestamp(L);
write(L, clkcyc, right, 7);
if str /= null_string then
write(L, str);
end if;
end procedure writetimestamp;
-- -------------------------------------
procedure writeoptint( -- write int if > 0
L: inout line; -- line
str : in string; -- string
dat : in integer; -- int value
field: in width:=0) is -- field width
begin
if dat > 0 then
write(L, str);
write(L, dat, right, field);
end if;
end procedure writeoptint;
-- -------------------------------------
procedure writetrace( -- debug trace - plain
str: in string) is -- string
variable oline : line;
begin
writetimestamp(oline, " ++ ");
write(oline, str);
writeline(output, oline);
end procedure writetrace;
-- -------------------------------------
procedure writetrace( -- debug trace - int
str: in string; -- string
dat : in integer) is -- value
variable oline : line;
begin
writetimestamp(oline, " ++ ");
write(oline, str);
write(oline, dat);
writeline(output, oline);
end procedure writetrace;
-- -------------------------------------
procedure writetrace( -- debug trace - slbit
str: in string; -- string
dat : in slbit) is -- value
variable oline : line;
begin
writetimestamp(oline, " ++ ");
write(oline, str);
write(oline, dat);
writeline(output, oline);
end procedure writetrace;
-- -------------------------------------
procedure writetrace( -- debug trace - slv
str: in string; -- string
dat : in slv) is -- value
variable oline : line;
begin
writetimestamp(oline, " ++ ");
write(oline, str);
write(oline, dat);
writeline(output, oline);
end procedure writetrace;
-- -------------------------------------
procedure wait_nextstim( -- wait for next stim time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
constant cnt : in positive := 1) is -- number of cycles to wait
begin
for i in 1 to cnt loop
wait until rising_edge(clk);
wait for clk_dsc.hold;
end loop; -- i
end procedure wait_nextstim;
-- -------------------------------------
procedure wait_nextmoni( -- wait for next moni time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
constant cnt : in positive := 1) is -- number of cycles to wait
begin
for i in 1 to cnt loop
wait until rising_edge(clk);
wait for clk_dsc.period - clk_dsc.setup;
end loop; -- i
end procedure wait_nextmoni;
-- -------------------------------------
procedure wait_stim2moni( -- wait from stim to moni time
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc) is -- clock descriptor
begin
wait for clk_dsc.period - clk_dsc.hold - clk_dsc.setup;
end procedure wait_stim2moni;
-- -------------------------------------
procedure wait_untilsignal( -- wait until signal
signal clk : in slbit; -- clock
constant clk_dsc : in clock_dsc; -- clock descriptor
signal sig : in slbit; -- signal
constant val : in slbit; -- value
variable cnt : out natural) is -- cycle count
variable cnt_l : natural := 0;
begin
cnt_l := 0;
while val /= sig loop
wait_nextmoni(clk, clk_dsc);
cnt_l := cnt_l + 1;
end loop;
cnt := cnt_l;
end procedure wait_untilsignal;
-- -------------------------------------
procedure simfifo_put( -- add item to simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
din : in std_logic_vector; -- element to add
val : in slbit := '1') is -- valid flag
variable din_imax : integer := din'length-1;
begin
if val = '0' then
return;
end if;
assert cnt < arr'high(1)
report "simfifo_put: fifo full"
severity failure;
assert arr'length(2) = din'length and
arr'ascending(2) = din'ascending
report "simfifo_put: arr,din range mismatch"
severity failure;
for i in 0 to din_imax loop
arr(cnt, arr'low(2)+i) := din(din'low+i);
end loop; -- i
cnt := cnt + 1;
end procedure simfifo_put;
-- -------------------------------------
procedure simfifo_get( -- get item from simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
dout : out std_logic_vector) is -- element retrieved
variable dout_imax : integer := dout'length-1;
begin
assert cnt > 0
report "simfifo_put: fifo empty"
severity failure;
assert arr'length(2) = dout'length and
arr'ascending(2) = dout'ascending
report "simfifo_put: arr,din range mismatch"
severity failure;
for i in 0 to dout_imax loop
dout(dout'low+i) := arr(0, arr'low(2)+i);
end loop; -- i
cnt := cnt - 1;
if cnt > 0 then
for i in 1 to cnt loop
for j in 0 to dout_imax loop
arr(i-1, arr'low(2)+j) := arr(i, arr'low(2)+j);
end loop; -- j
end loop; -- i
end if;
end procedure simfifo_get;
-- -------------------------------------
procedure simfifo_writetest( -- test value against simfifo and write
L: inout line; -- line
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
dat : in std_logic_vector) is -- data to test
variable refdata : slv(dat'range);
begin
if cnt = 0 then
write(L, string'(" FAIL: UNEXPECTED"));
else
simfifo_get(cnt, arr, refdata);
write(L, string'(" CHECK: "));
if dat = refdata then
write(L, string'("OK"));
else
write(L, string'("FAIL, EXP= "));
write(L, refdata);
end if;
end if;
end procedure simfifo_writetest;
-- -------------------------------------
procedure simfifo_dump( -- dump simfifo
cnt : inout natural; -- fifo element count
arr : inout simfifo_type; -- fifo data array
str: in string := null_string) is -- header text
variable oline : line;
variable data : slv(arr'range(2));
begin
writetimestamp(oline, " ++ ");
if str /= null_string then
write(oline, str);
end if;
write(oline, string'(" cnt= "));
write(oline, cnt);
write(oline, string'(" of "));
write(oline, arr'high(1));
write(oline, string'("; drange="));
write(oline, arr'left(2));
if arr'ascending(2) then
write(oline, string'(" to "));
else
write(oline, string'(" downto "));
end if;
write(oline, arr'right(2));
writeline(output, oline);
if cnt > 0 then
for i in 0 to cnt-1 loop
for j in data'range loop
data(j) := arr(i,j);
end loop; -- j
write(oline, string'(" - "));
write(oline, i, right, 2);
write(oline, string'(" "));
write(oline, data);
writeline(output, oline);
end loop; -- i
end if;
end procedure simfifo_dump;
end package body simlib;
| gpl-3.0 | 37a7945216671cd16e37a1028ce5745c | 0.532481 | 3.894732 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/sn_humanio.vhd | 1 | 4,380 | -- $Id: sn_humanio.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: BTN,SWI,LED and DSP handling for s3board, nexys, basys
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-24 637 14.7 131013 xc6slx16-2 77 79 0 28 s 3.5 ns (n4)
-- 2015-01-24 637 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns (n2)
-- 2015-01-24 410 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-24 637 1.3 add SWIDTH,LWIDTH,DCWIDTH (for nexys4,basys3)
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 2**DCWIDTH)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
DRV : sn_7segctl
generic map (
DCWIDTH => DCWIDTH,
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
| gpl-3.0 | 1f7cd66b68e7f34304dc496a71e10468 | 0.505251 | 3.218222 | false | false | false | false |
sjohann81/hf-risc | mips/platform/spartan3e_nexys2/spartan3e_nexys2_xtea.vhd | 1 | 7,594 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
uart_support : string := "yes"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
int_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
signal ext_periph, ext_periph_dly, ready: std_logic;
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
signal data_read_xtea: std_logic_vector(31 downto 0);
signal control: std_logic_vector(1 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
ext_periph_dly <= '0';
ext_irq <= x"00";
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
ext_periph_dly <= ext_periph;
ext_irq <= "0000000" & int_in;
end if;
end process;
process (clock, reset, address_cpu, key, input, output)
begin
if reset = '1' then
data_read_xtea <= (others => '0');
elsif clock'event and clock = '1' then
if (ext_periph = '1') then -- XTEA is at 0xfa000000
case address_cpu(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xfa000010
data_read_xtea <= key(127 downto 96);
when "0010" => -- key[1] 0xfa000020
data_read_xtea <= key(95 downto 64);
when "0011" => -- key[2] 0xfa000030
data_read_xtea <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea <= key(31 downto 0);
when "0101" => -- input[0] 0xfa000050
data_read_xtea <= input(63 downto 32);
when "0110" => -- input[1] 0xfa000060
data_read_xtea <= input(31 downto 0);
when "0111" => -- output[0] 0xfa000070
data_read_xtea <= output(63 downto 32);
when "1000" => -- output[1] 0xfa000080
data_read_xtea <= output(31 downto 0);
when others =>
data_read_xtea <= (others => '0');
end case;
end if;
end if;
end process;
process (clock, reset, address_cpu, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
input <= (others => '0');
control <= "00";
elsif clock'event and clock = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000
case address_cpu(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write(1 downto 0);
when "0001" => -- key[0] 0xfa000010
key(127 downto 96) <= data_write;
when "0010" => -- key[1] 0xfa000020
key(95 downto 64) <= data_write;
when "0011" => -- key[2] 0xfa000030
key(63 downto 32) <= data_write;
when "0100" => -- key[3] 0xfa000040
key(31 downto 0) <= data_write;
when "0101" => -- input[0] 0xfa000050
input(63 downto 32) <= data_write;
when "0110" => -- input[1] 0xfa000060
input(31 downto 0) <= data_write;
when others =>
end case;
end if;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';
data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_access => data_access_cpu
);
-- peripherals / busmux logic
peripherals_busmux: entity work.busmux
generic map(
uart_support => uart_support
)
port map(
clock => clock,
reset => reset,
stall => stall,
stall_cpu => stall_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => address,
data_read_mem => data_read,
data_write_mem => data_write,
data_we_mem => data_we,
extio_in => ext_irq,
extio_out => open,
uart_read => uart_read,
uart_write => uart_write
);
-- XTEA core
crypto_core: entity work.xtea
port map( clock => clock,
reset => reset,
start => control(0),
encrypt => control(1),
key => key,
input => input,
output => output,
ready => ready
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | 66aed01d15e17197b5380a1a0f27d2ca | 0.611009 | 2.670183 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd | 1 | 10,046 | -- $Id: sys_tst_rlink_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n2 - syn
-- Description: rlink tester design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-03-06 743 14.7 131013 xc3s1200e-4 933 2007 128 1348
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 914 1951 128 1321 t 15.7
-- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8
-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-12-23 444 1.2 remove clksys output hack
-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.1.1 use now sn_humanio
-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2) no function (only connected to sn_humanio_rbus)
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (1) timer 1 busy
-- (0) timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n2;
architecture syn of sys_tst_rlink_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"02"; -- nexys2
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | ea9d100c1be3d625f9dc8b075f463eba | 0.498905 | 3.047012 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/led_pulse_stretch.vhd | 1 | 2,260 | -- $Id: led_pulse_stretch.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: led_pulse_stretch - syn
-- Description: pulse stretcher for leds
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end entity led_pulse_stretch;
architecture syn of led_pulse_stretch is
type regs_type is record -- state registers
seen : slbit; -- DIN seen
busy : slbit; -- POUT busy
end record regs_type;
constant regs_init : regs_type := (
'0', -- seen
'0' -- busy
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, DIN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if CE_INT='1' then
n.seen := DIN;
n.busy := r.seen;
else
if DIN='1' then
n.seen := '1';
end if;
end if;
N_REGS <= n;
POUT <= r.busy;
end process proc_next;
end syn;
| gpl-3.0 | 80f5905795eaf0e2fdea6d4cb038b32e | 0.492478 | 3.741722 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/tb_nexys4d_dram.vhd | 1 | 5,475 | -- $Id: tb_nexys4d_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d_dram - sim
-- Description: Test bench for nexys4d (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_dram_aif [UUT]
--
-- To test: generic, any nexys4d_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d_dram is
end tb_nexys4d_dram;
architecture sim of tb_nexys4d_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal IO_DDR2_DQ : slv16 := (others=>'Z');
signal IO_DDR2_DQS_P : slv2 := (others=>'Z');
signal IO_DDR2_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
DDR2_DQ => IO_DDR2_DQ,
DDR2_DQS_P => IO_DDR2_DQS_P,
DDR2_DQS_N => IO_DDR2_DQS_N,
DDR2_ADDR => open,
DDR2_BA => open,
DDR2_RAS_N => open,
DDR2_CAS_N => open,
DDR2_WE_N => open,
DDR2_CK_P => open,
DDR2_CK_N => open,
DDR2_CKE => open,
DDR2_CS_N => open,
DDR2_DM => open,
DDR2_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | f1ebc45092f4422b5c5ce896a8023d8e | 0.521826 | 3.207381 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_uart_rxtx.vhd | 1 | 2,609 | -- $Id: serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx - syn
-- Description: serial port UART - transmitter + receiver
--
-- Dependencies: serport_uart_rx
-- serport_uart_tx
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_rxtx;
architecture syn of serport_uart_rxtx is
begin
RX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
TX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
| gpl-3.0 | 052027ddd3e01474a945527dfc3e3eba | 0.526255 | 4.082942 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04700_good.vhd | 1 | 4,766 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04700_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Finite State Machine single process based: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_04700_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_04700_good;
--CODE
architecture Behavioral of CNE_04700_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- sm_State signal
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
sm_State <= init;
elsif (rising_edge(i_Clock)) then
-- Set the length value
Length <= c_Length;
case sm_State is
when init =>
Raz <= '0';
Enable <= '0';
sm_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
sm_State <= Enabled;
else
Enable <= '0';
sm_State <= finished;
end if;
when others =>
sm_State <= init;
end case;
end if;
end process;
end Behavioral;
--CODE | gpl-3.0 | 9113893bcfbb175bd282cca0fdf8b763 | 0.471884 | 4.766 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02000_bad.vhd | 1 | 4,680 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02000_bad.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of Finite State Machine: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_02000_bad is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_02000_bad;
architecture Behavioral of CNE_02000_bad is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
--CODE
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal State : t_state; -- State signal
--CODE
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
State <= init;
elsif (rising_edge(i_Clock)) then
case State is
when init =>
-- Set the length value
Length <= c_Length;
State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
State <= Enabled;
else
Enable <= '0';
State <= finished;
end if;
when others =>
State <= init;
end case;
end if;
end process;
end Behavioral; | gpl-3.0 | cc122b4f4b211d1d1083cadd208be453 | 0.472863 | 4.849741 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd | 1 | 5,531 | -- $Id: migui_nexys4d_gsim.vhd 1201 2019-08-10 16:51:22Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui_nexys4d - sim
-- Description: MIG generated for nexys4d - simple simulator
--
-- Dependencies: bplib/mig/migui_core_gsim
-- Test bench: tb_tst_sram_nexys4d
-- Target Devices: arty board
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (cloned from arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
entity migui_nexys4d is -- MIG generated for nexys4d
port (
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end migui_nexys4d;
architecture sim of migui_nexys4d is
begin
-- On Nexys4 we have
-- SYS_CLK_I 100 Mhz
-- controller 300 MHz
-- UI_CLK 75 MHz (4:1)
-- therefore for simulation
-- f_vco 1200 MHz
-- --> mul 12 (f_vco/SYS_CLK)
-- --> div 16 (f_vco/UI_CLK)
MIG_SIM : migui_core_gsim
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth,
SAWIDTH => 24,
CLKMUI_MUL => 12,
CLKMUI_DIV => 16)
port map (
SYS_CLK => SYS_CLK_I,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK
);
DDR2_DQ <= (others=>'Z');
DDR2_DQS_P <= (others=>'Z');
DDR2_DQS_N <= (others=>'Z');
DDR2_ADDR <= (others=>'0');
DDR2_BA <= (others=>'0');
DDR2_RAS_N <= '1';
DDR2_CAS_N <= '1';
DDR2_WE_N <= '1';
DDR2_CK_P <= (others=>'0');
DDR2_CK_N <= (others=>'1');
DDR2_CKE <= (others=>'0');
DDR2_CS_N <= (others=>'1');
DDR2_DM <= (others=>'0');
DDR2_ODT <= (others=>'0');
APP_SR_ACTIVE <= '0';
end sim;
| gpl-3.0 | 1804aa064dff8dc337fc2ef948cd4612 | 0.495209 | 3.325917 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbdlib.vhd | 1 | 4,282 | -- $Id: rbdlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rbdlib
-- Description: Definitions for rbus devices
--
-- Dependencies: -
-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 4.1 add rbd_usracc
-- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2010-12-29 351 1.2 new address layout; add rbd_timer
-- 2010-12-27 349 1.1 now correct defs for _rbmon and _eyemon
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- two devices have standard addresses
-- rbd_rbmon x"ffe8"
-- rbd_tester x"ffe0"
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package rbdlib is
constant rbaddr_usracc : slv16 := x"fffa"; -- fffa/8: 1111 1111 1111 1010
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/8: 1111 1111 1110 1xxx
constant rbaddr_tester : slv16 := x"ffe0"; -- ffe0/8: 1111 1111 1110 0xxx
component rbd_tester is -- rbus dev: rbus tester
-- complete rbus_aif interface
generic (
RB_ADDR : slv16 := rbaddr_tester);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end component;
component rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv16 := rbaddr_rbmon;
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
);
end component;
component rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv16 := (others=>'0');
RDIV : slv8 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RXSD : in slbit; -- rx: serial data
RXACT : in slbit -- rx: active (start seen)
);
end component;
component rbd_bram is -- rbus dev: bram test target
-- incomplete rbus_aif interface
generic (
RB_ADDR : slv16 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end component;
component rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv16 := (others=>'0'));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DONE : out slbit; -- mark last timer cycle
BUSY : out slbit -- timer running
);
end component;
component rbd_usracc is -- rbus dev: return usr_access register
generic (
RB_ADDR : slv16 := rbaddr_usracc);
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end component;
end package rbdlib;
| gpl-3.0 | d5658498fe68ae969629133877428f69 | 0.510976 | 3.729965 | false | true | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/test/simulation/test_mmu_tb.vhd | 1 | 12,111 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: test_mmu
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library std;
use std.textio.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_textio.all;
use std.standard.all;
entity test_mmu_tb is
end test_mmu_tb;
architecture behavioral of test_mmu_tb is
-- Component declarations
component MMU
generic ( DEPTH_BANK : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
resetb : in std_logic;
-- Instruction Memory
we_i : in std_logic;
en_i : in std_logic;
addr_i : in std_logic_vector(31 downto 3);
ben_i : in std_logic_vector(7 downto 0);
di_i : in std_logic_vector(63 downto 0);
do_i : out std_logic_vector(63 downto 0);
-- Data Memory
we_d : in std_logic;
en_d : in std_logic;
addr_d : in std_logic_vector(31 downto 3);
ben_d : in std_logic_vector(7 downto 0);
di_d : in std_logic_vector(63 downto 0);
do_d : out std_logic_vector(63 downto 0)
);
end component MMU;
subtype word_t is std_logic_vector(31 downto 0);
type ram_t is array(0 to 1023) of word_t;
-- Signals
signal clk, resetb, we_i, en_i, we_d, en_d : std_logic;
signal ben_i, ben_d : std_logic_vector(7 downto 0);
signal addr_i, addr_d : std_logic_vector(31 downto 0);
signal di_i, di_d, do_i, do_d : std_logic_vector(63 downto 0);
-- Simulation control
shared variable END_SIMULATION : boolean := false;
-- Test procedures
procedure reset (
signal resetb : out std_logic;
signal en_i, we_i, en_d, we_d : out std_logic;
signal ben_i, ben_d : out std_logic_vector(7 downto 0)
) is
begin
wait until rising_edge(clk);
resetb <= '0';
en_i <= '0'; we_i <= '0';
en_d <= '0'; we_d <= '0';
ben_i <= (others => '1');
ben_d <= (others => '1');
wait until rising_edge(clk);
wait until rising_edge(clk);
resetb <= '1';
end procedure reset;
-- https://electronics.stackexchange.com/questions/180446/how-to-load-std-logic-vector-array-from-text-file-at-start-of-simulation
-- Read a *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : word_t;
variable Result : ram_t := (others => (others => '0'));
variable i : integer;
begin
for i in 0 to 1023 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := TempWord;
end loop;
return Result;
end function;
procedure test_1(
signal resetb : out std_logic;
signal en_i, we_i, en_d, we_d : out std_logic;
signal ben_i, ben_d : out std_logic_vector(7 downto 0);
signal addr_i, addr_d : inout std_logic_vector(31 downto 0);
signal di_i, di_d : inout std_logic_vector(63 downto 0)
-- signal do : out std_logic_vector(63 downto 0)
) is
variable addri_tmp, addrd_tmp : integer;
variable naddri_line, addri_line, datai_line : line;
variable naddrd_line, addrd_line, datad_line : line;
constant data_unsigned : unsigned(63 downto 0) :=
X"DEADBEEFBAADC0DE";
begin
reset(resetb, en_i, we_i, en_d, we_d, ben_i, ben_d);
--wait until rising_edge(resetb_tb);
--wait until rising_edge(clk_tb);
write(output, lf & "==============================================" & lf);
write(output, "(II) Test 1: Expected Behaviour:" & lf);
write(output, " 1. Instruction Address increment by 0x8 for each iteration" & lf);
write(output, " 2. Writes 0xDEADBEEFBAADC0DE every iteration" & lf);
write(output, " 3. Writes to all 8 bytes" & lf);
write(output, "==============================================" & lf);
wait until rising_edge(clk);
for i in 0 to 15 loop
-- Write 0xDEADBEEFBAADC0DE to address 0x0000000, 0x00000008, ...
addri_tmp := i * 8;
addr_i <= std_logic_vector(to_unsigned(addri_tmp, 32));
di_i <= std_logic_vector(data_unsigned);
en_i <= '1'; we_i <= '1';
ben_i <= (others => '0');
-- Display some info
display : if (i /= 0) then
hwrite(naddri_line, std_logic_vector(to_unsigned(addri_tmp, 32)));
hwrite(addri_line, addr_i);
hwrite(datai_line, do_i);
report lf & "(TT) Test 1 Iter " & integer'image(i-1) & lf &
"(TT) Addr in = 0x" & naddri_line.all & lf &
"(TT) Addr = 0x" & addri_line.all & lf &
"(TT) Data = 0x" & datai_line.all severity note;
deallocate(naddri_line);
deallocate(addri_line);
deallocate(datai_line);
end if display;
-- Wait a clock
wait until rising_edge(clk);
end loop;
end procedure test_1;
procedure test_2(
signal resetb : out std_logic;
signal en_i, we_i, en_d, we_d : out std_logic;
signal ben_i, ben_d : out std_logic_vector(7 downto 0);
signal addr_i, addr_d : inout std_logic_vector(31 downto 0);
signal di_i, di_d : inout std_logic_vector(63 downto 0)
-- signal do : out std_logic_vector(63 downto 0)
) is
variable addri_tmp, addrd_tmp : integer;
variable naddri_line, addri_line, datai_line : line;
variable naddrd_line, addrd_line, datad_line : line;
constant data_unsigned : unsigned(63 downto 0) :=
X"BADA661ECAFEF00D";
begin
reset(resetb, en_i, we_i, en_d, we_d, ben_i, ben_d);
--wait until rising_edge(resetb_tb);
--wait until rising_edge(clk_tb);
write(output, lf & "==============================================" & lf);
write(output, "(II) Test 2: Expected Behaviour:" & lf);
write(output, " 1. Instruction Address increment by 0x8 for each iteration" & lf);
write(output, " 2. Writes 0xBADA661ECAFEF00D every iteration" & lf);
write(output, " 3. Writes to all 8 bytes" & lf);
write(output, " 4. At the same time, Data Address increment by 0x8 for each iteration" & lf);
write(output, " 5. The two ports should give identical outputs" & lf);
write(output, "==============================================" & lf);
wait until rising_edge(clk);
for i in 0 to 15 loop
-- Write 0xBADA661ECAFEF00D to address 0x0000000, 0x00000008, ...
addri_tmp := i * 8;
addr_i <= std_logic_vector(to_unsigned(addri_tmp, 32));
di_i <= std_logic_vector(data_unsigned);
en_i <= '1'; we_i <= '1';
ben_i <= (others => '0');
addrd_tmp := i * 8;
addr_d <= std_logic_vector(to_unsigned(addrd_tmp, 32));
en_d <= '1'; we_d <= '0';
ben_d <= (others => '0');
-- Display some info
display : if (i /= 0) then
hwrite(naddri_line, std_logic_vector(to_unsigned(addri_tmp, 32)));
hwrite(addri_line, addr_i);
hwrite(datai_line, do_i);
hwrite(naddrd_line, std_logic_vector(to_unsigned(addrd_tmp, 32)));
hwrite(addrd_line, addr_d);
hwrite(datad_line, do_d);
report lf & "(TT) Test 2 Iter " & integer'image(i-1) & lf &
"(TT) I. Addr in = 0x" & naddri_line.all & lf &
"(TT) I. Addr = 0x" & addri_line.all & lf &
"(TT) I. Data = 0x" & datai_line.all & lf &
"(TT) D. Addr in = 0x" & naddrd_line.all & lf &
"(TT) D. Addr = 0x" & addrd_line.all & lf &
"(TT) D. Data = 0x" & datad_line.all severity note;
deallocate(naddri_line);
deallocate(addri_line);
deallocate(datai_line);
deallocate(naddrd_line);
deallocate(addrd_line);
deallocate(datad_line);
end if display;
-- Wait a clock
wait until rising_edge(clk);
end loop;
end procedure test_2;
procedure test_3(
signal resetb : out std_logic;
signal en_i, we_i, en_d, we_d : out std_logic;
signal ben_i, ben_d : out std_logic_vector(7 downto 0);
signal addr_i, addr_d : inout std_logic_vector(31 downto 0);
signal di_i, di_d : inout std_logic_vector(63 downto 0)
-- signal do : out std_logic_vector(63 downto 0)
) is
variable addri_tmp, addrd_tmp : integer;
variable naddri_line, addri_line, datai_line : line;
variable naddrd_line, addrd_line, datad_line : line;
constant data_unsigned : unsigned(63 downto 0) :=
X"0FF1CECAFEBADD06";
begin
reset(resetb, en_i, we_i, en_d, we_d, ben_i, ben_d);
--wait until rising_edge(resetb_tb);
--wait until rising_edge(clk_tb);
write(output, lf & "==============================================" & lf);
write(output, "(II) Test 3: Expected Behaviour:" & lf);
write(output, " 1. Instruction Address increment by 0x8 for each iteration" & lf);
write(output, " 2. Writes 0x0FF1CECAFEBADF00D every iteration" & lf);
write(output, " 3. Writes only high 4 bytes" & lf);
write(output, " 4. At the same time, Data Address increment by 0x8 for each iteration" & lf);
write(output, " 5. The two ports should give identical outputs" & lf);
write(output, "==============================================" & lf);
wait until rising_edge(clk);
for i in 0 to 15 loop
-- Write 0x0FF1CECAFEBADF00D to address 0x0000000, 0x00000008, ...
addri_tmp := i * 8;
addr_i <= std_logic_vector(to_unsigned(addri_tmp, 32));
di_i <= std_logic_vector(data_unsigned);
en_i <= '1'; we_i <= '1';
ben_i(7 downto 4) <= (others => '0');
addrd_tmp := i * 8;
addr_d <= std_logic_vector(to_unsigned(addrd_tmp, 32));
en_d <= '1'; we_d <= '0';
ben_d <= (others => '0');
-- Display some info
display : if (i /= 0) then
hwrite(naddri_line, std_logic_vector(to_unsigned(addri_tmp, 32)));
hwrite(addri_line, addr_i);
hwrite(datai_line, do_i);
hwrite(naddrd_line, std_logic_vector(to_unsigned(addrd_tmp, 32)));
hwrite(addrd_line, addr_d);
hwrite(datad_line, do_d);
report lf & "(TT) Test 3 Iter " & integer'image(i-1) & lf &
"(TT) I. Addr in = 0x" & naddri_line.all & lf &
"(TT) I. Addr = 0x" & addri_line.all & lf &
"(TT) I. Data = 0x" & datai_line.all & lf &
"(TT) D. Addr in = 0x" & naddrd_line.all & lf &
"(TT) D. Addr = 0x" & addrd_line.all & lf &
"(TT) D. Data = 0x" & datad_line.all severity note;
deallocate(naddri_line);
deallocate(addri_line);
deallocate(datai_line);
deallocate(naddrd_line);
deallocate(addrd_line);
deallocate(datad_line);
end if display;
-- Wait a clock
wait until rising_edge(clk);
end loop;
end procedure test_3;
begin
UUT : MMU port map(
clk => clk, resetb => resetb,
we_i => we_i, en_i => en_i,
addr_i => addr_i(31 downto 3), ben_i => ben_i,
di_i => di_i, do_i => do_i,
we_d => we_d, en_d => en_d,
addr_d => addr_d(31 downto 3), ben_d => ben_d,
di_d => di_d, do_d => do_d
);
clk_generation : process
begin
if (not END_SIMULATION) then
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
else
wait;
end if;
end process clk_generation;
stimulus : process
begin
-- test_1(resetb, en_i, we_i, en_d, we_d,
-- ben_i, ben_d, addr_i, addr_d,
-- di_i, di_d);
-- test_2(resetb, en_i, we_i, en_d, we_d,
-- ben_i, ben_d, addr_i, addr_d,
-- di_i, di_d);
test_3(resetb, en_i, we_i, en_d, we_d,
ben_i, ben_d, addr_i, addr_d,
di_i, di_d);
-- End Simulation
END_SIMULATION := true;
wait;
-- assert false report "Simulation Ended" severity failure;
end process stimulus;
end architecture behavioral;
| gpl-3.0 | 5c5cf02cd611521451f4359eccc1aecb | 0.56651 | 3.23564 | false | true | false | false |
wfjm/w11 | rtl/bplib/bpgen/rgbdrv_3x2mux.vhd | 1 | 2,915 | -- $Id: rgbdrv_3x2mux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_3x2mux - syn
-- Description: rgbled driver: mux three 2bit inputs
--
-- Dependencies: xlib/iob_reg_o_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version (derived from rgbdrv_3x4mux)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv2; -- red data
DATG : in slv2; -- green data
DATB : in slv2; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3 -- pad-o: rgb led 1
);
end rgbdrv_3x2mux;
architecture syn of rgbdrv_3x2mux is
signal R_LED : slv4 := "0001"; -- keep 4 states to keep brightness !
signal R_COL : slv3 := "001";
signal R_DIM : slbit := '1';
signal RGB0 : slv3 := (others=>'0');
signal RGB1 : slv3 := (others=>'0');
begin
IOB_RGB0: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0);
IOB_RGB1: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_LED <= "0001";
R_COL <= "001";
R_DIM <= '1';
else
if CE_USEC = '1' then
R_DIM <= not R_DIM;
if R_DIM = '1' then
R_COL <= R_COL(1) & R_COL(0) & R_COL(2);
if R_COL(2) = '1' then
R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3);
end if;
end if;
end if;
end if;
end if;
end process proc_regs;
proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB)
begin
RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0);
RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0);
RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0);
RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1);
RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1);
RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1);
end process proc_mux;
end syn;
| gpl-3.0 | e0f25b35f5cb313d72d997fe1b8e04a9 | 0.50223 | 2.998971 | false | false | false | false |
nanomolina/vhdl_examples | datapath/ALU.vhd | 2 | 1,364 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN std_logic_vector(2 DOWNTO 0);
zero: OUT std_logic;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCHITECTURE ALU_arq OF ALU IS
BEGIN
PROCESS(a, b, alucontrol)
VARIABLE temp: std_logic_vector(31 DOWNTO 0);
BEGIN
CASE alucontrol IS
WHEN "000" => temp:= a AND b;
WHEN "001" => temp:= a OR b;
WHEN "010" => temp:= std_logic_vector(unsigned(a) + unsigned(b));
WHEN "011" => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
WHEN "100" => temp:= a AND (NOT b);
WHEN "101" => temp:= a OR (NOT b);
WHEN "110" => temp:= std_logic_vector(unsigned(a) - unsigned(b));
WHEN "111" =>
IF a<b THEN
temp := x"00000001";
ELSE
temp := x"00000000";
END IF;
WHEN OTHERS => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
END CASE;
result <= temp;
IF temp=x"00000000" THEN
zero <= '1';
ELSIF temp=x"00000001" THEN
zero <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | bfdc175fdadbb24cc5ea919c379cdf05 | 0.515396 | 3.976676 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02300_good.vhd | 1 | 2,764 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02300_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of clock name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02300_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02300_good;
architecture Behavioral of CNE_02300_good is
begin
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 | b1fee7c55037ac09c0f2a174a24dbf1a | 0.473951 | 4.501629 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_InstructionROM_Device.vhdl | 1 | 15,785 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Wrapper module for up to 8 PicoBlaze ROM pages. All ROMs are
-- reprogrammable via JTAG_Loader
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- -----------------------------------------------------------------------------
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
use PoC.ocram.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
use L_PicoBlaze.pb_comp.all;
entity pb_InstructionROM_Device is
generic (
PAGES : POSITIVE := 1;
SOURCE_DIRECTORY : STRING := "";
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
ENABLE_JTAG_LOADER : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Fetch : in STD_LOGIC;
InstructionPointer : in T_PB_ADDRESS;
Instruction : out T_PB_INSTRUCTION;
Reboot : out STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
PageNumber : out STD_LOGIC_VECTOR(2 downto 0)
);
end;
architecture rtl of pb_InstructionROM_Device is
type T_PB_INSTRUCTION_VECTOR is array (NATURAL range <>) of T_PB_INSTRUCTION;
function reverse(vec : T_PB_INSTRUCTION_VECTOR) return T_PB_INSTRUCTION_VECTOR is
variable res : T_PB_INSTRUCTION_VECTOR(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high - i)) := vec(i);
end loop;
return res;
end function;
constant ENABLE_LOADER : BOOLEAN := ite((VENDOR = VENDOR_XILINX), ENABLE_JTAG_LOADER, FALSE);
constant FILENAME_PATTERN : STRING := ite((VENDOR = VENDOR_ALTERA), "main_Page#.mif", "main_Page#.hex");
constant REG_RW_PAGE_NUMBER : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_PageNumber : T_SLV_8 := (others => '0');
signal Reg_PageNumber_us : UNSIGNED(log2ceilnz(PAGES) - 1 downto 0) := (others => '0');
signal Page_Instructions : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal Pages_DataOut : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Clock : STD_LOGIC;
signal JTAGLoader_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Address : T_PB_ADDRESS;
signal JTAGLoader_WriteEnable : STD_LOGIC;
signal JTAGLoader_DataOut : T_PB_INSTRUCTION;
signal JTAGLoader_PB_Reset : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal Page_n_rst : STD_LOGIC;
signal Page_0_rst : STD_LOGIC;
signal Page_n_rst_d : STD_LOGIC := '0';
signal Page_0_rst_d : STD_LOGIC := '0';
signal Page_n_rst_re : STD_LOGIC;
signal Page_0_rst_fe : STD_LOGIC;
signal Reset_r : STD_LOGIC := '0';
begin
assert (PAGES <= 8) report "This ROM and JTAGLoader6 support 8 pages maximum." severity FAILURE;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset_r,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
-- Registers
process(Clock)
begin
if rising_edge(Clock) then
if (Reset_r = '1') then
Reg_PageNumber <= (others => '0');
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(0 downto 0) is
when REG_RW_PAGE_NUMBER => Reg_PageNumber <= AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_PageNumber)
begin
case AdrDec_ReadAddress(0 downto 0) IS
when REG_RW_PAGE_NUMBER => DataOut <= Reg_PageNumber;
when others => DataOut <= Reg_PageNumber;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
--
PageNumber <= Reg_PageNumber(PageNumber'range);
Reg_PageNumber_us <= unsigned(Reg_PageNumber(Reg_PageNumber_us'range));
Instruction <= Page_Instructions(to_index(Reg_PageNumber_us, Page_Instructions'length));
-- Reset control: keep PB in reset while programming, release after last ROM is written => reboot
Page_n_rst <= JTAGLoader_PB_Reset(PAGES - 1);
Page_0_rst <= JTAGLoader_PB_Reset(0);
Page_n_rst_d <= Page_n_rst when rising_edge(Clock);
Page_0_rst_d <= Page_0_rst when rising_edge(Clock);
Page_n_rst_re <= not Page_n_rst_d and Page_n_rst;
Page_0_rst_fe <= Page_0_rst_d and not Page_0_rst;
Reset_r <= ffrs(q => Reset_r, set => Page_n_rst_re, rst => Page_0_rst_fe) when rising_edge(Clock);
Reboot <= Reset_r;
genTemplate : if (str_length(SOURCE_DIRECTORY) = 0) generate
genPage0 : if (TRUE) generate
constant PAGE_NUMBER : NATURAL := 0;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page0
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage1 : if (PAGES > 1) generate
constant PAGE_NUMBER : NATURAL := 1;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page1
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage2 : if (PAGES > 2) generate
constant PAGE_NUMBER : NATURAL := 2;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page2
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage3 : if (PAGES > 3) generate
constant PAGE_NUMBER : NATURAL := 3;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page3
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage4 : if (PAGES > 4) generate
constant PAGE_NUMBER : NATURAL := 4;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page4
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage5 : if (PAGES > 5) generate
constant PAGE_NUMBER : NATURAL := 5;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page5
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage6 : if (PAGES > 6) generate
constant PAGE_NUMBER : NATURAL := 6;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page6
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage7 : if (PAGES > 7) generate
constant PAGE_NUMBER : NATURAL := 7;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page7
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
end generate;
genLoadFile : if (str_length(SOURCE_DIRECTORY) /= 0) generate
genPages : for i in 0 to PAGES - 1 generate
constant FILENAME : STRING := SOURCE_DIRECTORY & str_replace(FILENAME_PATTERN, "#", INTEGER'image(i));
signal Port1_Address : UNSIGNED(InstructionPointer'range);
signal Port2_Address : UNSIGNED(JTAGLoader_Address'range);
begin
assert PB_VERBOSE report "Loading ROM file: '" & FILENAME & "'" severity NOTE;
genOCROM : if (ENABLE_LOADER = FALSE) generate
Port1_Address <= unsigned(InstructionPointer);
genericMemory : ocrom_sp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk => Clock,
ce => Fetch,
a => Port1_Address,
q => Page_Instructions(i)
);
end generate;
genOCRAM : if (ENABLE_LOADER = TRUE) generate
Port1_Address <= unsigned(InstructionPointer);
Port2_Address <= unsigned(JTAGLoader_Address);
genericMemory : ocram_tdp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk1 => Clock,
ce1 => Fetch,
we1 => '0',
a1 => Port1_Address,
d1 => (others => '0'),
q1 => Page_Instructions(i),
clk2 => JTAGLoader_Clock,
ce2 => JTAGLoader_Enable(i),
we2 => JTAGLoader_WriteEnable,
a2 => Port2_Address,
d2 => JTAGLoader_DataOut,
q2 => Pages_DataOut(i)
);
end generate;
end generate;
end generate;
genNoJTAGLoader : if (ENABLE_LOADER = FALSE) generate
JTAGLoader_Clock <= '0';
JTAGLoader_Enable <= (others => '0');
JTAGLoader_Address <= (others => '0');
JTAGLoader_WriteEnable <= '0';
JTAGLoader_DataOut <= (others => '0');
end generate;
genJTAGLoader : if (ENABLE_LOADER = TRUE) generate
signal WorkAround_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal WorkAround_DataIn : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
begin
JTAGLoader : JTAGLoader6
generic map (
C_NUM_PICOBLAZE => PAGES,
C_ADDR_WIDTH => (others => T_PB_ADDRESS'length)
)
port map (
jtag_clk => JTAGLoader_Clock,
jtag_en => WorkAround_Enable,
jtag_din => JTAGLoader_DataOut,
jtag_addr => JTAGLoader_Address,
jtag_we => JTAGLoader_WriteEnable,
jtag_dout_0 => WorkAround_DataIn(imin(PAGES - 1, 0)),
jtag_dout_1 => WorkAround_DataIn(imin(PAGES - 1, 1)),
jtag_dout_2 => WorkAround_DataIn(imin(PAGES - 1, 2)),
jtag_dout_3 => WorkAround_DataIn(imin(PAGES - 1, 3)),
jtag_dout_4 => WorkAround_DataIn(imin(PAGES - 1, 4)),
jtag_dout_5 => WorkAround_DataIn(imin(PAGES - 1, 5)),
jtag_dout_6 => WorkAround_DataIn(imin(PAGES - 1, 6)),
jtag_dout_7 => WorkAround_DataIn(imin(PAGES - 1, 7)),
picoblaze_reset => JTAGLoader_PB_Reset
);
-- work around for a bug in JTAGLoader.exe
WorkAround_DataIn <= reverse(Pages_DataOut);
JTAGLoader_Enable <= reverse(WorkAround_Enable);
end generate;
end;
| apache-2.0 | bfa750659f11bb4a34401d799cdf4b85 | 0.59905 | 3.330169 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd | 1 | 17,418 | -- $Id: sys_w11a_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_arty - syn
-- Description: w11a design for arty (with dram via mig)
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/arty/sramif_mig_arty
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_arty
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x4mux
-- bplib/sysmon/sysmonx_rbus_arty
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1l 6842 9218 872 17.5 3210
-- 2019-05-19 1150 2017.2 xc7a35t-1l 6838 10574 923 17.5 3392 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1l 6706 10249 898 17.0 3380 +*buf
-- 2019-03-02 1116 2017.2 xc7a35t-1l 6625 10705 836 17.0 3218
-- 2019-02-02 1108 2018.3 xc7a35t-1l 6579 9839 819 17.0 3225
-- 2019-02-02 1108 2017.2 xc7a35t-1l 6575 9798 802 17.0 3182
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.2 use bufg_unisim
-- 2018-12-28 1096 1.1.1 setup reset for sramif_mig_arty
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce2c
-- 2018-11-18 1072 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft (derived from sys_w11a_br_arty)
------------------------------------------------------------------------------
--
-- w11a design for arty (using DDR3 memory via MIG)
-- w11a + rlink + serport
--
-- Usage of Arty switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows upper, RGB low nibble of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (3) kernel mode, non-wait, pri>0
-- (2) kernel mode, non-wait, pri=0
-- (1) supervisor mode
-- (0) user mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (3:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (3) MEM_ACT_W
-- (2) MEM_ACT_R
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR(11:08)
-- RGB_G DR( 7:04)
-- RGB_R DR( 3:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_arty.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_arty is -- top level
-- implements arty_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_arty;
architecture syn of sys_w11a_arty is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv4 := (others=>'0');
signal RGB_G : slv4 := (others=>'0');
signal RGB_B : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x4mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3
);
SMRB: sysmonx_rbus_arty -- always instantiated, needed for mig
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | eee36012fd5fad874e35879981707099 | 0.484327 | 3.223168 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys2/sys_tst_sram_n2.vhd | 1 | 10,255 | -- $Id: sys_tst_sram_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_n2 - syn
-- Description: test of nexys2 sram and its controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- tst_sram
-- bplib/nxcramlib/nx_cram_memctl_as
--
-- Test bench: tb/tb_tst_sram_n2
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 878 1881 96 1428 t 11.7 ns (85M)
-- 2014-08-13 581 14.7 131013 xc3s1200e-4 721 1515 64 1119 t 10.5 ns (95M)
-- 2011-12-21 442 13.1 O40d xc3s1200e-4 721 1510 64 1112 p 10.5 ns (95M)
-- 2010-12-31 352 12.1 M53d xc3s1200e-4 701 1426 36 901 p 10.5 ns (95M)
-- 2010-11-27 341 12.1 M53d xc3s1200e-4 674 1387 36 867 p 10.5 ns (95M)
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 665 1388 36 864 p 18.9 ns
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 667 1378 36 860 p 15.8 ns
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 659 1371 18 848 p 15.8 ns
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 663 1358 18 841 p 15.8 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-10 785 1.5.1 SWI(1) now XON
-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-12-23 444 1.2 remove clksys output hack
-- 2011-12-21 442 1.1.6 use rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_memctl_as now
-- 2011-11-23 432 1.1.4 now numeric_std clean; update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-08 390 1.1.2 use now sn_humanio
-- 2011-07-02 387 1.1.1 use bp_rs232_2line_iob now
-- 2010-12-31 352 1.1 port to rbv3
-- 2010-11-27 341 1.0.6 now proper clkdivce handling
-- 2010-11-22 339 1.0.5 use memctl delays from sys_conf constants
-- 2010-11-13 338 1.0.4 add DCM and O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.0.2 rename RRI_LAM->RB_LAM;
-- 2010-06-03 300 1.0.1 use default FAWIDTH for rri_core_serport
-- 2010-05-23 294 1.0 Initial version (derived from sys_tst_sram_s3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_sram_n2;
architecture syn of sys_tst_sram_n2 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv22 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"02"; -- nexys2
constant sysid_vers : slv8 := x"00";
begin
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
HIO : sn_humanio
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 22)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz
READ1DELAY => sys_conf_memctl_read1delay, -- was 2 "
WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 "
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
RB_SRES <= RB_SRES_TST; -- can be sres_or later...
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 | c0d6dae73ce0bb013cb164f778279afe | 0.506777 | 2.965587 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd | 1 | 1,772 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | 4c062acb7ca126bcb13843c6ae4d93bf | 0.563205 | 3.9117 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_rlim_slv.vhd | 1 | 3,790 | -- $Id: ib_rlim_slv.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_rlim_slv - syn
-- Description: ibus rate limter - slave
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-14 1131 1.1 RLIM_CEV now slv8
-- 2019-03-17 1123 1.0 Initial version
-- 2019-03-15 1122 0.1 First draft
--
-- Notes:
-- sel ce-scale rate in slv
-- 0 - 8 cycles
-- 1 1: 1 8 usec 125.0 kHz
-- 2 1: 2 16 usec 62.5 kHz
-- 3 1: 4 32 usec 31.2 kHz
-- 4 1: 8 64 usec 15.6 kHz
-- 5 1: 16 256 usec 3.9 kHz
-- 6 1: 32 512 usec 2.0 kHz
-- 7 1: 64 1024 usec 1.0 kHz
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
-- ----------------------------------------------------------------------------
entity ib_rlim_slv is -- ibus rate limter - slave
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
RLIM_CEV : in slv8; -- clock enable vector
SEL : in slv3; -- rlim select
START : in slbit; -- start timer
STOP : in slbit; -- stop timer
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end ib_rlim_slv;
architecture syn of ib_rlim_slv is
type regs_type is record -- state registers
cnt : slv3; -- counter
busy : slbit; -- busy
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- cnt
'0' -- busy
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RLIM_CEV, SEL, START, STOP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idone : slbit := '0';
variable ice : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ice := '0';
case SEL is
when "000" => ice := RLIM_CEV(0); -- every cycle
when "001" => ice := RLIM_CEV(1); -- every CE_USEC
when "010" => ice := RLIM_CEV(2); -- every 2nd CE_USEC
when "011" => ice := RLIM_CEV(3); -- every 4th CE_USEC
when "100" => ice := RLIM_CEV(4); -- every 8th CE_USEC
when "101" => ice := RLIM_CEV(5); -- every 32nd CE_USEC
when "110" => ice := RLIM_CEV(6); -- every 64th CE_USEC
when "111" => ice := RLIM_CEV(7); -- every 128th CE_USEC
when others => null;
end case;
idone := '0';
if STOP = '1' then
n.busy := '0';
idone := r.busy;
elsif START = '1' then
n.busy := '1';
n.cnt := "000";
elsif r.busy = '1' then
if ice = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111" then
n.busy := '0';
idone := '1';
end if;
end if;
end if;
N_REGS <= n;
DONE <= idone;
BUSY <= r.busy;
end process proc_next;
end syn;
| gpl-3.0 | 81ad3900ce93a10353fd7f63b7b86b73 | 0.46095 | 3.439201 | false | false | false | false |
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