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sjohann81/hf-risc | riscv/platform/rams/boot_ram.vhd | 1 | 22,558 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
RAMB16_S9_inst0 : RAMB16_S9
generic map (
INIT_00 => X"03630303230367138303836303b7139323932337b72323232313033763ef1317",
INIT_01 => X"6f330303036f13238337ef0323339303ef2323930303e3032303233333330303",
INIT_02 => X"830383ef036383132323232313676f63672393832383631313672337e31303b7",
INIT_03 => X"6313831363930313631313930323131363138323036f1303ef23036313671313",
INIT_04 => X"936f136f0303ef232303833313e3131363b313239363139383e3136313631363",
INIT_05 => X"63638313b76303936f13ef9303836f1363136f93136fe3939313031313331333",
INIT_06 => X"0303ef23239303e31313836f9313836f13130303ef2323036f1303ef230383e3",
INIT_07 => X"03830333838303ef23131393830383ef232323232323132313939337931313b3",
INIT_08 => X"b303b3676313670337e31303b7671303376f930303ef232303836fe393030323",
INIT_09 => X"139313136313836313839313639313138393232323136fa313676313336f2313",
INIT_0A => X"03833363230363e313933383038303ef23232323139313631363131383231393",
INIT_0B => X"9367138303831323636f136363036393ef23931313232323136f13e313671383",
INIT_0C => X"671313830383630313232323232313671383ef23232323231313932323136fa3",
INIT_0D => X"9393231303b313ef1337e3931303ef13639303ef13372383b313ef931337b303",
INIT_0E => X"936f13636313631393136f9313336393676313136f136f13ef13e3139303ef63",
INIT_0F => X"3767231303b723938323938337232393376f136f13671363e393933333636f93",
INIT_10 => X"ef133723b7ef3723232313931337b7676713371383ef2337b713133763133783",
INIT_11 => X"ef1337e393639363936393e39303ef23efef1337ef1337ef1337ef1337ef1337",
INIT_12 => X"37ef13376fb737ef13376703339313b7e393136fe713ef133793ef139313ef13",
INIT_13 => X"83ef630383ef2323133723339313efef1393379313ef139313ef13ef13376fb7",
INIT_14 => X"1303e31313efef13376fef133763036f932313e3136f938303ef231323631313",
INIT_15 => X"13ef13ef13376f133783e3138303ef13639303ef231323b3b703339323b71323",
INIT_16 => X"13ef133723ef139313ef13ef13376fef139303ef139313ef13ef133723ef1393",
INIT_17 => X"83ef131393ef13ef13376fef1313930383ef139313ef13ef133723ef139313ef",
INIT_18 => X"3cefefef23136f2303ef139313ef13ef133723ef139313ef13ef13376fef1337",
INIT_19 => X"200a4d2020506373200a0a2d64742020520a30204a202025780a00633834304c",
INIT_1A => X"65200a726577642072200a6c2f7568200a4f45657270200a0062200a79696175",
INIT_1B => X"0079252d3f506f740a00640a740a0a787861612020740a7820720a656c4d0a64",
INIT_1C => X"58d874747474747474747474744870e8741c0065640a0a250065650a2928670a",
INIT_1D => X"000000000000000000000000000000000000000000000000000000001074b474",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(31 downto 24),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(3));
RAMB16_S9_inst1 : RAMB16_S9
generic map (
INIT_00 => X"277a272524a780012424206c2745068428062064842a2c262e01274700000101",
INIT_01 => X"f007232527f00628266700252a05052700202205272574272627280707072325",
INIT_02 => X"242420f025924584202a2e2c0180f0848020862680260e85078020471c77a706",
INIT_03 => X"8205450414054507f8770705472204078c07262247f00426f022258e07800105",
INIT_04 => X"16f004f02326f02224254507070e07034e04030205940605249605820580056c",
INIT_05 => X"1284458616162604f086f0042545f0058405f00507f0fcf20205430407071787",
INIT_06 => X"2327f024260525d6060324f0050624f007062726f0242625f00727f02425255c",
INIT_07 => X"23254505232227002a8503042523230026282a2c2e2085240302061505060704",
INIT_08 => X"06c3868014078025470c77a70680752507f0842326f024262525f0fa82262780",
INIT_09 => X"050206049607459c074506049606040745842e2a2c01f00f0780140706f08007",
INIT_0A => X"24200584a02786940303052626222700222426280505876687f8870445200303",
INIT_0B => X"84800124242005809000059858270e06f02004070426222401f0876a87800124",
INIT_0C => X"8001052424206e27042220262a2801800120f020202e2c260506052a2801f08f",
INIT_0D => X"f6062406c58607f0051514060727f005180627f0051724c58607f08505170427",
INIT_0E => X"950005d60a05f8050607f0d5170584f680940507f005f004f0051a070627f064",
INIT_0F => X"0780a067a74620f62620e6264720280647f006f00680050496d5d6650766f096",
INIT_10 => X"f005172004f004222e200585011515800001070520f02405050601269a077726",
INIT_11 => X"f00515120600060206ce06c20627f022f0f00515f00515f00515f00515f00515",
INIT_12 => X"04f00515f00404f00515002707861716ec0607f08005f0051504f0050506f005",
INIT_13 => X"26f00c2726f0202207d700060607f0f00505150404f0050506f005f00515f004",
INIT_14 => X"5727100775f0f00515f0f005151a27000520871807f0862627f02005221ef607",
INIT_15 => X"06f005f0051500051525da072627f005987627f02405a0860526061680060722",
INIT_16 => X"05f0051524f0050506f005f00515f0f0050527f0050506f005f0051522f00505",
INIT_17 => X"45f0050605f005f00515f0f00586752726f0050506f005f0051522f0050506f0",
INIT_18 => X"4ef0f0f02401f00027f0050506f005f0051522f0050506f005f00515f0f00515",
INIT_19 => X"555b0053654d7465655b0020656c625349483239617c0030202500643935313e",
INIT_1A => X"637353642072207765775b6c206d65665b4d45786172205b006f425b006e6470",
INIT_1B => X"0074642d0a5220657700616e0a62002e25747262666977292865616465205300",
INIT_1C => X"090b08080808080808080808080b090a0809007820770030007820623a68746c",
INIT_1D => X"000000000000000000000000000000000000000000000000000000000c080908",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(23 downto 16),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(2));
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"81e5c181e105004181c101d741027404010511007d0191e181c107020010c100",
INIT_01 => X"5f6701c1811f77a141000001a1e5840100e1d1844101e601e181e1a7976701c1",
INIT_02 => X"4181c1df01050405a19111810100df0500d71607b60707050500a70307270603",
INIT_03 => X"a5300414b5c004f0e5f7079004e11400e60041e114df14411fc101e550000100",
INIT_04 => X"275f241f41819f61c101072743e3f0f3906710b10004460006a580a540a530b5",
INIT_05 => X"070506c6000606469f049f4601065f80a5501f9000df55f203140405076717e6",
INIT_06 => X"c1819fe161d001040346069fa046065ff716c1811fc1e1015ff781dfe10141e0",
INIT_07 => X"410105a7c1c18140610313050141c1c091b161e151c104d100414500a003f790",
INIT_08 => X"e506e500e60000070307170603001507035ff481c15f61c101415fb3120181a2",
INIT_09 => X"00940024e58014e500041015e50005d00505119181011fb71700c705c55f6617",
INIT_0A => X"81c1a006e40104829090e50141c18100c1e151d1060595e3f5e3051404819090",
INIT_0B => X"1400014181c10404e40000840501d5a01fe105f505119181011f95e3f5000141",
INIT_0C => X"008100c10141e44100b1a1911181810041c19fc1f1e1d111000105c1b1c15fa4",
INIT_0D => X"f605e1e006e4009f8500d7001781df00d770819f0700e106e4005f0487008701",
INIT_0E => X"1540000505f5e51010055f1517e50615000500059fe0df045fc0d7170081dfd6",
INIT_0F => X"0000e6070600d77607d746070107d720031f109f00000706061516d5b7b71f16",
INIT_10 => X"df870001001f0011918185c58100000007c10000811f110000064100e6170007",
INIT_11 => X"df4500d720d750d700e610e670419fa11f1f4500dfc5009f05005f05001f8500",
INIT_12 => X"001f45009f00009f45000707d7862700e650e75f04005f8500055fc100009fc1",
INIT_13 => X"015f0541015fd1e10703e6d400059f9f45040005051fc100005fc19f45001f00",
INIT_14 => X"2701e590f55f5fc500df5f05000701c007e11607f79f1601418fd1a0a106f605",
INIT_15 => X"005fc19f450040050001e6174181cf3006f7810fe150c6b60006d427068000e1",
INIT_16 => X"c11f0500a11fc100005fc19f45001f5f0705419fc10000dfc11f0500a11fc100",
INIT_17 => X"051fc100005fc19f45001fdf0706f581411fc100005fc19f0500a19fc10000df",
INIT_18 => X"55df9fdf11411fa7411fc100005fc19f8500a19fc10000dfc11f45009f1f0500",
INIT_19 => X"5d7500527820206c5d730025726f6f6f534632206e0000320030006561363200",
INIT_1A => X"7465500a77692f6f615d72006670785d640050746d6f5d50006f5d620061206c",
INIT_1B => X"0065203e004f45207200746f006f002e302079696f6e613a6873640063735200",
INIT_1C => X"0000000000000000000000000000000000000029286f00380029287900656865",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(15 downto 8),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(1));
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"00060000000000020101020001e11a84000002000100000000fd00e10046ff50",
INIT_01 => X"f900010000f61a0000006e0100001a006f00001a0101fa010000004000000100",
INIT_02 => X"030303fa0002000000020202fc00fb000000000000000000000000e1fe0040e1",
INIT_03 => X"0e070000000600ff0c0ffd00000000020a03000000fb0000f800000002000400",
INIT_04 => X"00f500fd0000eb000000000002f4ffff1c4000020316000100f80514060c060a",
INIT_05 => X"020000c700000000ec00e4000000f5070807fe0000f3fc0ffd000000fd000000",
INIT_06 => X"0000da00000200fe000000ed000000fbff000000df000000feff00e0000000fc",
INIT_07 => X"010100000001003d000000000101003e00000000000200000002c8000000ff40",
INIT_08 => X"0000000000000000e1fe0040e1000040e1e0ff0000cf00000000e2f800020100",
INIT_09 => X"000001000007000003000000000000020000000000fefffe0000000000fe0000",
INIT_0A => X"01014000000000fa010000010000001f000000000000fc06fb00fd0000000100",
INIT_0B => X"00000100000000000201000000000000e900000400000000fff9fafcf9000201",
INIT_0C => X"0001000001010000000000000000fe000200b100020000000001000000fdfbfe",
INIT_0D => X"0ffe0005000000f2ca00fc010000a302000000f5ca0000000000f700c9000000",
INIT_0E => X"0002000002ff00020000fe000000000000000000fd02f3019e07fc0001009f02",
INIT_0F => X"3300001500e100ff00000000e100001be1fa00fa00000000fe0000004000fe00",
INIT_10 => X"d8cd000040da40060406cbcaf90000000000400000c4004033f0ff0002bbb50e",
INIT_11 => X"d0d900f8040a0516050406fa0700b800b9d5d500d5d300d6d200d7d100d8cf00",
INIT_12 => X"30c9d800f04040cad700000000e30000f201f9f40000cedc0000b9000001c900",
INIT_13 => X"00a5020000a50000090000000000a8c4da00000000b0000001c000c7d900ef30",
INIT_14 => X"4000e005fd9ebadd00e1bbdd00000009000000fafffa000000ee000300003f00",
INIT_15 => X"01aa00b1d90012df0000fa000000e302000f00d6000000003b000000003b0000",
INIT_16 => X"00a9e0000094000001a400abd900d3b000000097000001a700afe000009a0000",
INIT_17 => X"008b0001009b00a2d900ca8b00000f00008f0000019f00a6e1000091000001a1",
INIT_18 => X"4cbcb8b400ffc100008500000195009ce200008700000197009fd900c6a0e200",
INIT_19 => X"202c0041742f5365202c007320616f43432d0032200000780038006662373300",
INIT_1A => X"656c4d006f74207264202c00692064202c005220206720200074202c0072626f",
INIT_1B => X"00736220004d457469006120006f002e3830206e726769006573640074654100",
INIT_1C => X"000000000000000000000000000000000000003a68720078003a68740078206e",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(7 downto 0),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(0));
end; --architecture logic
| gpl-2.0 | 382b40aa6eefbcbbcf535f8f229e32ee | 0.855351 | 3.943706 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd | 1 | 14,510 | -- $Id: ram_2swsr_xfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
architecture syn of ram_2swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
| gpl-3.0 | 6f36d20a6bb37e170f0b59324b03356f | 0.464438 | 3.24101 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd | 1 | 15,758 | -- $Id: sys_w11a_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_b3 - syn
-- Description: w11a test design for basys3
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_sys_w11a_b3
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 3011 5669 267 48.0 1906
-- 2019-05-19 1150 2017.2 xc7a35t-1 2968 6360 273 48.0 1963 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1 2835 6032 248 47.5 1879 +*buf
-- 2019-03-02 1116 2017.2 xc7a35t-1 2748 5725 186 47.5 1811 +ibtst
-- 2019-02-02 1108 2018.3 xc7a35t-1 2711 5910 170 47.5 1825
-- 2019-02-02 1108 2017.2 xc7a35t-1 2698 5636 170 47.5 1728
-- 2018-10-13 1055 2017.2 xc7a35t-1 2698 5636 170 47.5 1723 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2475 5282 138 47.5 1643 +KW11P
-- 2017-04-16 881 2016.4 xc7a35t-1 2412 5228 138 47.5 1608 +DEUNA
-- 2017-01-29 846 2016.4 xc7a35t-1 2362 5239 138 47.5 1619 +int24
-- 2016-05-26 768 2016.1 xc7a35t-1 2361 5203 138 47.5 1600 fsm+dsm=0
-- 2016-05-22 767 2016.1 xc7a35t-1 2362 5340 138 48.5 1660 fsm
-- 2016-03-29 756 2015.4 xc7a35t-1 2240 4518 138 48.5 1430 serport2
-- 2016-03-27 753 2015.4 xc7a35t-1 2131 4398 138 48.5 1362 meminf
-- 2016-03-13 742 2015.4 xc7a35t-1 2135 4420 162 48.5 1396 +XADC
-- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17%
-- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17%
-- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.5 use s7_cmt_1ce1ce
-- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.2 define rlink SYSID
-- 2016-03-18 745 2.2.1 hardwire XON=1
-- 2016-03-13 742 2.2 add sysmon_rbus
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-11 666 1.1.1 rearrange XON handling
-- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4)
------------------------------------------------------------------------------
--
-- w11a test design for basys3
-- w11a + rlink + serport
--
-- Usage of Basys 3 Switches, Buttons, LEDs
--
-- SWI(15:6): no function (only connected to sn_humanio_rbus)
-- SWI(5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- SWI(3): select LED display
-- 0 overall status
-- 1 DR emulation
-- SWI(2): unused-reserved (USB port select)
-- SWI(1): unused-reserved (XON, is hardwired to '1')
-- SWI(0): unused-reserved (serial port select)
--
-- LEDs if SWI(3) = 1
-- (15:0) DR emulation; shows R0 during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS depending on SWI(4)
-- DSP(3:0) shows DISPREG
-- DP(3:0) shows IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_b3 is -- top level
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_w11a_b3;
architecture syn of sys_w11a_b3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"06"; -- basys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 2,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | 98535c9c99a0e7661ddd85fdf56385f0 | 0.493844 | 3.144682 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/sys_conf1.vhd | 1 | 1,913 | -- $Id: sys_conf1.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_uart_cdinit : integer :=
(sys_conf_clksys/sys_conf_uart_defbaud)-1;
end package sys_conf;
| gpl-3.0 | c9d2092e0c40143443d850adadd45a63 | 0.550444 | 4.176856 | false | true | false | false |
wfjm/w11 | rtl/vlib/comlib/misc/gen_crc8_tbl.vhd | 1 | 1,544 | -- $Id: gen_crc8_tbl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (function)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.slvtypes.all;
use work.comlib.all;
entity gen_crc8_tbl is
end gen_crc8_tbl;
architecture sim of gen_crc8_tbl is
begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable nxt : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := slv(to_unsigned(i,8));
nxt := crc8_update(crc, dat);
write(oline, to_integer(unsigned(nxt)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;
if (i mod 8) = 7 then
writeline(output, oline);
end if;
end loop; -- i
wait;
end process;
end sim;
| gpl-3.0 | bd9141248c61b80127c976a7b43ef7b0 | 0.55829 | 3.393407 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2rlink/fx2rlinklib.vhd | 1 | 4,578 | -- $Id: fx2rlinklib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: fx2rlinklib
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.2.1 use rbaddr_ constants
-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
package fx2rlinklib is
--
-- core + fx2 interface combo
--
component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
end package fx2rlinklib;
| gpl-3.0 | 084c69c272ce80704ad4d0d6a0c4e33c | 0.533639 | 3.576563 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_tester.vhd | 1 | 12,017 | -- $Id: rbd_tester.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_tester - syn
-- Description: rbus dev: rbus tester
--
-- Dependencies: memlib/fifo_simple_dram
--
-- Test bench: rlink/tb/tb_rlink (used as test target)
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-08-31 590 14.7 131013 xc6slx16-2 74 162 16 73 s 5.8 ver 4.1
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2019-02-09 1109 4.2 use fifo_simple_dram (instead of _1c_dram_raw)
-- 2014-09-05 591 4.1 use new iface with 8 regs
-- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.4 now numeric_std clean
-- 2010-12-31 352 1.0.3 simplify irb_ack logic
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic
-- 2010-12-04 343 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/- Control register
-- 15 wchk r/w/- write check seen (cleared on data write)
-- 09:00 nbusy r/w/- busy cycles (for data,dinc,fifo,lnak)
-- 001 03:00 stat r/w/- status send to RB_STAT
-- 010 attn -/w/f Attn register: ping RB_LAM lines
-- 011 09:00 ncyc r/-/- return cycle length of last access
-- 100 data r/w/- Data register (plain read/write)
-- 101 dinc r/w/- Data register (autoinc and write check)
-- 110 fifo r/w/- Fifo interface register
-- 111 lnak r/w/- delayed ack deassert
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.rbdlib.all;
entity rbd_tester is -- rbus dev: rbus tester
-- complete rrirp_aif interface
generic (
RB_ADDR : slv16 := rbaddr_tester);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end entity rbd_tester;
architecture syn of rbd_tester is
constant awidth : positive := 4; -- fifo address width
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
constant rbaddr_stat : slv3 := "001"; -- stat address offset
constant rbaddr_attn : slv3 := "010"; -- attn address offset
constant rbaddr_ncyc : slv3 := "011"; -- ncyc address offset
constant rbaddr_data : slv3 := "100"; -- data address offset
constant rbaddr_dinc : slv3 := "101"; -- dinc address offset
constant rbaddr_fifo : slv3 := "110"; -- fifo address offset
constant rbaddr_lnak : slv3 := "111"; -- lnak address offset
constant cntl_rbf_wchk : integer := 15;
subtype cntl_rbf_nbusy is integer range 9 downto 0;
constant init_rbf_cntl : integer := 0;
constant init_rbf_data : integer := 1;
constant init_rbf_fifo : integer := 2;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
wchk : slbit; -- write check flag
stat : slv4; -- stat setting
nbusy : slv10; -- nbusy setting
data : slv16; -- data register
act_1 : slbit; -- rbsel and (re or we) in last cycle
ncyc : slv10; -- cycle length of last access
cntbusy : slv10; -- busy timer
cntcyc : slv10; -- cycle length counter
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- rbsel, wchk
(others=>'0'), -- stat
(others=>'0'), -- nbusy
(others=>'0'), -- data
'0', -- act_1
(others=>'0'), -- ncyc
(others=>'0'), -- cntbusy
(others=>'0') -- cntcyc
);
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_RESET : slbit := '0';
signal FIFO_CE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => awidth,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
CE => FIFO_CE,
WE => FIFO_WE,
DI => RB_MREQ.din,
DO => FIFO_DO,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL,
SIZE => FIFO_SIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irblam : slv16 := (others=>'0');
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable ififo_reset : slbit := '0';
variable isbusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irblam := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ififo_ce := '0';
ififo_we := '0';
ififo_reset := '0';
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
n.cntcyc := (others=>'0'); -- clear cycle length counter
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
if r.cntcyc /= cntcyc_max then -- if cycle counter < max
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter
end if;
end if;
irb_ack := irbena; -- ack all (some rejects later)
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we='1' then
n.wchk := RB_MREQ.din(cntl_rbf_wchk);
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
end if;
when rbaddr_stat =>
if RB_MREQ.we='1' then
n.stat := RB_MREQ.din(r.stat'range);
end if;
when rbaddr_attn =>
if RB_MREQ.we = '1' then -- on we
irblam := RB_MREQ.din; -- ping lam lines
elsif RB_MREQ.re = '1' then -- on re
irb_err := '1'; -- reject
end if;
when rbaddr_ncyc =>
if RB_MREQ.we = '1' then -- on we
irb_err := '1'; -- reject
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if RB_MREQ.we='1' and isbusy='0' then
n.wchk := '0';
n.data := RB_MREQ.din;
end if;
when rbaddr_dinc =>
irb_busy := irbena and isbusy;
if RB_MREQ.we = '1' then
if r.data /= RB_MREQ.din then
n.wchk := '1';
end if;
end if;
if (RB_MREQ.re='1' or RB_MREQ.we='1') and isbusy='0' then
n.data := slv(unsigned(r.data) + 1);
end if;
when rbaddr_fifo =>
irb_busy := irbena and isbusy;
if RB_MREQ.re='1' and isbusy='0' then
if FIFO_EMPTY = '1' then
irb_err := '1';
else
ififo_ce := '1';
end if;
end if;
if RB_MREQ.we='1' and isbusy='0' then
if FIFO_FULL = '1' then
irb_err := '1';
else
ififo_ce := '1';
ififo_we := '1';
end if;
end if;
when rbaddr_lnak =>
irb_ack := '0'; -- nak it
if isbusy = '1' then -- or do a delayed nak
irb_ack := irbena;
irb_busy := irbena;
end if;
when others => null;
end case;
end if;
-- rbus output driver
-- send a '0101...' pattern when selected and busy or err
-- send data only when busy=0 and err=0
-- this extra logic allows to debug rlink state machine
if r.rbsel = '1' then
irb_dout := "0101010101010101"; -- drive this pattern when selected
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
irb_dout := (others=>'0');
irb_dout(cntl_rbf_wchk) := r.wchk;
irb_dout(cntl_rbf_nbusy) := r.nbusy;
when rbaddr_stat =>
irb_dout := (others=>'0');
irb_dout(r.stat'range) := r.stat;
when rbaddr_attn => null;
when rbaddr_ncyc =>
irb_dout := (others=>'0');
irb_dout(r.cntcyc'range) := r.ncyc;
when rbaddr_data | rbaddr_dinc =>
irb_dout := r.data;
when rbaddr_fifo =>
if FIFO_EMPTY = '0' then
irb_dout := FIFO_DO;
end if;
when rbaddr_lnak => null;
when others => null;
end case;
end if;
end if;
-- init transactions
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then
if RB_MREQ.din(init_rbf_cntl) = '1' then
n.wchk := '0';
n.stat := (others=>'0');
n.nbusy := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_data) = '1' then
n.data := (others=>'0');
end if;
if RB_MREQ.din(init_rbf_fifo) = '1' then
ififo_reset := '1';
end if;
end if;
-- other transactions
if irbena='0' and r.act_1='1' then
n.ncyc := r.cntcyc;
end if;
n.act_1 := irbena;
N_REGS <= n;
FIFO_CE <= ififo_ce;
FIFO_WE <= ififo_we;
FIFO_RESET <= ififo_reset;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_LAM <= irblam;
RB_STAT <= r.stat;
end process proc_next;
end syn;
| gpl-3.0 | 5fc47b09d6ad1913cfdb1ee9604528ba | 0.492968 | 3.523014 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd | 1 | 1,879 | -- $Id: ram_1swsr_wfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_wfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w port, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_wfirst_gen;
architecture syn of ram_1swsr_wfirst_gen is
begin
UMEM: ram_1swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLK => CLK,
EN => EN,
WE => WE,
ADDR => ADDR,
DI => DI,
DO => DO
);
end syn;
| gpl-3.0 | faf2ddf86e4bbeb6d899a297cfb632ca | 0.523151 | 3.641473 | false | false | false | false |
abcsds/Micros | RS232Write_16/RightShift.vhd | 4 | 1,386 | library IEEE;
use IEEE.std_logic_1164.all;
entity RightShft is
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end RightShft;
architecture simple of RightShft is
signal Txn, Txp: std_logic;
begin
MUX: process(CTRL,DATAWR)
begin
case CTRL is
when "0000"=> Txn<= '1';-- Hold
when "0001"=> Txn<= '0';-- Start
when "0010"=> Txn<= DATAWR(0);-- DATARD(0)
when "0011"=> Txn<= DATAWR(1);-- DATARD(1)
when "0100"=> Txn<= DATAWR(2);-- DATARD(2)
when "0101"=> Txn<= DATAWR(3);-- DATARD(3)
when "0110"=> Txn<= DATAWR(4);-- DATARD(4)
when "0111"=> Txn<= DATAWR(5);-- DATARD(5)
when "1000"=> Txn<= DATAWR(6);-- DATARD(6)
when "1001"=> Txn<= DATAWR(7);-- DATARD(7)
when "1010"=> Txn<= '1';-- Stop
when others => Txn<= '1';
end case;
end process MUX;
FF: process(RST,CLK)
begin
if(RST='0')then
Txp<= '0';
elsif(CLK'event and CLK='1')then
Txp<= Txn;
end if;
end process FF;
Tx <= Txp;
end simple; | gpl-3.0 | 1b4d43675cfb50ccb06acd2d637eef44 | 0.455988 | 3.517766 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/JTAGLoader6.vhdl | 1 | 19,088 | -------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library UniSim;
use UniSim.vComponents.all;
--
library PoC;
use PoC.utils.all;
entity JTAGLoader6 is
generic (
C_NUM_PICOBLAZE : integer := 1;
C_JTAG_CHAIN : INTEGER := 2;
C_ADDR_WIDTH : T_INTVEC(0 to 7) := (others => 10)
);
port (
picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE - 1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE - 1 downto 0);
jtag_din : out std_logic_vector(17 downto 0);
jtag_addr : out std_logic_vector(imax(C_ADDR_WIDTH) - 1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in std_logic_vector(17 downto 0);
jtag_dout_1 : in std_logic_vector(17 downto 0);
jtag_dout_2 : in std_logic_vector(17 downto 0);
jtag_dout_3 : in std_logic_vector(17 downto 0);
jtag_dout_4 : in std_logic_vector(17 downto 0);
jtag_dout_5 : in std_logic_vector(17 downto 0);
jtag_dout_6 : in std_logic_vector(17 downto 0);
jtag_dout_7 : in std_logic_vector(17 downto 0)
);
end;
architecture rtl of JTAGLoader6 is
constant C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : INTEGER := 18;
constant C_BRAM_MAX_ADDR_WIDTH : POSITIVE := imax(C_ADDR_WIDTH);
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag : entity PoC.xil_BSCAN
generic map (
JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE
)
port map (
Reset => open,
RunTest => open,
sel => bram_ce_valid,
Capture => capture,
drck => drck,
Shift => shift,
Test_Clock => open,
Test_DataIn => shift_din,
Test_DataOut => shift_dout,
Test_ModeSelect => open,
Update => jtag_clk_int
);
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock : BUFG
port map (
I => drck,
O => shift_clk
);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= reverse(conv_std_logic_vector(C_NUM_PICOBLAZE-1,3)); -- work around for a bug in JTAGLoader.exe
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(0) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(1) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(2) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(3) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(4) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(5) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(6) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH(7) - 1, 5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end;
| apache-2.0 | 2ef26b8aee0007a58f877ccd1a688786 | 0.590947 | 3.670769 | false | false | false | false |
wfjm/w11 | rtl/bplib/sysmon/sysmonrbuslib.vhd | 1 | 9,848 | -- $Id: sysmonrbuslib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sysmonrbuslib
-- Description: generic (all with SYSMON or XADC)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-28 770 1.0.1 ensure to_unsigned() has a type natural argument
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package sysmonrbuslib is
subtype bv is bit_vector; -- vector
subtype bv16 is bit_vector(15 downto 0); -- 16 bit word
-- config reg #0 fields as bit masks (to be or'ed)
constant xadc_conf0_cavg: bv16 := x"8000"; -- 15 dis calib avr
constant xadc_conf0_avg_off: bv16 := x"0000"; -- 13:12 avr mode: off
constant xadc_conf0_avg_16: bv16 := x"1000"; -- " avr mode: 16 samples
constant xadc_conf0_avg_64: bv16 := x"2000"; -- " avr mode: 64 samples
constant xadc_conf0_avg_256: bv16 := x"3000"; -- " avr mode: 256 samples
constant xadc_conf0_mux: bv16 := x"0800"; -- 11 ena ext mux
constant xadc_conf0_bu: bv16 := x"0400"; -- 10 ena bipolar
constant xadc_conf0_ec: bv16 := x"0200"; -- 9 ena event mode
constant xadc_conf0_acq: bv16 := x"0100"; -- 8 ena inc settle
-- bit 4:0 holds channel select, not used, only for single channel mode
-- config reg #1 fields as bit masks (to be or'ed)
constant xadc_conf1_seq_default: bv16 := x"0000"; -- 15:12 seq mode: default
constant xadc_conf1_seq_spass: bv16 := x"1000"; -- " seq mode: single pass
constant xadc_conf1_seq_cont: bv16 := x"2000"; -- " seq mode: continuous
constant xadc_conf1_seq_schan: bv16 := x"3000"; -- " seq mode: single chan
constant xadc_conf1_dis_alm6: bv16 := x"0800"; -- 11 dis alm(6)
constant xadc_conf1_dis_alm5: bv16 := x"0400"; -- 10 dis alm(5)
constant xadc_conf1_dis_alm4: bv16 := x"0200"; -- 9 dis alm(4)
constant xadc_conf1_dis_alm3: bv16 := x"0100"; -- 8 dis alm(3)
constant xadc_conf1_cal3_supog: bv16 := x"0080"; -- 7 ena sup off+gain
constant xadc_conf1_cal2_supo: bv16 := x"0040"; -- 6 ena sup off
constant xadc_conf1_cal1_adcog: bv16 := x"0020"; -- 5 ena adc off+gain
constant xadc_conf1_cal0_adco: bv16 := x"0010"; -- 4 ena adc off
constant xadc_conf1_dis_alm2: bv16 := x"0008"; -- 3 dis alm(2)
constant xadc_conf1_dis_alm1: bv16 := x"0004"; -- 2 dis alm(1)
constant xadc_conf1_dis_alm0: bv16 := x"0002"; -- 1 dis alm(0)
constant xadc_conf1_dis_ot: bv16 := x"0001"; -- 0 dis ot
-- bit numbers for sequence registers (even word for build-in channels)
constant xadc_select_vccbram: integer := 14;
constant xadc_select_vrefn: integer := 13;
constant xadc_select_vrefp: integer := 12;
constant xadc_select_vpvn: integer := 11;
constant xadc_select_vccaux: integer := 10;
constant xadc_select_vccint: integer := 9;
constant xadc_select_temp: integer := 8;
constant xadc_select_vccoddr: integer := 7;
constant xadc_select_vccpaux: integer := 6;
constant xadc_select_vccpint: integer := 5;
constant xadc_select_calib: integer := 0;
-- defaults for plain build-in power monitoring
constant xadc_init_40_default: bv16 := xadc_conf0_cavg or
xadc_conf0_avg_16;
constant xadc_init_41_default: bv16 := xadc_conf1_seq_cont or
xadc_conf1_dis_alm6 or
xadc_conf1_dis_alm5 or
xadc_conf1_dis_alm4 or
xadc_conf1_cal3_supog or
xadc_conf1_cal2_supo or
xadc_conf1_cal1_adcog or
xadc_conf1_cal0_adco;
constant xadc_init_48_default: bv16 := (xadc_select_vccbram => '1',
xadc_select_vccaux => '1',
xadc_select_vccint => '1',
xadc_select_temp => '1',
xadc_select_calib => '1',
others => '0');
-- OT limit and reset are in general hardwired to 125 and 70 deg
-- the 4 lsbs of reg 53 contain the 'automatic shutdown enable'
-- must be set to "0011' to enable. done by default, seems prudent
constant xadc_init_53_default: bv16 := x"ca33"; -- OT LIMIT (125) + OT ENABLE
constant xadc_init_57_default: bv16 := x"ae40"; -- OT RESET (70)
constant xadc_init_4a_default: bv16 := (others => '0');
pure function xadc_temp2alim(temp : real) return bv16;
pure function xadc_svolt2alim (volt : real) return bv16;
component sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end component;
component sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12 -- xadc: die temp
);
end component;
component sysmonx_rbus_arty is -- XADC interface to rbus (arty pwrmon)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end component;
end package sysmonrbuslib;
-- ----------------------------------------------------------------------------
package body sysmonrbuslib is
-- -------------------------------------
pure function xadc_temp2alim(temp : real) return bv16 is
variable ival : natural := 0;
begin
ival := natural(((temp + 273.14) * 16.0 * 4096.0) / 503.975);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_temp2alim;
-- -------------------------------------
pure function xadc_svolt2alim (volt : real) return bv16 is
variable ival : natural := 0;
begin
ival := natural((volt * 16.0 * 4096.0) / 3.0);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_svolt2alim;
end package body sysmonrbuslib;
| gpl-3.0 | 265e76f67bdb84323ea062c78b4e7880 | 0.541227 | 3.42301 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_mmu.vhd | 1 | 14,453 | -- $Id: pdp11_mmu.vhd 1294 2022-09-07 14:21:20Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu - syn
-- Description: pdp11: mmu - memory management unit
--
-- Dependencies: pdp11_mmu_padr
-- pdp11_mmu_mmr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-09-05 1294 1,4.4 BUGFIX: correct trap and PDR A logic
-- 2022-08-13 1279 1.4.3 ssr->mmr rename
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
-- BUGFIX: set mmr0 trap_mmu even when traps disabled
-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-27 139 1.3.3 allow mmr1/2 tracing even with mmu_ena=0
-- 2008-04-25 138 1.3.2 add BRESET port, clear mmr0/3 with BRESET
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
-- cpacc handling; PADDR generation now on _vmbox
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ: in ib_mreq_type; -- ibus request
IB_SRES: out ib_sres_type -- ibus response
);
end pdp11_mmu;
architecture syn of pdp11_mmu is
constant ibaddr_mmr0 : slv16 := slv(to_unsigned(8#177572#,16));
constant ibaddr_mmr3 : slv16 := slv(to_unsigned(8#172516#,16));
constant mmr0_ibf_abo_nonres : integer := 15;
constant mmr0_ibf_abo_length : integer := 14;
constant mmr0_ibf_abo_rdonly : integer := 13;
constant mmr0_ibf_trap_mmu : integer := 12;
constant mmr0_ibf_ena_trap : integer := 9;
constant mmr0_ibf_inst_compl : integer := 7;
subtype mmr0_ibf_page_mode is integer range 6 downto 5;
constant mmr0_ibf_dspace : integer := 4;
subtype mmr0_ibf_page_num is integer range 3 downto 1;
constant mmr0_ibf_ena_mmu : integer := 0;
constant mmr3_ibf_ena_ubmap : integer := 5;
constant mmr3_ibf_ena_22bit : integer := 4;
constant mmr3_ibf_dspace_km : integer := 2;
constant mmr3_ibf_dspace_sm : integer := 1;
constant mmr3_ibf_dspace_um : integer := 0;
signal IBSEL_MMR0 : slbit := '0'; -- ibus select MMR0
signal IBSEL_MMR3 : slbit := '0'; -- ibus select MMR3
signal R_MMR0 : mmu_mmr0_type := mmu_mmr0_init;
signal N_MMR0 : mmu_mmr0_type := mmu_mmr0_init;
signal R_MMR3 : mmu_mmr3_type := mmu_mmr3_init;
signal APN : slv4 := "0000"; -- augmented page number (1+3 bit)
signal AIB_WE : slbit := '0'; -- update AIB
signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
signal TRACE : slbit := '0'; -- enable tracing in mmr1/2
signal DSPACE : slbit := '0'; -- use dspace
signal IB_SRES_PADR : ib_sres_type := ib_sres_init;
signal IB_SRES_MMR12 : ib_sres_type := ib_sres_init;
signal IB_SRES_MMR03 : ib_sres_type := ib_sres_init;
signal PARPDR : parpdr_type := parpdr_init;
begin
PADR : pdp11_mmu_padr port map (
CLK => CLK,
MODE => CNTL.mode,
APN => APN,
AIB_WE => AIB_WE,
AIB_SETA => AIB_SETA,
AIB_SETW => AIB_SETW,
PARPDR => PARPDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PADR);
MMR12 : pdp11_mmu_mmr12 port map (
CLK => CLK,
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMR12);
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_PADR,
IB_SRES_2 => IB_SRES_MMR12,
IB_SRES_3 => IB_SRES_MMR03,
IB_SRES_OR => IB_SRES);
SEL_MMR0 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR0
);
SEL_MMR3 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR3
);
proc_ibres : process (IBSEL_MMR0, IBSEL_MMR3, IB_MREQ, R_MMR0, R_MMR3)
variable mmr0out : slv16 := (others=>'0');
variable mmr3out : slv16 := (others=>'0');
begin
mmr0out := (others=>'0');
if IBSEL_MMR0 = '1' then
mmr0out(mmr0_ibf_abo_nonres) := R_MMR0.abo_nonres;
mmr0out(mmr0_ibf_abo_length) := R_MMR0.abo_length;
mmr0out(mmr0_ibf_abo_rdonly) := R_MMR0.abo_rdonly;
mmr0out(mmr0_ibf_trap_mmu) := R_MMR0.trap_mmu;
mmr0out(mmr0_ibf_ena_trap) := R_MMR0.ena_trap;
mmr0out(mmr0_ibf_inst_compl) := R_MMR0.inst_compl;
mmr0out(mmr0_ibf_page_mode) := R_MMR0.page_mode;
mmr0out(mmr0_ibf_dspace) := R_MMR0.dspace;
mmr0out(mmr0_ibf_page_num) := R_MMR0.page_num;
mmr0out(mmr0_ibf_ena_mmu) := R_MMR0.ena_mmu;
end if;
mmr3out := (others=>'0');
if IBSEL_MMR3 = '1' then
mmr3out(mmr3_ibf_ena_ubmap) := R_MMR3.ena_ubmap;
mmr3out(mmr3_ibf_ena_22bit) := R_MMR3.ena_22bit;
mmr3out(mmr3_ibf_dspace_km) := R_MMR3.dspace_km;
mmr3out(mmr3_ibf_dspace_sm) := R_MMR3.dspace_sm;
mmr3out(mmr3_ibf_dspace_um) := R_MMR3.dspace_um;
end if;
IB_SRES_MMR03.dout <= mmr0out or mmr3out;
IB_SRES_MMR03.ack <= (IBSEL_MMR0 or IBSEL_MMR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_MMR03.busy <= '0';
end process proc_ibres;
proc_mmr0 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_MMR0 <= mmu_mmr0_init;
else
R_MMR0 <= N_MMR0;
end if;
end if;
end process proc_mmr0;
proc_mmr3 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_MMR3 <= mmu_mmr3_init;
elsif IBSEL_MMR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_MMR3.ena_ubmap <= IB_MREQ.din(mmr3_ibf_ena_ubmap);
R_MMR3.ena_22bit <= IB_MREQ.din(mmr3_ibf_ena_22bit);
R_MMR3.dspace_km <= IB_MREQ.din(mmr3_ibf_dspace_km);
R_MMR3.dspace_sm <= IB_MREQ.din(mmr3_ibf_dspace_sm);
R_MMR3.dspace_um <= IB_MREQ.din(mmr3_ibf_dspace_um);
end if;
end if;
end if;
end process proc_mmr3;
proc_paddr : process (R_MMR0, R_MMR3, CNTL, PARPDR, VADDR)
variable ipaddrh : slv16 := (others=>'0');
variable dspace_ok : slbit := '0';
variable dspace_en : slbit := '0';
variable apf : slv3 := (others=>'0'); -- va: active page field
variable bn : slv7 := (others=>'0'); -- va: block number
variable iapn : slv4 := (others=>'0');-- augmented page number
begin
apf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
dspace_en := '0';
case CNTL.mode is
when "00" => dspace_en := R_MMR3.dspace_km;
when "01" => dspace_en := R_MMR3.dspace_sm;
when "11" => dspace_en := R_MMR3.dspace_um;
when others => null;
end case;
dspace_ok := CNTL.dspace and dspace_en;
iapn(3) := dspace_ok;
iapn(2 downto 0) := apf;
ipaddrh := slv(unsigned("000000000"&bn) + unsigned(PARPDR.paf));
DSPACE <= dspace_ok;
APN <= iapn;
PADDRH <= ipaddrh;
end process proc_paddr;
proc_nmmr0 : process (R_MMR0, R_MMR3, IB_MREQ, IBSEL_MMR0, DSPACE,
CNTL, MONI, PARPDR, VADDR)
variable nmmr0 : mmu_mmr0_type := mmu_mmr0_init;
variable apf : slv3 := (others=>'0');
variable bn : slv7 := (others=>'0');
variable abo_nonres : slbit := '0';
variable abo_length : slbit := '0';
variable abo_rdonly : slbit := '0';
variable mmr_freeze : slbit := '0';
variable doabort : slbit := '0';
variable dotrap : slbit := '0';
variable dotrace : slbit := '0';
variable iswrite : slbit := '0';
begin
nmmr0 := R_MMR0;
AIB_WE <= '0';
AIB_SETA <= '0';
AIB_SETW <= '0';
mmr_freeze := R_MMR0.abo_nonres or R_MMR0.abo_length or R_MMR0.abo_rdonly;
dotrace := not(CNTL.cacc or mmr_freeze);
iswrite := CNTL.wacc or CNTL.macc;
apf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
abo_nonres := '0';
abo_length := '0';
abo_rdonly := '0';
doabort := '0';
dotrap := '0';
if PARPDR.ed = '0' then -- ed=0: upward expansion
if unsigned(bn) > unsigned(PARPDR.plf) then
abo_length := '1';
end if;
else -- ed=0: downward expansion
if unsigned(bn) < unsigned(PARPDR.plf) then
abo_length := '1';
end if;
end if;
-- ACF decision logic
-- w11 has 4 memory cycle types, the ACF is based only on read or write
-- wacc='0' macc'0' : read cycle --> read
-- wacc='1' macc'0' : write cycle --> write
-- wacc='0' macc'1' : read part of rmw --> write
-- wacc='1' macc'1' : write part of rmw --> write
-- Depending of ACF the MMU aborts, queues a trap, sets A and W bit in PDR
-- ACF abort trap Comment
-- 000 nonres - non-resident: abort all accesses
-- 001 rdonly R read-only: abort on write, trap on read
-- 010 rdonly read-only: abort on write
-- 011 nonres - unused: abort all accesses
-- 100 - R+W read/write: no abort, trap on read or write
-- 101 - W read/write: no abort, trap on write
-- 110 - - read/write: no abort, no trap
-- 111 nonres - unused: abort all accesses
--
-- The PDR W bit is set for non-aborted write accesses
-- The PDR A bit is set if the trap condition is fulfilled and not aborted
case PARPDR.acf is -- evaluate accecc control field
when "000" => -- page non-resident
abo_nonres := '1';
when "001" => -- read-only; trap on read
if iswrite='1' then
abo_rdonly := '1';
end if;
dotrap := not iswrite;
when "010" => -- read-only
if iswrite='1' then
abo_rdonly := '1';
end if;
when "100" => -- read/write; trap on read&write
dotrap := '1';
when "101" => -- read/write; trap on write
dotrap := iswrite;
when "110" => null; -- read/write;
when others => -- unused codes: abort access
abo_nonres := '1';
end case;
if IBSEL_MMR0='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nmmr0.abo_nonres := IB_MREQ.din(mmr0_ibf_abo_nonres);
nmmr0.abo_length := IB_MREQ.din(mmr0_ibf_abo_length);
nmmr0.abo_rdonly := IB_MREQ.din(mmr0_ibf_abo_rdonly);
nmmr0.trap_mmu := IB_MREQ.din(mmr0_ibf_trap_mmu);
nmmr0.ena_trap := IB_MREQ.din(mmr0_ibf_ena_trap);
end if;
if IB_MREQ.be0 = '1' then
nmmr0.ena_mmu := IB_MREQ.din(mmr0_ibf_ena_mmu);
end if;
elsif nmmr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nmmr0.inst_compl := '0';
elsif MONI.idone = '1' then
nmmr0.inst_compl := '0'; -- disable instr.compl logic
end if;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if mmr_freeze = '0' then
nmmr0.abo_nonres := abo_nonres;
nmmr0.abo_length := abo_length;
nmmr0.abo_rdonly := abo_rdonly;
end if;
doabort := abo_nonres or abo_length or abo_rdonly;
if doabort = '0' then
AIB_SETA <= dotrap;
AIB_SETW <= iswrite;
end if;
if mmr_freeze = '0' then
nmmr0.dspace := DSPACE;
nmmr0.page_num := apf;
nmmr0.page_mode := CNTL.mode;
end if;
end if;
end if;
if CNTL.req='1' and R_MMR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then
nmmr0.trap_mmu := '1';
end if;
nmmr0.trace_prev := dotrace;
if MONI.trace_prev = '0' then
TRACE <= dotrace;
else
TRACE <= R_MMR0.trace_prev;
end if;
N_MMR0 <= nmmr0;
if R_MMR0.ena_mmu='1' and CNTL.cacc='0' then
STAT.vaok <= not doabort;
else
STAT.vaok <= '1';
end if;
if R_MMR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
R_MMR0.ena_trap='1' and R_MMR0.trap_mmu='0' and dotrap='1' then
STAT.trap <= '1';
else
STAT.trap <= '0';
end if;
STAT.ena_mmu <= R_MMR0.ena_mmu;
STAT.ena_22bit <= R_MMR3.ena_22bit;
STAT.ena_ubmap <= R_MMR3.ena_ubmap;
end process proc_nmmr0;
end syn;
| gpl-3.0 | 16a0712a635b6cb2b284c7edd18a1cac | 0.543693 | 3.14743 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_dl11.vhd | 1 | 11,572 | -- $Id: ibdr_dl11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-27 1140 1.3.3 drop rbuf.rrdy, set rbuf.[rx]size0 instead
-- 2019-04-24 1138 1.3.2 add rcsr.ir and xcsr.ir (intreq monitors)
-- 2019-04-14 1131 1.3.1 RLIM_CEV now slv8
-- 2019-04-07 1127 1.3 for dl11_buf compat: xbuf.val in bit 15 and 8;
-- use rbuf instead xbuf for rdry reporting; remove
-- maintenance mode; use ib_rlim_slv; drop CE_USEC
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
-- 2008-01-27 115 1.0.3 BUGFIX: set ilam when rbuf read by cpu;
-- add xdone and rrdy bits to rri xbuf read
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
-- 2008-01-20 112 1.0.1 use BRESET
-- 2008-01-05 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11;
architecture syn of ibdr_dl11 is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rbuf_ibf_rsize0: integer := 8;
constant rbuf_ibf_xsize0: integer := 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xir : integer := 5;
constant xbuf_ibf_xval : integer := 15;
constant xbuf_ibf_xval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0', -- rval,rintreq
'1', -- xrdy !! is set !!
'0', -- xie
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
begin
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- keep RLIM flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irrlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then -- rcsr write
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then
if r.rdone='1' and r.rie='0' then -- ie set while done=1
n.rintreq := '1'; -- request interrupt
end if;
else
n.rintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
idout(rcsr_ibf_rir) := r.rintreq;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := r.rbuf;
if ibrd = '1' then -- rbuf read
n.rintreq := '0'; -- cancel interrupt
end if;
if ibrd='1' and r.rdone='1' then
n.rval := '0'; -- clear rbuf valid
irrlimsta := '1'; -- start rx timer
ilam := '1'; -- request rb attention
end if;
else -- rri ---------------------
idout(rbuf_ibf_rsize0) := r.rval; -- rbuf occupied when rval=1
idout(rbuf_ibf_xsize0) := not r.xrdy; -- xbuf empty when xrdy=1
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(rbuf_ibf_data);
n.rval := '1'; -- set rbuf valid
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else
n.xintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(xcsr_ibf_xir) := r.xintreq;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
ilam := '1';
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_xval8) := not r.xrdy;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
n.xintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
if (RRLIM_BUSY or (not r.rval)) = '1' then -- busy or no data
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- clear pending interrupts
else -- not busy and data valid
n.rdone := '1'; -- set done
if r.rdone='0' and r.rie='1' then -- done going 0->1 and ie=1
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
N_REGS <= n;
RRLIM_START <= irrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
| gpl-3.0 | 79fad87bc63feacddace49daa325fa6c | 0.459212 | 3.70304 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_usracc.vhd | 1 | 2,546 | -- $Id: rbd_usracc.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_usracc - syn
-- Description: rbus dev: return usr_access register (bitfile+jtag timestamp)
--
-- Dependencies: xlib/usr_access_unisim
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 ua0 r/-/- use_accress lsb
-- 1 ua1 r/-/- use_accress msb
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.rblib.all;
use work.rbdlib.all;
entity rbd_usracc is -- rbus dev: return usr_access register
generic (
RB_ADDR : slv16 := rbaddr_usracc);
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_usracc;
architecture syn of rbd_usracc is
signal R_SEL : slbit := '0';
signal DATA : slv32 := (others=>'0');
begin
RBSEL : rb_sel
generic map (
RB_ADDR => RB_ADDR,
SAWIDTH => 1)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
SEL => R_SEL
);
UA : usr_access_unisim
port map (DATA => DATA);
proc_next : process (R_SEL, RB_MREQ, DATA)
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
irb_ack := '0';
irb_err := '0';
irb_dout := (others=>'0');
-- rbus transactions
if R_SEL = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
case (RB_MREQ.addr(0)) is
when '0' => irb_dout := DATA(15 downto 0);
when '1' => irb_dout := DATA(31 downto 16);
when others => null;
end case;
end if;
end if;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= '0';
end process proc_next;
end syn;
| gpl-3.0 | 2e0c5b82f7a78cff9624980372e6ecd6 | 0.511783 | 3.297927 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_reg_o_gen.vhd | 1 | 1,629 | -- $Id: iob_reg_o_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_o_gen - syn
-- Description: Registered IOB, output only, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_o_gen;
architecture syn of iob_reg_o_gen is
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INIT);
attribute iob : string;
attribute iob of R_DO : signal is "true";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
PAD <= R_DO;
end syn;
| gpl-3.0 | 5705938aabe95de72565546e092d2884 | 0.527931 | 3.400835 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_statleds.vhd | 1 | 2,693 | -- $Id: pdp11_statleds.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_statleds - syn
-- Description: pdp11: status leds
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-20 649 1.0 Initial version
------------------------------------------------------------------------------
-- LED (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_statleds is -- status leds
port (
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end pdp11_statleds;
architecture syn of pdp11_statleds is
begin
proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_EXP.dp_psw)
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
iled(7) := MEM_ACT_W;
iled(6) := MEM_ACT_R;
iled(5) := CP_STAT.cmdbusy;
if CP_STAT.cpugo = '1' then
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '1' then
iled(2) := '1';
elsif unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
iled(3) := '1';
else
iled(4) := '1';
end if;
when c_psw_smode =>
iled(1) := '1';
when c_psw_umode =>
iled(0) := '1';
when others => null;
end case;
else
iled(4) := '1';
iled(3 downto 0) := CP_STAT.cpurust;
end if;
STATLEDS <= iled;
end process proc_led;
end syn;
| gpl-3.0 | 25b6f50babb14217eb6ea304d6488dd6 | 0.47902 | 3.430573 | false | false | false | false |
nanomolina/vhdl_examples | signext/signext.vhd | 4 | 667 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY signext IS
PORT (a: IN std_logic_vector(0 TO 15);
y: OUT std_logic_vector(0 TO 31));
END signext;
ARCHITECTURE signext_arq OF signext IS
BEGIN
PROCESS(a)
VARIABLE temp: std_logic_vector(0 TO 31);
BEGIN
IF (a(0)='0') THEN
FOR i IN 0 TO 15 LOOP
temp(i) := '0';
END LOOP;
ELSIF (a(0)='1') THEN
FOR i IN 0 TO 15 LOOP
temp(i) := '1';
END LOOP;
END IF;
FOR i IN 16 TO 31 LOOP
temp(i) := a(i-16);
END LOOP;
y <= temp;
END PROCESS;
END signext_arq;
| gpl-3.0 | 561436e6148195419cd55a8daa4887a8 | 0.496252 | 3.473958 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd | 1 | 9,319 | -- $Id: ram_1swsr_xfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_xfirst_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_xfirst_gen_unisim;
architecture syn of ram_1swsr_xfirst_gen_unisim is
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => O"000000000000",
SRVAL => O"000000000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(36*i+31 downto 36*i),
DOP => L_DO(36*i+35 downto 36*i+32),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(36*i+31 downto 36*i),
DIP => L_DI(36*i+35 downto 36*i+32),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_09_S36;
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => X"00000000",
SRVAL => X"00000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(32*i+31 downto 32*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(32*i+31 downto 32*i),
DIP => "0000",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_09_S32;
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => O"000000",
SRVAL => O"000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(18*i+15 downto 18*i),
DOP => L_DO(18*i+17 downto 18*i+16),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(18*i+15 downto 18*i),
DIP => L_DI(18*i+17 downto 18*i+16),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_10_S18;
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => X"0000",
SRVAL => X"0000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(16*i+15 downto 16*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(16*i+15 downto 16*i),
DIP => "00",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_10_S16;
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => O"000",
SRVAL => O"000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(9*i+7 downto 9*i),
DOP => L_DO(9*i+8 downto 9*i+8),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(9*i+7 downto 9*i),
DIP => L_DI(9*i+8 downto 9*i+8),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_11_S9;
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => X"00",
SRVAL => X"00",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(8*i+7 downto 8*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(8*i+7 downto 8*i),
DIP => "0",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_11_S8;
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4
generic map (
INIT => X"0",
SRVAL => X"0",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(4*i+3 downto 4*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(4*i+3 downto 4*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_12_S4;
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2
generic map (
INIT => "00",
SRVAL => "00",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(2*i+1 downto 2*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(2*i+1 downto 2*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
DO <= L_DO(DO'range);
end generate AW_13_S2;
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1
generic map (
INIT => "0",
SRVAL => "0",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(i downto i),
ADDR => ADDR,
CLK => CLK,
DI => DI(i downto i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_14_S1;
end syn;
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
| gpl-3.0 | 36065132b793df5b96e22f1a446bb526 | 0.478163 | 3.287125 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dspmux.vhd | 1 | 3,056 | -- $Id: pdp11_dspmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dspmux - syn
-- Description: pdp11: hio dsp mux
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-22 650 1.0 Initial version
-- 2015-02-21 649 0.1 First draft
------------------------------------------------------------------------------
-- selects display data
-- 4 Digit Displays
-- SEL(1:0) 00 ABCLKDIV
-- 01 DM_STAT_EXP.dp_pc
-- 10 DISPREG
-- 11 DM_STAT_EXP.dp_dsrc
--
-- 8 Digit Displays
-- SEL(1) select DSP(7:4)
-- 0 ABCLKDIV
-- 1 DM_STAT_EXP.dp_pc
-- SEL(0) select DSP(7:4)
-- 0 DISPREG
-- 1 DM_STAT_EXP.dp_dsrc
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dspmux is -- hio dsp mux
generic (
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end pdp11_dspmux;
architecture syn of pdp11_dspmux is
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
begin
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity failure;
proc_mux: process (SEL, ABCLKDIV, DM_STAT_EXP, DISPREG)
variable idat : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
idat := (others=>'0');
if DCWIDTH = 2 then
case SEL is
when "00" =>
idat(dspdat_lsb) := ABCLKDIV;
when "01" =>
idat(dspdat_lsb) := DM_STAT_EXP.dp_pc;
when "10" =>
idat(dspdat_lsb) := DISPREG;
when "11" =>
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
else
if SEL(1) = '0' then
idat(dspdat_msb) := ABCLKDIV;
else
idat(dspdat_msb) := DM_STAT_EXP.dp_pc;
end if;
if SEL(0) = '0' then
idat(dspdat_lsb) := DISPREG;
else
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
end if;
end if;
DSP_DAT <= idat;
end process proc_mux;
end syn;
| gpl-3.0 | 93e310c48e72917abc3993e574195b3e | 0.507853 | 3.488584 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop2_n3.vhd | 1 | 4,242 | -- $Id: tb_tst_serloop2_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n3 - sim
-- Description: Test bench for sys_tst_serloop2_n3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0.1 temporarily use with ser=usr=100 MHz
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop2_n3 is
end tb_tst_serloop2_n3;
architecture sim of tb_tst_serloop2_n3 is
signal CLK100 : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- currently 1-to-1
CLKFX_MULTIPLY => 1,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLK100,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- currently 1-to-1
CLKFX_MULTIPLY => 1,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLK100,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 605e11a5a2aaa22242cc5f1b83c35588 | 0.502122 | 3.027837 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/gray_cnt_4.vhd | 1 | 3,292 | -- $Id: gray_cnt_4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007--2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
architecture syn of gray_cnt_4 is
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
-- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
-- this code up to 2016.2. With 2016.3 and later it is converted into a
-- 31 state one-hot fsm, unless explicitely suppressed
attribute fsm_encoding : string;
attribute fsm_encoding of R_DATA : signal is "none";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
| gpl-3.0 | a3cc205b31f8820e13040c81703b000f | 0.520352 | 3.321897 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01900_good.vhd | 1 | 2,978 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01900_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of registered signals: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01900_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D_re : out std_logic -- Rising edge of My_Sig
);
end CNE_01900_good;
architecture Behavioral of CNE_01900_good is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D_re <= D_r1 and not D_r2;
end Behavioral;
--CODE | gpl-3.0 | 488efdb0210a01cecad0ec0bc07f3387 | 0.487911 | 4.353801 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd | 1 | 8,675 | -- $Id: tst_rlink_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_rlink_cuff - syn
-- Description: tester for rlink over cuff
--
-- Dependencies: vlib/rlink/rlink_core8
-- vlib/rlink/rlink_rlbmux
-- vlib/serport/serport_1clock
-- ../tst_rlink/rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.2.1 define rlink SYSID
-- 2015-04-11 666 1.2 rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity tst_rlink_cuff is -- tester for rlink over cuff
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
SWI : in slv8; -- hio: switches
BTN : in slv4; -- hio: buttons
LED : out slv8; -- hio: leds
DSP_DAT : out slv16; -- hio: display data
DSP_DP : out slv4; -- hio: display decimal points
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RTS_N : out slbit; -- receive rts (uart view, act.low)
CTS_N : in slbit; -- transmit cts (uart view, act.low)
FX2_RXDATA : in slv8; -- fx2: receiver data out
FX2_RXVAL : in slbit; -- fx2: receiver data valid
FX2_RXHOLD : out slbit; -- fx2: receiver data hold
FX2_TXDATA : out slv8; -- fx2: transmit data in
FX2_TXENA : out slbit; -- fx2: transmit data enable
FX2_TXBUSY : in slbit; -- fx2: transmit busy
FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
);
end tst_rlink_cuff;
architecture syn of tst_rlink_cuff is
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_TX2ENA_L : slbit := '0';
signal FX2_TXENA_L : slbit := '0';
signal FX2_TX2ENA_LED : slbit := '0';
signal FX2_TXENA_LED : slbit := '0';
signal FX2_RXVAL_LED : slbit := '0';
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
constant sysid_proj : slv16 := x"0103"; -- tst_rlink_cuff
constant sysid_board : slv8 := x"00"; -- generic
constant sysid_vers : slv8 := x"00";
begin
RLCORE : rlink_core8
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon)
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
ESCXON => SWI(1),
ESCFILL => '0',
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLBMUX : rlink_rlbmux
port map (
SEL => SWI(2),
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA_L,
P1_TXBUSY => FX2_TXBUSY
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXSD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_TOP,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
TX2ENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TX2ENA_L,
POUT => FX2_TX2ENA_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TXENA_L,
POUT => FX2_TXENA_LED
);
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_RXVAL,
POUT => FX2_RXVAL_LED
);
proc_clkdiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_clkdiv;
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
begin
DSP_DAT <= SER_MONI.abclkdiv;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
if SWI(2) = '0' then
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
else
DSP_DP(3) <= FX2_TX2BUSY;
DSP_DP(2) <= FX2_TX2ENA_LED;
DSP_DP(1) <= FX2_TXENA_LED;
DSP_DP(0) <= FX2_RXVAL_LED;
end if;
end process proc_hiomux;
RB_MREQ_TOP <= RB_MREQ;
FX2_TX2ENA <= FX2_TX2ENA_L;
FX2_TXENA <= FX2_TXENA_L;
end syn;
| gpl-3.0 | a34f074c86a3f00a5cfd84d50eeb3059 | 0.496023 | 3.262505 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd | 1 | 1,665 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | 0369fe2578a7ee68e6c98af14ce65b0c | 0.551351 | 3.917647 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd | 1 | 2,443 | -- $Id: rlink_cext_iface_vhpi.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_cext_iface - sim
-- Description: Interface to external C code for tbcore_rlink - VHPI version
--
-- Dependencies: -
--
-- To test: -
--
-- Target Devices: generic
-- Tool versions: ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-07 729 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlink_cext_vhpi.all;
entity rlink_cext_iface is -- interface to external C code - VHPI
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv32; -- clock cycle number
RX_DATA : out slv32; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end rlink_cext_iface;
architecture sim of rlink_cext_iface is
signal R_RXDATA : slv32 := (others=>'1');
signal R_RXVAL : slbit := '0';
begin
proc_put: process (CLK)
variable itxrc : integer := 0;
begin
if rising_edge(CLK) then
if TX_ENA = '1' then
itxrc := rlink_cext_putbyte(to_integer(unsigned(TX_DATA)));
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end if;
end process proc_put;
proc_get: process (CLK)
variable irxint : integer := 0;
begin
if rising_edge(CLK) then
if RX_HOLD = '0' or R_RXVAL = '0' then
irxint := rlink_cext_getbyte(to_integer(signed(CLK_CYCLE)));
R_RXDATA <= slv(to_signed(irxint, 32));
if irxint >= 0 then
R_RXVAL <= '1';
else
R_RXVAL <= '0';
end if;
end if;
end if;
end process proc_get;
RX_DATA <= R_RXDATA;
RX_VAL <= R_RXVAL;
end sim;
| gpl-3.0 | b31f9606aa41282891a7fce03c5e4ecc | 0.530495 | 3.587372 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dmscnt.vhd | 1 | 12,238 | -- $Id: pdp11_dmscnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmscnt - syn
-- Description: pdp11: debug&moni: state counter
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-06-26 695 14.7 131013 xc6slx16-2 91 107 0 41 s 5.4
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.1.2 use rbaddr_ constants
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
-- 2015-07-19 702 1.0 Initial version
-- 2015-06-26 695 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
--
-- 00 cntl r/w/- control
-- 01 clr r/w/- if 1 starts mem clear
-- 00 ena r/w/- if 1 enables counting
-- 01 addr r/w/- memory address
-- 10:02 laddr r/w/- line address (state number)
-- 01:00 waddr r/-/- word address (cleared on write)
-- 10 15:00 data r/-/- memory data
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end pdp11_dmscnt;
architecture syn of pdp11_dmscnt is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_addr : slv2 := "01"; -- addr address offset
constant rbaddr_data : slv2 := "10"; -- data address offset
constant cntl_rbf_clr : integer := 1;
constant cntl_rbf_ena : integer := 0;
subtype addr_rbf_mem is integer range 10 downto 2;
subtype addr_rbf_word is integer range 1 downto 0;
type state_type is (
s_idle, -- s_idle: rbus access or count
s_mread -- s_mread: memory read
);
type regs_type is record
state : state_type; -- state
rbsel : slbit; -- rbus select
clr : slbit; -- clr flag
ena0 : slbit; -- ena flag
ena1 : slbit; -- ena flag (delayed)
snum0 : slv9; -- snum stage 0
snum1 : slv9; -- snum stage 1
same : slbit; -- same snum flag
laddr : slv9; -- line addr
waddr : slv2; -- word addr
scnt : slv(35 downto 0); -- scnt buffer
mbuf : slv20; -- lsb memory buffer
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
'0','0','0', -- clr,ena0,ena1
(others=>'0'), -- snum0
(others=>'0'), -- snum1
'0', -- same
(others=>'0'), -- laddr
(others=>'0'), -- waddr
(others=>'0'), -- scnt
(others=>'0') -- mbuf
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CMEM_CEA : slbit := '0';
signal CMEM_CEB : slbit := '0';
signal CMEM_WEA : slbit := '0';
signal CMEM_WEB : slbit := '0';
signal CMEM_ADDRA : slv9 := (others=>'0');
signal CMEM_DIB : slv(35 downto 0) := (others=>'0');
signal CMEM_DOA : slv(35 downto 0) := (others=>'0');
constant cmem_data_zero : slv(35 downto 0) := (others=>'0');
begin
CMEM : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_CEA,
ENB => CMEM_CEB,
WEA => CMEM_WEA,
WEB => CMEM_WEB,
ADDRA => CMEM_ADDRA,
ADDRB => R_REGS.snum1,
DIA => cmem_data_zero,
DIB => CMEM_DIB,
DOA => CMEM_DOA,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
DM_STAT_CO, CMEM_DOA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable icea : slbit := '0';
variable iwea : slbit := '0';
variable iweb : slbit := '0';
variable iaddra : slv9 := (others=>'0');
variable iscnt0 : slv(35 downto 0) := (others=>'0');
variable iscnt1 : slv(35 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
icea := '0';
iwea := '0';
iweb := '0';
iaddra := r.snum0;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
end if;
case r.state is
when s_idle => -- s_idle: rbus access or count ------
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
n.clr := RB_MREQ.din(cntl_rbf_clr);
if RB_MREQ.din(cntl_rbf_clr) = '1' then -- if clr set
n.laddr := (others=>'0'); -- reset mem addr
end if;
n.ena0 := RB_MREQ.din(cntl_rbf_ena);
end if;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.clr = '1' then -- if clr active
irb_err := '1'; -- block addr writes
else -- otherwise
n.laddr := RB_MREQ.din(addr_rbf_mem); -- set mem addr
n.waddr := (others=>'0'); -- clr word addr
end if;
end if;
when rbaddr_data => -- data ------------------
if RB_MREQ.we = '1' then -- writes not allowed
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
if r.clr = '1' then -- if clr active
irb_err := '1'; -- block data reads
else -- otherwise
case r.waddr is -- handle word addr
when "00" => -- 1st access
icea := '1'; -- enable mem read
iaddra := r.laddr; -- of current line
irb_busy := '1';
n.state := s_mread;
when "01" => -- 2nd part
n.waddr := "10"; -- inc word addr
when "10" => -- 3rd part
n.waddr := "00"; -- wrap to next line
n.laddr := slv(unsigned(r.laddr) + 1);
when others => null;
end case;
end if;
end if;
when others => -- <> --------------------
irb_err := '1';
end case;
end if;
when s_mread => --s_mread: memory read ---------------
irb_ack := irbena; -- ack access
n.waddr := "01"; -- inc word addr
n.mbuf := CMEM_DOA(35 downto 16); -- capture msb part
n.state := s_idle;
when others => null;
end case;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_clr) := r.clr;
irb_dout(cntl_rbf_ena) := r.ena0;
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_mem) := r.laddr;
irb_dout(addr_rbf_word) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "00" => irb_dout := CMEM_DOA(15 downto 0);
when "01" => irb_dout := r.mbuf(15 downto 0);
when "10" => irb_dout(3 downto 0) := r.mbuf(19 downto 16);
when others => null;
end case;
when others => null;
end case;
end if;
-- latch state number
-- 1 msb determined from cpu mode: 0 if kernel and 1 when user or super
-- 8 lsb taken from sequencer snum
n.snum0(8) := '0';
if DM_STAT_DP.psw.cmode /= c_psw_kmode then
n.snum0(8) := '1';
end if;
n.snum0(7 downto 0) := DM_STAT_SE.snum;
n.snum1 := r.snum0;
-- incrementer pipeline
n.same := '0';
if r.snum0=r.snum1 and r.ena1 ='1' then -- in same state ?
n.same := '1'; -- don't read mem and remember
else -- otherwise
icea := '1'; -- enable mem read
end if;
-- increment state count
if r.same = '0' then -- was mem read ?
iscnt0 := CMEM_DOA; -- take memory value
else -- otherwise
iscnt0 := r.scnt; -- use scnt reg
end if;
iscnt1 := slv(unsigned(iscnt0) + 1); -- increment
n.scnt := iscnt1; -- and store
-- finally setup memory access
n.ena1 := r.ena0;
if r.clr = '1' then -- mem clear action
icea := '1';
iwea := '1';
iaddra := r.laddr;
n.laddr := slv(unsigned(r.laddr) + 1);
if r.laddr = "111111111" then
n.clr := '0';
end if;
elsif r.ena1 = '1' then -- state count action
iweb := '1';
end if;
N_REGS <= n;
CMEM_CEA <= icea;
CMEM_CEB <= iweb;
CMEM_WEA <= iwea;
CMEM_WEB <= iweb;
CMEM_ADDRA <= iaddra;
CMEM_DIB <= iscnt1;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 5d709d99cbfddd83519a0a138e673ae9 | 0.431688 | 3.827964 | false | false | false | false |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 1 | 7,088 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
-- Date : Fri Jun 23 10:02:11 2017
-- Host : dshwdev running 64-bit Ubuntu 16.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/h-ishihara/workspace/FPGAMAG18/FPGA/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
end clk_wiz_0_clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 30.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
| mit | 93f8766f54f1fb72675e856ed67e7709 | 0.638685 | 3.307513 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04500_good.vhd | 1 | 3,431 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-17 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04900_good.vhd
-- File Creation date : 2015-04-17
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset registers: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_04500_good is
generic (
g_Width : positive := 4
);
port (
i_Clock : in std_logic;
i_Reset_n : in std_logic;
i_Data : in std_logic_vector(g_Width-1 downto 0);
o_Sum : out std_logic_vector(g_Width downto 0)
);
end CNE_04500_good;
architecture Behavioral of CNE_04500_good is
type Data_4_Reg is array (0 to 3) of std_logic_vector(g_Width-1 downto 0);
signal Data_Reg : Data_4_Reg;
signal Sum : std_logic_vector(g_Width downto 0);
signal Sum_r : std_logic_vector(g_Width downto 0);
begin
p_Reg:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Data_Reg <= (others => (others => '0'));
elsif (rising_edge(i_Clock)) then
Data_Reg(3) <= Data_Reg(2);
Data_Reg(2) <= Data_Reg(1);
Data_Reg(1) <= Data_Reg(0);
Data_Reg(0) <= i_Data;
end if;
end process;
Sum <= std_logic_vector(unsigned('0' & Data_Reg(3)) + unsigned('0' & Data_Reg(2)));
p_Reg_Uninitialized:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Sum_r <= (others => '0');
elsif (rising_edge(i_Clock)) then
Sum_r <= Sum;
end if;
end process;
o_Sum <= Sum_r;
end Behavioral;
--CODE | gpl-3.0 | 44252d1f80aa5ff56ff31cacaae1292a | 0.495482 | 4.079667 | false | false | false | false |
sjohann81/hf-risc | mips/core_mips/int_control.vhd | 1 | 6,522 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity interrupt_controller is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
stall_cpu: out std_logic;
mwait_cpu: out std_logic;
irq_vector_cpu: out std_logic_vector(31 downto 0);
irq_cpu: out std_logic;
irq_ack_cpu: in std_logic;
exception_cpu: in std_logic;
inst_addr_cpu: in std_logic_vector(31 downto 0);
inst_in_cpu: out std_logic_vector(31 downto 0);
data_addr_cpu: in std_logic_vector(31 downto 0);
data_in_cpu: out std_logic_vector(31 downto 0);
data_out_cpu: in std_logic_vector(31 downto 0);
data_w_cpu: in std_logic_vector(3 downto 0);
data_access_cpu: in std_logic;
addr_mem: out std_logic_vector(31 downto 0);
data_read_mem: in std_logic_vector(31 downto 0);
data_write_mem: out std_logic_vector(31 downto 0);
data_we_mem: out std_logic_vector(3 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end interrupt_controller;
architecture arch_interrupt_controller of interrupt_controller is
signal irq_cause, irq_mask_reg, irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
signal periph_data, irq_vector_reg, irq_epc_reg, inst_reg: std_logic_vector(31 downto 0);
signal interrupt, irq, data_access_cpu_dly: std_logic;
type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
signal pulse_state: pulse_state_type;
signal pulse_next_state: pulse_state_type;
signal periph_access, periph_access_dly, periph_access_we: std_logic;
signal data_we_mem_s: std_logic_vector(3 downto 0);
begin
-- address decoder, read from peripheral registers
process(clock, reset, periph_access, data_addr_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, data_read_mem, extio_in, extio_out_reg)
begin
if reset = '1' then
periph_data <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' then
case data_addr_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR (RW)
periph_data <= irq_vector_reg;
when "0001" => -- IRQ_CAUSE (RO)
periph_data <= x"000000" & irq_cause(7 downto 0);
when "0010" => -- IRQ_MASK (RW)
periph_data <= x"000000" & irq_mask_reg(7 downto 0);
when "0011" => -- IRQ_STATUS (RW)
periph_data <= x"000000" & irq_status_reg;
when "0100" => -- IRQ_EPC (RO)
periph_data <= irq_epc_reg(31 downto 0);
when "1000" => -- EXTIO_IN (RO)
periph_data <= x"000000" & extio_in;
when "1001" => -- EXTIO_OUT (RW)
periph_data <= x"000000" & extio_out_reg;
when others =>
periph_data <= data_read_mem;
end case;
end if;
end if;
end process;
inst_in_cpu <= data_read_mem when data_access_cpu = '0' else inst_reg;
data_in_cpu <= data_read_mem when periph_access_dly = '0' else periph_data;
-- peripheral register logic, write to peripheral registers
process(clock, reset, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
begin
if reset = '1' then
irq_vector_reg <= (others => '0');
irq_mask_reg <= (others => '0');
irq_status_reg <= (others => '0');
extio_out_reg <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' and periph_access_we = '1' then
case data_addr_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR
irq_vector_reg <= data_out_cpu(31 downto 0);
when "0010" => -- IRQ_MASK
irq_mask_reg <= data_out_cpu(7 downto 0);
when "0011" => -- IRQ_STATUS
irq_status_reg <= data_out_cpu(7 downto 0);
when "1001" => -- EXTIO_OUT
extio_out_reg <= data_out_cpu(7 downto 0);
when others =>
end case;
end if;
if irq_ack_cpu = '1' or exception_cpu = '1' then
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
end if;
end if;
end process;
-- EPC register register load on interrupts
process(clock, reset, inst_addr_cpu, irq, irq_ack_cpu)
begin
if reset = '1' then
irq_epc_reg <= x"00000000";
elsif clock'event and clock = '1' then
if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
irq_epc_reg <= inst_addr_cpu;
end if;
end if;
end process;
-- interrupt state machine
process(clock, reset, pulse_state, interrupt, irq_status_reg, stall)
begin
if reset = '1' then
pulse_state <= irq_idle;
pulse_next_state <= irq_idle;
irq <= '0';
elsif clock'event and clock = '1' then
if stall = '0' then
pulse_state <= pulse_next_state;
case pulse_state is
when irq_idle =>
if interrupt = '1' and irq_status_reg(0) = '1' then
pulse_next_state <= irq_int;
end if;
when irq_int =>
irq <= '1';
pulse_next_state <= irq_req;
when irq_req =>
if irq_ack_cpu = '1' then
irq <= '0';
pulse_next_state <= irq_ackn;
end if;
when irq_ackn =>
pulse_next_state <= irq_done;
when irq_done =>
if irq_status_reg(0) = '1' then
pulse_next_state <= irq_idle;
end if;
when others =>
pulse_next_state <= irq_idle;
end case;
end if;
end if;
end process;
-- data / peripheral access delay
process(clock, reset, irq_ack_cpu, periph_access, stall, data_read_mem)
begin
if reset = '1' then
periph_access_dly <= '0';
data_access_cpu_dly <= '0';
inst_reg <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
periph_access_dly <= periph_access;
data_access_cpu_dly <= data_access_cpu;
if (data_access_cpu = '0') then
inst_reg <= data_read_mem;
end if;
end if;
end if;
end process;
periph_access <= '1' when data_addr_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
-- memory address / write enable muxes
addr_mem <= data_addr_cpu when data_access_cpu = '1' else inst_addr_cpu;
data_write_mem <= data_out_cpu;
data_we_mem_s <= data_w_cpu when data_access_cpu = '1' and periph_access = '0' else "0000";
data_we_mem <= data_we_mem_s;
mwait_cpu <= '1' when data_access_cpu = '1' and data_access_cpu_dly = '0' else '0';
stall_cpu <= stall;
-- interrupts masking
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
irq_cause <= extio_in;
irq_cpu <= irq;
irq_vector_cpu <= irq_vector_reg;
extio_out <= extio_out_reg;
end arch_interrupt_controller;
| gpl-2.0 | 1ad9041c9f9887337a2135c7a02933a3 | 0.631248 | 2.72887 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dmhbpt_unit.vhd | 1 | 9,148 | -- $Id: pdp11_dmhbpt_unit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmhbpt_unit - syn
-- Description: pdp11: dmhbpt - individual unit
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-07-12 700 14.7 131013 xc6slx16-2 39 67 0 21 s 3.8
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2015-07-19 702 1.0 Initial version
-- 2015-07-05 698 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 cntl r/w/- Control register
-- 05:04 mode r/w/- mode select (k=00,s=01,u=11; 10->all)
-- 02 irena r/w/- enable instruction read bpt
-- 01 dwena r/w/- enable data write bpt
-- 00 drena r/w/- enable data read bpt
-- 01 stat r/w/- Status register
-- 01 dwseen r/w/- dw bpt seen
-- 02 irseen r/w/- ir bpt seen
-- 00 drseen r/w/- dr bpt seen
-- 10 15:01 hilim r/w/- upper address limit, inclusive (def: 000000)
-- 11 15:01 lolim r/w/- lower address limit, inclusive (def: 000000)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
INDEX : natural := 0);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end pdp11_dmhbpt_unit;
architecture syn of pdp11_dmhbpt_unit is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_stat : slv2 := "01"; -- stat address offset
constant rbaddr_hilim : slv2 := "10"; -- hilim address offset
constant rbaddr_lolim : slv2 := "11"; -- lolim address offset
subtype cntl_rbf_mode is integer range 5 downto 4;
constant cntl_rbf_irena : integer := 2;
constant cntl_rbf_dwena : integer := 1;
constant cntl_rbf_drena : integer := 0;
constant stat_rbf_irseen : integer := 2;
constant stat_rbf_dwseen : integer := 1;
constant stat_rbf_drseen : integer := 0;
-- the mode 10 is used a wildcard, cpu only uses 00 (k) 01 (s) and 11 (u)
constant cntl_mode_all : slv2 := "10";
subtype lim_rbf is integer range 15 downto 1;
type regs_type is record
rbsel : slbit; -- rbus select
mode : slv2; -- mode select
irena : slbit; -- ir enable
dwena : slbit; -- dw enable
drena : slbit; -- dr enable
irseen : slbit; -- ir seen
dwseen : slbit; -- dw seen
drseen : slbit; -- dr seen
hilim : slv16_1; -- hilim
lolim : slv16_1; -- lolim
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
"00", -- mode
'0','0','0', -- *ena
'0','0','0', -- *seen
(others=>'0'), -- hilim
(others=>'0') -- lolim
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE, DM_STAT_DP,
DM_STAT_VM, DM_STAT_VM.vmcntl, -- xst needs sub-records
DM_STAT_CO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0'; -- FIXME: needed ??
variable irb_busy : slbit := '0'; -- FIXME: needed ??
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ihbpt : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_err := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and -- address valid
RB_MREQ.addr(12 downto 4)=RB_ADDR(12 downto 4) and -- block address
RB_MREQ.addr( 3 downto 2)=slv(to_unsigned(INDEX,2)) -- unit address
then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
n.mode := RB_MREQ.din(cntl_rbf_mode);
n.irena := RB_MREQ.din(cntl_rbf_irena);
n.dwena := RB_MREQ.din(cntl_rbf_dwena);
n.drena := RB_MREQ.din(cntl_rbf_drena);
end if;
when rbaddr_stat => -- stat ------------------
if RB_MREQ.we = '1' then
n.irseen := RB_MREQ.din(stat_rbf_irseen);
n.dwseen := RB_MREQ.din(stat_rbf_dwseen);
n.drseen := RB_MREQ.din(stat_rbf_drseen);
end if;
when rbaddr_hilim => -- hilim -----------------
if RB_MREQ.we = '1' then
n.hilim := RB_MREQ.din(lim_rbf);
end if;
when rbaddr_lolim => -- lolim -----------------
if RB_MREQ.we = '1' then
n.lolim := RB_MREQ.din(lim_rbf);
end if;
when others => null; -- <> --------------------
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_mode) := r.mode;
irb_dout(cntl_rbf_irena) := r.irena;
irb_dout(cntl_rbf_dwena) := r.dwena;
irb_dout(cntl_rbf_drena) := r.drena;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_irseen) := r.irseen;
irb_dout(stat_rbf_dwseen) := r.dwseen;
irb_dout(stat_rbf_drseen) := r.drseen;
when rbaddr_hilim => -- hilim -----------------
irb_dout(lim_rbf) := r.hilim;
when rbaddr_lolim => -- lolim -----------------
irb_dout(lim_rbf) := r.lolim;
when others => null;
end case;
end if;
-- breakpoint unit logic
ihbpt := '0';
if DM_STAT_VM.vmcntl.req = '1' and
DM_STAT_VM.vmcntl.cacc = '0' and
(DM_STAT_VM.vmcntl.mode = r.mode or r.mode = cntl_mode_all )and
unsigned(DM_STAT_VM.vmaddr(lim_rbf))>=unsigned(r.lolim) and
unsigned(DM_STAT_VM.vmaddr(lim_rbf))<=unsigned(r.hilim) then
if r.irena = '1' then
if DM_STAT_SE.istart = '1' and -- only for instruction fetches !
DM_STAT_VM.vmcntl.dspace = '0' and
DM_STAT_VM.vmcntl.wacc = '0' then
ihbpt := '1';
n.irseen := '1';
end if;
end if;
if r.dwena = '1' then
if DM_STAT_VM.vmcntl.dspace = '1' and
DM_STAT_VM.vmcntl.wacc = '1' then
ihbpt := '1';
n.dwseen := '1';
end if;
end if;
if r.drena = '1' then
if DM_STAT_VM.vmcntl.dspace = '1' and
DM_STAT_VM.vmcntl.wacc = '0' then
ihbpt := '1';
n.drseen := '1';
end if;
end if;
end if;
N_REGS <= n;
HBPT <= ihbpt;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 3894b35383fbbe3a7412600e6ff21b27 | 0.479012 | 3.47041 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd | 1 | 2,497 | -- $Id: dcm_sfs_unisim_s3e.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3E version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E; Spartan-6
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3E version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture syn of dcm_sfs is
begin
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end generate DCM1;
end syn;
| gpl-3.0 | d86f3294bca27dced7e6a289a5085ddc | 0.553865 | 3.618841 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys3/sys_conf.vhd | 1 | 1,886 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-10 786 1.2 memctl with page mode, new read1delay
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 0f6641b04b192375b98545e16a28fd77 | 0.617179 | 3.518657 | false | false | false | false |
wfjm/w11 | rtl/bplib/issi/tb/tb_is61lv25616al.vhd | 1 | 5,814 | -- $Id: tb_is61lv25616al.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_is61lv25616al - sim
-- Description: Test bench for is61lv25616al memory model
--
-- Dependencies: is61lv25616al [UUT]
--
-- To test: is61lv25616al
--
-- Verified (with tb_is61lv25616al_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-05-16 291 - 0.26 - - c:ok
-- 2007-12-15 101 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.1 initial values for all act.low signals now '1'
-- 2007-12-14 101 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_is61lv25616al is
end tb_is61lv25616al;
architecture sim of tb_is61lv25616al is
signal CE_N : slbit := '1';
signal OE_N : slbit := '1';
signal WE_N : slbit := '1';
signal UB_N : slbit := '1';
signal LB_N : slbit := '1';
signal ADDR : slv18 := (others=>'0');
signal DATA : slv16 := (others=>'0');
begin
UUT : entity work.is61lv25616al
port map (
CE_N => CE_N,
OE_N => OE_N,
WE_N => WE_N,
UB_N => UB_N,
LB_N => LB_N,
ADDR => ADDR,
DATA => DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_is61lv25616al_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival18 : slv18 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable iaddr : slv18 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival18, 16);
if imatch then iaddr := ival18; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
CE_N <= not ice;
OE_N <= not ioe;
WE_N <= not iwe;
LB_N <= not ibe(0);
UB_N <= not ibe(1);
ADDR <= iaddr;
if ide = '1' then
DATA <= idata;
else
DATA <= (others=>'Z');
end if;
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
write(oline, string'(" be="));
write(oline, ibe, right, 2);
write(oline, string'(" a="));
writegen(oline, iaddr, right, 5, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop;
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
wait; -- suspend proc_stim forever
-- no clock, sim will end
end process proc_stim;
end sim;
| gpl-3.0 | de1a68586e1bf527313dd38a1968bc33 | 0.489508 | 3.881175 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/s7_cmt_1ce1ce2c.vhd | 1 | 5,451 | -- $Id: s7_cmt_1ce1ce2c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_1ce1ce2c - syn
-- Description: clocking block for 7-Series: 2 clk+CEs + 2 clk
--
-- Dependencies: s7_cmt_sfs
-- s7_cmt_sfs_2
-- clkdivce
-- Test bench: -
-- Target Devices: generic 7-Series
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
entity s7_cmt_1ce1ce2c is -- clocking block: 2 clk+CEs; 2 clk
generic (
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
CLK0_OUTDIV : positive := 1; -- clk0: output divide
CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
CLK1_OUTDIV : positive := 1; -- clk1: output divide
CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
CLK1_MSECDIV : positive := 1000; -- clk1: divider ratio for msec pulse
CLK23_VCODIV : positive := 1; -- clk2+3: vco clock divide
CLK23_VCOMUL : positive := 1; -- clk2+3: vco clock multiply
CLK2_OUTDIV : positive := 1; -- clk2: output divide
CLK3_OUTDIV : positive := 1; -- clk3: output divide
CLK23_GENTYPE : string := "PLL"); -- clk2+3: PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLK0 : out slbit; -- clk0: clock output
CE0_USEC : out slbit; -- clk0: usec pulse
CE0_MSEC : out slbit; -- clk0: msec pulse
CLK1 : out slbit; -- clk1: clock output
CE1_USEC : out slbit; -- clk1: usec pulse
CE1_MSEC : out slbit; -- clk1: msec pulse
CLK2 : out slbit; -- clk2: clock output
CLK3 : out slbit; -- clk3: clock output
LOCKED : out slbit -- all PLL/MMCM locked
);
end s7_cmt_1ce1ce2c;
architecture syn of s7_cmt_1ce1ce2c is
signal CLK0_L : slbit := '0';
signal CLK1_L : slbit := '0';
signal LOCKED0 : slbit := '0';
signal LOCKED1 : slbit := '0';
signal LOCKED23 : slbit := '0';
begin
GEN_CLK0 : s7_cmt_sfs -- clock generator 0 -----------------
generic map (
VCO_DIVIDE => CLK0_VCODIV,
VCO_MULTIPLY => CLK0_VCOMUL,
OUT_DIVIDE => CLK0_OUTDIV,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKIN_JITTER => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT,
GEN_TYPE => CLK0_GENTYPE)
port map (
CLKIN => CLKIN,
CLKFX => CLK0_L,
LOCKED => LOCKED0
);
DIV_CLK0 : clkdivce -- usec/msec clock divider 0 ---------
generic map (
CDUWIDTH => CLK0_CDUWIDTH,
USECDIV => CLK0_USECDIV,
MSECDIV => CLK0_MSECDIV)
port map (
CLK => CLK0_L,
CE_USEC => CE0_USEC,
CE_MSEC => CE0_MSEC
);
GEN_CLK1 : s7_cmt_sfs -- clock generator 1 -----------------
generic map (
VCO_DIVIDE => CLK1_VCODIV,
VCO_MULTIPLY => CLK1_VCOMUL,
OUT_DIVIDE => CLK1_OUTDIV,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKIN_JITTER => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT,
GEN_TYPE => CLK1_GENTYPE)
port map (
CLKIN => CLKIN,
CLKFX => CLK1_L,
LOCKED => LOCKED1
);
DIV_CLK1 : clkdivce -- usec/msec clock divider 1 ---------
generic map (
CDUWIDTH => CLK1_CDUWIDTH,
USECDIV => CLK1_USECDIV,
MSECDIV => CLK1_MSECDIV)
port map (
CLK => CLK1_L,
CE_USEC => CE1_USEC,
CE_MSEC => CE1_MSEC
);
GEN_CLK23 : s7_cmt_sfs_2 -- clock generator 2+3 ---------------
generic map (
VCO_DIVIDE => CLK23_VCODIV,
VCO_MULTIPLY => CLK23_VCOMUL,
OUT0_DIVIDE => CLK2_OUTDIV,
OUT1_DIVIDE => CLK3_OUTDIV,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKIN_JITTER => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT,
GEN_TYPE => CLK23_GENTYPE)
port map (
CLKIN => CLKIN,
CLKOUT0 => CLK2,
CLKOUT1 => CLK3,
LOCKED => LOCKED23
);
CLK0 <= CLK0_L;
CLK1 <= CLK1_L;
LOCKED <= LOCKED0 and LOCKED1 and LOCKED23;
end syn;
| gpl-3.0 | 162a7d7bfd6c2f07fdf4578cba2bb5c3 | 0.523757 | 3.496472 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdc_signal_s1.vhd | 1 | 1,639 | -- $Id: cdc_signal_s1.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdc_signal_s1 - syn
-- Description: clock domain crossing for a signal, 2 stage
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-11 774 1.1 add INIT generic
-- 2016-04-08 459 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cdc_signal_s1 is -- cdc for signal (2 stage)
generic (
INIT : slbit := '0'); -- initial state
port (
CLKO : in slbit; -- O|output clock
DI : in slbit; -- I|input data
DO : out slbit -- O|output data
);
end entity cdc_signal_s1;
architecture syn of cdc_signal_s1 is
signal R_DO_S0 : slbit := INIT;
signal R_DO_S1 : slbit := INIT;
attribute ASYNC_REG: string;
attribute ASYNC_REG of R_DO_S0 : signal is "true";
attribute ASYNC_REG of R_DO_S1 : signal is "true";
begin
proc_regs: process (CLKO)
begin
if rising_edge(CLKO) then
R_DO_S0 <= DI; -- synch 0: CLKI->CLKO
R_DO_S1 <= R_DO_S0; -- synch 1: CLKO
end if;
end process proc_regs;
DO <= R_DO_S1;
end syn;
| gpl-3.0 | 21324823ba88b496853d40cc8c323995 | 0.517389 | 3.42887 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/cmoda7/tb/sys_conf_sim.vhd | 1 | 1,831 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_c7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.1; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 322da0034b023efb4301b7ace4ef485a | 0.616057 | 3.604331 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/sramif2migui_core.vhd | 1 | 14,591 | -- $Id: sramif2migui_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sramif2migui_core - syn
-- Description: SRAM to MIG interface core
--
-- Dependencies: memlib/fifo_2c_dram2
-- cdclib/cdc_signal_s1
-- Test bench: tb/tb_sramif2migui_core
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-11-04 1066 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.cdclib.all;
use work.miglib.all;
entity sramif2migui_core is -- SRAM to MIG interface core
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28); -- memory address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
MONI : out sramif2migui_moni_type; -- monitor signals
UI_CLK : in slbit; -- MIGUI clock
UI_CLK_SYNC_RST : in slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : in slbit; -- MIGUI calibration done
APP_RDY : in slbit; -- MIGUI ready for cmd
APP_EN : out slbit; -- MIGUI command enable
APP_CMD : out slv3; -- MIGUI command
APP_ADDR : out slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : in slbit; -- MIGUI ready for data write
APP_WDF_WREN : out slbit; -- MIGUI data write enable
APP_WDF_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : out slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : out slbit; -- MIGUI write end
APP_RD_DATA_VALID : in slbit; -- MIGUI read valid
APP_RD_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : in slbit -- MIGUI read end
);
end sramif2migui_core;
architecture syn of sramif2migui_core is
constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16)
constant dwidth : positive := 8*mwidth; -- data width (64 or 128)
constant tawidth : positive := 20-(BAWIDTH-2); -- tag address width
constant rfwidth : positive := dwidth+mwidth+tawidth+1; -- req fifo width
-- sram address fields
subtype sa_f_ta is integer range 20-1 downto BAWIDTH-2; -- tag addr
subtype sa_f_ga is integer range BAWIDTH-3 downto 0; -- group addr
-- mig address fields
subtype ma_f_ta is integer range 22-1 downto BAWIDTH; -- tag addr
-- request fifo data fields
subtype rf_f_data is integer range dwidth+mwidth+tawidth
downto MWIDTH+tawidth+1;
subtype rf_f_mask is integer range mwidth+tawidth downto tawidth+1;
subtype rf_f_addr is integer range tawidth downto 1;
constant rf_f_we : integer := 0;
constant ngrp : positive := 2**(BAWIDTH-2); -- # of 32bit groups (2 or 4)
type regs_type is record
actr : slbit; -- active read flag
actw : slbit; -- active write flag
ackr : slbit; -- read acknowledge
req_addr : slv20; -- request address
req_be : slv4; -- request be
req_di : slv32; -- request di
res_do : slv32; -- response do
rdbuf : slv(dwidth-1 downto 0); -- read buffer
rdtag : slv(tawidth-1 downto 0); -- read tag address
rdval : slbit; -- read buffer valid
rdnew : slbit; -- read buffer new
rdpend : slbit; -- read request pending
wrbuf : slv(dwidth-1 downto 0); -- write buffer
wrtag : slv(tawidth-1 downto 0); -- write tag address
wrpend : slv(mwidth-1 downto 0); -- write buffer pending flags
end record regs_type;
constant bufzero : slv(dwidth-1 downto 0) := (others=>'0');
constant tagzero : slv(tawidth-1 downto 0) := (others=>'0');
constant pendzero : slv(mwidth-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0','0','0', -- actr,actw,ackr
(others=>'0'), -- req_addr
(others=>'0'), -- req_be
(others=>'0'), -- req_di
(others=>'0'), -- res_do
bufzero, -- rdbuf
tagzero, -- rdtag
'0','0','0', -- rdval,rdnew,rdpend
bufzero, -- wrbuf
tagzero, -- wrtag
pendzero -- wrpend
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal REQ_DI : slv(rfwidth-1 downto 0) := (others=>'0');
signal REQ_DO : slv(rfwidth-1 downto 0) := (others=>'0');
signal REQ_ENA : slbit := '0';
signal REQ_VAL : slbit := '0';
signal REQ_HOLD : slbit := '0';
signal REQ_SIZE : slv4 := (others=>'0');
signal RES_DI : slv(dwidth-1 downto 0) := (others=>'0');
signal RES_DO : slv(dwidth-1 downto 0) := (others=>'0');
signal RES_ENA : slbit := '0';
signal RES_VAL : slbit := '0';
signal APP_RDY_CLK : slbit := '0'; -- APP_RDY sync'ed to CLK
signal APP_WDF_RDY_CLK : slbit := '0'; -- APP_WDF_RDY_CLK sync'ed to CLK
signal MIGUIRST_CLK : slbit := '0'; -- UI_CLK_SYNC_RST sync'ed to CLK
signal MIGCACO_CLK : slbit := '0'; -- INIT_CALIB_COMPLETE sync'ed to CLK
begin
assert BAWIDTH = 3 or BAWIDTH = 4
report "assert( BAWIDTH = 3 or 4 )"
severity failure;
REQFIFO : fifo_2c_dram2 -- request fifo
generic map (
AWIDTH => 4,
DWIDTH => rfwidth)
port map (
CLKW => CLK,
CLKR => UI_CLK,
RESETW => '0',
RESETR => '0',
DI => REQ_DI,
ENA => REQ_ENA,
BUSY => open,
DO => REQ_DO,
VAL => REQ_VAL,
HOLD => REQ_HOLD,
SIZEW => REQ_SIZE,
SIZER => open
);
RESFIFO : fifo_2c_dram2 -- response fifo
generic map (
AWIDTH => 4,
DWIDTH => dwidth)
port map (
CLKW => UI_CLK,
CLKR => CLK,
RESETW => '0',
RESETR => '0',
DI => RES_DI,
ENA => RES_ENA,
BUSY => open,
DO => RES_DO,
VAL => RES_VAL,
HOLD => '0',
SIZEW => open,
SIZER => open
);
-- cdc for monitoring sigals from UI_CLK to CLK
CDC_CRDY : cdc_signal_s1
port map (
CLKO => CLK,
DI => APP_RDY,
DO => APP_RDY_CLK
);
CDC_WRDY : cdc_signal_s1
port map (
CLKO => CLK,
DI => APP_WDF_RDY,
DO => APP_WDF_RDY_CLK
);
CDC_UIRST : cdc_signal_s1
port map (
CLKO => CLK,
DI => UI_CLK_SYNC_RST,
DO => MIGUIRST_CLK
);
CDC_CACO : cdc_signal_s1
port map (
CLKO => CLK,
DI => INIT_CALIB_COMPLETE,
DO => MIGCACO_CLK
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, REQ, ADDR, BE, DI, WE,
REQ_SIZE, RES_VAL, RES_DO,
APP_RDY_CLK, APP_WDF_RDY_CLK, MIGUIRST_CLK, MIGCACO_CLK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iga : integer := 0;
variable ireqena : slbit := '0';
variable iackw : slbit := '0';
variable imoni : sramif2migui_moni_type := sramif2migui_moni_init;
variable iwrbuf : slv(dwidth-1 downto 0) := (others=>'0');
variable ireqdi : slv(rfwidth-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iga := 0;
ireqena := '0';
iackw := '0';
imoni := sramif2migui_moni_init;
imoni.migcbusy := not APP_RDY_CLK;
imoni.migwbusy := not APP_WDF_RDY_CLK;
imoni.miguirst := MIGUIRST_CLK;
imoni.migcacow := not MIGCACO_CLK;
-- setup request fifo data for write (the default)
ireqdi(rf_f_data) := r.wrbuf;
ireqdi(rf_f_mask) := not r.wrpend; -- -- MASK = not WE !!
ireqdi(rf_f_addr) := r.wrtag;
ireqdi(rf_f_we) := '1';
n.ackr := '0'; -- ensure one-shot
-- handle idle state, capture input, and activate read or write
if r.actr='0' and r.actw='0' then
if REQ = '1' then
n.req_addr := ADDR;
n.req_be := BE;
n.req_di := DI;
if WE = '1' then -- write request
n.actw := '1';
if r.wrtag = ADDR(sa_f_ta) then -- row hit
imoni.wrrhit := '1';
else -- row miss
if r.wrpend /= pendzero then -- if write buffer pending
ireqena := '1'; -- queue write request
n.wrpend := pendzero; -- clear pending flags
imoni.wrflush := '1';
end if;
end if;
else -- read request
n.actr := '1';
end if; -- WE='1'
end if; -- REQ='1'
end if;
iga := to_integer(unsigned(r.req_addr(sa_f_ga))); -- current group index
-- handle write request
if r.actw = '1' then
-- write into wrbuf and wrpend, no pending data left when here
if r.req_be(0) = '1' then
n.wrbuf(32*iga+ 7 downto 32*iga ) := r.req_di( 7 downto 0);
end if;
if r.req_be(1) = '1' then
n.wrbuf(32*iga+15 downto 32*iga+ 8) := r.req_di(15 downto 8);
end if;
if r.req_be(2) = '1' then
n.wrbuf(32*iga+23 downto 32*iga+16) := r.req_di(23 downto 16);
end if;
if r.req_be(3) ='1' then
n.wrbuf(32*iga+31 downto 32*iga+24) := r.req_di(31 downto 24);
end if;
n.wrtag := r.req_addr(sa_f_ta); -- set new tag address
n.wrpend(4*iga+3 downto 4*iga) := -- and update pending flags
n.wrpend(4*iga+3 downto 4*iga) or r.req_be;
if r.rdtag = r.req_addr(sa_f_ta) then -- invalidate rdbuf if same tag
n.rdval := '0';
end if;
-- ensure that at most 4 pending writes in queue
-- REQ_SIZE gives # of available slots, empty FIFO has REQ_SIZE=15
-- REQ_SIZE is 11 when 4 requests are on flight
if unsigned(REQ_SIZE) >= 11 then
n.actw := '0'; -- mark request done
iackw := '1'; -- send ack signal
end if;
end if;
-- handle read request
if r.actr = '1' then
if r.rdtag=r.req_addr(sa_f_ta) and r.rdval='1' then --
n.res_do := r.rdbuf(32*iga+31 downto 32*iga);
n.actr := '0'; -- mark request done
n.ackr := '1'; -- send ack signal
n.rdnew := '0'; -- mark used
imoni.rdrhit := not r.rdnew;
else
if r.wrpend /= pendzero then -- if write buffer pending
ireqena := '1'; -- queue write request
n.wrpend := pendzero; -- clear pending flags
imoni.wrflush := '1';
elsif r.rdpend = '0' then
ireqdi(rf_f_addr) := r.req_addr(sa_f_ta);
ireqdi(rf_f_we) := '0';
n.rdtag := r.req_addr(sa_f_ta); -- new tag
n.rdval := '0'; -- mark rdbuf invalid
n.rdpend := '1'; -- assert read pending
ireqena := '1'; -- queue read request
end if;
end if;
end if;
-- handle read response
if RES_VAL = '1' then
n.rdbuf := RES_DO; -- capture data
n.rdval := '1'; -- mark valid
n.rdnew := '1'; -- mark new
n.rdpend := '0'; -- deassert read pending
end if;
N_REGS <= n;
REQ_DI <= ireqdi;
REQ_ENA <= ireqena;
MONI <= imoni;
-- block input if busy or UI clock in RESET
BUSY <= r.actr or r.actw or MIGUIRST_CLK;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= r.actr;
ACT_W <= r.actw;
DO <= r.res_do;
end process proc_next;
proc_req2app: process (APP_RDY, APP_WDF_RDY, REQ_VAL, REQ_DO,
INIT_CALIB_COMPLETE)
begin
REQ_HOLD <= '0';
APP_ADDR <= (others=>'0');
APP_ADDR(ma_f_ta) <= REQ_DO(rf_f_addr);
APP_WDF_DATA <= REQ_DO(rf_f_data);
APP_WDF_MASK <= REQ_DO(rf_f_mask);
APP_EN <= '0';
APP_CMD <= c_migui_cmd_read;
APP_WDF_WREN <= '0';
APP_WDF_END <= '0';
if APP_RDY='1' and APP_WDF_RDY='1' and INIT_CALIB_COMPLETE='1' then
if REQ_VAL = '1' then
APP_EN <= '1';
if REQ_DO(rf_f_we) = '1' then
APP_CMD <= c_migui_cmd_write;
APP_WDF_WREN <= '1';
APP_WDF_END <= '1';
end if; -- REQ_DO(rf_f_we) = '1'
end if; -- REQ_VAL = '1'
else
REQ_HOLD <= '1';
end if; -- APP_RDY='1' and APP_WDF_RDY='1
end process proc_req2app;
proc_app2res: process (APP_RD_DATA_VALID, APP_RD_DATA)
begin
RES_ENA <= APP_RD_DATA_VALID;
RES_DI <= APP_RD_DATA;
end process proc_app2res;
end syn;
| gpl-3.0 | 2fedcaa98bd3180d86ab4307aa5e83f1 | 0.492358 | 3.488166 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/tb/arty_dummy.vhd | 1 | 2,029 | -- $Id: arty_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: arty_dummy - syn
-- Description: arty minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_arty
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-01-31 726 1.0 Initial version (cloned from basys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity arty_dummy is -- ARTY dummy (base; loopback)
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end arty_dummy;
architecture syn of arty_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
O_RGBLED2 <= (others=>'0');
O_RGBLED3 <= (others=>'0');
end syn;
| gpl-3.0 | 7008bbbf91b5bae117ebcf920b6efddc | 0.480532 | 3.729779 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | PC.vhd | 1 | 578 | library ieee;
use ieee.std_logic_1164.all;
entity PC is
generic(
DATA_WIDTH : natural := 5
);
port(
clk, rst: in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end PC;
architecture rtl of PC is
signal Temp: std_logic_vector((DATA_WIDTH-1) downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
Temp <= (others => '0');
elsif (clk'event and clk='0')then -- ver a borda!
Temp <= D;
end if;
end process;
Q <= Temp;
end rtl; | mit | d426fa8f0db31892a21382ea17a12776 | 0.572664 | 2.76555 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlinklib.vhd | 1 | 16,437 | -- $Id: rlinklib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rlinklib
-- Description: Definitions for rlink interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
--
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2016-03-28 755 4.2 add rlink_sp2c
-- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL);
-- rlink_sp1c: rename ENAESC->ESCFILL
-- 2015-02-21 649 4.1.1 add ioleds_sp1c
-- 2014-12-21 617 4.1 use stat(2) to signal rbus timeout
-- 2014-10-12 596 4.0 now rlink v4.0 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2013-04-21 509 3.3.2 add rlb_moni record definition
-- 2012-12-29 466 3.3.1 add rlink_rlbmux
-- 2011-12-23 444 3.3 CLK_CYCLE now integer
-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
-- 2011-12-09 437 3.2 add rlink_core8
-- 2011-11-18 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- new rlink_serport interface;
-- rename rlink_core_serport->rlink_base_serport
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames
-- rri_ -> rlink and c_rri -> c_rlink;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete
-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic
-- 2010-04-10 275 2.1.1 add rri_core_serport
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport;
-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3
-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
-- 2007-11-24 98 1.1 added RP_IINT for rri_core.
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.serportlib.all;
package rlinklib is
constant c_rlink_dat_sop : slv9 := "100000000";
constant c_rlink_dat_eop : slv9 := "100000001";
constant c_rlink_dat_nak : slv9 := "100000010";
constant c_rlink_dat_attn : slv9 := "100000011";
constant c_rlink_cmd_rreg : slv3 := "000";
constant c_rlink_cmd_rblk : slv3 := "001";
constant c_rlink_cmd_wreg : slv3 := "010";
constant c_rlink_cmd_wblk : slv3 := "011";
constant c_rlink_cmd_labo : slv3 := "100";
constant c_rlink_cmd_attn : slv3 := "101";
constant c_rlink_cmd_init : slv3 := "110";
subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
subtype c_rlink_stat_rbf_stat is integer range 7 downto 4; -- ext status bits
constant c_rlink_stat_rbf_attn: integer := 3; -- attention flags set
constant c_rlink_stat_rbf_rbtout: integer := 2; -- rbus timeout
constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack
constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set
constant c_rlink_nakcode_ccrc : slv3 := "000"; -- cmd crc error
constant c_rlink_nakcode_dcrc : slv3 := "001"; -- data crc error
constant c_rlink_nakcode_frame : slv3 := "010"; -- framing error
constant c_rlink_nakcode_unused : slv3 := "011"; -- <unused code>
constant c_rlink_nakcode_cmd : slv3 := "100"; -- bad cmd
constant c_rlink_nakcode_cnt : slv3 := "101"; -- bad cnt
constant c_rlink_nakcode_rtovfl : slv3 := "110"; -- rtbuf ovfl
constant c_rlink_nakcode_rtwblk : slv3 := "111"; -- rtbuf ovfl in wblk
type rl_moni_type is record -- rlink_core monitor port
eop : slbit; -- eop send in last cycle
attn : slbit; -- attn send in last cycle
lamp : slbit; -- attn (lam) pending
end record rl_moni_type;
constant rl_moni_init : rl_moni_type :=
('0','0','0'); -- eop,attn,lamp
type rlb_moni_type is record -- rlink 8b monitor port
rxval : slbit; -- data in valid
rxhold : slbit; -- data in hold
txena : slbit; -- data out enable
txbusy : slbit; -- data out busy
end record rlb_moni_type;
constant rlb_moni_init : rlb_moni_type :=
('0','0','0','0'); -- rxval,rxhold,txena,txbusy
-- these definitions logically belongs into the 'for test benches' section'
-- it is here for convenience to simplify instantiations.
constant sbcntl_sbf_rlmon : integer := 15;
constant sbcntl_sbf_rlbmon : integer := 14;
component rlink_core is -- rlink core with 9bit iface
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
component rlink_aif is -- rlink, abstract interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit := '0' -- rlink 9b: data hold
);
end component;
component rlink_core8 is -- rlink core with 8bit iface
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
RESET : in slbit; -- reset
ESCXON : in slbit := '0'; -- enable xon/xoff escaping
ESCFILL : in slbit := '0'; -- enable fill escaping
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
component rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end component;
--
-- core + concrete_interface combo's
--
component rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit := '0'; -- enable xon/xoff handling
ESCFILL : in slbit := '0'; -- enable fill escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end component;
component rlink_sp2c is -- rlink_core8+serport_2clock2 combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- U|clock (user design)
CE_USEC : in slbit; -- U|1 usec clock enable
CE_MSEC : in slbit; -- U|1 msec clock enable
CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable
RESET : in slbit; -- U|reset
CLKS : in slbit; -- S|clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ESCFILL : in slbit; -- U|enable fill escaping
RXSD : in slbit; -- S|receive serial data (board view)
TXSD : out slbit; -- S|transmit serial data (board view)
CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view)
RTS_N : out slbit; -- S|request to send (act.low, brd view)
RB_MREQ : out rb_mreq_type; -- U|rbus: request
RB_SRES : in rb_sres_type; -- U|rbus: response
RB_LAM : in slv16; -- U|rbus: look at me
RB_STAT : in slv4; -- U|rbus: status flags
RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port
SER_MONI : out serport_moni_type -- U|serport: monitor port
);
end component;
--
-- io activity leds
--
component ioleds_sp1c -- io activity leds for rlink_sp1c
port (
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
component rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end component;
end package rlinklib;
| gpl-3.0 | 9e3e4899c9b1730aa913e19aa9821e8a | 0.531788 | 3.563964 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serportlib_tb.vhd | 1 | 1,075 | -- $Id: serportlib_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: serportlib_tb
-- Description: serial port interface components (SIM only!)
--
-- Dependencies: -
-- Tool versions: ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serportlib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package serportlib_tb is
-- here only constant definitions
-- no component defintions, use direct instantiation !
constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
end package serportlib_tb;
| gpl-3.0 | 5225ae8005c3272d34ed017ef278b033 | 0.571163 | 3.732639 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/IO_ctl.vhd | 2 | 2,116 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
ipins_data : out std_logic_vector(31 downto 0);
ipins_sel : in std_logic_vector(2 downto 0);
oport : out std_logic_vector(31 downto 0);
oport_data : in std_logic_vector(31 downto 0);
oport_en : in std_logic;
opins : out std_logic_vector(7 downto 0);
opins_data : in std_logic_vector(31 downto 0);
opins_sel : in std_logic_vector(2 downto 0);
opins_en : in std_logic
);
end IO_ctl;
architecture behavioral of IO_ctl is
signal iport_reg : std_logic_vector(31 downto 0);
signal ipins_reg : std_logic_vector(7 downto 0);
signal oport_reg : std_logic_vector(31 downto 0);
signal opins_reg : std_logic_vector(7 downto 0);
begin
iport_ctl : process (clk, rst) is
begin
if rst = '1' then
iport_reg <= (others => '0');
elsif rising_edge(clk) then
iport_reg <= iport;
end if;
end process;
iport_data <= iport_reg;
ipins_ctl : process (clk, rst) is
begin
if rst = '1' then
ipins_reg <= (others => '0');
elsif rising_edge(clk) then
ipins_reg <= ipins;
end if;
end process;
ipins_data <= "0000000000000000000000000000000" & ipins_reg(conv_integer(unsigned(ipins_sel)));
oport_ctl : process (clk, rst) is
begin
if rst = '1' then
oport_reg <= (others => '0');
elsif falling_edge(clk) then
if oport_en = '1' then
oport_reg <= oport_data;
end if;
end if;
end process;
oport <= oport_reg;
opins_ctl : process (clk, rst) is
begin
if rst = '1' then
opins_reg <= (others => '0');
elsif falling_edge(clk) then
if opins_en = '1' then
opins_reg(conv_integer(unsigned(opins_sel))) <= opins_data(0);
end if;
end if;
end process;
opins <= opins_reg;
end behavioral; | mit | bc4360ee784e0592b9e5d6ef43f6ec36 | 0.626654 | 2.992928 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_rbmon.vhd | 1 | 21,523 | -- $Id: rbd_rbmon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_rbmon - syn
-- Description: rbus dev: rbus monitor
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2018.3; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-14 873 14.7 131013 xc6slx16-2 124 187 - 67 s 5.9
-- 2017-04-08 758 14.7 131013 xc6slx16-2 112 200 - 73 s 5.7
-- 2014-12-22 619 14.7 131013 xc6slx16-2 114 209 - 72 s 5.6
-- 2014-12-21 593 14.7 131013 xc6slx16-2 99 207 - 77 s 7.0
-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 6.0.2 use rbaddr_ constants
-- 2019-03-02 1116 6.0.1 more robust ack,err trace when busy
-- 2017-04-16 879 6.0 revised interface, add suspend and repeat collapse
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses
-- 2014-09-13 593 4.1 change default address -> ffe8
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded)
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 05 rcolw r/w/- repeat collapse writes
-- 04 rcolr r/w/- repeat collapse reads
-- 03 wstop r/w/- stop on wrap
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb)
-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000)
-- 100 addr r/w/- Address register
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- 101 data r/w/- Data register
--
-- data format:
-- word 3 15 : burst (2nd re/we in a aval sequence)
-- 14 : tout (busy in last re-we cycle)
-- 13 : nak (no ack in last non-busy cycle)
-- 12 : ack (ack seen)
-- 11 : busy (busy seen)
-- 10 : err (err seen)
-- 09 : we (write cycle)
-- 08 : init (init cycle)
-- 07:00 : delay to prev (msb's)
-- word 2 15:10 : delay to prev (lsb's)
-- 09:00 : number of busy cycles
-- word 1 : data
-- word 0 : addr
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.rbdlib.all;
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv16 := rbaddr_rbmon;
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
);
end entity rbd_rbmon;
architecture syn of rbd_rbmon is
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
constant rbaddr_stat : slv3 := "001"; -- stat address offset
constant rbaddr_hilim : slv3 := "010"; -- hilim address offset
constant rbaddr_lolim : slv3 := "011"; -- lolim address offset
constant rbaddr_addr : slv3 := "100"; -- addr address offset
constant rbaddr_data : slv3 := "101"; -- data address offset
constant cntl_rbf_rcolw : integer := 5;
constant cntl_rbf_rcolr : integer := 4;
constant cntl_rbf_wstop : integer := 3;
subtype cntl_rbf_func is integer range 2 downto 0;
subtype stat_rbf_bsize is integer range 15 downto 13;
constant stat_rbf_wrap : integer := 2;
constant stat_rbf_susp : integer := 1;
constant stat_rbf_run : integer := 0;
subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_rbf_waddr is integer range 1 downto 0;
constant dat3_rbf_burst : integer := 15;
constant dat3_rbf_tout : integer := 14;
constant dat3_rbf_nak : integer := 13;
constant dat3_rbf_ack : integer := 12;
constant dat3_rbf_busy : integer := 11;
constant dat3_rbf_err : integer := 10;
constant dat3_rbf_we : integer := 9;
constant dat3_rbf_init : integer := 8;
subtype dat3_rbf_ndlymsb is integer range 7 downto 0;
subtype dat2_rbf_ndlylsb is integer range 15 downto 10;
subtype dat2_rbf_nbusy is integer range 9 downto 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
susp : slbit; -- suspended flag
go : slbit; -- go flag
hilim : slv16; -- upper address limit
lolim : slv16; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrsame: slbit; -- curr rb addr equal last rb addr
addrwind: slbit; -- curr rb addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
rbtake_1 : slbit; -- rb capture active in last cycle
rbaddr : slv16; -- rbus trace: addr
rbinit : slbit; -- rbus trace: init
rbwe : slbit; -- rbus trace: we
rback : slbit; -- rbus trace: ack seen
rbbusy : slbit; -- rbus trace: busy seen
rberr : slbit; -- rbus trace: err seen
rbnak : slbit; -- rbus trace: nak detected
rbtout : slbit; -- rbus trace: tout detected
rbburst : slbit; -- rbus trace: burst detected
rbdata : slv16; -- rbus trace: data
rbnbusy : slv10; -- rbus number of busy cycles
rbndly : slv14; -- rbus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
'0', -- rbsel
'0','0','0', -- rcolw,rcolr,wstop
'0','1', -- susp,go
x"fffb", -- hilim (def: fffb)
x"0000", -- lolim (def: 0000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- rbtake_1
x"ffff", -- rbaddr (startup: ffff)
'0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr
'0','0','0', -- rbnak,rbtout,rbburst
(others=>'0'), -- rbdata
(others=>'0'), -- rbnbusy
(others=>'0') -- rbndly
);
constant rbnbusylast : slv10 := (others=>'1');
constant rbndlylast : slv14 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM0_DI : slv32 := (others=>'0');
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
severity failure;
BRAM1 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
BRAM0 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RB_SRES_SUM, BRAM0_DO, BRAM1_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable rbtake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat0 : slv16 := (others=>'0');
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
ibramwe := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := RB_MREQ.din(cntl_rbf_rcolw);
n.rcolr := RB_MREQ.din(cntl_rbf_rcolr);
n.wstop := RB_MREQ.din(cntl_rbf_wstop);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => null; -- stat ------------------
when rbaddr_hilim => -- hilim -----------------
if RB_MREQ.we = '1' then
n.hilim := RB_MREQ.din;
end if;
when rbaddr_lolim => -- lolim -----------------
if RB_MREQ.we = '1' then
n.lolim := RB_MREQ.din;
end if;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := RB_MREQ.din(addr_rbf_laddr);
n.waddr := RB_MREQ.din(addr_rbf_waddr);
else
irb_err := '1'; -- otherwise error
end if;
end if;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1';
end if;
-- read to data always allowed, addr only incremented when not active
if RB_MREQ.re = '1' and r.go = '0' then
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
end if;
when others => -- <> --------------------
irb_err := '1';
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_rcolw) := r.rcolw;
irb_dout(cntl_rbf_rcolr) := r.rcolr;
irb_dout(cntl_rbf_wstop) := r.wstop;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-9,3));
irb_dout(stat_rbf_wrap) := r.wrap;
irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
irb_dout(stat_rbf_run) := r.go or r.susp; -- started
when rbaddr_hilim => -- hilim -----------------
irb_dout := r.hilim;
when rbaddr_lolim => -- lolim -----------------
irb_dout := r.lolim;
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "11" => irb_dout := BRAM1_DO(31 downto 16);
when "10" => irb_dout := BRAM1_DO(15 downto 0);
when "01" => irb_dout := BRAM0_DO(31 downto 16);
when "00" => irb_dout := BRAM0_DO(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- rbus monitor
-- a rbus transaction are captured if the address is in alim window
-- and the access is not refering to rbd_rbmon itself
-- Note: rbus init cycles come with aval=0 but addr is valid and checked !
-- rbus address monitor
if (RB_MREQ.aval='1' and r.aval_1='0') or RB_MREQ.init='1' then
n.rbaddr := RB_MREQ.addr;
n.addrsame := '0';
if RB_MREQ.addr = r.rbaddr then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := RB_MREQ.aval;
-- rbus data monitor
if (RB_MREQ.aval='1' and irbena='1') or RB_MREQ.init='1' then
if RB_MREQ.init='1' or RB_MREQ.we='1' then -- for write/init of din
n.rbdata := RB_MREQ.din;
else -- for read of dout
n.rbdata := RB_SRES_SUM.dout;
end if;
end if;
-- track state and decide on storage
rbtake := '0';
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
if r.addrwind='1' and r.rbsel='0' then -- and in window and not self
rbtake := '1';
end if;
end if;
if RB_MREQ.init = '1' then -- also take init's
rbtake := '1';
end if;
if rbtake = '1' then -- if capture active
n.rbinit := RB_MREQ.init; -- keep track of some state
n.rbwe := RB_MREQ.we;
if r.rbtake_1 = '0' then -- if initial cycle of a transaction
n.rback := RB_SRES_SUM.ack;
n.rbbusy := RB_SRES_SUM.busy;
n.rberr := RB_SRES_SUM.err;
n.rbnbusy := (others=>'0');
else -- if non-initial cycles
n.rback := r.rback or RB_SRES_SUM.ack; -- keep track of ack
n.rberr := r.rberr or RB_SRES_SUM.err; -- keep track of err
if r.rbnbusy /= rbnbusylast then -- and count
n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
end if;
end if;
n.rbnak := not RB_SRES_SUM.ack;
n.rbtout := RB_SRES_SUM.busy;
if RB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.addrsame := '1'; -- in case of burst
n.arm1r := r.rcolr and RB_MREQ.re;
n.arm1w := r.rcolw and RB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and RB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and RB_MREQ.we;
n.rcol := ((r.arm2r and RB_MREQ.re) or
(r.arm2w and RB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
n.rbburst := '1'; -- assume burst
end if;
if r.rbtake_1 = '1' then -- rbus transaction just ended
n.rbndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.rbndly /= rbndlylast then -- count cycles
n.rbndly := slv(unsigned(r.rbndly) + 1);
end if;
end if;
end if;
if RB_MREQ.aval = '0' then -- if aval gone
n.rbburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
idat3 := (others=>'0');
idat3(dat3_rbf_burst) := r.rbburst;
idat3(dat3_rbf_tout) := r.rbtout;
idat3(dat3_rbf_nak) := r.rbnak;
idat3(dat3_rbf_ack) := r.rback;
idat3(dat3_rbf_busy) := r.rbbusy;
idat3(dat3_rbf_err) := r.rberr;
idat3(dat3_rbf_we) := r.rbwe;
idat3(dat3_rbf_init) := r.rbinit;
idat3(dat3_rbf_ndlymsb):= r.rbndly(13 downto 6);
idat2(dat2_rbf_ndlylsb):= r.rbndly( 5 downto 0);
idat2(dat2_rbf_nbusy) := r.rbnbusy;
idat1 := r.rbdata;
idat0 := r.rbaddr;
n.rbtake_1 := rbtake;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
| gpl-3.0 | badede13a1ff57ca225e3e5703214b49 | 0.475398 | 3.619136 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_2.vhd | 1 | 2,012 | -- $Id: rb_sres_or_2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 33041ee288b2666a11f4ac7a16b88cb3 | 0.504473 | 3.081164 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/migui_core_gsim.vhd | 1 | 12,181 | -- $Id: migui_core_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui_core_gsim - sim
-- Description: MIG interface simulation core
--
-- Dependencies: sfs_gsim_core
-- Test bench: tb/tb_sramif2migui_core
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-11-10 1067 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.miglib.all;
entity migui_core_gsim is -- MIG interface simulation core
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
SAWIDTH : positive := 24; -- simulator memory address width
CLKMUI_MUL : positive := 6; -- multiplier for MIG UI clock
CLKMUI_DIV : positive := 12; -- divider for MIG UI clock
CACO_WAIT : positive := 50); -- UI_CLK cycles till CALIB_COMP = 1
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit -- MIGUI ZQ calibrate acknowledge
);
end migui_core_gsim;
architecture sim of migui_core_gsim is
constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16)
constant dwidth : positive := 8*mwidth; -- data width (64 or 128)
-- row/col split only relevant for timing simulation
-- use 16kbit->2kByte column width as used in MT41K128M16 on arty board
constant colwidth : positive := 11;
constant rowwidth : positive := MAWIDTH-colwidth;
subtype addr_f_row is integer range MAWIDTH-1 downto colwidth;
subtype bv8 is bit_vector(7 downto 0);
constant memsize : positive := 2**SAWIDTH;
constant datzero : bv8 := (others=>'0');
type ram_type is array (0 to memsize-1) of bv8;
-- timing constants
constant c_rdwait_rhit : positive := 2; -- read wait row match
constant c_rdwait_rmis : positive := 5; -- read wait row miss
constant c_wrwait_rhit : positive := 2; -- write wait row match
constant c_wrwait_rmis : positive := 5; -- write wait row miss
constant c_wrwait_max : positive := c_wrwait_rmis; -- write wait maximum
-- the REF and ZQ delays are as observed for arty board
constant c_refwait : positive := 10; -- REF_REQ to REF_ACK delay
constant c_zqwait : positive := 8; -- ZQ_REQ to ZQ_ACK delay
-- the RDY pattern gives 23% busy (4 out of 13 cycles)
-- good enough for simulation; observed pattern on arty shows ~6% busy,
constant c_crdy_init : slv13 := "0001111110111"; -- block 4 of 13;
type regs_type is record
cacowait : natural; -- CACO wait down counter
enacaco : slbit; -- CACO enable
enardy : slbit; -- RDY enable
rowaddr : slv(rowwidth-1 downto 0); -- current row address
rdwait : natural; -- read wait cycles pending
wrwait : natural; -- write wait cycles pending
crdypat : slv13; -- crdy pattern
refwait : natural; -- req_ack wait counter
zqwait : natural; -- zq_ack wait counter
end record regs_type;
constant rowaddr_init : slv(rowwidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
CACO_WAIT,'0','0', -- cacowait,enacaco,enardy
rowaddr_init, -- rowaddr
0,0, -- rdwait,wrwait
c_crdy_init, -- crdypat
0,0 -- refwait,zqwait
);
signal CLK : slbit; -- local copy of UI_CLK
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CLKFX : slbit;
signal MEM_EN : slbit := '0'; -- sim mem enable
signal MEM_WE : slbit := '0'; -- sim mem write enable
signal MEM_ADDR : slv(SAWIDTH-BAWIDTH-1 downto 0); -- sim mem base address
signal R_MEMDO : slv(dwidth-1 downto 0) := (others=>'0');
begin
assert BAWIDTH = 3 or BAWIDTH = 4
report "assert( BAWIDTH = 3 or 4 )"
severity failure;
UICLKGEN : sfs_gsim_core -- mig ui clock generator
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKMUI_MUL,
OUT_DIVIDE => CLKMUI_DIV)
port map (
CLKIN => SYS_CLK,
CLKFX => CLKFX,
LOCKED => open
);
CLK <= CLKFX; -- !! copy both local CLK and exported
UI_CLK <= CLKFX; -- !! UI_CLK to avoid delta cycle diff
UI_CLK_SYNC_RST <= '0';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, APP_EN, APP_ADDR, APP_CMD,
APP_WDF_WREN, APP_WDF_END,
APP_REF_REQ,APP_ZQ_REQ, R_MEMDO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iappcrdy : slbit := '0';
variable iappwrdy : slbit := '0';
variable iapprefack : slbit := '0';
variable iappzqack : slbit := '0';
variable imemen : slbit := '0';
variable imemwe : slbit := '0';
variable irdval : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iappcrdy := '1';
iappwrdy := '1';
iapprefack := '0';
iappzqack := '0';
imemen := '0';
imemwe := '0';
irdval := '0';
n.crdypat := r.crdypat(11 downto 0) & r.crdypat(12); -- circular right shift
-- simulate CACO wait
if r.cacowait > 0 then
n.cacowait := r.cacowait - 1;
if r.cacowait <= CACO_WAIT/2 then -- half of CACO wait reached ?
n.enardy := '1'; -- enable RDY's
end if;
if r.cacowait = 1 then -- CACO wait ended ?
n.enacaco := '1'; -- assert CACO
end if;
end if;
-- process cmd requests
if r.wrwait >= c_wrwait_max then
iappcrdy := '0';
iappwrdy := '0';
elsif r.rdwait > 0 then
iappcrdy := '0';
elsif r.enardy='0' or r.crdypat(0)='0' then
iappcrdy := '0';
else
if APP_EN = '1' then
if APP_CMD = c_migui_cmd_read then
imemen := '1';
if r.rowaddr = APP_ADDR(addr_f_row) then
n.rdwait := r.rdwait + c_rdwait_rhit;
else
n.rdwait := r.rdwait + c_rdwait_rmis;
n.rowaddr := APP_ADDR(addr_f_row);
end if;
elsif APP_CMD = c_migui_cmd_write then
imemen := '1';
imemwe := '1';
if r.rowaddr = APP_ADDR(addr_f_row) then
n.wrwait := r.wrwait + c_wrwait_rhit;
else
n.wrwait := r.wrwait + c_wrwait_rmis;
n.rowaddr := APP_ADDR(addr_f_row);
end if;
else
end if;
end if;
end if;
-- handle cmd waits, issue read responses
if r.enacaco = '1' then -- process commands only after CACO
if r.wrwait > 0 then -- first wait for pending writes
n.wrwait := r.wrwait - 1;
else
if r.rdwait > 0 then -- next of for pending reads
n.rdwait := r.rdwait - 1;
if r.rdwait = 1 then
irdval := '1';
end if;
end if;
end if;
end if;
-- process ref_req requests
if APP_REF_REQ = '1' then
n.refwait := c_refwait;
else
if r.refwait > 0 then
n.refwait := r.refwait -1;
if r.refwait = 1 then
iapprefack := '1';
end if;
end if;
end if;
-- process zq_req requests
if APP_ZQ_REQ = '1' then
n.zqwait := c_zqwait;
else
if r.zqwait > 0 then
n.zqwait := r.zqwait -1;
if r.zqwait = 1 then
iappzqack := '1';
end if;
end if;
end if;
N_REGS <= n;
INIT_CALIB_COMPLETE <= r.enacaco;
APP_RDY <= iappcrdy;
APP_WDF_RDY <= iappwrdy;
APP_RD_DATA_VALID <= irdval;
APP_RD_DATA_END <= irdval;
APP_REF_ACK <= iapprefack;
APP_ZQ_ACK <= iappzqack;
if irdval = '1' then -- only in the RD_DATA_END cycle
APP_RD_DATA <= R_MEMDO; -- export the data
else -- otherwise
APP_RD_DATA <= (others=>'1'); -- send all ones
end if;
MEM_EN <= imemen;
MEM_WE <= imemwe;
MEM_ADDR <= APP_ADDR(SAWIDTH-1 downto BAWIDTH);
end process proc_next;
proc_mem: process (CLK)
variable ram : ram_type := (others=>datzero);
variable membase : integer := 0;
begin
if rising_edge(CLK) then
if MEM_EN = '1' then
membase := mwidth*to_integer(unsigned(MEM_ADDR));
-- write to memory
if APP_WDF_WREN = '1' then
for i in 0 to mwidth-1 loop
if APP_WDF_MASK(i) = '0' then -- WE = not MASK !!
ram(membase + i) :=
to_bitvector(to_x01(APP_WDF_DATA(8*i+7 downto 8*i)));
end if;
end loop;
end if;
-- read from memory
for i in 0 to mwidth-1 loop
R_MEMDO(8*i+7 downto 8*i) <= to_stdlogicvector(ram(membase + i));
end loop;
end if;
end if;
end process proc_mem;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '0' then
if APP_EN = '1' then
assert APP_CMD = c_migui_cmd_read or
APP_CMD = c_migui_cmd_write
report "migui_core_gsim: FAIL: APP_CMD not 000 or 001"
severity error;
assert unsigned(APP_ADDR(MAWIDTH-1 downto SAWIDTH)) = 0
report "migui_core_gsim: FAIL: out of sim-memory size access"
severity error;
end if;
if APP_EN = '1' and APP_CMD = c_migui_cmd_write then
assert APP_WDF_WREN='1' and APP_WDF_END='1'
report "migui_core_gsim: FAIL: APP_WDF_(END,WREN) missed on write"
severity error;
else
assert APP_WDF_WREN='0' and APP_WDF_END='0'
report "migui_core_gsim: FAIL: spurious APP_WDF_(END,WREN)"
severity error;
end if;
end if;
end if;
end process proc_moni;
end sim;
| gpl-3.0 | 1e2dccb737521b119c6cb1a01c54ca49 | 0.524259 | 3.637205 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/tst_serloop.vhd | 1 | 7,400 | -- $Id: tst_serloop.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop - syn
-- Description: simple stand-alone tester for serport components
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 1.0.3 fix for ghdl V0.36 -Whide warnings
-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-06 420 1.0 Initial version
-- 2011-10-14 416 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end tst_serloop;
architecture syn of tst_serloop is
type regs_type is record
rxdata : slv8; -- next rx char
txdata : slv8; -- next tx char
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
rxok_1 : slbit; -- rxok last cycle
txok_1 : slbit; -- txok last cycle
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0'), -- txokcnt
'0','0', -- rxok_1,txok_1
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
RXDATA, RXVAL, TXBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxhold : slbit := '1';
variable itxena : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable skipxon : slbit := '0';
function nextchar(pskipxon: in slbit; pdata: in slv8) return slv8 is
variable inc : slv8 := (others=>'0');
begin
inc := "00000001";
if pskipxon='1' and (pdata=c_serport_xon or pdata=c_serport_xoff) then
inc := "00000010";
end if;
return slv(unsigned(pdata)+unsigned(inc));
end function nextchar;
begin
r := R_REGS;
n := R_REGS;
irxhold := '1';
itxena := '0';
itxdata := RXDATA;
if HIO_CNTL.mode = c_mode_txblast then
itxdata := r.txdata;
end if;
skipxon := '0';
if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
skipxon := '1';
end if;
if HIO_CNTL.enathrottle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXVAL='1' and r.rxthrottle='0' then
irxhold := '0';
if RXDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := nextchar(skipxon, RXDATA);
end if;
when c_mode_txblast =>
if TXBUSY = '0' then
itxena := '1';
n.txdata := nextchar(skipxon, r.txdata);
end if;
irxhold := '0';
if RXVAL = '1' then
n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
n.rxuidat := RXDATA;
end if;
when c_mode_loop =>
if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
irxhold := '0';
itxena := '1';
end if;
when others => null;
end case;
if SER_MONI.abact = '1' then -- if auto bauder active
n.rxfecnt := (others=>'0'); -- reset frame error counter
else -- otherwise
if SER_MONI.rxerr = '1' then -- count rx frame errors
n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
end if;
end if;
if SER_MONI.rxovr = '1' then
n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
end if;
if RXVAL='1' and irxhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
n.rxok_1 := SER_MONI.rxok;
n.txok_1 := SER_MONI.txok;
if SER_MONI.rxok='0' and r.rxok_1='1' then
n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
end if;
if SER_MONI.txok='0' and r.txok_1='1' then
n.txokcnt := slv(unsigned(r.txokcnt) + 1);
end if;
N_REGS <= n;
RXHOLD <= irxhold;
TXENA <= itxena;
TXDATA <= itxdata;
HIO_STAT.rxfecnt <= r.rxfecnt;
HIO_STAT.rxoecnt <= r.rxoecnt;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.rxuicnt <= r.rxuicnt;
HIO_STAT.rxuidat <= r.rxuidat;
HIO_STAT.rxokcnt <= r.rxokcnt;
HIO_STAT.txokcnt <= r.txokcnt;
end process proc_next;
end syn;
| gpl-3.0 | 7bdc04faf6c24480f58f69768e65d301 | 0.490541 | 3.870293 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_intmap24.vhd | 1 | 6,977 | -- $Id: ib_intmap24.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_intmap24 - syn
-- Description: pdp11: external interrupt mapper (23 line)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2016.4-2017.2; ghdl 0.33-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2016-05-26 641 2016.4 xc7a100t-1 0 48 0 0 - -
-- 2015-02-22 641 i 14.7 xc6slx16-2 0 38 0 0 20 -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 1.1 BUGFIX: ensure ACK send to correct device
-- 2017-01-28 846 1.0 Initial version (cloned from ib_intmap.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_intmap24 is -- external interrupt mapper (23 line)
generic (
INTMAP : intmap24_array_type := intmap24_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv24_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end ib_intmap24;
architecture syn of ib_intmap24 is
signal EI_LINE : slv5 := (others=>'0'); -- external interrupt line
signal R_LINE : slv5 := (others=>'0'); -- line on last cycle
type intp_type is array (23 downto 0) of slv3;
type intv_type is array (23 downto 0) of slv9;
constant conf_intp : intp_type :=
(slv(to_unsigned(INTMAP(23).pri,3)), -- line 23
slv(to_unsigned(INTMAP(22).pri,3)), -- line 22
slv(to_unsigned(INTMAP(21).pri,3)), -- line 21
slv(to_unsigned(INTMAP(20).pri,3)), -- line 20
slv(to_unsigned(INTMAP(19).pri,3)), -- line 19
slv(to_unsigned(INTMAP(18).pri,3)), -- line 18
slv(to_unsigned(INTMAP(17).pri,3)), -- line 17
slv(to_unsigned(INTMAP(16).pri,3)), -- line 16
slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
);
constant conf_intv : intv_type :=
(
slv(to_unsigned(INTMAP(23).vec,9)), -- line 23
slv(to_unsigned(INTMAP(22).vec,9)), -- line 22
slv(to_unsigned(INTMAP(21).vec,9)), -- line 21
slv(to_unsigned(INTMAP(20).vec,9)), -- line 20
slv(to_unsigned(INTMAP(19).vec,9)), -- line 19
slv(to_unsigned(INTMAP(18).vec,9)), -- line 18
slv(to_unsigned(INTMAP(17).vec,9)), -- line 17
slv(to_unsigned(INTMAP(16).vec,9)), -- line 16
slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
);
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
begin
EI_LINE <= "10111" when EI_REQ(23)='1' else
"10110" when EI_REQ(22)='1' else
"10101" when EI_REQ(21)='1' else
"10100" when EI_REQ(20)='1' else
"10011" when EI_REQ(19)='1' else
"10010" when EI_REQ(18)='1' else
"10001" when EI_REQ(17)='1' else
"10000" when EI_REQ(16)='1' else
"01111" when EI_REQ(15)='1' else
"01110" when EI_REQ(14)='1' else
"01101" when EI_REQ(13)='1' else
"01100" when EI_REQ(12)='1' else
"01011" when EI_REQ(11)='1' else
"01010" when EI_REQ(10)='1' else
"01001" when EI_REQ( 9)='1' else
"01000" when EI_REQ( 8)='1' else
"00111" when EI_REQ( 7)='1' else
"00110" when EI_REQ( 6)='1' else
"00101" when EI_REQ( 5)='1' else
"00100" when EI_REQ( 4)='1' else
"00011" when EI_REQ( 3)='1' else
"00010" when EI_REQ( 2)='1' else
"00001" when EI_REQ( 1)='1' else
"00000";
proc_line: process (CLK)
begin
if rising_edge(CLK) then
R_LINE <= EI_LINE;
end if;
end process proc_line;
-- Note: EI_ACKM comes one cycle after vector is latched ! Therefore
-- - use EI_LINE to select vector to send to EI_PRI and EI_VECT
-- - use R_LINE to select EI_ACM line for acknowledge
proc_intmap : process (EI_LINE, EI_ACKM, R_LINE)
variable ilinecur : integer := 0;
variable ilinelst : integer := 0;
variable iei_ack : slv24 := (others=>'0');
begin
ilinecur := to_integer(unsigned(EI_LINE));
ilinelst := to_integer(unsigned(R_LINE));
-- send info of currently highest priority request
EI_PRI <= conf_intp(ilinecur);
EI_VECT <= conf_intv(ilinecur)(8 downto 2);
-- route acknowledge back to winner line of last cycle
iei_ack := (others=>'0');
if EI_ACKM = '1' then
iei_ack(ilinelst) := '1';
end if;
EI_ACK <= iei_ack(EI_ACK'range);
end process proc_intmap;
end syn;
| gpl-3.0 | 4f32c0b81ce4a7cd843954fefb5573ab | 0.541493 | 3.174249 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_deuna.vhd | 1 | 14,495 | -- $Id: ibdr_deuna.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_deuna - syn
-- Description: ibus dev(rem): DEUNA
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2016.4-2017.1; ghdl 0.33-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-05-06 894 14.7 131013 xc6slx16-2 53 92 0 42 s 4.4
-- 2017-04-14 874 14.7 131013 xc6slx16-2 50 79 0 40 s 4.1
-- 2017-01-29 847 14.7 131013 xc6slx16-2 42 70 0 36 s 4.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-05-06 894 1.0 Initial version (full functionality)
-- 2017-04-14 875 0.5 Initial version (partial functionality)
-- 2014-06-09 561 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_deuna is -- ibus dev(rem): DEUNA
-- fixed address: 174510
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_deuna;
architecture syn of ibdr_deuna is
constant ibaddr_deuna : slv16 := slv(to_unsigned(8#174510#,16));
constant ibaddr_pr0 : slv2 := "00"; -- pcsr0 address offset
constant ibaddr_pr1 : slv2 := "01"; -- pcsr1 address offset
constant ibaddr_pr2 : slv2 := "10"; -- pcsr2 address offset
constant ibaddr_pr3 : slv2 := "11"; -- pcsr3 address offset
constant pr0_ibf_seri : integer := 15;
constant pr0_ibf_pcei : integer := 14;
constant pr0_ibf_rxi : integer := 13;
constant pr0_ibf_txi : integer := 12;
constant pr0_ibf_dni : integer := 11;
constant pr0_ibf_rcbi : integer := 10;
constant pr0_ibf_usci : integer := 8;
constant pr0_ibf_intr : integer := 7;
constant pr0_ibf_inte : integer := 6;
constant pr0_ibf_rset : integer := 5;
subtype pr0_ibf_pcmd is integer range 3 downto 0;
-- additional rem view assignments
subtype pr0_ibf_pcmdbp is integer range 15 downto 12;
constant pr0_ibf_pdmdwb: integer := 10;
constant pr0_ibf_busy : integer := 9;
constant pr0_ibf_pcwwb : integer := 8;
constant pr0_ibf_brst : integer := 4;
constant pcmd_noop : slv4 := "0000"; -- pcmd: noop (DNI not set !)
constant pcmd_pdmd : slv4 := "1000"; -- pcmd: pdmd
constant pr1_ibf_xpwr : integer := 15;
constant pr1_ibf_icab : integer := 14;
subtype pr1_ibf_ecod is integer range 13 downto 8;
constant pr1_ibf_pcto : integer := 7;
constant pr1_ibf_deuna : integer := 4; -- id bit 0 (0=DEUNA;1=DELUA)
subtype pr1_ibf_state is integer range 3 downto 0;
constant state_reset : slv4 := "0000"; -- state: reset
constant state_ready : slv4 := "0010"; -- state: ready
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
pr0seri : slbit; -- pr0: status error intr
pr0pcei : slbit; -- pr0: port command error intr
pr0rxi : slbit; -- pr0: receive ring intr
pr0txi : slbit; -- pr0: transmit ring intr
pr0dni : slbit; -- pr0: done interrupt
pr0rcbi : slbit; -- pr0: receive buffer unavail intr
pr0usci : slbit; -- pr0: unsolicited state change intr
pr0intr : slbit; -- pr0: intr summary
pr0inte : slbit; -- pr0: intr enable
pr0rset : slbit; -- pr0: software reset
pr0brst : slbit; -- pr0: BRESET reset
pr0pcmd : slv4; -- pr0: port command
pr1xpwr : slbit; -- pr1: transmitter power fail
pr1icab : slbit; -- pr1: port/link cabling fail
pr1pcto : slbit; -- pr1: port command time out
pr1deuna : slbit; -- pr1: bit 0 of ID (0=DEUNA;1=DELUA)
pr1state : slv4; -- pr1: port status
pcbb : slv18_1; -- pr2+3: port conrol block base
pdmdwb : slbit; -- restart for pdmd while busy
busy : slbit; -- busy
pcmdwwb : slbit; -- pcmd written while busy
pcmdbp : slv4; -- pcmd busy protected
resreq : slbit; -- reset requested
ireq : slbit; -- interrupt request flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0', -- pr0seri,pr0pcei,pr0rxi,pr0txi
'0','0','0', -- pr0dni,pr0rcbi,pr0usci
'0','0', -- pr0intr,pr0inte
'0','0', -- pr0rset,pr0brst
(others=>'0'), -- pr0pcmd
'1','1', -- pr1xpwr,pr1icab
'0','0', -- pr1pcto,pr1deuna
state_reset, -- pr1state
(others=>'0'), -- pcbb
'0','0','0', -- pdmdwb,busy,pcmdwwb
(others=>'0'), -- pcmdbp
'0', -- resreq
'0' -- ireq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, BRESET)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 3)=ibaddr_deuna(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel='1' then -- selected
case IB_MREQ.addr(2 downto 1) is
when ibaddr_pr0 => -- PCSR0 - intr and pcmd -----------
if ibrem = '0' then -- loc view of upper byte
idout(pr0_ibf_seri) := r.pr0seri;
idout(pr0_ibf_pcei) := r.pr0pcei;
idout(pr0_ibf_rxi) := r.pr0rxi;
idout(pr0_ibf_txi) := r.pr0txi;
idout(pr0_ibf_dni) := r.pr0dni;
idout(pr0_ibf_rcbi) := r.pr0rcbi;
idout(pr0_ibf_usci) := r.pr0usci;
else -- rem view of upper byte
idout(pr0_ibf_pcmdbp) := r.pcmdbp;
idout(pr0_ibf_pdmdwb) := r.pdmdwb;
idout(pr0_ibf_busy) := r.busy;
idout(pr0_ibf_pcwwb) := r.pcmdwwb;
end if;
idout(pr0_ibf_intr) := r.pr0intr;
idout(pr0_ibf_inte) := r.pr0inte;
if ibrem = '1' then
idout(pr0_ibf_rset) := r.pr0rset; -- only seen from rem side
idout(pr0_ibf_brst) := r.pr0brst; -- only seen from rem side
end if;
idout(pr0_ibf_pcmd) := r.pr0pcmd;
if IB_MREQ.we = '1' then
if ibrem = '1' then -- rem write
if IB_MREQ.din(pr0_ibf_seri) = '1' then n.pr0seri := '1'; end if;
if IB_MREQ.din(pr0_ibf_pcei) = '1' then
n.pcmdwwb := '0';
n.pdmdwb := '0';
n.busy := '0';
n.pr0pcei := '1';
end if;
if IB_MREQ.din(pr0_ibf_rxi) = '1' then n.pr0rxi := '1'; end if;
if IB_MREQ.din(pr0_ibf_txi) = '1' then n.pr0txi := '1'; end if;
if IB_MREQ.din(pr0_ibf_dni) = '1' then
n.pcmdwwb := '0';
n.pdmdwb := '0';
-- if pdmd issued while busy, restart with pdmd, else end pcmd
if r.pcmdwwb = '1' and r.pr0pcmd = pcmd_pdmd then
n.pcmdbp := pcmd_pdmd;
n.pdmdwb := '1';
ilam := '1'; -- rri lam: restart with pdmd
else
n.busy := '0';
n.pr0dni := '1';
end if;
end if;
if IB_MREQ.din(pr0_ibf_rcbi) = '1' then n.pr0rcbi := '1'; end if;
if IB_MREQ.din(pr0_ibf_busy) = '1' then n.busy := '0'; end if;
if IB_MREQ.din(pr0_ibf_usci) = '1' then n.pr0usci := '1'; end if;
if IB_MREQ.din(pr0_ibf_rset) = '1' then
n.busy := '0';
n.pr0rset := '0';
end if;
if IB_MREQ.din(pr0_ibf_brst) = '1' then
n.busy := '0';
n.pr0brst := '0';
end if;
else -- loc write
if IB_MREQ.be1 = '1' then
if IB_MREQ.din(pr0_ibf_seri) = '1' then n.pr0seri := '0'; end if;
if IB_MREQ.din(pr0_ibf_pcei) = '1' then n.pr0pcei := '0'; end if;
if IB_MREQ.din(pr0_ibf_rxi) = '1' then n.pr0rxi := '0'; end if;
if IB_MREQ.din(pr0_ibf_txi) = '1' then n.pr0txi := '0'; end if;
if IB_MREQ.din(pr0_ibf_dni) = '1' then n.pr0dni := '0'; end if;
if IB_MREQ.din(pr0_ibf_rcbi) = '1' then n.pr0rcbi := '0'; end if;
if IB_MREQ.din(pr0_ibf_usci) = '1' then n.pr0usci := '0'; end if;
end if;
if IB_MREQ.be0 = '1' then
if IB_MREQ.din(pr0_ibf_rset) = '1' then -- RESET requested ?
n.resreq := '1';
n.pr0rset := '1';
elsif IB_MREQ.din(pr0_ibf_inte) /= r.pr0inte then -- INTE change?
n.pr0inte := IB_MREQ.din(pr0_ibf_inte);
n.pr0dni := '1';
elsif r.pr1state /= state_reset then -- not in reset
n.pr0pcmd := IB_MREQ.din(pr0_ibf_pcmd);
if r.busy = '0' then -- if not busy execute
n.pcmdbp := IB_MREQ.din(pr0_ibf_pcmd);
if IB_MREQ.din(pr0_ibf_pcmd) /= pcmd_noop then
n.busy := '1'; -- signal busy
ilam := '1'; -- rri lam
end if;
else -- if busy set pcmdwwf flag
n.pcmdwwb := '1';
end if;
end if;
end if; -- if IB_MREQ.be0 = '1'
end if; -- else ibrem = '1'
end if; -- if IB_MREQ.we = '1'
when ibaddr_pr1 => -- PCSR1 - status ------------------
idout(pr1_ibf_xpwr) := r.pr1xpwr;
idout(pr1_ibf_icab) := r.pr1icab;
idout(pr1_ibf_pcto) := r.pr1pcto;
idout(pr1_ibf_deuna) := r.pr1deuna;
idout(pr1_ibf_state) := r.pr1state;
if IB_MREQ.we = '1' then
if ibrem = '1' then
n.pr1xpwr := IB_MREQ.din(pr1_ibf_xpwr);
n.pr1icab := IB_MREQ.din(pr1_ibf_icab);
n.pr1pcto := IB_MREQ.din(pr1_ibf_pcto);
n.pr1deuna := IB_MREQ.din(pr1_ibf_deuna);
n.pr1state := IB_MREQ.din(pr1_ibf_state);
end if;
end if;
when ibaddr_pr2 => -- PCSR2 - pcbb low order ----------
idout(15 downto 1) := r.pcbb(15 downto 1);
if IB_MREQ.we = '1' then
n.pcbb(15 downto 1) := IB_MREQ.din(15 downto 1);
end if;
when ibaddr_pr3 => -- PCSR2 - pcbb high order ---------
idout( 1 downto 0) := r.pcbb(17 downto 16);
if IB_MREQ.we = '1' then
n.pcbb(17 downto 16) := IB_MREQ.din( 1 downto 0);
end if;
when others => null;
end case;
end if;
if BRESET = '1' then
n.resreq := '1';
n.pr0brst := '1';
end if;
if r.resreq = '1' then
n.pr0seri := '0';
n.pr0pcei := '0';
n.pr0rxi := '0';
n.pr0txi := '0';
n.pr0dni := '0';
n.pr0rcbi := '0';
n.pr0usci := '0';
n.pr1pcto := '0';
n.pr0inte := '0';
n.pr1state := state_reset;
n.pcbb := (others => '0');
n.resreq := '0';
-- send lam on soft or bus reset only when not in state_reset
-- the startup default is state_reset, so without active backend
-- this device will not send lam's on bus resets
if r.pr1state /= state_reset then
n.busy := '1'; -- signal busy
ilam := '1'; -- rri lam unless reset handling pending
end if;
end if;
n.pr0intr := r.pr0seri or r.pr0pcei or r.pr0rxi or r.pr0txi or
r.pr0dni or r.pr0rcbi or r.pr0usci;
if r.pr0inte = '1' then
n.ireq := r.pr0intr;
else
n.ireq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= r.ireq;
end process proc_next;
end syn;
| gpl-3.0 | 8b4440815e3974b65d9c101e296437f0 | 0.465816 | 3.362329 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/mul.vhd | 1 | 2,988 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul is
generic (
mul_width: integer := 32
);
port ( clock: in std_logic;
reset: in std_logic;
trg: in std_logic;
sig0: in std_logic;
sig1: in std_logic;
i0: in std_logic_vector(mul_width-1 downto 0);
i1: in std_logic_vector(mul_width-1 downto 0);
o0: out std_logic_vector(mul_width-1 downto 0);
o1: out std_logic_vector(mul_width-1 downto 0);
rdy: out std_logic
);
end mul;
architecture mul_arch of mul is
type states is (start, multiply, done);
signal current_state, next_state: states;
signal reg: std_logic_vector(mul_width*2 downto 0);
signal i0_reg: std_logic_vector(mul_width-1 downto 0);
signal a, add_sub: std_logic_vector(mul_width downto 0);
signal sign, rdy_sig: std_logic;
signal counter: std_logic_vector(4 downto 0);
begin
process(clock, reset)
begin
if reset = '1' then
rdy_sig <= '1';
reg <= (others => '0');
elsif clock'event and clock = '1' then
case current_state is
when start =>
i0_reg <= i0;
reg(mul_width*2 downto mul_width+1) <= (others => '0');
-- if (sig1 = '1') then
-- reg(mul_width downto 0) <= i1(mul_width-1) & i1;
-- else
reg(mul_width downto 0) <= '0' & i1;
-- end if;
counter <= (others => '0');
when multiply =>
rdy_sig <= '0';
if (reg(0) = '1') then
reg <= ((sig0 and add_sub(mul_width)) & add_sub & reg(mul_width-1 downto 1));
counter <= counter + 1;
elsif (reg(3 downto 0) = "0000" and counter < mul_width-4) then
reg <= (reg(mul_width*2) & reg(mul_width*2) & reg(mul_width*2) & reg(mul_width*2) & reg((mul_width*2) downto 4));
counter <= counter + 4;
else
reg <= (reg(mul_width*2) & reg((mul_width*2) downto 1));
counter <= counter + 1;
end if;
when done =>
rdy_sig <= '1';
when others => null;
end case;
end if;
end process;
process(clock, reset)
begin
if reset = '1' then
current_state <= start;
elsif clock'event and clock = '1' then
current_state <= next_state;
end if;
end process;
process(current_state, counter, trg)
begin
case current_state is
when start =>
if trg = '1' then
next_state <= multiply;
else
next_state <= start;
end if;
when multiply =>
if counter = mul_width-1 then
next_state <= done;
else
next_state <= multiply;
end if;
when done =>
next_state <= start;
end case;
end process;
sign <= i0_reg(mul_width-1) when sig0 = '1' else '0';
a <= sign & i0_reg;
add_sub <= reg(mul_width*2 downto mul_width) - a when (counter = mul_width-1) and sig0 = '1' else
reg(mul_width*2 downto mul_width) + a;
o1 <= reg((mul_width*2)-1 downto mul_width);
-- o1 <= not reg((mul_width*2)-1 downto mul_width) + 1 when sig1 = '1' and i0_reg(mul_width-1) = '1' else reg((mul_width*2)-1 downto mul_width);
o0 <= reg(mul_width-1 downto 0);
rdy <= rdy_sig;
end mul_arch;
| gpl-2.0 | 4b8f3372f2baac41ca435acca63eb9b1 | 0.609103 | 2.665477 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04500_bad.vhd | 1 | 3,223 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-17 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04500_bad.vhd
-- File Creation date : 2015-04-17
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset registers: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_04500_bad is
generic (
g_Width : positive := 4
);
port (
i_Clock : in std_logic;
i_Reset_n : in std_logic;
i_Data : in std_logic_vector(g_Width-1 downto 0);
o_Sum : out std_logic_vector(g_Width downto 0)
);
end CNE_04500_bad;
architecture Behavioral of CNE_04500_bad is
type Data_4_Reg is array (0 to 3) of std_logic_vector(g_Width-1 downto 0);
signal Data_Reg : Data_4_Reg;
signal Sum : std_logic_vector(g_Width downto 0);
signal Sum_r : std_logic_vector(g_Width downto 0);
begin
p_Reg:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Data_Reg <= (others => (others => '0'));
elsif (rising_edge(i_Clock)) then
Data_Reg(3) <= Data_Reg(2);
Data_Reg(2) <= Data_Reg(1);
Data_Reg(1) <= Data_Reg(0);
Data_Reg(0) <= i_Data;
Sum_r <= Sum;
end if;
end process;
Sum <= std_logic_vector(unsigned('0' & Data_Reg(3)) + unsigned('0' & Data_Reg(2)));
o_Sum <= Sum_r;
end Behavioral;
--CODE | gpl-3.0 | 69faf55f053d6cd21a62c1189adeb31c | 0.492709 | 4.153351 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd | 1 | 5,841 | -- $Id: bp_rs232_2l4l_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal(2line) + external(4line) rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14,7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
begin
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
proc_regs_mux: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
| gpl-3.0 | 18cac0967af2f1839dbc379c8f0ea6da | 0.469611 | 3.074211 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | ULA.vhd | 1 | 1,795 | Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
Entity ULA is
port (
in0, in1: in std_logic_vector(31 downto 0);
oper: in std_logic_vector(3 downto 0);
zero: out std_logic;
output : out std_logic_vector(31 downto 0)
);
end ULA;
architecture rtl of ULA is
signal sig_output: std_logic_vector(31 downto 0);
begin
process(oper, in0, in1)
begin
case oper is
when "0000" =>
sig_output <= in0 and in1;
when "0001" =>
sig_output <= in0 or in1;
when "0010" =>
sig_output <= in0 + in1;
--when "0011" =>
--sig_output <= in0 * in1;
--when "0100" =>
--sig_output <= in0 / in1;
when "0101" =>
sig_output <= in0 nor in1;
when "0110" =>
sig_output <= in0 - in1;
when "0111" => -- verificar
sig_output <= (0 => '1', others => '0');
when "1000" =>
sig_output <= in0 xor in1;
when "1001" =>
sig_output <= std_logic_vector(signed(in0) sll to_integer(signed(in1)));
when "1010" =>
sig_output <= std_logic_vector(signed(in0) srl to_integer(signed(in1)));
when "1011" =>
sig_output <= std_logic_vector(shift_right(signed(in0),to_integer(signed(in1))));
when "1100" =>
if (in0 < in1) then
sig_output <= "00000000000000000000000000000001";
else
sig_output <= "00000000000000000000000000000000";
end if;
when "1101" =>
if (unsigned(in0) < unsigned(in1)) then
sig_output <= "00000000000000000000000000000001";
else
sig_output <= "00000000000000000000000000000000";
end if;
WHEN OTHERS =>
sig_output <= in0;
end case;
end process;
zero <= '1' when sig_output = "00000000000000000000000000000000"
else '0';
output <= sig_output;
end rtl; | mit | 5667673dad79213933f79a137abecbb4 | 0.599443 | 2.981728 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/UART6_TX.unconstrained.vhdl | 1 | 15,513 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6_unconstrained is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6_unconstrained;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6
--
architecture rtl of uart_tx6_unconstrained is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
-- attribute hblknm of pointer3_lut : label is "uart_tx6_1";
-- attribute hblknm of pointer3_flop : label is "uart_tx6_1";
-- attribute hblknm of pointer2_lut : label is "uart_tx6_1";
-- attribute hblknm of pointer2_flop : label is "uart_tx6_1";
-- attribute hblknm of pointer01_lut : label is "uart_tx6_1";
-- attribute hblknm of pointer1_flop : label is "uart_tx6_1";
-- attribute hblknm of pointer0_flop : label is "uart_tx6_1";
-- attribute hblknm of data_present_lut : label is "uart_tx6_1";
-- attribute hblknm of data_present_flop : label is "uart_tx6_1";
-- --
-- attribute hblknm of sm0_lut : label is "uart_tx6_2";
-- attribute hblknm of sm0_flop : label is "uart_tx6_2";
-- attribute hblknm of sm1_lut : label is "uart_tx6_2";
-- attribute hblknm of sm1_flop : label is "uart_tx6_2";
-- attribute hblknm of sm2_lut : label is "uart_tx6_2";
-- attribute hblknm of sm2_flop : label is "uart_tx6_2";
-- attribute hblknm of sm3_lut : label is "uart_tx6_2";
-- attribute hblknm of sm3_flop : label is "uart_tx6_2";
-- --
-- attribute hblknm of div01_lut : label is "uart_tx6_3";
-- attribute hblknm of div23_lut : label is "uart_tx6_3";
-- attribute hblknm of div0_flop : label is "uart_tx6_3";
-- attribute hblknm of div1_flop : label is "uart_tx6_3";
-- attribute hblknm of div2_flop : label is "uart_tx6_3";
-- attribute hblknm of div3_flop : label is "uart_tx6_3";
-- attribute hblknm of next_lut : label is "uart_tx6_3";
-- attribute hblknm of next_flop : label is "uart_tx6_3";
-- attribute hblknm of read_flop : label is "uart_tx6_3";
-- --
-- attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
-- attribute hblknm of msb_data_lut : label is "uart_tx6_4";
-- attribute hblknm of serial_lut : label is "uart_tx6_4";
-- attribute hblknm of serial_flop : label is "uart_tx6_4";
-- attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
-- attribute hblknm of storage_srl : label is "uart_tx6_5";
-- attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | 45f91b4af2ed23d0c0ad069f1ed6334b | 0.489912 | 3.845563 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/Shift.vhd | 1 | 2,345 | --------------------------------------------------------------------------
-- Shift
--------------------------------------------------------------------------
-- 0,01,000 SLL (Shift Left logical)
-- 0,01,010 SRL (Shift Right logical)
-- 0,01,011 SRA (Shift Right arithmetic)
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift is
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end shift;
architecture beh_shift of shift is
begin
process (Control, Operand1, Operand2)
variable Temp : STD_LOGIC_VECTOR (31 downto 0);
begin
Temp := Operand1;
if Control(1) = '0' then -- left
if Operand2(0) = '1' then
Temp := Temp(30 downto 0) & '0';
end if;
if Operand2(1) = '1' then
Temp := Temp(29 downto 0) & "00";
end if;
if Operand2(2) = '1' then
Temp := Temp(27 downto 0) & X"0";
end if;
if Operand2(3) = '1' then
Temp := Temp(23 downto 0) & X"00";
end if;
if Operand2(4) = '1' then
Temp := Temp(15 downto 0) & X"0000";
end if;
end if;
if Control(1) = '1' then -- right
if Control(0) = '0' then -- logical
if Operand2(0) = '1' then
Temp := '0' & Temp(31 downto 1);
end if;
if Operand2(1) = '1' then
Temp := "00" & Temp(31 downto 2);
end if;
if Operand2(2) = '1' then
Temp := X"0" & Temp(31 downto 4);
end if;
if Operand2(3) = '1' then
Temp := X"00" & Temp(31 downto 8);
end if;
if Operand2(4) = '1' then
Temp := X"0000" & Temp(31 downto 16);
end if;
else -- arithmetic
Temp := std_logic_vector(shift_right(signed(Operand1), to_integer(unsigned(Operand2(4 downto 0)))));
end if;
end if;
Result1 <= Temp;
Result2 <= X"00000000";
Debug <= X"0000000";
end process;
end beh_shift; | gpl-2.0 | 15d6b2aec5f7229f9cae460888ead051 | 0.471642 | 3.585627 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdc_pulse.vhd | 1 | 3,609 | -- $Id: cdc_pulse.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdc_pulse - syn
-- Description: clock domain crossing for a pulse
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; viv 2015.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-11 774 1.2 add INIT generic
-- 2016-03-29 756 1.1 rename regs; add ASYNC_REG attributes
-- 2011-11-09 422 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false; -- if true: busy waits for ack
INIT : slbit := '0'); -- initial state
port (
CLKM : in slbit; -- M|clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- S|clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end entity cdc_pulse;
architecture syn of cdc_pulse is
signal RM_REQ : slbit := INIT; -- request active
signal RS_REQ_S0 : slbit := INIT; -- request: CLKM->CLKS
signal RS_REQ_S1 : slbit := INIT; -- request: CLKS->CLKS
signal RM_ACK_S0 : slbit := '0'; -- acknowledge: CLKS->CLKM
signal RM_ACK_S1 : slbit := '0'; -- acknowledge: CLKM->CLKM
attribute ASYNC_REG: string;
attribute ASYNC_REG of RS_REQ_S0 : signal is "true";
attribute ASYNC_REG of RS_REQ_S1 : signal is "true";
attribute ASYNC_REG of RM_ACK_S0 : signal is "true";
attribute ASYNC_REG of RM_ACK_S1 : signal is "true";
begin
proc_master: process (CLKM)
begin
if rising_edge(CLKM) then
if RESET = '1' then
RM_REQ <= '0';
else
if PIN = '1' then
RM_REQ <= '1';
elsif RM_ACK_S1 = '1' then
RM_REQ <= '0';
end if;
end if;
RM_ACK_S0 <= RS_REQ_S1; -- synch 0: CLKS->CLKM
RM_ACK_S1 <= RM_ACK_S0; -- synch 1: CLKM
end if;
end process proc_master;
proc_slave: process (CLKS)
begin
if rising_edge(CLKS) then
RS_REQ_S0 <= RM_REQ; -- synch 0: CLKM->CLKS
RS_REQ_S1 <= RS_REQ_S0; -- synch 1: CLKS
end if;
end process proc_slave;
-- Note: no pulse at startup when POUT_SINGLE=true, INIT=1 and PIN=1 initially
SINGLE1: if POUT_SINGLE = true generate
signal RS_ACK_1 : slbit := INIT;
signal RS_POUT : slbit := '0';
begin
proc_pout: process (CLKS)
begin
if rising_edge(CLKS) then
RS_ACK_1 <= RS_REQ_S1;
if RS_REQ_S1='1' and RS_ACK_1='0' then
RS_POUT <= '1';
else
RS_POUT <= '0';
end if;
end if;
end process proc_pout;
POUT <= RS_POUT;
end generate SINGLE1;
SINGLE0: if POUT_SINGLE = false generate
begin
POUT <= RS_REQ_S1;
end generate SINGLE0;
BUSY1: if BUSY_WACK = true generate
begin
BUSY <= RM_REQ or RM_ACK_S1;
end generate BUSY1;
BUSY0: if BUSY_WACK = false generate
begin
BUSY <= RM_REQ;
end generate BUSY0;
end syn;
| gpl-3.0 | 8d9c2947b84326bcf2e9082b06b010d1 | 0.535605 | 3.42735 | false | false | false | false |
wfjm/w11 | rtl/vlib/simlib/simclk.vhd | 1 | 1,999 | -- $Id: simclk.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simclk - sim
-- Description: Clock generator for test benches
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP now optional port
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-10 72 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity simclk is -- test bench clock generator
generic (
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclk;
architecture sim of simclk is
begin
proc_clk: process
constant clock_halfperiod : Delay_length := PERIOD/2;
begin
CLK <= '0';
wait for OFFSET;
clk_loop: loop
CLK <= '1';
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for clock_halfperiod;
CLK <= '0';
wait for PERIOD-clock_halfperiod;
wait; -- endless wait, simulator will stop
end process proc_clk;
end sim;
| gpl-3.0 | f9ca28d7637867729ea1b9ac6aca1c71 | 0.547774 | 3.661172 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/cmoda7_dummy.vhd | 1 | 1,695 | -- $Id: cmoda7_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cmoda7_dummy - syn
-- Description: cmoda7 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_cmoda7
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cmoda7_dummy is -- CmodA7 dummy (base; loopback)
-- implements cmoda7_aif
port (
I_CLK12 : in slbit; -- 12 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3 -- c7 rgb-led 0 (act.low)
);
end cmoda7_dummy;
architecture syn of cmoda7_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_BTN; -- mirror BTN on LED
O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red
O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green
O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white
end syn;
| gpl-3.0 | b94d769ebdc81eac63e6aeea3e05ed66 | 0.471976 | 3.606383 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd | 1 | 9,872 | -- $Id: tb_nexys2_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp_cuff - sim
-- Description: Test bench for nexys2 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tbcore/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/tb/serport_master_tb
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp_cuff is
end tb_nexys2_fusp_cuff;
architecture sim of tb_nexys2_fusp_cuff is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_cuff_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | f8a9f0a5fc9dc56ec4df031b4eddb031 | 0.519145 | 2.991515 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd | 1 | 3,463 | -- $Id: ram_2swsr_rfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- The code is inspired by Xilinx example rams_16.vhd. The
-- 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- now initialize DO to all '0' at start
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
architecture syn of ram_2swsr_rfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
begin
proc_clka: process (CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
if WEA = '1' then
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
end process proc_clka;
proc_clkb: process (CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
if WEB = '1' then
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
end if;
end if;
end process proc_clkb;
DOA <= R_DOA;
DOB <= R_DOB;
end syn;
| gpl-3.0 | e49e7d221beb60722fab84ebddfbecec | 0.556454 | 3.522889 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/bshifter.vhd | 4 | 1,568 | library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0)
);
end entity bshift;
architecture logic of bshift is
signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0);
signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0);
signal fill : std_logic_vector(31 downto 16);
begin
fill <= (others => input(31)) when logical = '0' else x"0000";
shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input;
shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l;
shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l;
shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l;
shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l;
shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input;
shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r;
shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r;
shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r;
shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r;
output <= shift16r when left = '0' else shift16l;
end;
| gpl-2.0 | dd6e262b57d613925652ee0ba8d4f843 | 0.658163 | 2.574713 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/sn_7segctl.vhd | 1 | 5,823 | -- $Id: sn_7segctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sn_7segctl - syn
-- Description: 7 segment display controller (for s3board,nexys,basys)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-24 637 14.7 131013 xc6slx16-2 9 27 0 16 s 3.1 ns DC=3
-- 2015-01-24 637 14.7 131013 xc6slx16-2 8 19 0 9 s 3.1 ns DC=2
-- 2015-01-24 410 14.7 131013 xc6slx16-2 8 19 0 8 s 3.1 ns
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-24 637 1.3 renamed from sn_4x7segctl; add DCWIDTH,
-- allow 4(DC=2) or 8(DC=3) digit display
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_7segctl is -- 7 segment display controller
generic (
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32
DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8
ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8
SEG_N : out slv8 -- segements (act.low)
);
end sn_7segctl;
architecture syn of sn_7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv(DCWIDTH-1 downto 0); -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)), -- cdiv
slv(to_unsigned(0,DCWIDTH)) -- dcnt
);
type hex2segtbl_type is array (0 to 15) of slv7;
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CHEX : slv4 := (others=>'0'); -- current hex number
signal CDP : slbit := '0'; -- current decimal point
begin
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity failure;
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, CHEX, CDP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := (others=>'1');
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (CDP & hex2segtbl(to_integer(unsigned(CHEX))));
end process proc_next;
proc_mux: process (R_REGS, DIN, DP)
begin
CDP <= DP(to_integer(unsigned(R_REGS.dcnt)));
CHEX(0) <= DIN(0+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(1) <= DIN(1+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(2) <= DIN(2+4*to_integer(unsigned(R_REGS.dcnt)));
CHEX(3) <= DIN(3+4*to_integer(unsigned(R_REGS.dcnt)));
end process proc_mux;
end syn;
| gpl-3.0 | 61288f18695237e80fb641668a641f0c | 0.526704 | 3.46195 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_tb.vhd | 1 | 7,359 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 16;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | 791a37f515fd7fef46891e7874e2b8a7 | 0.593423 | 2.718508 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dpath.vhd | 1 | 11,099 | -- $Id: pdp11_dpath.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dpath - syn
-- Description: pdp11: CPU datapath
--
-- Dependencies: pdp11_gr
-- pdp11_psr
-- pdp11_ounit
-- pdp11_aunit
-- pdp11_lunit
-- pdp11_munit
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.2.6 rename _gpr -> _gr
-- 2015-07-19 702 1.2.5 set new DM_STAT_DP fields
-- 2014-08-10 581 1.2.4 use c_cc_f_*
-- 2014-07-12 569 1.2.3 use DIV_QUIT and S_DIV_SR for pdp11_munit
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit
-- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port;
-- remove CPADDR out port; drop R_CPADDR, proc_cpaddr;
-- added R_CPDOUT, proc_cpdout
-- 2009-05-30 220 1.1.6 final removal of snoopers (were already commented)
-- 2008-12-14 177 1.1.5 fill gpr_* fields in DM_STAT_DP
-- 2008-08-22 161 1.1.4 rename ubf_ -> ibf_; use iblib
-- 2008-04-19 137 1.1.3 add DM_STAT_DP port
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-02-24 119 1.1.1 add CPADDR register, remove R_MDIN (not needed)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now (for psr access)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end pdp11_dpath;
architecture syn of pdp11_dpath is
signal R_DSRC : slv16 := (others=>'0'); -- SRC register
signal R_DDST : slv16 := (others=>'0'); -- DST register
signal R_DTMP : slv16 := (others=>'0'); -- TMP register
signal R_IREG : slv16 := (others=>'0'); -- IREG register
signal R_CPDOUT : slv16 := (others=>'0'); -- cp dout buffer
signal GR_DSRC : slv16 := (others=>'0'); -- source register
signal GR_DDST : slv16 := (others=>'0'); -- destination register
signal GR_PC : slv16 := (others=>'0'); -- program counter
signal PSW : psw_type := psw_init; --
signal CCIN : slv4 := (others=>'0'); -- cc input to xbox's
signal CCOUT : slv4 := (others=>'0'); -- cc output from xbox's
signal DRES : slv16 := (others=>'0'); -- result bus
signal DRESE : slv16 := (others=>'0'); -- result bus extra
signal OUNIT_DOUT : slv16 := (others=>'0'); -- result ounit
signal AUNIT_DOUT : slv16 := (others=>'0'); -- result aunit
signal LUNIT_DOUT : slv16 := (others=>'0'); -- result lunit
signal MUNIT_DOUT : slv16 := (others=>'0'); -- result munit
signal OUNIT_NZOUT : slv2 := (others=>'0'); -- nz flags ounit
signal OUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags ounit
signal AUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags aunit
signal LUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags lunit
signal MUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags munit
subtype lal_ibf_addr is integer range 15 downto 1;
subtype lah_ibf_addr is integer range 5 downto 0;
constant lah_ibf_ena_22bit: integer := 6;
constant lah_ibf_ena_ubmap: integer := 7;
begin
GR : pdp11_gr port map (
CLK => CLK,
DIN => DRES,
ASRC => CNTL.gr_asrc,
ADST => CNTL.gr_adst,
MODE => CNTL.gr_mode,
RSET => CNTL.gr_rset,
WE => CNTL.gr_we,
BYTOP => CNTL.gr_bytop,
PCINC => CNTL.gr_pcinc,
DSRC => GR_DSRC,
DDST => GR_DDST,
PC => GR_PC
);
PSR : pdp11_psr port map(
CLK => CLK,
CRESET => CRESET,
DIN => DRES,
CCIN => CCOUT,
CCWE => CNTL.psr_ccwe,
WE => CNTL.psr_we,
FUNC => CNTL.psr_func,
PSW => PSW,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES
);
OUNIT : pdp11_ounit port map (
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
PC => GR_PC,
ASEL => CNTL.ounit_asel,
AZERO => CNTL.ounit_azero,
IREG8 => R_IREG(7 downto 0),
VMDOUT => VM_DOUT,
CONST => CNTL.ounit_const,
BSEL => CNTL.ounit_bsel,
OPSUB => CNTL.ounit_opsub,
DOUT => OUNIT_DOUT,
NZOUT => OUNIT_NZOUT
);
AUNIT : pdp11_aunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CI => CCIN(c_cc_f_c),
SRCMOD => CNTL.aunit_srcmod,
DSTMOD => CNTL.aunit_dstmod,
CIMOD => CNTL.aunit_cimod,
CC1OP => CNTL.aunit_cc1op,
CCMODE => CNTL.aunit_ccmode,
BYTOP => CNTL.aunit_bytop,
DOUT => AUNIT_DOUT,
CCOUT => AUNIT_CCOUT
);
LUNIT : pdp11_lunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CCIN => CCIN,
FUNC => CNTL.lunit_func,
BYTOP => CNTL.lunit_bytop,
DOUT => LUNIT_DOUT,
CCOUT => LUNIT_CCOUT
);
MUNIT : pdp11_munit port map (
CLK => CLK,
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
GR_DSRC => GR_DSRC,
FUNC => CNTL.munit_func,
S_DIV => CNTL.munit_s_div,
S_DIV_CN => CNTL.munit_s_div_cn,
S_DIV_CR => CNTL.munit_s_div_cr,
S_DIV_SR => CNTL.munit_s_div_sr,
S_ASH => CNTL.munit_s_ash,
S_ASH_CN => CNTL.munit_s_ash_cn,
S_ASHC => CNTL.munit_s_ashc,
S_ASHC_CN => CNTL.munit_s_ashc_cn,
SHC_TC => STAT.shc_tc,
DIV_CR => STAT.div_cr,
DIV_CQ => STAT.div_cq,
DIV_QUIT => STAT.div_quit,
DOUT => MUNIT_DOUT,
DOUTE => DRESE,
CCOUT => MUNIT_CCOUT
);
CCIN <= PSW.cc;
OUNIT_CCOUT <= OUNIT_NZOUT & "0" & CCIN(c_cc_f_c); -- clear v, keep c
proc_dres_sel: process (OUNIT_DOUT, AUNIT_DOUT, LUNIT_DOUT, MUNIT_DOUT,
VM_DOUT, R_IREG, CP_DIN, CNTL)
begin
case CNTL.dres_sel is
when c_dpath_res_ounit => DRES <= OUNIT_DOUT;
when c_dpath_res_aunit => DRES <= AUNIT_DOUT;
when c_dpath_res_lunit => DRES <= LUNIT_DOUT;
when c_dpath_res_munit => DRES <= MUNIT_DOUT;
when c_dpath_res_vmdout => DRES <= VM_DOUT;
when c_dpath_res_fpdout => DRES <= (others=>'0');
when c_dpath_res_ireg => DRES <= R_IREG;
when c_dpath_res_cpdin => DRES <= CP_DIN;
when others => null;
end case;
end process proc_dres_sel;
proc_cres_sel: process (OUNIT_CCOUT, AUNIT_CCOUT, LUNIT_CCOUT, MUNIT_CCOUT,
CCIN, CNTL)
begin
case CNTL.cres_sel is
when c_dpath_res_ounit => CCOUT <= OUNIT_CCOUT;
when c_dpath_res_aunit => CCOUT <= AUNIT_CCOUT;
when c_dpath_res_lunit => CCOUT <= LUNIT_CCOUT;
when c_dpath_res_munit => CCOUT <= MUNIT_CCOUT;
when c_dpath_res_vmdout => CCOUT <= CCIN;
when c_dpath_res_fpdout => CCOUT <= "0000";
when c_dpath_res_ireg => CCOUT <= CCIN;
when c_dpath_res_cpdin => CCOUT <= CCIN;
when others => null;
end case;
end process proc_cres_sel;
proc_dregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.dsrc_we = '1' then
if CNTL.dsrc_sel = '0' then
R_DSRC <= GR_DSRC;
else
R_DSRC <= DRES;
end if;
end if;
if CNTL.ddst_we = '1' then
if CNTL.ddst_sel = '0' then
R_DDST <= GR_DDST;
else
R_DDST <= DRES;
end if;
end if;
if CNTL.dtmp_we = '1' then
case CNTL.dtmp_sel is
when c_dpath_dtmp_dsrc => R_DTMP <= GR_DSRC;
when c_dpath_dtmp_psw =>
R_DTMP <= (others=>'0');
R_DTMP(psw_ibf_cmode) <= PSW.cmode;
R_DTMP(psw_ibf_pmode) <= PSW.pmode;
R_DTMP(psw_ibf_rset) <= PSW.rset;
R_DTMP(psw_ibf_pri) <= PSW.pri;
R_DTMP(psw_ibf_tflag) <= PSW.tflag;
R_DTMP(psw_ibf_cc) <= PSW.cc;
when c_dpath_dtmp_dres => R_DTMP <= DRES;
when c_dpath_dtmp_drese => R_DTMP <= DRESE;
when others => null;
end case;
end if;
end if;
end process proc_dregs;
proc_mregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.ireg_we = '1' then
R_IREG <= VM_DOUT;
end if;
end if;
end process proc_mregs;
proc_cpdout: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_CPDOUT <= (others=>'0');
else
if CNTL.cpdout_we = '1' then
R_CPDOUT <= DRES;
end if;
end if;
end if;
end process proc_cpdout;
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GR_PC, CNTL)
begin
case CNTL.vmaddr_sel is
when c_dpath_vmaddr_dsrc => VM_ADDR <= R_DSRC;
when c_dpath_vmaddr_ddst => VM_ADDR <= R_DDST;
when c_dpath_vmaddr_dtmp => VM_ADDR <= R_DTMP;
when c_dpath_vmaddr_pc => VM_ADDR <= GR_PC;
when others => null;
end case;
end process proc_vmaddr_sel;
STAT.ccout_z <= CCOUT(c_cc_f_z); -- current Z cc flag
PSWOUT <= PSW;
PCOUT <= GR_PC;
IREG <= R_IREG;
VM_DIN <= DRES;
CP_DOUT <= R_CPDOUT;
DM_STAT_DP.pc <= GR_PC;
DM_STAT_DP.psw <= PSW;
DM_STAT_DP.psr_we <= CNTL.psr_we;
DM_STAT_DP.ireg <= R_IREG;
DM_STAT_DP.ireg_we <= CNTL.ireg_we;
DM_STAT_DP.dsrc <= R_DSRC;
DM_STAT_DP.dsrc_we <= CNTL.dsrc_we;
DM_STAT_DP.ddst <= R_DDST;
DM_STAT_DP.ddst_we <= CNTL.ddst_we;
DM_STAT_DP.dtmp <= R_DTMP;
DM_STAT_DP.dtmp_we <= CNTL.dtmp_we;
DM_STAT_DP.dres <= DRES;
DM_STAT_DP.cpdout_we <= CNTL.cpdout_we;
DM_STAT_DP.gr_adst <= CNTL.gr_adst;
DM_STAT_DP.gr_mode <= CNTL.gr_mode;
DM_STAT_DP.gr_bytop <= CNTL.gr_bytop;
DM_STAT_DP.gr_we <= CNTL.gr_we;
end syn;
| gpl-3.0 | a96997792cde2d7cb58119fb862d1615 | 0.532751 | 3.124718 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/s3board/tb/sys_conf_sim.vhd | 1 | 1,153 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_s3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer := 50000000;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | 55f6e7e760e6d045eb829258e966ab94 | 0.534258 | 3.921769 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd | 1 | 18,448 | -- $Id: tb_tst_serloop.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/simlib/simclkcnt
-- vlib/serport/serport_uart_rxtx_tb
-- vlib/serport/serport_xontx_tb
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2.2 remove CLK_STOP logic (simstop via report)
-- 2016-08-18 799 1.2.1 remove 'assert false' from report statements
-- 2016-04-23 764 1.2 use serport/tb/serport_(uart_rxtx|xontx)_tb
-- use assert to halt simulation
-- 2011-12-23 444 1.1 use new simclkcnt
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.serportlib_tb.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE);
UART : entity work.serport_uart_rxtx_tb
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : entity work.serport_xontx_tb
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
end process proc_stim;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 740ddcf1d262cf0ae499b4db521bc426 | 0.485527 | 4.084127 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_eyemon.vhd | 1 | 11,624 | -- $Id: rbd_eyemon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_eyemon - syn
-- Description: rbus dev: eye monitor for serport's
--
-- Dependencies: memlib/ram_2swsr_wfirst_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2016.1; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7
-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 4.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 cntl r/w/- Control register
-- 03 ena01 r/w/- track 0->1 rxsd transitions
-- 02 ena10 r/w/- track 1->0 rxsd transitions
-- 01 clr r/-/f w: writing a 1 starts memory clear
-- r: 1 indicates clr in progress (512 cyc)
-- 00 go r/w/- enables monitor
-- 01 7:00 rdiv r/w/- Sample rate divider
-- 10 addr r/w/- Address register
-- 9:01 laddr r/w/ line address
-- 00 waddr r/w/ word address
-- 11 15:00 data r/-/- Data register
--
-- data format:
-- word 1 counter msb's
-- word 0 counter lsb's
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv16 := (others=>'0');
RDIV : slv8 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RXSD : in slbit; -- rx: serial data
RXACT : in slbit -- rx: active (start seen)
);
end entity rbd_eyemon;
architecture syn of rbd_eyemon is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_rdiv : slv2 := "01"; -- rdiv address offset
constant rbaddr_addr : slv2 := "10"; -- addr address offset
constant rbaddr_data : slv2 := "11"; -- data address offset
constant cntl_rbf_ena01 : integer := 3;
constant cntl_rbf_ena10 : integer := 2;
constant cntl_rbf_clr : integer := 1;
constant cntl_rbf_go : integer := 0;
subtype addr_rbf_laddr is integer range 9 downto 1;
constant addr_rbf_waddr : integer := 0;
type state_type is (
s_idle, -- s_idle: wait for char or clr
s_char, -- s_char: processing a char
s_clr -- s_clr: clear memory
);
type regs_type is record -- state registers
state : state_type; -- state
rbsel : slbit; -- rbus select
go : slbit; -- go flag
clr : slbit; -- clear pending
ena10 : slbit; -- enable 1->0
ena01 : slbit; -- enable 0->1
rdiv : slv8; -- rate divider
laddr : slv9; -- line address
waddr : slbit; -- word address
laddr_1 : slv9; -- line address last cycle
rxsd_1 : slbit; -- rxsd last cycle
memwe : slbit; -- write bram (clr or inc)
memclr : slbit; -- write zero into bram
rdivcnt : slv8; -- rate divider counter
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
'0', -- go (default is off)
'0','0','0', -- clr,ena01,ena10
(others=>'0'), -- rdiv
(others=>'0'), -- laddr
'0', -- waddr
(others=>'0'), -- laddr_1
'0','0','0', -- rxsd_1,memwe,memclr
(others=>'0') -- rdivcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal BRAM_ENA : slbit := '0';
signal BRAM_DIA : slv32 := (others=>'0');
signal BRAM_DIB : slv32 := (others=>'0');
signal BRAM_DOA : slv32 := (others=>'0');
begin
BRAM_DIA <= (others=>'0'); -- always 0, no writes on this port
BRAM : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 32)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_ENA,
ENB => R_REGS.memwe,
WEA => '0',
WEB => R_REGS.memwe,
ADDRA => R_REGS.laddr,
ADDRB => R_REGS.laddr_1,
DIA => BRAM_DIA,
DIB => BRAM_DIB,
DOA => BRAM_DOA,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RXSD, RXACT, BRAM_DOA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0';
variable ibramdi : slv32 := (others=>'0');
variable laddr_we : slbit := '0';
variable laddr_clr : slbit := '0';
variable laddr_inc : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
laddr_we := '0';
laddr_clr := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.ena01 := RB_MREQ.din(cntl_rbf_ena01);
n.ena10 := RB_MREQ.din(cntl_rbf_ena10);
if RB_MREQ.din(cntl_rbf_clr) = '1' then
n.clr := '1';
end if;
n.go := RB_MREQ.din(cntl_rbf_go);
end if;
when rbaddr_rdiv =>
if RB_MREQ.we = '1' then
n.rdiv := RB_MREQ.din(n.rdiv'range);
end if;
when rbaddr_addr =>
if RB_MREQ.we = '1' then
laddr_we := '1';
n.waddr := RB_MREQ.din(addr_rbf_waddr);
end if;
when rbaddr_data =>
if RB_MREQ.we='1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
if r.go='0' and r.clr='0' and r.state=s_idle then
n.waddr := not r.waddr;
if r.waddr = '1' then
laddr_inc := '1';
end if;
else
irb_err := '1';
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_ena01) := r.ena01;
irb_dout(cntl_rbf_ena10) := r.ena10;
irb_dout(cntl_rbf_clr) := r.clr;
irb_dout(cntl_rbf_go) := r.go;
when rbaddr_rdiv =>
irb_dout(r.rdiv'range) := r.rdiv;
when rbaddr_addr =>
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data =>
case r.waddr is
when '1' => irb_dout := BRAM_DOA(31 downto 16);
when '0' => irb_dout := BRAM_DOA(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- eye monitor
n.memwe := '0';
n.memclr := '0';
case r.state is
when s_idle => -- s_idle: wait for char or clr ------
if r.clr = '1' then
laddr_clr := '1';
n.state := s_clr;
elsif r.go = '1' and RXSD='0' then
laddr_clr := '1';
n.rdivcnt := r.rdiv;
n.state := s_char;
end if;
when s_char => -- s_char: processing a char ---------
n.state := s_char; -- needed to prevent vivado iSTATE
if RXACT = '0' then -- uart went unactive
if RXSD = '1' then -- line idle -> to s_idle
n.state := s_idle;
else -- already next start bit seen
laddr_clr := '1'; -- clear and restart
n.rdivcnt := r.rdiv; -- happens only in simulation...
end if;
else
if (r.ena01='1' and r.rxsd_1='0' and RXSD='1') or
(r.ena10='1' and r.rxsd_1='1' and RXSD='0') then
n.memwe := '1';
ibramen := '1';
end if;
end if;
if unsigned(r.rdiv)=0 or unsigned(r.rdivcnt)=0 then
n.rdivcnt := r.rdiv;
if unsigned(r.laddr) /= (2**r.laddr'length)-1 then
laddr_inc := '1';
end if;
else
n.rdivcnt := slv(unsigned(r.rdivcnt) - 1);
end if;
when s_clr => -- s_clr: clear memory ---------------
laddr_inc := '1';
n.memwe := '1';
n.memclr := '1';
if unsigned(r.laddr) = (2**r.laddr'length)-1 then
n.clr := '0';
n.state := s_idle;
end if;
when others => null;
end case;
if laddr_we = '1' then
n.laddr := RB_MREQ.din(addr_rbf_laddr);
elsif laddr_clr = '1' then
n.laddr := (others=>'0');
elsif laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
end if;
n.laddr_1 := r.laddr;
n.rxsd_1 := RXSD;
ibramdi := (others=>'0');
if r.memclr = '0' then
ibramdi := slv(unsigned(BRAM_DOA) + 1);
end if;
N_REGS <= n;
BRAM_ENA <= ibramen;
BRAM_DIB <= ibramdi;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
| gpl-3.0 | 918d9f890e27544d4134c38c2c85df67 | 0.462233 | 3.534205 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/ALU.vhd | 1 | 12,952 | --------------------------------------------------------------------------
-- Multiplexer
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity multiplexer is
Port ( I0 : in STD_LOGIC_VECTOR ( 31 downto 0);
I1 : in STD_LOGIC_VECTOR ( 31 downto 0);
I2 : in STD_LOGIC_VECTOR ( 31 downto 0);
I3 : in STD_LOGIC_VECTOR ( 31 downto 0);
I4 : in STD_LOGIC_VECTOR ( 31 downto 0);
I5 : in STD_LOGIC_VECTOR ( 31 downto 0);
I6 : in STD_LOGIC_VECTOR ( 31 downto 0);
I7 : in STD_LOGIC_VECTOR ( 31 downto 0);
CH : in STD_LOGIC_VECTOR ( 2 downto 0);
OPT : out STD_LOGIC_VECTOR ( 31 downto 0));
end multiplexer;
architecture beh_multiplexer of multiplexer is
begin
with CH select
OPT <= I0 when "000",
I1 when "001",
I2 when "010",
I3 when "011",
I4 when "100",
I5 when "101",
I6 when "110",
I7 when others;
end beh_multiplexer;
--------------------------------------------------------------------------
-- Arithmetic
--------------------------------------------------------------------------
-- 0,10,000 ADD
-- 0,10,001 ADDU
-- 0,10,010 SUB
-- 0,10,011 SUBU
-- 0,10,110 SLT (set less than)
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity arithmetic is
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end arithmetic;
architecture beh_arithmetic of arithmetic is
component addsub_lookahead
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end component;
signal Output1 : STD_LOGIC_VECTOR (31 downto 0);
signal Output2 : STD_LOGIC_VECTOR (31 downto 0);
signal Oflags : STD_LOGIC_VECTOR (27 downto 0);
begin
ADDSUB: addsub_lookahead port map (Control, Operand1, Operand2, Output1, Output2, Oflags);
Result1 <= Output1 when (Control /= "110") else
X"00000000" when (Control = "110" AND Output1(31)='0') else
X"00000001" when (Control = "110" AND Output1(31)='1') else
(others => 'X');
Result2 <= Output2 when Control(2) = '0' else X"00000000";
Debug <= Oflags when Control(2) = '0' else X"0000000";
end beh_arithmetic;
--------------------------------------------------------------------------
-- Complex Op
--------------------------------------------------------------------------
-- 0,11,000 MULT
-- 0,11,001 MULTU
-- 0,11,010 DIV
-- 0,11,011 DIVU
--------------------------------------------------------------------------
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity complexop is
--Port (
-- Control : in STD_LOGIC_VECTOR ( 2 downto 0);
-- Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
-- Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
-- Result1 : out STD_LOGIC_VECTOR (31 downto 0);
-- Result2 : out STD_LOGIC_VECTOR (31 downto 0);
-- Debug : out STD_LOGIC_VECTOR (27 downto 0);
-- Done : out STD_LOGIC);
--end complexop;
--
--architecture beh_complexop of complexop is
-- component Multiply is
-- port(
-- Control_a : in STD_LOGIC_VECTOR ( 2 downto 0);
-- Operand1_a : in STD_LOGIC_VECTOR (31 downto 0);
-- Operand2_a : in STD_LOGIC_VECTOR (31 downto 0);
-- Result1_a : out STD_LOGIC_VECTOR (31 downto 0);
-- Result2_a : out STD_LOGIC_VECTOR (31 downto 0);
-- Done_a : out STD_LOGIC
-- );
-- end component;
--
-- component divider is
-- port (
-- Control_a: in std_logic_vector(2 downto 0);
-- dividend_i : in std_logic_vector(31 downto 0);
-- divisor_i : in std_logic_vector(31 downto 0);
-- quotient_o : out std_logic_vector(31 downto 0);
-- remainder_o : out std_logic_vector(31 downto 0);
-- done_b : out std_logic;
-- debug_b : out std_logic_vector(27 downto 0)
-- );
-- end component;
--
-- signal mul_result1 : std_logic_vector (31 downto 0);
-- signal mul_result2 : std_logic_vector (31 downto 0);
-- signal div_quotient: std_logic_vector (31 downto 0);
-- signal div_remainder: std_logic_vector (31 downto 0);
--
-- signal done_mul: std_logic;
-- signal done_div: std_logic;
-- signal debug_s : std_logic_vector(27 downto 0);
--begin
-- MULTIPLIER: multiply port map (Control,Operand1,Operand2,mul_result1,mul_result2,done_mul);
-- DIVIDER_part: divider port map (Control,Operand1, Operand2, div_quotient, div_remainder, done_div,debug_s);
--
-- Result1 <= mul_result1 when (Control(1)='0')
-- else div_quotient when (Control(1) ='1' and done_div ='1')
-- else (others => 'Z');
-- Result2 <= mul_result2 when (Control(1)='0')
-- else div_remainder when (Control(1) ='1' and done_div ='1')
-- else (others => 'Z');
-- Debug <= debug_s when (Control(1) = '1')
-- else (others => '0');
-- Done <= done_mul when (Control(1) ='0')
-- else done_div when(Control(1) ='1')
-- else '0';
--
--end beh_complexop;
--------------------------------------------------------------------------
-- ALU main
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity alu is
Port (
Control : in STD_LOGIC_VECTOR ( 5 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (31 downto 0));
end alu;
architecture Behavioral of alu is
component multiplexer
Port ( I0 : in STD_LOGIC_VECTOR ( 31 downto 0);
I1 : in STD_LOGIC_VECTOR ( 31 downto 0);
I2 : in STD_LOGIC_VECTOR ( 31 downto 0);
I3 : in STD_LOGIC_VECTOR ( 31 downto 0);
I4 : in STD_LOGIC_VECTOR ( 31 downto 0);
I5 : in STD_LOGIC_VECTOR ( 31 downto 0);
I6 : in STD_LOGIC_VECTOR ( 31 downto 0);
I7 : in STD_LOGIC_VECTOR ( 31 downto 0);
CH : in STD_LOGIC_VECTOR ( 2 downto 0);
OPT : out STD_LOGIC_VECTOR ( 31 downto 0));
end component;
component logic
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end component;
component shift
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end component;
component arithmetic
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end component;
-- component complexop
-- Port (
-- Control : in STD_LOGIC_VECTOR ( 2 downto 0);
-- Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
-- Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
-- Result1 : out STD_LOGIC_VECTOR (31 downto 0);
-- Result2 : out STD_LOGIC_VECTOR (31 downto 0);
-- Debug : out STD_LOGIC_VECTOR (27 downto 0);
-- Done : out STD_LOGIC);
-- end component;
signal OpDone : std_logic;
signal OpType : std_logic_vector(2 downto 0);
signal OpCode : std_logic_vector(2 downto 0);
signal OpFlag : std_logic_vector(3 downto 0);
-- inputs
signal Input1 : std_logic_vector(31 downto 0);
signal Input2 : std_logic_vector(31 downto 0);
-- logic
signal LOutput1: std_logic_vector(31 downto 0);
signal LOutput2: std_logic_vector(31 downto 0);
signal LFlags : std_logic_vector(27 downto 0);
signal OLFlags : std_logic_vector(31 downto 0);
-- shift
signal SOutput1: std_logic_vector(31 downto 0);
signal SOutput2: std_logic_vector(31 downto 0);
signal SFlags : std_logic_vector(27 downto 0);
signal OSFlags : std_logic_vector(31 downto 0);
-- aritchmetic
signal AOutput1: std_logic_vector(31 downto 0);
signal AOutput2: std_logic_vector(31 downto 0);
signal AFlags : std_logic_vector(27 downto 0);
signal OAFlags : std_logic_vector(31 downto 0);
-- complexop
-- signal COutput1: std_logic_vector(31 downto 0);
-- signal COutput2: std_logic_vector(31 downto 0);
-- signal CFlags : std_logic_vector(27 downto 0);
-- signal OCFlags : std_logic_vector(31 downto 0);
begin
--------------------------------------------------------------------------
-- Control Definitions
--
-- **Positions**
-- Control(5) : Reset Bit, Triggered when = 1;
-- Control(4,3) : Operation Type
-- 00: Logical: NOP, AND, OR, XOR, NOR
-- 01: Shift: SLL, SRL, SRA
-- 10: Arithmetics: ADD, ADDU, SUB, SUBU, BEQ, BNE, SLT
-- 11: Complex Long Cycles: MULT, MULTU, DIV, DIVU
-- Control(2,0) : Individual Ops in Each Type
--
-- **Ops**
------------------
-- 1,xx,xxx RESET
------------------ Logical
-- 0,00,000 NOP
-- 0,00,001 AND
-- 0,00,010 OR
-- 0,00,011 XOR
-- 0,00,100 NOR
------------------ Shift
-- 0,01,000 SLL (Shift Left logical)
-- 0,01,010 SRL (Shift Right logical)
-- 0,01,011 SRA (Shift Right arithmetic)
------------------ Arithmetic
-- 0,10,000 ADD
-- 0,10,001 ADDU
-- 0,10,010 SUB
-- 0,10,011 SUBU
-- 0,10,100 BEQ (equality check only)
-- 0,10,101 BNE (inequality check only)
-- 0,10,110 SLT (set less than)
------------------ ComplexOp
-- 0,11,000 MULT
-- 0,11,001 MULTU
-- 0,11,010 DIV
-- 0,11,011 DIVU
--------------------------------------------------------------------------
-- logical operations
LG: logic port map(OpCode, Input1, Input2, LOutput1, LOutput2, LFlags);
-- shift operations
SF: shift port map(OpCode, Input1, Input2, SOutput1, SOutput2, SFlags);
-- arithmetics operations
AR: arithmetic port map(OpCode, Input1, Input2, AOutput1, AOutput2, AFlags);
-- complex operations
--CO: complexop port map(OpCode, Input1, Input2, COutput1, COutput2, CFlags, OpDone);
-- multiplex output
R1: multiplexer port map(X"00000000", -- reset
LOutput1, -- logic
SOutput1, -- shift
AOutput1, -- arithmetic
--COutput1, -- long cycles
X"00000000",
X"00000000", X"00000000", X"00000000",
OpType, Result1);
R2: multiplexer port map(X"00000000", -- reset
LOutput2, -- logic
SOutput2, -- shift
AOutput2, -- arithmetic
--COutput2, -- long cycles
X"00000000",
X"00000000", X"00000000", X"00000000",
OpType, Result2);
-- concatentae flags
OLFlags <= OpFlag & LFlags;
OSFlags <= OpFlag & SFlags;
OAFlags <= OpFlag & AFlags;
--OCFlags <= OpFlag & CFlags;
DB: multiplexer port map(X"00000000", -- reset
OLFlags, -- logic
OSFlags, -- shift
OAFlags, -- arithmetic
--OCFlags, -- complex
X"00000000",
X"00000000", X"00000000", X"00000000",
OpType, Debug);
process (Control, Operand1, Operand2)
begin
if Control(5) = '1' then -- reset
OpType <= "000";
OpCode <= "000";
OpFlag <= (others => '0');
Input1 <= (others => '0');
Input2 <= (others => '0');
else
OpCode <= Control(2 downto 0);
Input1 <= Operand1;
Input2 <= Operand2;
case (Control(4 downto 3)) is
when "00" => -- logical
OpType <= "001";
when "01" => -- shift
OpType <= "010";
when "10" => -- arithmetics
OpType <= "011";
when others => -- complex op
OpType <= "100";
end case;
OpFlag <= '0' & OpType;
end if;
end process;
end Behavioral; | gpl-2.0 | d8bf078915f438a8085b251e388271df | 0.54617 | 3.390576 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/comlib.vhd | 1 | 13,266 | -- $Id: comlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-20 749 1.6.2 crc*_update*: leave return type unconstraint
-- 2016-03-13 744 1.6.1 crc16_update_tbl: work around XSim 2015.4 issue
-- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial)
-- 2014-09-14 593 1.5 new iface for cdata2byte and byte2cdata
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
constant c_cdata_escape : slv8 := "11001010"; -- char escape
constant c_cdata_fill : slv8 := "11010101"; -- char fill
constant c_cdata_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_cdata_xoff : slv8 := "00010011"; -- char xoff: ^S = hex 13
constant c_cdata_ec_xon : slv3 := "100"; -- escape code: xon
constant c_cdata_ec_xoff : slv3 := "101"; -- escape code: xoff
constant c_cdata_ec_fill : slv3 := "110"; -- escape code: fill
constant c_cdata_ec_esc : slv3 := "111"; -- escape code: escape
constant c_cdata_ed_pref : slv2 := "01"; -- edata: prefix
subtype c_cdata_edf_pref is integer range 7 downto 6; -- edata pref field
subtype c_cdata_edf_eci is integer range 5 downto 3; -- edata inv field
subtype c_cdata_edf_ec is integer range 2 downto 0; -- edata code field
component cdata2byte is -- 9bit comma,data -> byte stream
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- input data enable
BUSY : out slbit; -- input data busy
DO : out slv8; -- output data
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- input data enable
ERR : in slbit; -- input data error
BUSY : out slbit; -- input data busy
DO : out slv9; -- output data; bit 8 = comma flag
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
component crc16 is -- crc-16 generator, checker
generic (
INIT: slv16 := (others=>'0')); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv16 -- crc code
);
end component;
-- Note: leave return type unconstraint ! A direction constraint return
-- type works fine in ghdl and ISim, but XSim will abort with an
-- run time error (there is indeed a mismatch, some simulators
-- tolerate this, some not, so never constrain a return type...).
function crc8_update (crc : in slv8; data : in slv8) return slv;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv;
function crc16_update (crc : in slv16; data : in slv8) return slv;
function crc16_update_tbl (crc : in slv16; data : in slv8) return slv;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
-- crc8_update and crc8_update_tbl implement the 'A6' polynomial of
-- Koopman and Chakravarty
-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6)
-- see
-- http://dx.doi.org/10.1109%2FDSN.2004.1311885
-- http://www.ece.cmu.edu/~koopman/roses/dsn04/koopman04_crc_poly_embedded.pdf
--
function crc8_update (crc: in slv8; data: in slv8) return slv is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
-- crc16_update and crc16_update_tbl implement the CCITT polynomial
-- x^16 + x^12 + x^5 + 1 (0x1021)
--
function crc16_update (crc: in slv16; data: in slv8) return slv is
variable n : slv16 := (others=>'0');
variable t : slv8 := (others=>'0');
begin
t := data xor crc(15 downto 8);
n(0) := t(4) xor t(0);
n(1) := t(5) xor t(1);
n(2) := t(6) xor t(2);
n(3) := t(7) xor t(3);
n(4) := t(4);
n(5) := t(5) xor t(4) xor t(0);
n(6) := t(6) xor t(5) xor t(1);
n(7) := t(7) xor t(6) xor t(2);
n(8) := t(7) xor t(3) xor crc(0);
n(9) := t(4) xor crc(1);
n(10) := t(5) xor crc(2);
n(11) := t(6) xor crc(3);
n(12) := t(7) xor t(4) xor t(0) xor crc(4);
n(13) := t(5) xor t(1) xor crc(5);
n(14) := t(6) xor t(2) xor crc(6);
n(15) := t(7) xor t(3) xor crc(7);
return n;
end function crc16_update;
function crc16_update_tbl (crc: in slv16; data: in slv8) return slv is
type crc16_tbl_type is array (0 to 255) of integer;
variable crc16_tbl : crc16_tbl_type :=
( 0, 4129, 8258, 12387, 16516, 20645, 24774, 28903,
33032, 37161, 41290, 45419, 49548, 53677, 57806, 61935,
4657, 528, 12915, 8786, 21173, 17044, 29431, 25302,
37689, 33560, 45947, 41818, 54205, 50076, 62463, 58334,
9314, 13379, 1056, 5121, 25830, 29895, 17572, 21637,
42346, 46411, 34088, 38153, 58862, 62927, 50604, 54669,
13907, 9842, 5649, 1584, 30423, 26358, 22165, 18100,
46939, 42874, 38681, 34616, 63455, 59390, 55197, 51132,
18628, 22757, 26758, 30887, 2112, 6241, 10242, 14371,
51660, 55789, 59790, 63919, 35144, 39273, 43274, 47403,
23285, 19156, 31415, 27286, 6769, 2640, 14899, 10770,
56317, 52188, 64447, 60318, 39801, 35672, 47931, 43802,
27814, 31879, 19684, 23749, 11298, 15363, 3168, 7233,
60846, 64911, 52716, 56781, 44330, 48395, 36200, 40265,
32407, 28342, 24277, 20212, 15891, 11826, 7761, 3696,
65439, 61374, 57309, 53244, 48923, 44858, 40793, 36728,
37256, 33193, 45514, 41451, 53516, 49453, 61774, 57711,
4224, 161, 12482, 8419, 20484, 16421, 28742, 24679,
33721, 37784, 41979, 46042, 49981, 54044, 58239, 62302,
689, 4752, 8947, 13010, 16949, 21012, 25207, 29270,
46570, 42443, 38312, 34185, 62830, 58703, 54572, 50445,
13538, 9411, 5280, 1153, 29798, 25671, 21540, 17413,
42971, 47098, 34713, 38840, 59231, 63358, 50973, 55100,
9939, 14066, 1681, 5808, 26199, 30326, 17941, 22068,
55628, 51565, 63758, 59695, 39368, 35305, 47498, 43435,
22596, 18533, 30726, 26663, 6336, 2273, 14466, 10403,
52093, 56156, 60223, 64286, 35833, 39896, 43963, 48026,
19061, 23124, 27191, 31254, 2801, 6864, 10931, 14994,
64814, 60687, 56684, 52557, 48554, 44427, 40424, 36297,
31782, 27655, 23652, 19525, 15522, 11395, 7392, 3265,
61215, 65342, 53085, 57212, 44955, 49082, 36825, 40952,
28183, 32310, 20053, 24180, 11923, 16050, 3793, 7920
);
variable ch : slv16 := (others=>'0');
variable cu : slv16 := (others=>'0');
variable t : slv8 := (others=>'0');
variable td : integer := 0;
begin
-- (crc<<8) ^ crc16_tbl[((crc>>8) ^ data) & 0x00ff]
ch := crc(7 downto 0) & "00000000";
t := data xor crc(15 downto 8);
td := crc16_tbl(to_integer(unsigned(t)));
return ch xor slv(to_unsigned(td, 16));
end function crc16_update_tbl;
end package body comlib;
| gpl-3.0 | 11d6f61fb9bdab2f28536f7d09e4baed | 0.510403 | 3.026694 | false | false | false | false |
sjohann81/hf-risc | devices/peripherals/minimal_soc_uart.vhd | 1 | 11,393 | -- file: minimal_soc_uart.vhd
-- description: minimal SoC with peripherals, including a UART
-- date: 01/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Very simple SoC configuration for prototyping. A single GPIO port,
-- a counter, a timer and a UART are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(7 downto 0);
gpioa_out: out std_logic_vector(7 downto 0);
gpioa_ddr: out std_logic_vector(7 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal paaltcfg0: std_logic_vector(7 downto 0);
signal s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(7 downto 0);
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal paalt0, paalt2: std_logic;
signal int_uart, uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "0000" else '0';
s0cause <= int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "000" & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
pain <= gpioa_in(7 downto 0);
gpioa_out <= paout(7 downto 3) & paalt2 & paout(1) & paalt0;
gpioa_ddr <= paddr;
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= "00" & uart0_write_busy & uart0_data_avail;
paalt0 <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt2 <= uart0_tx when paaltcfg0(5 downto 4) = "01" else paout(2);
uart0_rx <= gpioa_in(3) when paaltcfg0(7 downto 6) = "01" else '1';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"0000000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= x"000000" & paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"000000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"000000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"000000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"000000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"000000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(7 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(7 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(7 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(7 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(7 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
end peripherals_arch;
| gpl-2.0 | 200bcab88221cc0f84ae831a0dcdc218 | 0.546739 | 2.802706 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01600_good.vhd | 1 | 3,905 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01600_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of package element: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity CNE_01600_good is
port (
i_Clock : in std_logic; -- Global clock signal
i_Reset_n : in std_logic; -- Global reset signal
i_Raz : in std_logic; -- Reset counting and load length
i_Enable : in std_logic; -- Enable the counter
i_Length : in std_logic_vector(pkg_Width downto 0); -- How much the module should count (Value expected - 1)
o_Done : out std_logic -- Counter output
);
end CNE_01600_good;
architecture Behavioral of CNE_01600_good is
signal Count : signed(pkg_Width downto 0); -- Counting signal
signal Length : signed(pkg_Width downto 0); -- How much the module should count
signal Done : std_logic; -- Counter output
begin
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
Length <= (others => '0');
Done <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Raz='1') then
-- Reset the counting
Length <= signed(i_Length);
Count <= (others => '0');
elsif (i_Enable='1' and Done='0') then
-- Counter activated and not finished
Count <= Count + 1;
end if;
if (Count>=Length) then -- Compared elements are of the same type and dimension
-- Counter finished
Done <= '1';
else
Done <= '0';
end if;
end if;
end process;
o_Done <= Done;
end Behavioral; | gpl-3.0 | e8cb275a21bf06f29ea652f6c0cc6ed6 | 0.476312 | 4.733333 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/Mult.vhd | 1 | 1,105 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Multiply is
port(
Control_a : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1_a : in STD_LOGIC_VECTOR (31 downto 0);
Operand2_a : in STD_LOGIC_VECTOR (31 downto 0);
Result1_a : out STD_LOGIC_VECTOR (31 downto 0);
Result2_a : out STD_LOGIC_VECTOR (31 downto 0);
--Debug : out STD_LOGIC_VECTOR (27 downto 0);
Done_a : out STD_LOGIC
);
end Multiply;
architecture beh of multiply is
signal prod: std_logic_vector(63 downto 0);
begin
Result2_a <= prod(63 downto 32);
Result1_a <= prod(31 downto 0);
process(Operand1_a,Operand2_a,Control_a)
variable sign: std_logic;
variable tmp: std_logic_vector(63 downto 0);
variable a_in: std_logic_vector(31 downto 0);
variable b_in: std_logic_vector(31 downto 0);
begin
if (Control_a(0)='0') then
prod <= std_logic_vector(signed(Operand1_a) * signed(Operand2_a));
elsif (Control_a(0)='1') then
prod <= std_logic_vector(unsigned(Operand1_a) * unsigned(Operand2_a));
else
prod <= (others => 'Z');
end if;
end process;
end beh; | gpl-2.0 | b2ff73e7d0b7c10570b881eb9b8a6024 | 0.667873 | 2.783375 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf2_sim.vhd | 1 | 1,460 | -- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n3 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 30; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
| gpl-3.0 | fe0628aa69f42c995cc1e65a71943bc5 | 0.607534 | 3.782383 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd | 1 | 3,559 | -- $Id: tb_tst_serloop1_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n3 - sim
-- Description: Test bench for sys_tst_serloop1_n3
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop1_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_tst_serloop1_n3 is
end tb_tst_serloop1_n3;
architecture sim of tb_tst_serloop1_n3 is
signal CLK100 : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
UUT : entity work.sys_tst_serloop1_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK100,
CLKH => CLK100,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | d8a660999e01bb344bbf3f248ab85348 | 0.50857 | 2.970785 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/c7_sram_memctl.vhd | 1 | 13,189 | -- $Id: c7_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: c7_sram_memctl - syn
-- Description: Cmod A7 SRAM controller
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
--
-- Test bench: tb/tb_c7_sram_memctl
-- fw_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7
--
-- Target Devices: generic
-- Tool versions: viv 2017.1; ghdl 0.34
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram
-- 2017-06-19 914 2017.1 xc7a35t-1 109 81 0 0 syn level
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-07-01 920 1.0.1 shorten ce and oe times
-- 2017-06-19 914 1.0 Initial version
-- 2017-06-11 912 0.5 First draft
--
-- Timing of some signals:
--
-- single read request:
--
-- state |_idle |_read0 |_read1 |...._read0 |_read1 |_idle |
--
-- CLK __|^^^|___|^^^|___|^^^|___|....^^^|___|^^^|___|^^^|___|^^
--
-- REQ _________|^^^^^^^|____________________________________
-- WE ______________________________________________________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^....^^^^^^^^^^^^^^^|_________
-- IOB_OE __________|^^^^^^^^^^^^^^^^....^^^^^^^^^^^^^^^|_________
--
-- ADDR[1:0] | 00 | 00 |.... 11 | 11 |---------
-- DATA ----------| data-0 | data-3 |---------
-- BUSY __________|^^^^^^^^^^^^^^^^....^^^^^^^^^^^^^^^|________
-- ACK_R ___________________________...._______|^^^^^^^|________
--
-- single write request (assume BE="0011")
--
-- state |_idle |_write0|_write1|_write0|_write1|_idle |
--
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^
--
-- REQ _________|^^^^^^^|____________________________________
-- WE _________|^^^^^^^|____________________________________
--
-- ADDR[1:0] | 00 | 00 |.... 01 | 01 |---------
-- DATA ----------| data-0 |....data-1 |---------
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
-- IOB_OE ________________________________________________________
-- IOB_WE ______________|^^^^^^^|___________|^^^^^^^|_____________
--
-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
-- ACK_W ______________________________________|^^^^^^^|_________
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity c7_sram_memctl is -- SRAM controller for Cmod A7
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv17; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end c7_sram_memctl;
architecture syn of c7_sram_memctl is
type state_type is (
s_idle, -- s_idle: wait for req
s_read0, -- s_read0: read cycle, 1st half
s_read1, -- s_read1: read cycle, 2nd half
s_write0, -- s_write0: write cycle, 1st half
s_write1 -- s_write1: write cycle, 2nd half
);
type regs_type is record
state : state_type; -- state
addrb : slv2; -- byte address
be : slv4; -- be pending
memdi : slv32; -- MEM_DI buffer
memdo : slv24; -- MEM_DO buffer for byte 0,1,2
ackr : slbit; -- signal ack_r
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
"00", -- addrb
"0000", -- be
(others=>'0'), -- memdi
(others=>'0'), -- memdo
'0' -- ackr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CLK_180 : slbit := '0';
signal MEM_CE_N : slbit := '0';
signal MEM_WE_N : slbit := '0';
signal MEM_OE_N : slbit := '0';
signal MEM_DI : slv8 := "00000000";
signal MEM_DO : slv8 := "00000000";
signal ADDRB : slv2 := "00";
signal ADDRW_CE : slbit := '0';
signal ADDRB_CE : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
signal DATA_OE : slbit := '0';
begin
CLK_180 <= not CLK;
IOB_MEM_CE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CE_N,
PAD => O_MEM_CE_N
);
IOB_MEM_WE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK_180,
CE => '1',
DO => MEM_WE_N,
PAD => O_MEM_WE_N
);
IOB_MEM_OE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_OE_N,
PAD => O_MEM_OE_N
);
IOB_MEM_ADDRW : iob_reg_o_gen
generic map (
DWIDTH => 17)
port map (
CLK => CLK,
CE => ADDRW_CE,
DO => ADDR,
PAD => O_MEM_ADDR(18 downto 2)
);
IOB_MEM_ADDRB : iob_reg_o_gen
generic map (
DWIDTH => 2)
port map (
CLK => CLK,
CE => ADDRB_CE,
DO => ADDRB,
PAD => O_MEM_ADDR(1 downto 0)
);
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
CEO => DATA_CEO,
OE => DATA_OE,
DI => MEM_DO,
DO => MEM_DI,
PAD => IO_MEM_DATA
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, REQ, WE, BE, MEM_DO, DI)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibusy : slbit := '0';
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable iaddrw_ce : slbit := '0';
variable iaddrb : slv2 := "00";
variable iaddrb_be : slv2 := "00";
variable iaddrb_ce : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imem_di : slv8 := "00000000";
begin
r := R_REGS;
n := R_REGS;
n.ackr := '0';
ibusy := '0';
iackw := '0';
iactr := '0';
iactw := '0';
imem_ce := '0';
imem_we := '0';
imem_oe := '0';
iaddrw_ce := '0';
iaddrb := "00";
iaddrb_be := "00";
iaddrb_ce := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imem_di := "00000000";
if r.be(0) = '1' then
iaddrb_be := "00";
imem_di := r.memdi( 7 downto 0);
elsif r.be(1) = '1' then
iaddrb_be := "01";
imem_di := r.memdi(15 downto 8);
elsif r.be(2) = '1' then
iaddrb_be := "10";
imem_di := r.memdi(23 downto 16);
elsif r.be(3) = '1' then
iaddrb_be := "11";
imem_di := r.memdi(31 downto 24);
end if;
case r.state is
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
if WE = '0' then -- if READ requested
iaddrw_ce := '1'; -- latch word address
iaddrb_ce := '1'; -- latch byte address (use 0)
imem_ce := '1'; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
n.state := s_read0; -- next: read0
else -- if WRITE requested
iaddrw_ce := '1'; -- latch word address
n.be := BE; -- latch pending BEs
n.memdi := DI; -- latch data
n.state := s_write1; -- next: write 2nd part
end if;
end if;
when s_read0 => -- s_read0: read cycle, 1st half
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
case r.addrb is -- capture last byte; inc byte count
when "00" => n.addrb := "01";
when "01" => n.addrb := "10"; n.memdo( 7 downto 0) := MEM_DO;
when "10" => n.addrb := "11"; n.memdo(15 downto 8) := MEM_DO;
when "11" => n.addrb := "00"; n.memdo(23 downto 16) := MEM_DO;
when others => null;
end case;
n.state := s_read1; -- next: read1
when s_read1 => -- s_read1: read cycle, 2nd half
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
idata_cei := '1'; -- latch input data
if r.addrb = "00" then -- last byte seen (counter wrapped) ?
n.ackr := '1'; -- ACK_R next cycle
n.state := s_idle;
else -- more bytes to do ?
imem_ce := '1'; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
iaddrb := r.addrb; -- use addrb counter
iaddrb_ce := '1'; -- latch byte address (use r.addrb)
n.state := s_read0;
end if;
when s_write0 => -- s_write0: write cycle, 1st half
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce SRAM next cycle
imem_we := '1'; -- we SRAM next shifted cycle
n.state := s_write1; -- next: write cycle, 2nd half
when s_write1 => -- s_write1: write cycle, 2nd half
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
if r.be = "0000" then -- all done ?
iackw := '1'; -- signal write acknowledge
n.state := s_idle; -- next: idle
else -- more to do ?
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce SRAM next cycle
idata_ceo := '1'; -- latch output data (to SRAM)
iaddrb := iaddrb_be; -- use addrb from be encode
iaddrb_ce := '1'; -- latch byte address (use iaddr_be)
n.be(to_integer(unsigned(iaddrb_be))) := '0'; -- mark byte done
n.state := s_write0; -- next: write 1st half
end if;
when others => null;
end case;
N_REGS <= n;
MEM_CE_N <= not imem_ce;
MEM_WE_N <= not imem_we;
MEM_OE_N <= not imem_oe;
MEM_DI <= imem_di;
ADDRW_CE <= iaddrw_ce;
ADDRB <= iaddrb;
ADDRB_CE <= iaddrb_ce;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;
DATA_OE <= idata_oe;
BUSY <= ibusy;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= iactr;
ACT_W <= iactw;
DO <= MEM_DO & r.memdo;
end process proc_next;
end syn;
| gpl-3.0 | 2df516b039cd267375f3b44fdb6b1d99 | 0.399803 | 3.751138 | false | false | false | false |
project-oak/silveroak | investigations/kami/counter/counter4_top.vhdl | 1 | 2,774 | --
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- A simple test program for the Xilinx ZCU104605 development board that
-- makes the user GPIO LEDs flash for the binary sequence 0..7, with a
-- reset from the push button GPIO_PB_SW3 SW18 at a 1 second frequency.
library ieee;
use ieee.std_logic_1164.all;
package counter_package is
subtype count_type is natural range 0 to 15;
component mkModule1 is
port(signal CLK : in std_ulogic;
signal RST_N : in std_ulogic;
signal EN_count_value : in std_ulogic;
signal count_value : out count_type;
signal RDY_count_value : out std_ulogic);
end component mkModule1;
end package counter_package;
library ieee;
use ieee.std_logic_1164.all;
use work.counter_package.all;
entity counter4 is
port (signal CLK_125_P : in std_ulogic; -- 125MHz clock P at pin H11 LVDS
signal CLK_125_N : in std_ulogic; -- 125MHz clock N at pin G11 LVDS
signal GPIO_PB_SW3 : in std_ulogic; -- pin C3 LVCMOS33 connected to push-button GPIO_PB_SW3 SW18
signal GPIO_LED : out count_type -- LEDs at pins D5 (LSB), D6, A5, B5 (MSB) LVCMOS33
);
end entity counter4;
library unisim;
use unisim.vcomponents.all;
architecture behavioral of counter4 is
signal count : count_type;
signal clk125MHz, clk1Hz : std_ulogic := '0';
signal inv_rest : std_ulogic;
signal en : std_ulogic := '1';
signal inv_reset : std_ulogic;
begin
clock_buffer : ibufgds port map (o => clk125MHz, i => CLK_125_P, ib => CLK_125_N);
clock_divider : process is
variable divider_count : natural := 0;
begin
wait until clk125MHz'event and clk125MHz = '1';
if divider_count = 62500000 then
clk1Hz <= not clk1Hz;
divider_count := 0;
else
divider_count := divider_count + 1;
end if;
end process clock_divider;
inv_reset <= not GPIO_PB_SW3;
kami_counter : mkModule1 port map (CLK => clk1Hz,
RST_N => inv_reset,
EN_count_value => en,
count_value => count,
RDY_count_value => open);
GPIO_LED <= count;
end architecture behavioral;
| apache-2.0 | 8cb7980f49028197e4a2b24ae5e4a198 | 0.65429 | 3.708556 | false | false | false | false |
wfjm/w11 | rtl/vlib/simlib/simclkv.vhd | 1 | 2,095 | -- $Id: simclkv.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simclkv - sim
-- Description: Clock generator for test benches, variable period
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP,CLK_HOLD now optional ports
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-21 432 1.0.2 now numeric_std clean
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-12-27 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simclkv is -- test bench clock generator
-- with variable period
port (
CLK : out slbit; -- clock
CLK_PERIOD : in Delay_length; -- clock period
CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclkv;
architecture sim of simclkv is
begin
clk_proc: process
variable half_period : Delay_length := 0 ns;
begin
CLK <= '0';
clk_loop: loop
if CLK_HOLD = '1' then
wait until CLK_HOLD='0';
end if;
half_period := CLK_PERIOD/2;
CLK <= '1';
wait for half_period;
CLK <= '0';
wait for CLK_PERIOD-half_period;
exit clk_loop when CLK_STOP = '1';
end loop;
CLK <= '1'; -- final clock cycle for clk_sim
wait for CLK_PERIOD/2;
CLK <= '0';
wait for CLK_PERIOD-CLK_PERIOD/2;
wait; -- endless wait, simulator will stop
end process;
end sim;
| gpl-3.0 | f0143bbf514f98e67077aa76a18161b9 | 0.524582 | 3.669002 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vhd | 1 | 3,933 | -- $Id: nexys3_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys3_fusp_cuff_dummy;
architecture syn of nexys3_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
| gpl-3.0 | 822f22fcab27f3242aa9448ec8a3730d | 0.487668 | 3.184615 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_tb_xtea.vhd | 1 | 10,610 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 15;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
signal ext_periph, ext_periph_dly, ready: std_logic;
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
signal data_read_xtea, data_read_xtea_s: std_logic_vector(31 downto 0);
signal control: std_logic_vector(1 downto 0);
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
data_read_xtea <= data_read_xtea_s(7 downto 0) & data_read_xtea_s(15 downto 8) & data_read_xtea_s(23 downto 16) & data_read_xtea_s(31 downto 24);
ext_periph <= '1' when address(31 downto 24) = x"e7" else '0';
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
ext_periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
ext_periph_dly <= ext_periph;
end if;
end process;
process (clock_in, reset, address, key, input, output)
begin
if reset = '1' then
data_read_xtea_s <= (others => '0');
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1') then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea_s <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xe7000010
data_read_xtea_s <= key(127 downto 96);
when "0010" => -- key[1] 0xe7000020
data_read_xtea_s <= key(95 downto 64);
when "0011" => -- key[2] 0xe7000030
data_read_xtea_s <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea_s <= key(31 downto 0);
when "0101" => -- input[0] 0xe7000050
data_read_xtea_s <= input(63 downto 32);
when "0110" => -- input[1] 0xe7000060
data_read_xtea_s <= input(31 downto 0);
when "0111" => -- output[0] 0xe7000070
data_read_xtea_s <= output(63 downto 32);
when "1000" => -- output[1] 0xe7000080
data_read_xtea_s <= output(31 downto 0);
when others =>
data_read_xtea_s <= (others => '0');
end case;
end if;
end if;
end process;
process (clock_in, reset, address, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
input <= (others => '0');
control <= "00";
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xe7000000
case address(7 downto 4) is
when "0000" => -- control 0xe7000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write_periph(1 downto 0);
when "0001" => -- key[0] 0xe7000010
key(127 downto 96) <= data_write_periph;
when "0010" => -- key[1] 0xe7000020
key(95 downto 64) <= data_write_periph;
when "0011" => -- key[2] 0xe7000030
key(63 downto 32) <= data_write_periph;
when "0100" => -- key[3] 0xe7000040
key(31 downto 0) <= data_write_periph;
when "0101" => -- input[0] 0xe7000050
input(63 downto 32) <= data_write_periph;
when "0110" => -- input[1] 0xe7000060
input(31 downto 0) <= data_write_periph;
when others =>
end case;
end if;
end if;
end process;
-- XTEA core
crypto_core: entity work.xtea
port map( clock => clock_in,
reset => reset,
start => control(0),
encrypt => control(1),
key => key,
input => input,
output => output,
ready => ready
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | 6d09bd57b5a290f2d6c15ed8c75e6d11 | 0.590198 | 2.737358 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdlib.vhd | 1 | 17,242 | -- $Id: ibdlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: ibdlib
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.3.8 add ibd_m9312
-- 2019-04-26 1139 1.3.7 add ibdr_dl11_buf
-- 2019-04-14 1131 1.3.6 RLIM_CEV now slv8
-- 2019-04-07 1129 1.3.5 add ibdr_pc11_buf
-- 2019-04-07 1128 1.3.4 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2019-03-09 1121 1.3.3 add ibdr_lp11_buf
-- 2018-10-13 1055 1.3.2 update ibdr_maxisys (add IDEC port)
-- 2018-09-08 1043 1.3.1 update ibd_kw11p
-- 2017-01-29 847 1.3.1 add ibdr_deuna
-- 2015-05-09 676 1.3 start/stop/suspend overhaul
-- 2015-03-13 658 1.2.1 add rprm declaration (later renaned to rhrp)
-- 2014-06-08 561 1.2 fix rl11 declaration
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq;
-- 2009-06-01 221 1.0.3 add RESET to kw11l; add iist;
-- 2009-05-30 220 1.0.2 add most additional device def's
-- 2009-05-24 219 1.0.1 add CE_MSEC to _rk11; add _maxisys
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
package ibdlib is
type iist_line_type is record -- iist line
dcf : slbit; -- disconnect flag
req : slbit; -- request
stf : slbit; -- sanity timer flag
imask : slv4; -- interrupt mask
bmask : slv4; -- boot mask
par : slbit; -- parity (odd)
frm : slbit; -- frame error flag
end record iist_line_type;
constant iist_line_init : iist_line_type := ('1','0','0',"0000","0000",'0','0');
type iist_bus_type is array (3 downto 0) of iist_line_type;
constant iist_bus_init : iist_bus_type := (others=>iist_line_init);
type iist_mreq_type is record -- iist->cpu requests
lock : slbit; -- lock-up CPU
boot : slbit; -- boot-up CPU
end record iist_mreq_type;
constant iist_mreq_init : iist_mreq_type := ('0','0');
type iist_sres_type is record -- cpu->iist responses
ack_lock : slbit; -- release lock
ack_boot : slbit; -- boot started
end record iist_sres_type;
constant iist_sres_init : iist_sres_type := ('0','0');
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16));
component ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end component;
component ibd_kw11p is -- ibus dev(loc): KW11-P (prog clock)
-- fixed address: 172540
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
EXTEVT : in slbit; -- external event for RATE="11"
CPUSUSP : in slbit; -- cpu suspended
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
CPUSUSP : in slbit; -- cpu suspended
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_deuna is -- ibus dev(rem): DEUNA
-- fixed address: 174510
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rhrp is -- ibus dev(rem): RH+RP
-- fixed address: 174400
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rl11 is -- ibus dev(rem): RL11
-- fixed address: 174400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_tm11 is -- ibus dev(rem): TM11
-- fixed address: 172520
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_dz11 is -- ibus dev(rem): DZ11
generic (
IB_ADDR : slv16 := ibaddr_dz11;
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := ibaddr_dl11);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_dl11_buf is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := ibaddr_dl11;
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end component;
component ibdr_pc11_buf is -- ibus dev(rem): PC11 (buffered)
-- fixed address: 177550
generic (
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end component;
component ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_lp11_buf is -- ibus dev(rem): LP11 (buffered)
-- fixed address: 177514
generic (
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibd_m9312 is -- ibus dev: M9312
-- fixed address: 165***,173***
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DISPREG : out slv16 -- display register
);
end component;
component ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
component ibdr_maxisys is -- ibus(rem) full system
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
IDEC : in slbit; -- instruction decode
CPUSUSP : in slbit; -- cpu suspended
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
end package ibdlib;
| gpl-3.0 | c8cc0d1ab1e4a99863e04d93d1b6cb6d | 0.492344 | 4.152697 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_ibtst.vhd | 1 | 16,470 | -- $Id: ibd_ibtst.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibtst - syn
-- Description: ibus dev(rem): ibus tester
--
-- Dependencies: memlib/fifo_simple_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 1.0.1 rnam dly[rw]->bsy[rw]; datto for write; add datab
-- 2019-02-16 1112 1.0 Initial version
-- 2019-02-09 1110 0.1 First draft
------------------------------------------------------------------------------
--
-- ibus registers:
--
-- Addr Bits IB RB IR Name Function
-- 00 cntl Control register
-- 15 -- 0W 00 fclr fifo clear
-- 8 -- RW 00 datab ibus ack while busy for data nak
-- 7 -- RW 00 datto ibus timeout for data nak
-- 6 -- RW 00 nobyt disallow byte writes to data (loc+rem)
-- 5 -- RW 00 bsyw enable loc write busy for fifo/data
-- 4 -- RW 00 bsyr enable loc read busy for fifo/data
-- 3 -- RW 11 remw enable rem write for fifo/data
-- 2 -- RW 11 remr enable rem read for fifo/data
-- 1 -- RW 00 locw enable loc write for fifo/data
-- 0 -- RW 00 locr enable loc read for fifo/data
-- 01 -- R- stat Status register (moni last data/fifo)
-- 15:12 -- R- fsize fifo size
-- 6 -- R- racc remote access seen
-- 5 -- R- cacc console access seen
-- 4 -- R- be1 byte enable high seen
-- 3 -- R- be0 byte enable low seen
-- 2 -- R- rmw read-modify-write seen
-- 1 -- R- we write enable seen
-- 0 -- R- re read enable seen
-- 10 rw rw 00 data data register (byte/word writable)
-- 11 rw rw fifo fifo interface register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16))); -- base address
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_ibtst;
architecture syn of ibd_ibtst is
constant ibaddr_cntl : slv2 := "00"; -- cntl address offset
constant ibaddr_stat : slv2 := "01"; -- stat address offset
constant ibaddr_data : slv2 := "10"; -- bdat address offset
constant ibaddr_fifo : slv2 := "11"; -- wdat address offset
constant cntl_ibf_fclr : integer := 15;
constant cntl_ibf_datab : integer := 8;
constant cntl_ibf_datto : integer := 7;
constant cntl_ibf_nobyt : integer := 6;
constant cntl_ibf_bsyw : integer := 5;
constant cntl_ibf_bsyr : integer := 4;
constant cntl_ibf_remw : integer := 3;
constant cntl_ibf_remr : integer := 2;
constant cntl_ibf_locw : integer := 1;
constant cntl_ibf_locr : integer := 0;
subtype stat_ibf_fsize is integer range 15 downto 12;
constant stat_ibf_racc : integer := 6;
constant stat_ibf_cacc : integer := 5;
constant stat_ibf_be1 : integer := 4;
constant stat_ibf_be0 : integer := 3;
constant stat_ibf_rmw : integer := 2;
constant stat_ibf_we : integer := 1;
constant stat_ibf_re : integer := 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
datab : slbit; -- cntl: ibus busy for bad loc data
datto : slbit; -- cntl: ibus timeout for bad loc data
nobyt : slbit; -- cntl: disallow byte writes to data
bsyw : slbit; -- cntl: enable loc write busy
bsyr : slbit; -- cntl: enable loc read busy
remw : slbit; -- cntl: enable rem write
remr : slbit; -- cntl: enable rem read
locw : slbit; -- cntl: enable loc write
locr : slbit; -- cntl: enable loc read
racc : slbit; -- stat: racc seen
cacc : slbit; -- stat: cacc seen
be1 : slbit; -- stat: be1 seen
be0 : slbit; -- stat: be0 seen
rmw : slbit; -- stat: rmw seen
we : slbit; -- stat: we seen
re : slbit; -- stat: re seen
data : slv16; -- data register
dcnt : slv3; -- delay counter
req_1 : slbit; -- (re or we) of last cycle
rwm_1 : slbit; -- (re or we or rmw) of last cycle
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0','0', -- datab,datto,nobyt,bsyw,bsyr
'1','1','0','0', -- remw,remr,locw,locr
'0','0','0','0', -- racc,cacc,be1,be0
'0','0','0', -- rmw,we,re
(others=>'0'), -- data
(others=>'0'), -- dcnt
'0','0' -- req_1,rwm_1
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_CE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_RESET : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv4 := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
CE => FIFO_CE,
WE => FIFO_WE,
DI => IB_MREQ.din,
DO => FIFO_DO,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL,
SIZE => FIFO_SIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, RESET, FIFO_DO, FIFO_EMPTY,
FIFO_FULL, FIFO_SIZE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibreq : slbit := '0';
variable ibbusy : slbit := '0';
variable iback : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ififo_rst : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable bsyok : slbit := '0'; -- fifo/data busy ok
variable dobsy : slbit := '0'; -- fifo/data do busy
variable wrok : slbit := '0'; -- fifo/data write ok
variable rdok : slbit := '0'; -- fifo/data read ok
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibbusy := '0';
iback := r.ibsel and ibreq;
ififo_rst := RESET;
ififo_ce := '0';
ififo_we := '0';
bsyok := '0';
if IB_MREQ.racc = '0' then -- loc
bsyok := (r.bsyr and IB_MREQ.re) or (r.bsyw and IB_MREQ.we);
end if;
dobsy := '0';
if IB_MREQ.racc = '1' then -- rem
wrok := r.remw;
rdok := r.remr;
else -- loc
wrok := r.locw;
rdok := r.locr;
end if;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- re,we,rmw edge detectors
n.req_1 := r.ibsel and (ibreq);
n.rwm_1 := r.ibsel and (ibreq or IB_MREQ.rmw);
-- ibus mreq monitor
if r.ibsel = '1' then
if (ibreq or IB_MREQ.rmw) = '1' and -- re or we or rmw
IB_MREQ.addr(2) = '1' then -- and addr = (data or fifo)
if r.rwm_1 = '0' then -- leading edge
n.racc := IB_MREQ.racc;
n.cacc := IB_MREQ.cacc;
n.be1 := IB_MREQ.be1;
n.be0 := IB_MREQ.be0;
n.rmw := IB_MREQ.rmw;
n.we := IB_MREQ.we;
n.re := IB_MREQ.re;
else -- later
n.we := r.we or IB_MREQ.we;
n.re := r.re or IB_MREQ.re;
end if;
end if;
end if;
-- delay counter
if r.ibsel='1' and ibreq='1' and bsyok='1' then -- selected,active,busy
if r.req_1 = '0' then -- leading edge
n.dcnt := "111";
dobsy := '1';
else -- later
if r.dcnt /= "000" then
n.dcnt := slv(unsigned(r.dcnt) - 1);
dobsy := '1';
end if;
end if;
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
if IB_MREQ.racc = '1' then -- rem
if IB_MREQ.we = '1' then -- write
ififo_rst := IB_MREQ.din(cntl_ibf_fclr);
n.datab := IB_MREQ.din(cntl_ibf_datab);
n.datto := IB_MREQ.din(cntl_ibf_datto);
n.nobyt := IB_MREQ.din(cntl_ibf_nobyt);
n.bsyw := IB_MREQ.din(cntl_ibf_bsyw);
n.bsyr := IB_MREQ.din(cntl_ibf_bsyr);
n.remw := IB_MREQ.din(cntl_ibf_remw);
n.remr := IB_MREQ.din(cntl_ibf_remr);
n.locw := IB_MREQ.din(cntl_ibf_locw);
n.locr := IB_MREQ.din(cntl_ibf_locr);
end if;
else -- loc
iback := '0'; -- reject loc access to CNTL
end if;
when ibaddr_stat => -- STAT
if IB_MREQ.racc = '0' then -- loc
iback := '0'; -- reject loc access to STAT
end if;
when ibaddr_data => -- DATA
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if r.nobyt = '1' and -- byte write allowed check
(IB_MREQ.be1='0' or IB_MREQ.be0='0') then
iback := '0'; -- send nak
else -- byte check ok
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- no busy active
if IB_MREQ.be1 = '1' then
n.data(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.data(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
end if; -- dobsy = '1'
end if; -- byte check
else -- write disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
end if;
else -- read disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- rdok = '0'
end if; -- IB_MREQ.re = '1'
when ibaddr_fifo => -- FIFO
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_FULL = '0' then -- fifo not full
ififo_ce := '1';
ififo_we := '1';
else -- fifo full
iback := '0'; -- send nak
end if; -- FIFO_FULL = '0'
end if; -- dobsy = '1'
else -- write disabled
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_EMPTY = '0' then -- fifo not empty
ififo_ce := '1';
else -- fifo empty
iback := '0'; -- send nak
end if; -- FIFO_EMPTY = '0'
end if; -- dobsy = '1'
else -- read disabled
iback := '0'; -- send nak
end if; -- rdok = '1'
end if; -- IB_MREQ.re = '1'
when others => null;
end case; --
end if; --r.ibsel = '1'
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
idout(cntl_ibf_datab) := r.datab;
idout(cntl_ibf_datto) := r.datto;
idout(cntl_ibf_nobyt) := r.nobyt;
idout(cntl_ibf_bsyw) := r.bsyw;
idout(cntl_ibf_bsyr) := r.bsyr;
idout(cntl_ibf_remw) := r.remw;
idout(cntl_ibf_remr) := r.remr;
idout(cntl_ibf_locw) := r.locw;
idout(cntl_ibf_locr) := r.locr;
when ibaddr_stat => -- STAT
idout(stat_ibf_fsize) := FIFO_SIZE;
idout(stat_ibf_racc) := r.racc;
idout(stat_ibf_cacc) := r.cacc;
idout(stat_ibf_be1) := r.be1;
idout(stat_ibf_be0) := r.be0;
idout(stat_ibf_rmw) := r.rmw;
idout(stat_ibf_we) := r.we;
idout(stat_ibf_re) := r.re;
when ibaddr_data => -- DATA
idout := r.data;
when ibaddr_fifo => -- FIFO
idout := FIFO_DO;
when others => null;
end case;
end if;
N_REGS <= n;
FIFO_RESET <= ififo_rst;
FIFO_CE <= ififo_ce;
FIFO_WE <= ififo_we;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= ibbusy;
end process proc_next;
end syn;
| gpl-3.0 | 957b4bc6b0ae03a36e279d4188c32b42 | 0.421676 | 3.805453 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_sres_or_2.vhd | 1 | 1,964 | -- $Id: ib_sres_or_2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_2 - syn
-- Description: ibus: result or, 2 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_2;
architecture syn of ib_sres_or_2 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => ib_sres_init,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
| gpl-3.0 | faefbf58fd7096768baf3a92d5c5f877 | 0.51222 | 3.102686 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/s3board/sys_conf.vhd | 1 | 3,643 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.3.7 drop iist
-- 2018-09-22 1050 1.3.6 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.5 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.3.4 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-03-04 858 1.3.3 enable deuna
-- 2017-01-29 847 1.3.2 add sys_conf_ibd_deuna
-- 2016-05-27 770 1.3.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2014-12-22 619 1.1.2 add _rbmon_awidth
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
-- 2008-02-23 118 1.1 add memory config
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
end package sys_conf;
| gpl-3.0 | 653ecee21d39d5f7e754e704da0034d7 | 0.586055 | 3.238222 | false | true | false | false |
jasonpeng/cg3207-proj | Fetch.vhd | 1 | 3,438 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:51:54 10/29/2013
-- Design Name:
-- Module Name: InstructionMemory - Behavioral_InstructionMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Fetch is
PORT(
clk: in std_logic;
reset: in std_logic;
In_stall_if: in std_logic;
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BEQ_PC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PCSrc : IN STD_LOGIC;
Jump : IN STD_LOGIC;
JumpPC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 ); -- JUmp address
IF_ID_Flush: out std_logic
);
end Fetch;
architecture Behavioral of Fetch is
component ram_instr
port (
ADDR : in std_logic_vector(31 downto 0);
DATA : out std_logic_vector(31 downto 0));
end component;
signal PC: std_logic_vector (31 downto 0); -- fetched instruction
signal nextPC: std_logic_vector(31 downto 0); -- Next PC
signal read_addr: std_logic_vector(31 downto 0);
signal IncPC: std_logic_vector (31 downto 0); -- PC + 4
begin
instr_mem: ram_instr port map (ADDR => read_addr, DATA => Instruction);
-- multiplex next PC
nextPC <= (JumpPC - x"00000004") when (Jump = '1')
else BEQ_PC when (PCSrc = '1')
else incPC;
incPC <= PC + X"00000004"; -- incPC = PC +4 ;
PC_out <= incPC;
read_addr <= "00"&PC(31 downto 2);
IF_ID_Flush <='1' when (Jump='1' or PCSrc = '1') -- in case Jump and Branch, flush the IF_ID
else '0';
process (Clk,Reset)
begin
if (Reset = '1') then
PC <= X"00000000"; -- currently start from 0 for test
elsif (Clk'event and Clk = '1') then
if(In_stall_if = '0') then
PC <= nextPC;
else
PC <= PC;
end if;
end if;
end process;
end Behavioral;
--------------------------------------------------------------------------
-- Instruction RAM
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_instr is
port (
ADDR : in std_logic_vector(31 downto 0);
DATA : out std_logic_vector(31 downto 0)
);
end ram_instr;
architecture syn of ram_instr is
type rom_type is array (0 to 31) of std_logic_vector (31 downto 0);
-- currently, set 0-6 for test purpose
CONSTANT ROM : rom_type := (
x"34020003",x"34030009",x"00432020",x"00822020",x"00832020",x"8c050004",x"00852020",x"ac040008",
x"8c060008",x"0086382a",x"28480004",X"000341c0",x"00622804",x"00033843",x"00433807",x"00034042",
x"00434006",x"10420002",x"34020007",x"34020009",x"3402000b",x"08000019",x"34030008",x"3403000a",
x"3403000c",x"08000019",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
DATA <= ROM(conv_integer(ADDR));
end syn; | gpl-2.0 | 3bdcfe2e7df452e99b7e5973766bb0dc | 0.598022 | 3.315333 | false | false | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/core.vhd | 1 | 17,670 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: core
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This is the CPU core with its pipeline. The pipeline is as following:
-- IF | ID | XB | MEM | WB
-- Here, branch is handled in XB (eXecute/Branch) stage. Due to the
-- restriction of SUBLEQ instruction, an early branch is not possible.
-- However, since only SUBLEQ and LW/SW are supported, we have lots of
-- slack in XB stage to handle branch.
entity CPUCore is
port (
clk : in std_logic;
resetb : in std_logic;
-- Interface with register file
core_rf_en : out std_logic;
core_rf_rs_a : out std_logic_vector(4 downto 0);
core_rf_rs_d : in std_logic_vector(63 downto 0);
core_rf_rt_a : out std_logic_vector(4 downto 0);
core_rf_rt_d : in std_logic_vector(63 downto 0);
core_rf_wb_we : out std_logic;
core_rf_wb_a : out std_logic_vector(4 downto 0);
core_rf_wb_d : out std_logic_vector(63 downto 0);
-- Interface with MMU
---- Instruction Port
core_mmu_we_i : out std_logic;
core_mmu_en_i : out std_logic;
core_mmu_addr_i : out std_logic_vector(31 downto 3);
core_mmu_ben_i : out std_logic_vector(7 downto 0);
core_mmu_di_i : out std_logic_vector(63 downto 0);
core_mmu_do_i : in std_logic_vector(63 downto 0);
---- Data Port
core_mmu_we_d : out std_logic;
core_mmu_en_d : out std_logic;
core_mmu_addr_d : out std_logic_vector(31 downto 3);
core_mmu_ben_d : out std_logic_vector(7 downto 0);
core_mmu_di_d : out std_logic_vector(63 downto 0);
core_mmu_do_d : in std_logic_vector(63 downto 0)
);
end entity CPUCore;
architecture simple_pipeline of CPUCore is
subtype opcode_t is std_logic_vector(6 downto 0);
subtype int64_t is signed(63 downto 0);
subtype func3_t is std_logic_vector(2 downto 0);
subtype func7_t is std_logic_vector(6 downto 0);
subtype addr_t is signed(31 downto 0);
subtype rf_addr_t is std_logic_vector(4 downto 0);
subtype data_t is std_logic_vector(63 downto 0);
subtype instr_t is std_logic_vector(31 downto 0);
-- IF stage signals
signal IF_PC : addr_t;
signal IF_Instr : instr_t;
signal mmu_addr_i_s32 : signed(31 downto 3);
signal IF_nextPC : signed(31 downto 0);
signal IF_Valid : std_logic;
-- ID stage signals
signal ID_PC : addr_t;
signal stall : std_logic;
signal ID_highword : std_logic;
signal ID_XMXB1, ID_XMXB2 : std_logic;
signal ID_XMMEM1, ID_XMMEM2 : std_logic;
signal ID_Valid : std_logic;
signal ID_RType, ID_IType, ID_SType, ID_UType : std_logic;
signal ID_Instr : instr_t;
alias ID_opcode : opcode_t is ID_Instr(6 downto 0);
alias ID_rs1 : rf_addr_t is ID_Instr(19 downto 15);
alias ID_rs2 : rf_addr_t is ID_Instr(24 downto 20);
alias ID_rs1_d : data_t is core_rf_rs_d;
alias ID_rs2_d : data_t is core_rf_rt_d;
alias ID_wb_d : data_t is core_rf_wb_d;
alias ID_rd : rf_addr_t is ID_Instr(11 downto 7);
alias ID_func3 : func3_t is ID_Instr(14 downto 12);
alias ID_func7 : func7_t is ID_Instr(31 downto 25);
--signal ID_RegWrite, ID_MemRead, ID_MemWrite : std_logic;
-- XB stage signals
signal XB_PC : addr_t;
signal XB_RType, XB_IType, XB_SType, XB_UType : std_logic;
---- Note that add and negate can make subtract
---- ls3 = Left Shift 3 bits
signal XB_is_bubble : std_logic;
signal XB_aluop1, XB_aluop2, XB_aluout, XB_forwrs1, XB_forwrs2 : int64_t;
signal XB_opadd, XB_opneg, XB_opls3, XB_opbranch : std_logic;
signal XB_op2rs2, XB_op2imm : std_logic;
signal XB_Branch : std_logic;
signal XB_Imm : signed(31 downto 0);
signal XB_rs1, XB_rs2, XB_rd : rf_addr_t;
signal XB_rs1_d, XB_rs2_d : int64_t;
signal XB_RegWrite, XB_MemRead, XB_MemWrite : std_logic;
signal XB_FORW1_MEM_XB, XB_FORW1_WB_XB : std_logic;
signal XB_FORW2_MEM_XB, XB_FORW2_WB_XB : std_logic;
-- MEM stage signals
signal MEM_RType, MEM_IType, MEM_SType, MEM_UType : std_logic;
signal MEM_MemRead, MEM_MemWrite, MEM_RegWrite : std_logic;
signal MEM_rs1, MEM_rs2, MEM_rd : rf_addr_t;
signal MEM_aluresult, MEM_rs2_d : int64_t;
-- WB stage signals
signal WB_RegWrite : std_logic;
signal WB_rd : rf_addr_t;
signal WB_data : int64_t;
-- Constants
---- Opcode types
------ This means "S-type Custom"
constant OP_SC : opcode_t := "0001000";
constant OP_LOAD : opcode_t := "0000011";
constant OP_STORE : opcode_t := "0100011";
constant FUNC3_SUBLEQ : func3_t := "000";
constant FUNC3_LD : func3_t := "011";
constant FUNC3_SD : func3_t := "011";
constant ZERO64 : int64_t := (others => '0');
begin
core_mmu_en_i <= '1';
core_mmu_we_i <= '0';
core_rf_en <= '1';
-- Signed/Unsigned signals for convenience
core_mmu_addr_i <= std_logic_vector(mmu_addr_i_s32);
-- Check source/destination matches
ID_XMXB1 <= '1' when
XB_RegWrite = '1' and
((ID_rs1 = XB_rd and XB_SType = '0') or
(ID_rs1 = XB_rs1 and XB_SType = '1')) and
ID_rs1 /= "00000" and
(ID_RType = '1' or ID_Itype = '1' or ID_SType = '1')
else '0';
ID_XMXB2 <= '1' when
XB_RegWrite = '1'and
((ID_rs2 = XB_rd and XB_SType = '0') or
(ID_rs2 = XB_rs1 and XB_SType = '1')) and
ID_rs2 /= "00000" and (ID_RType = '1' or ID_SType = '1')
else '0';
ID_XMMEM1 <= '1' when
MEM_RegWrite = '1' and
((ID_rs1 = MEM_rd and MEM_SType = '0') or
(ID_rs1 = MEM_rs1 and MEM_SType = '1')
) and
ID_rs1 /= "00000" and
(ID_RType = '1' or ID_Itype = '1' or ID_SType = '1')
else '0';
ID_XMMEM2 <= '1' when
MEM_RegWrite = '1' and
((ID_rs2 = MEM_rd and MEM_SType = '0') or
(ID_rs2 = MEM_rs1 and MEM_SType = '1')
) and
ID_rs2 /= "00000" and
(ID_RType = '1' or ID_SType = '1')
else '0';
-- The stall signal.
-- Stall is needed when source register is dependant on an immediate
-- senior LW.
stall <= '1' when (ID_XMXB1 = '1' or ID_XMXB2 = '1')
and XB_MemRead = '1' and XB_RegWrite = '1'
else '0';
-- ID Stage Combinational
---- No R type here
ID_RType <= '0';
---- Loads are itype, so is subleq
ID_IType <= '1' when
ID_opcode = OP_LOAD
else '0';
ID_SType <= '1' when (ID_opcode = OP_STORE or ID_opcode = OP_SC) else '0';
ID_UType <= '0';
-- IF stage combinational
core_mmu_ben_i <= "00000000";
if_comb : process (IF_PC, core_mmu_do_i, IF_Instr)
begin
IF_Instr <= (others=>'-');
core_rf_rs_a <= (others=>'-');
core_rf_rt_a <= (others=>'-');
if (IF_PC(2) = '0') then
IF_Instr <= core_mmu_do_i(31 downto 0);
else
IF_Instr <= core_mmu_do_i(63 downto 32);
end if;
core_rf_rs_a <= IF_Instr(19 downto 15);
core_rf_rt_a <= IF_Instr(24 downto 20);
end process if_comb;
-- Branch overrides stall, or there will be deadlock
update_pc : process (stall, XB_Branch, IF_PC, XB_Imm)
begin
if (stall = '0' or XB_Branch = '1') then
if (XB_Branch = '0') then
-- PC increment by 4 when not branching
IF_nextPC <= IF_PC + to_signed(4, 32);
else
-- PC increment by signed extended branch offset. Aligned to 4-bytes
IF_nextPC <= XB_PC + to_signed(4, 32) + shift_left(resize(XB_Imm(11 downto 0), 32), 2);
end if;
else
IF_nextPC <= IF_PC;
end if;
end process;
mmu_addr_i_s32(31 downto 3) <= IF_nextPC(31 downto 3);
-- XB stage combinational
-- Helper
XB_is_bubble <= '1' when XB_RegWrite = '0' and XB_opbranch = '0' and
XB_MemRead = '0' and XB_MemWrite = '0' else '0';
xb_comb : process
(
XB_rs1_d, XB_RegWrite,
XB_FORW1_MEM_XB, MEM_aluresult, XB_FORW1_WB_XB, WB_data,
XB_rs2_d,
XB_FORW2_MEM_XB, XB_FORW2_WB_XB, XB_forwrs1,
XB_forwrs2, XB_op2rs2, XB_op2imm, XB_IType, XB_SType, XB_Imm,
XB_opls3, XB_opneg, XB_opadd, XB_opbranch, XB_aluout,
XB_aluop1, XB_aluop2,
XB_MemRead, XB_MemWrite
)
--variable XB_forwrs1 : int64_t;
variable XB_op1, XB_op2 : int64_t;
begin
-- Forwarding
XB_forwrs1 <= XB_rs1_d;
if (XB_FORW1_MEM_XB = '1') then
-- Forward from Mem stage
if (MEM_MemRead = '1')then
XB_forwrs1 <= signed(core_mmu_do_d);
else
XB_forwrs1 <= MEM_aluresult;
end if;
elsif (XB_FORW1_WB_XB = '1') then
-- Forward from WB stage
XB_forwrs1 <= WB_data;
end if;
XB_forwrs2 <= XB_rs2_d;
if (XB_FORW2_MEM_XB = '1') then
-- Forward from Mem stage
if (MEM_MemRead = '1')then
XB_forwrs2 <= signed(core_mmu_do_d);
else
XB_forwrs2 <= MEM_aluresult;
end if;
elsif (XB_FORW2_WB_XB = '1') then
-- Forward from WB stage
XB_forwrs2 <= WB_data;
end if;
XB_op1 := XB_forwrs1;
XB_op2 := (others => '-');
XB_op2_mux : if (XB_op2rs2 = '1') then
XB_op2 := XB_forwrs2;
elsif (XB_op2imm = '1') then
if (XB_IType = '1' or XB_SType = '1') then
-- Sign extend
XB_op2 := resize(XB_Imm(11 downto 0), 64);
end if;
end if XB_op2_mux;
---- Left shift op2 when needed, such as in LD and SD
if (XB_opls3 = '1') then
XB_op2 := shift_left(XB_op2, 3);
end if;
---- Negate op2 when needed, such as in SUBLEQ
if (XB_opneg = '1') then
XB_op2 := -XB_op2;
end if;
---- Compute
XB_aluop1 <= XB_op1;
XB_aluop2 <= XB_op2;
XB_aluout <= (others => '-');
if XB_opadd = '1' then
XB_aluout <= XB_aluop1 + XB_aluop2;
end if;
---- Branch
XB_Branch <= '0';
if XB_opbranch = '1' then
-- There is only one branch condition: Less than or Equal to 0
if XB_aluout <= ZERO64 then
XB_Branch <= '1';
end if;
end if;
---- Memory
core_mmu_en_d <= '0';
core_mmu_we_d <= '0';
core_mmu_ben_d <= "00000000";
core_mmu_di_d <= (others => '-');
if (XB_MemRead = '1' or XB_MemWrite = '1') then
core_mmu_en_d <= '1';
-- No memory protection!
core_mmu_addr_d <= std_logic_vector(XB_aluout(31 downto 3));
if (XB_MemWrite = '1') then
core_mmu_we_d <= '1';
end if;
end if;
if (XB_MemWrite = '1') then
core_mmu_di_d <= std_logic_vector(XB_rs2_d);
end if;
end process xb_comb;
-- MEM stage combinational
mem_comb : process (MEM_RegWrite, MEM_rd,
MEM_MemRead, core_mmu_do_d, MEM_aluresult)
begin
-- Note that WB signals are shadow registers
core_rf_wb_we <= MEM_RegWrite;
core_rf_wb_a <= MEM_rd;
core_rf_wb_d <= (others=>'-');
if (MEM_MemRead = '1') then
core_rf_wb_d <= core_mmu_do_d;
else
core_rf_wb_d <= std_logic_vector(MEM_aluresult);
end if;
end process mem_comb;
-- PC_ben : process (PC)
-- begin
-- core_mmu_ben_i <= (others => 'X');
-- if (PC(2 downto 0) = "000") then
-- core_mmu_ben_i <= "11110000";
-- elsif (PC(2 downto 0) = "100") then
-- core_mmu_ben_i <= "00001111";
-- end if;
-- end process;
-- THE CPU CORE IS HERE!!!!!!
core : process (clk, resetb)
--variable IF_Instr : instr_t;
--variable XB_Branch : std_logic;
--variable inc_pc : addr_t;
begin
main_clock : if (resetb = '0') then
-- IF reset
IF_PC <= X"FFFFFFFC";
IF_Valid <= '0';
--mmu_addr_i_s32 <= (others => '0');
-- ID reset
ID_Valid <= '0';
-- XB reset
XB_MemRead <= '0';
XB_MemWrite <= '0';
XB_RegWrite <= '0';
XB_opbranch <= '0';
-- MEM reset
MEM_MemRead <= '0';
MEM_MemWrite <= '0';
MEM_RegWrite <= '0';
-- WB reset
WB_RegWrite <= '0';
elsif (clk'event and clk = '1') then
------------------------------------- WB stage
------------------------------------- MEM stage
-- Note that WB signals are shadow registers
WB_RegWrite <= MEM_RegWrite;
WB_rd <= MEM_rd;
if (MEM_MemRead = '1') then
WB_data <= signed(core_mmu_do_d);
else
WB_data <= MEM_aluresult;
end if;
------------------------------------- XB stage
---- Note that the mem control signals are shadow registers
MEM_MemRead <= XB_MemRead;
MEM_MemWrite <= XB_MemWrite;
MEM_RegWrite <= XB_RegWrite;
MEM_Rs1 <= XB_Rs1;
MEM_Rs2 <= XB_Rs2;
MEM_Rd <= XB_Rd;
MEM_RType <= XB_RType;
MEM_ITYPE <= XB_IType;
MEM_SType <= XB_SType;
MEM_UType <= XB_UType;
MEM_rs2_d <= XB_forwrs2;
MEM_aluresult <= XB_aluout;
------------------------------------- IF stage
---- Update PC
IF_Valid <= '1';
ID_highword <= IF_PC(2);
if (stall = '0' or XB_Branch = '1') then
if (XB_Branch = '0') then
ID_valid <= IF_Valid;
--inc_pc := to_signed(4, 32);
else
ID_valid <= '0';
--inc_pc := shift_left(resize(XB_Imm(19 downto 8), 32), 2);
end if;
IF_PC <= IF_nextPC;
ID_PC <= IF_PC;
ID_Instr <= IF_Instr;
end if;
------------------------------------- ID stage
XB_RType <= ID_RType;
XB_IType <= ID_IType;
XB_SType <= ID_SType;
XB_UType <= ID_UType;
XB_PC <= ID_PC;
immediate_field : if (ID_IType = '1') then
XB_Imm(11 downto 0) <= signed(ID_Instr(31 downto 20));
elsif (ID_SType = '1') then
XB_Imm(11 downto 5) <= signed(ID_Instr(31 downto 25));
XB_Imm(4 downto 0) <= signed(ID_Instr(11 downto 7));
elsif (ID_UType = '1') then
XB_Imm(31 downto 12) <= signed(ID_Instr(31 downto 12));
end if immediate_field;
-- Defaults
XB_RegWrite <= '0';
XB_MemRead <= '0';
XB_MemWrite <='0';
XB_opbranch <= '0';
XB_opls3 <= '0';
XB_op2rs2 <= '0';
XB_op2imm <= '0';
XB_opneg <= '0';
-- Only continue if instruction is valid
ID_is_valid : if (ID_Valid = '1' and stall = '0' and
XB_Branch = '0') then
side_effect_signals : if (ID_IType = '1') then
case ID_opcode is
when OP_LOAD =>
if (ID_func3 = FUNC3_LD) then
-- Immediate value left shift 3 bits, add to register value
XB_rs1 <= ID_rs1;
XB_rs1_d <= signed(ID_rs1_d);
XB_rd <= ID_rd;
XB_opls3 <= '1';
XB_op2imm <= '1';
XB_opadd <= '1';
XB_MemRead <= '1';
XB_RegWrite <= '1';
else -- No illegal instructions here
end if;
when others => NULL; -- No illegal instruction here
end case;
elsif (ID_SType = '1') then
case ID_opcode is
when OP_SC =>
if (ID_func3 = FUNC3_SUBLEQ) then
-- There is only the SubLEq instruction
XB_RegWrite <= '1';
XB_rs1 <= ID_rs1;
XB_rs1_d <= signed(ID_rs1_d);
XB_rs2 <= ID_rs2;
XB_rs2_d <= signed(ID_rs2_d);
XB_rd <= ID_rs1;
XB_op2rs2 <= '1'; XB_op2imm <= '0';
XB_opadd <= '1';
XB_opneg <= '1';
XB_opbranch <= '1';
else -- No illegal instruction here
end if;
when OP_STORE =>
if (ID_func3 = FUNC3_SD) then
-- Immediate value left shift 3 bits, add to register value
XB_rs1 <= ID_rs1;
XB_rs1_d <= signed(ID_rs1_d);
XB_rs2 <= ID_rs2;
XB_rs2_d <= signed(ID_rs2_d);
XB_opls3 <= '1';
XB_opadd <= '1';
XB_op2imm <= '1';
XB_MemWrite <= '1';
else -- No illegal instructions here
end if;
when others => NULL;
end case;
end if side_effect_signals;
end if ID_is_valid;
------------------------------------- Hazard Detection Unit in ID
-- Default Value
XB_FORW1_MEM_XB <= '0';
XB_FORW1_WB_XB <= '0';
hdu_rs1 : if (ID_XMXB1 = '1') then
-- RS1 forwarding from MEM to XB.
-- When an instr in XB needs immediate senior's help.
-- | XB | MEM |
-- | SUBLEQ x2, x3, C1 | SUBLEQ x3, x8, C2 |
-- ^-----Depend-----^
-- | LW x4, (off)x2 | SUBLEQ x2, x0, C4 |
-- ^---Depend---^
XB_FORW1_MEM_XB <= '1';
elsif (ID_XMMEM1 = '1') then
-- RS1 forwarding from WB to XB
XB_FORW1_WB_XB <= '1';
end if hdu_rs1;
XB_FORW2_MEM_XB <= '0';
XB_FORW2_WB_XB <= '0';
hdu_rs2 : if (ID_XMXB2 = '1') then
-- RS2 forwarding from MEM to XB
XB_FORW2_MEM_XB <= '1';
elsif (ID_XMMEM2 = '1')then
XB_FORW2_WB_XB <= '1';
end if hdu_rs2;
end if main_clock;
end process core;
end architecture simple_pipeline;
| gpl-3.0 | ebb7108c92b5b9c036594a70d62563b4 | 0.529768 | 3.166099 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/tb_nexys3_core.vhd | 1 | 3,877 | -- $Id: tb_nexys3_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.1 use simbididly
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | abb4497513cefe3cd2c4ca976bacccfe | 0.539077 | 2.910661 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_6.vhd | 1 | 2,944 | -- $Id: rb_sres_or_6.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_6 - syn
-- Description: rbus result or, 6 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
-- 2016-03-12 741 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_6 is -- rbus result or, 6 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
RB_SRES_6 : in rb_sres_type := rb_sres_init; -- rb_sres input 6
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_6;
architecture syn of rb_sres_or_6 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3,
RB_SRES_4, RB_SRES_5, RB_SRES_6)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack or
RB_SRES_4.ack or
RB_SRES_5.ack or
RB_SRES_6.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy or
RB_SRES_4.busy or
RB_SRES_5.busy or
RB_SRES_6.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err or
RB_SRES_4.err or
RB_SRES_5.err or
RB_SRES_6.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout or
RB_SRES_4.dout or
RB_SRES_5.dout or
RB_SRES_6.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => RB_SRES_4,
RB_SRES_5 => RB_SRES_5,
RB_SRES_6 => RB_SRES_6
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 9b23c4e1a88e450855fd168d2e6eaba9 | 0.455842 | 3.300448 | false | false | false | false |
sjohann81/hf-risc | tools/xilinx/ram_xilinx.vhd | 1 | 22,558 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
RAMB16_S9_inst0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(31 downto 24),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(3));
RAMB16_S9_inst1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(23 downto 16),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(2));
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(15 downto 8),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(1));
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(7 downto 0),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(0));
end; --architecture logic
| gpl-2.0 | e774210b077211a67a05ac8ad37ead0e | 0.855351 | 7.427725 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_bram.vhd | 1 | 3,784 | -- $Id: pdp11_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram - syn
-- Description: pdp11: BRAM based ext. memory dummy
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
-- 2008-02-17 117 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_bram is -- cache
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end pdp11_bram;
architecture syn of pdp11_bram is
type regs_type is record
req_r : slbit; -- read request
req_w : slbit; -- write request
be : slv2; -- byte enables
addr : slv(AWIDTH-1 downto 1); -- address
end record regs_type;
constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
constant regs_init : regs_type := (
'0','0', -- req_r,w
(others=>'0'), -- be
addrzero -- addr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal MEM_ENB : slbit := '0';
signal MEM_WEA : slv2 := "00";
signal MEM_DOA : slv16 := (others=>'0');
begin
MEM_BYT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(0),
WEB => R_REGS.be(0),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(7 downto 0),
DIB => MEM_DOA(7 downto 0),
DOA => MEM_DOA(7 downto 0),
DOB => open
);
MEM_BYT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(1),
WEB => R_REGS.be(1),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(15 downto 8),
DIB => MEM_DOA(15 downto 8),
DOA => MEM_DOA(15 downto 8),
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
N_REGS.be <= EM_MREQ.be;
N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
EM_SRES.ack_r <= R_REGS.req_r;
EM_SRES.ack_w <= R_REGS.req_w;
EM_SRES.dout <= MEM_DOA;
end syn;
| gpl-3.0 | f0d104824b48ce0f27fc62a722fe88d5 | 0.511892 | 3.228669 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tb_fifo_2c_dram.vhd | 1 | 9,946 | -- $Id: tb_fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_2c_dram - sim
-- Description: Test bench for fifo_2c_dram
--
-- Dependencies: simlib/simclkv
-- simlib/simclkvcnt
-- tbd_fifo_2c_dram [UUT]
--
-- To test: fifo_2c_dram
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.3, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-07 421 1.0.5 now numeric_std clean
-- 2010-06-03 299 1.0.4 use sv_ prefix for shared variables
-- 2010-04-17 277 1.0.3 use direct instantiation of tbd_
-- 2009-11-22 252 1.0.2 CLK*_CYCLE now 31 bits
-- 2007-12-28 107 1.0.1 add reset and check handling
-- 2007-12-28 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_2c_dram is
end tb_fifo_2c_dram;
architecture sim of tb_fifo_2c_dram is
signal CLKW : slbit := '0';
signal CLKR : slbit := '0';
signal RESETW : slbit := '0';
signal RESETR : slbit := '0';
signal DI : slv16 := (others=>'0');
signal ENA : slbit := '0';
signal BUSY : slbit := '0';
signal DO : slv16 := (others=>'0');
signal VAL : slbit := '0';
signal SIZEW : slv4 := (others=>'0');
signal SIZER : slv4 := (others=>'0');
signal N_HOLD : slbit := '0';
signal R_HOLD : slbit := '0';
signal CLKW_PERIOD : Delay_length := 20 ns;
signal CLKR_PERIOD : Delay_length := 20 ns;
signal CLK_HOLD : slbit := '1';
signal CLK_STOP : slbit := '0';
signal CLKW_CYCLE : integer := 0;
signal CLKR_CYCLE : integer := 0;
signal CLKR_C2OUT : Delay_length := 10 ns;
shared variable sv_nrstr : integer := 0;
shared variable sv_ndatar : integer := 0; -- data counter (fifo data output)
begin
CLKWGEN : simclkv
port map (
CLK => CLKW,
CLK_PERIOD => CLKW_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKWCNT : simclkcnt port map (CLK => CLKW, CLK_CYCLE => CLKW_CYCLE);
CLKRGEN : simclkv
port map (
CLK => CLKR,
CLK_PERIOD => CLKR_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKRCNT : simclkcnt port map (CLK => CLKR, CLK_CYCLE => CLKR_CYCLE);
UUT : entity work.tbd_fifo_2c_dram
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => R_HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_2c_dram_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable dtime : Delay_length := 0 ns;
variable nwait : integer := 0; --
variable nword : integer := 0; --
variable nbusy : integer := 0; -- number of busy before accept
variable idi : slv16 := (others=>'0');
variable ndataw : integer := 0; -- data counter (fifo data input)
variable iclkw_period : Delay_length := 20 ns;
variable iclkw_setup : Delay_length := 5 ns;
variable iclkr_period : Delay_length := 20 ns;
variable iclkr_c2out : Delay_length := 10 ns;
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".chold" => -- .chold time
write(oline, string'(".chold"));
writeline(output, oline);
read_ea(iline, dtime);
CLK_HOLD <= '1';
wait for dtime;
CLK_HOLD <= '0';
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
when ".cdef " => -- .cdef wper wset rper rout
write(oline, string'(".cdef "));
writeline(output, oline);
read_ea(iline, iclkw_period);
read_ea(iline, iclkw_setup);
read_ea(iline, iclkr_period);
read_ea(iline, iclkr_c2out);
CLKW_PERIOD <= iclkw_period;
CLKR_PERIOD <= iclkr_period;
CLKR_C2OUT <= iclkr_c2out;
if CLK_HOLD = '0' then
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
end if;
when ".ndata" => -- .ndata num
read_ea(iline, ndataw);
sv_ndatar := ndataw;
when ".hold " => -- .hold time
read_ea(iline, dtime);
if dtime > 0 ns then
N_HOLD <= '1', '0' after dtime;
else -- allow hold abort with 0ns
N_HOLD <= '0';
end if;
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
wait for nwait*iclkw_period;
when "resetw" => -- resetw ncyc
read_ea(iline, nwait);
RESETW <= '1';
wait for nwait*iclkw_period;
RESETW <= '0';
when "resetr" => -- resetr ncyc
read_ea(iline, nwait);
sv_nrstr := nwait;
when "send " => -- send nw nd
read_ea(iline, nwait);
read_ea(iline, nword);
for i in 1 to nword loop
wait for nwait*iclkw_period;
idi := slv(to_unsigned(ndataw, 16));
ndataw := ndataw + 1;
DI <= idi;
ENA <= '1';
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for iclkw_period;
end loop;
writetimestamp(oline, CLKW_CYCLE, ": stim ");
write(oline, idi, right, 18);
write(oline, SIZEW, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(idi)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZEW)), right, 2);
write(oline, string'(")"));
if nbusy > 0 then
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
end if;
writeline(output, oline);
wait for iclkw_period;
ENA <= '0';
end loop; -- i
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
if N_HOLD = '1' then
wait until N_HOLD='0';
end if;
wait for 20*(iclkw_period+iclkr_period);
CLK_STOP <= '1';
writetimestamp(oline, CLKW_CYCLE, ": DONE-w ");
writeline(output, oline);
writetimestamp(oline, CLKR_CYCLE, ": DONE-r ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable nhold : integer := 0; -- number of hold cycles before accept
variable isizer_last : slv4 := (others=>'0');
variable ido : slv16 := (others=>'0');
begin
loop
wait until rising_edge(CLKR);
wait for CLKR_C2OUT;
if VAL = '1' then
if R_HOLD = '1' then
nhold := nhold + 1;
else
ido := slv(to_unsigned(sv_ndatar, 16));
sv_ndatar := sv_ndatar + 1;
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(DO)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
if nhold > 0 then
write(oline, string'(" nhold="));
write(oline, nhold, right, 2);
end if;
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
nhold := 0;
end if;
else
if SIZER /= isizer_last then
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, string'(" "));
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
writeline(output, oline);
end if;
end if;
isizer_last := SIZER;
end loop;
end process proc_moni;
proc_clkr: process (CLKR)
begin
if rising_edge(CLKR) then
R_HOLD <= N_HOLD;
if sv_nrstr > 0 then
RESETR <= '1';
sv_nrstr := sv_nrstr - 1;
else
RESETR <= '0';
end if;
end if;
end process proc_clkr;
end sim;
| gpl-3.0 | 2fed62881e37e23c5705ba0cffe98733 | 0.496984 | 3.912667 | false | false | false | false |
sjohann81/hf-risc | mips/sim/hf-risc_tb.vhd | 1 | 7,149 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | 78f3be1c4bf7aeee8e88a46edde5b5be | 0.590152 | 2.715154 | false | false | false | false |
wfjm/w11 | rtl/w11a/sys_conf.vhd | 1 | 1,554 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Default definitions
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-09-22 1051 1.1.3 add missing config's
-- 2016-05-28 770 1.1.2 sys_conf_mem_losize now type natural
-- 2015-06-26 695 1.1.1 add sys_conf_dmscnt
-- 2015-05-01 672 1.1 adopt to pdp11_sys70
-- 2008-02-23 118 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM
constant sys_conf_mem_losize : natural := 8#000777#;-- 32 kByte
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
end package sys_conf;
| gpl-3.0 | e1361c073a0e2f4d3ad157d36d8f9429 | 0.57529 | 3.334764 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf2_sim.vhd | 1 | 2,723 | -- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n4 (for test bench)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-18 775 1.0.1 use PLL for clkser_gentype
-- 2016-04-09 760 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !!
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !!
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | b21a042b2aa5c36f0255699860bbc072 | 0.583915 | 3.980994 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/KCPSM6.vhdl | 4 | 108,754 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
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-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
-- Version 1.3 - 21st May 2014.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | 3b876cf691194e0812cd9f4f74692ca0 | 0.498584 | 3.607576 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/tb_rlink.vhd | 1 | 36,931 | -- $Id: tb_rlink.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink - sim
-- Description: Test bench for rlink_core
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/tb/clkdivce_tb
-- rbus/rbd_tester
-- tbd_rlink_gen [UUT]
--
-- To test: rlink_core (via tbd_rlink_direct)
-- rlink_base (via tbd_rlink_serport)
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2019.1; ghdl 0.18-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 4.1.3 fix for ghdl V0.36 -Whide warnings
-- 2019-06-02 1159 4.1.2 use rbaddr_ constants
-- 2016-09-10 806 4.1.1 use clkdivce_tb
-- 2014-10-12 596 4.1 use readgen_ea; add get_cmd_ea; labo instead of stat
-- add txblk,rxblk,rxrbeg,rxrend,rxcbs,anmsg commands
-- 2014-08-28 588 4.0 now rlink v4 iface -> txcac has 16 bit; 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; adopt txca,txcad,txcac
-- 2011-12-23 444 3.1 use new simclk/simclkcnt
-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
-- add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd
-- 2010-12-12 344 3.0.1 add .attn again; add .txbad, .txoof; ren oob->oof
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- use rbd_tester instead of sim target;
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix
-- for shared variables
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits
-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce
-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test
-- for missing responses
-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
-- command set:
-- .reset assert RESET for 1 clk
-- .rlmon ien enable rlink monitor (9 bit)
-- .rlbmo ien enable rlink monitor (8 bit)
-- .rbmon ien enable rbus monitor
-- .wait n wait n clks
-- .iowt n wait n clks for rlink i/o; auto-extend
-- .attn dat(16) pulse attn lines with dat
--
-- - high level ---
-- anmsg apat attn notify message
-- sop start packet
-- eop end packet
-- rreg seq addr data stat rreg cmd
-- wreg seq addr data stat wreg cmd
-- init seq addr data stat init cmd
-- attn seq data stat attn cmd
-- labo seq data stat labo cmd
-- rblks seq addr nblk data stat rblk cmd (with seq)
-- wblks seq addr nblk data stat wblk cmd (with seq)
-- rblkd seq addr ndone stat rblk cmd (with data list)
-- wblkd seq addr ndone stat wblk cmd (with data list)
-- .dclr clear data list
-- .dwrd data add word to data list
-- .dseq nblk data add sequence to data list
--
-- - low level ---
-- txcrc send crc
-- txbad send bad (inverted) crc
-- txc cmd(8) send cmd - crc
-- txca cmd(8) addr(16) send cmd - al ah - crcl crch
-- txcad cmd(8) addr(16) dat(16) send cmd - al ah - dl dh - crcl crch
-- txcac cmd(8) addr(16) cnt(16) send cmd - al ah - cl ch - crcl crch
-- txoof dat(9) send out-of-frame symbol
-- rxcrc expect crc
-- rxcs cmd(8) stat(8) expect cmd - stat - crcl crch
-- rxcds cmd(8) dat(16) stat(8) expect cmd - dl dh - stat - crcl crch
-- rxcbs cmd(8) dat(8) stat(8) expect cmd - dl - stat - crcl crch
-- rxrbeg cmd(8) cnt(16) expect cmd - cl ch
-- rxrend dcnt(16) expect dcl dch - stat - crcl crch
-- rxoof dat(9) expect out-of-frame symbol
--
-- - raw level ---
-- txsop send <sop>
-- txeop send <eop>
-- txnak send <nak>
-- txattn send <attn>
-- tx8 dat(8) send 8 bit value
-- tx16 dat(16) send 16 bit value
-- txblk n start send n 16 values
-- rxsop reset rx list; expect sop
-- rxeop expect <eop>
-- rxnak expect <nak>
-- rxattn expect <attn>
-- rx8 dat(8) expect 8 bit value
-- rx16 dat(16) expect 16 bit value
-- rxblk n start expect n 16 values
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_rlink is
end tb_rlink;
architecture sim of tb_rlink is
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_data is integer range 7 downto 0; -- d9: data field
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv16 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RB_LAM_TBENCH : slv16 := (others=>'0');
signal RB_LAM_TESTER : slv16 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal TXRXACT : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant rxlist_size : positive := 4096; -- size of rxlist
constant txlist_size : positive := 4096; -- size of txlist
constant datlist_size : positive := 2048; -- size of datlist
constant slv9_zero : slv9 := (others=>'0');
constant slv16_zero : slv16 := (others=>'0');
type rxlist_array_type is array (0 to rxlist_size-1) of slv9;
type txlist_array_type is array (0 to txlist_size-1) of slv9;
type datlist_array_type is array (0 to datlist_size-1) of slv16;
shared variable sv_rxlist : rxlist_array_type := (others=>slv9_zero);
shared variable sv_nrxlist : natural := 0;
shared variable sv_rxind : natural := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
component tbd_rlink_gen is -- rlink, generic tb design interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end component;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CLKDIV : entity work.clkdivce_tb
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
RBTEST : rbd_tester
generic map (
RB_ADDR => rbaddr_tester)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM_TESTER,
RB_STAT => RB_STAT
);
RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH;
UUT : tbd_rlink_gen
port map (
CLK => CLK,
CE_INT => CE_MSEC,
CE_USEC => CE_USEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
TXRXACT => TXRXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_stim";
variable iline : line;
variable oline : line;
variable ien : slbit := '0';
variable icmd : slv8 := (others=>'0');
variable iaddr : slv16 := (others=>'0');
variable icnt : slv16 := (others=>'0');
variable ibabo : slv8 := (others=>'0');
variable istat : slv8 := (others=>'0');
variable iattn : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable idat8 : slv8 := (others=>'0');
variable ioof : slv9 := (others=>'0');
variable iblkval : slv16 := (others=>'0');
variable iblkmsk : slv16 := (others=>'0');
variable nblk : natural := 1;
variable ndone : natural := 1;
variable rxlabo : boolean := false;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iowait : integer := 0;
variable txcrc,rxcrc : slv16 := (others=>'0');
variable txlist : txlist_array_type := (others=>slv9_zero);
variable ntxlist : natural := 0;
variable datlist : datlist_array_type := (others=>slv16_zero);
variable ndatlist : natural := 0;
-- read command line helpers ------------------------------------
procedure get_cmd_ea ( -- ---- get_cmd_ea -----------
L : inout line;
picmd : out slv8) is
variable cname : string(1 to 4) := (others=>' ');
variable ival : natural;
variable lok : boolean;
variable cmd : slv3;
variable dat : slv8;
begin
readword_ea(L, cname);
ival := 0;
readoptchar(L, ',', lok);
if lok then
readint_ea(L, ival, 0, 31);
end if;
case cname is
when "rreg" => cmd := c_rlink_cmd_rreg;
when "rblk" => cmd := c_rlink_cmd_rblk;
when "wreg" => cmd := c_rlink_cmd_wreg;
when "wblk" => cmd := c_rlink_cmd_wblk;
when "labo" => cmd := c_rlink_cmd_labo;
when "attn" => cmd := c_rlink_cmd_attn;
when "init" => cmd := c_rlink_cmd_init;
when others =>
report "unknown cmd code" severity failure;
end case;
dat := (others=>'0');
dat(c_rlink_cmd_rbf_seq) := slv(to_unsigned(ival,5));
dat(c_rlink_cmd_rbf_code) := cmd;
picmd := dat;
end procedure get_cmd_ea;
procedure get_seq_ea ( -- ---- get_seq_ea -----------
L : inout line;
pcode : in slv3;
picmd : out slv8) is
variable ival : natural;
variable dat : slv8;
begin
readint_ea(L, ival, 0, 31);
dat := (others=>'0');
dat(c_rlink_cmd_rbf_seq) := slv(to_unsigned(ival,5));
dat(c_rlink_cmd_rbf_code) := pcode;
picmd := dat;
end procedure get_seq_ea;
-- tx helpers ----------------------------------------------------
procedure do_tx9 (data : in slv9) is -- ---- do_tx9 -------------
begin
txlist(ntxlist) := data;
ntxlist := ntxlist + 1;
end procedure do_tx9;
procedure do_tx8 (data : in slv8) is -- ---- do_tx8 -------------
begin
do_tx9('0' & data);
txcrc := crc16_update_tbl(txcrc, data);
end procedure do_tx8;
procedure do_tx16 (data : in slv16) is -- ---- do_tx16 ----------
begin
do_tx8(data( f_byte0));
do_tx8(data(f_byte1));
end procedure do_tx16;
procedure do_txcrc is -- ---- do_txcrc -------------
begin
do_tx9('0' & txcrc(f_byte0));
do_tx9('0' & txcrc(f_byte1));
end procedure do_txcrc;
procedure do_txsop is -- ---- do_txsop -------------
begin
do_tx9(c_rlink_dat_sop);
txcrc := (others=>'0');
end procedure do_txsop;
procedure do_txeop is -- ---- do_txeop -------------
begin
do_tx9(c_rlink_dat_eop);
end procedure do_txeop;
procedure do_txc (picmd : in slv8) is -- ---- do_txc -------------
begin
do_tx8(picmd);
do_txcrc;
end procedure do_txc;
procedure do_txca ( -- ---- do_txca --------------
picmd : in slv8;
piaddr : in slv16) is
begin
do_tx8(picmd);
do_tx16(piaddr);
do_txcrc;
end procedure do_txca;
procedure do_txcad ( -- ---- do_txcad -------------
picmd : in slv8;
piaddr : in slv16;
pidata : in slv16) is
begin
do_tx8(picmd);
do_tx16(piaddr);
do_tx16(pidata);
do_txcrc;
end procedure do_txcad;
procedure do_txblks ( -- ---- do_txblks ------------
pnblk : in natural;
pstart : in slv16) is
variable lidata : slv16;
begin
lidata := pstart;
for i in 1 to pnblk loop
do_tx16(lidata);
lidata := slv(unsigned(lidata) + 1);
end loop;
end procedure do_txblks;
-- rx helpers ----------------------------------------------------
procedure checkmiss_rx is -- ---- checkmiss_rx ---------
begin
if sv_rxind < sv_nrxlist then
for i in sv_rxind to sv_nrxlist-1 loop
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, sv_rxlist(i)(d_f_cflag));
write(oline, string'(" "));
write(oline, sv_rxlist(i)(f_byte0));
writeline(output, oline);
end loop;
end if;
end procedure checkmiss_rx;
procedure do_rx9 (data : in slv9) is -- ---- do_rx9 -------------
begin
sv_rxlist(sv_nrxlist) := data;
sv_nrxlist := sv_nrxlist + 1;
end procedure do_rx9;
procedure do_rx8 (data : in slv8) is -- ---- do_rx8 -------------
begin
if not rxlabo then
do_rx9('0' & data);
rxcrc := crc16_update_tbl(rxcrc, data);
end if;
end procedure do_rx8;
procedure do_rx16 (data : in slv16) is -- ---- do_rx16 ----------
begin
do_rx8(data(f_byte0));
do_rx8(data(f_byte1));
end procedure do_rx16;
procedure do_rxattn is -- ---- do_rxattn ------------
begin
do_rx9(c_rlink_dat_attn);
rxcrc := (others=>'0');
end procedure do_rxattn;
procedure do_rxcrc is -- ---- do_rxcrc -------------
begin
if not rxlabo then
do_rx9('0' & rxcrc(f_byte0));
do_rx9('0' & rxcrc(f_byte1));
end if;
end procedure do_rxcrc;
procedure do_rxsop is -- ---- do_rxsop -------------
begin
checkmiss_rx;
sv_nrxlist := 0;
sv_rxind := 0;
rxcrc := (others=>'0');
do_rx9(c_rlink_dat_sop);
end procedure do_rxsop;
procedure do_rxeop is -- ---- do_rxeop -------------
begin
do_rx9(c_rlink_dat_eop);
end procedure do_rxeop;
procedure do_rxcs ( -- ---- do_rxcs ----------
picmd : in slv8;
pistat : in slv8) is
begin
do_rx8(picmd);
do_rx8(pistat);
do_rxcrc;
end procedure do_rxcs;
procedure do_rxcds ( -- ---- do_rxcds ----------
picmd : in slv8;
pidata : in slv16;
pistat : in slv8) is
begin
do_rx8(picmd);
do_rx16(pidata);
do_rx8(pistat);
do_rxcrc;
end procedure do_rxcds;
procedure do_rxcbs ( -- ---- do_rxcbs ----------
picmd : in slv8;
pibabo : in slv8;
pistat : in slv8) is
begin
do_rx8(picmd);
do_rx8(pibabo);
do_rx8(pistat);
do_rxcrc;
end procedure do_rxcbs;
procedure do_rxrbeg ( -- ---- do_rxrbeg -------------
picmd : in slv8;
pnblk : in natural) is
begin
do_rx8(picmd);
do_rx16(slv(to_unsigned(pnblk,16)));
end procedure do_rxrbeg;
procedure do_rxrend ( -- ---- do_rxrend -------------
pnblk : in natural;
pistat : in slv8) is
begin
do_rx16(slv(to_unsigned(pnblk,16)));
do_rx8(pistat);
do_rxcrc;
end procedure do_rxrend;
procedure do_rxblks ( -- ---- do_rxblks ------------
pnblk : in natural;
pstart : in slv16) is
variable lidata : slv16;
begin
lidata := pstart;
for i in 1 to pnblk loop
do_rx16(lidata);
lidata := slv(unsigned(lidata) + 1);
end loop;
end procedure do_rxblks;
begin
SB_CNTL <= (others=>'0');
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
SB_CNTL(sbcntl_sbf_rlmon) <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rlbmo" => -- .rlbmo
read_ea(iline, ien);
SB_CNTL(sbcntl_sbf_rlbmon) <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
SB_CNTL(sbcntl_sbf_rbmon) <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".iowt " => -- .iowt
read_ea(iline, iowait);
idelta := iowait;
while idelta > 0 loop -- until time has expired
if TXRXACT = '1' then -- if any io activity
idelta := iowait; -- restart timer
else
idelta := idelta - 1; -- otherwise count down time
end if;
wait for clock_period;
end loop;
when ".attn " => -- .attn
read_ea(iline, iattn);
RB_LAM_TBENCH <= iattn; -- pulse attn lines
wait for clock_period; -- for 1 clock
RB_LAM_TBENCH <= (others=>'0');
when "txsop " => -- txsop send sop
do_txsop;
when "txeop " => -- txeop send eop
do_txeop;
when "txnak " => -- txnak send nak
do_tx9(c_rlink_dat_nak);
when "txattn" => -- txattn send attn
do_tx9(c_rlink_dat_attn);
when "tx8 " => -- tx8 send 8 bit value
readgen_ea(iline, idat8, 2);
do_tx8(idat8);
when "tx16 " => -- tx16 send 16 bit value
readgen_ea(iline, idata, 2);
do_tx16(idata);
when "txblk " => -- txblk send n 16 bit values
read_ea(iline, nblk);
readgen_ea(iline, idata, 2);
do_txblks(nblk, idata);
when "txcrc " => -- txcrc send crc
do_txcrc;
when "txbad " => -- txbad send bad crc
do_tx9('0' & (not txcrc(f_byte0)));
do_tx9('0' & (not txcrc(f_byte1)));
when "txc " => -- txc send: cmd crc
get_cmd_ea(iline, icmd);
do_txc(icmd);
when "txca " => -- txc send: cmd addr crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, iaddr, 2);
do_txca(icmd, iaddr);
when "txcad " => -- txc send: cmd addr data crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, iaddr, 2);
readgen_ea(iline, idata, 2);
do_txcad(icmd, iaddr, idata);
when "txcac " => -- txc send: cmd addr cnt crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, iaddr, 2);
readgen_ea(iline, icnt, 2);
do_txcad(icmd, iaddr, icnt);
when "txoof " => -- txoof send out-of-frame symbol
readgen_ea(iline, txlist(0), 2);
ntxlist := 1;
when "rxsop " => -- rxsop expect sop
do_rxsop;
when "rxeop " => -- rxeop expect eop
do_rxeop;
when "rxnak " => -- rxnak expect nak
do_rx9(c_rlink_dat_nak);
when "rxattn" => -- rxattn expect attn
do_rxattn;
when "rx8 " => -- rx8 expect 8 bit value
readgen_ea(iline, idat8, 2);
do_rx8(idat8);
when "rx16 " => -- rx16 expect 16 bit value
readgen_ea(iline, idata, 2);
do_rx16(idata);
when "rxblk " => -- rxblk expect n 16 bit values
read_ea(iline, nblk);
readgen_ea(iline, idata, 2);
do_rxblks(nblk, idata);
when "rxcrc " => -- rxcrc expect crc
do_rxcrc;
when "rxcs " => -- rxcs expect: cmd stat crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, istat, 2);
do_rxcs(icmd, istat);
when "rxcds " => -- rxcsd expect: cmd data stat crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, idata, 2);
readgen_ea(iline, istat, 2);
do_rxcds(icmd, idata, istat);
when "rxcbs " => -- rxcsd expect: cmd babo stat crc
get_cmd_ea(iline, icmd);
readgen_ea(iline, ibabo, 2);
readgen_ea(iline, istat, 2);
do_rxcbs(icmd, ibabo, istat);
when "rxrbeg" => -- rxrbeg expect: cmd - cl ch
get_cmd_ea(iline, icmd);
read_ea(iline, nblk);
do_rxrbeg(icmd, nblk);
when "rxrend" => -- rxrend expect: dcl dch - stat - crc
read_ea(iline, nblk);
readgen_ea(iline, istat, 2);
do_rxrend(nblk, istat);
when "rxoof " => -- rxoof expect: out-of-frame symbol
readgen_ea(iline, ioof, 2);
sv_rxlist(sv_nrxlist) := ioof;
sv_nrxlist := sv_nrxlist + 1;
when "anmsg " => -- anmsg
readgen_ea(iline, idata, 2); -- apat
do_rxattn;
do_rx16(idata);
do_rxcrc;
do_rxeop;
when "sop " => -- sop
do_rxsop;
do_txsop;
rxlabo := false;
when "eop " => -- eop
do_rxeop;
do_txeop;
when "rreg " => -- rreg seq addr data stat
get_seq_ea(iline, c_rlink_cmd_rreg, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
readgen_ea(iline, idata, 2); -- data
readgen_ea(iline, istat, 2); -- stat
do_rxcds(icmd, idata, istat); -- rx: cmd dl sh stat ccsr
do_txca (icmd, iaddr); -- tx: cmd al ah ccsr
when "wreg " => -- wreg seq addr data stat
get_seq_ea(iline, c_rlink_cmd_wreg, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
readgen_ea(iline, idata, 2); -- data
readgen_ea(iline, istat, 2); -- stat
do_rxcs (icmd, istat); -- rx: cmd stat ccsr
do_txcad(icmd, iaddr, idata); -- tx: cmd al ah dl dh ccsr
when "init " => -- init seq addr data stat
get_seq_ea(iline, c_rlink_cmd_init, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
readgen_ea(iline, idata, 2); -- data
readgen_ea(iline, istat, 2); -- stat
do_rxcs (icmd, istat); -- rx: cmd stat ccsr
do_txcad(icmd, iaddr, idata); -- tx: cmd al ah dl dh ccsr
when "attn " => -- attn seq data stat
get_seq_ea(iline, c_rlink_cmd_attn, icmd); -- seq
readgen_ea(iline, idata, 2); -- data
readgen_ea(iline, istat, 2); -- stat
do_rxcds (icmd, idata, istat); -- rx: cmd dl dh stat ccsr
do_txc (icmd); -- tx: cmd ccsr
when "labo " => -- labo seq babo stat
get_seq_ea(iline, c_rlink_cmd_labo, icmd); -- seq
readgen_ea(iline, ibabo, 2); -- babo
readgen_ea(iline, istat, 2); -- stat
do_rxcbs (icmd, ibabo, istat); -- rx: cmd dl stat ccsr
do_txc (icmd); -- tx: cmd ccsr
rxlabo := ibabo /= x"00"; -- set rxlabo flag
when "rblks " => -- rblks seq addr nblk data stat
get_seq_ea(iline, c_rlink_cmd_rblk, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
read_ea(iline, nblk); -- nblk
readgen_ea(iline, idata, 2); -- start
readgen_ea(iline, istat, 2); -- stat
do_rxrbeg(icmd, nblk); --rx: cmd cl ch
do_rxblks(nblk, idata); -- nblk*(dl dh)
do_rxrend(nblk, istat); -- dcl dch stat ccrc
do_txcad(icmd, iaddr, -- tx: cmd al ah cl ch ccrc
slv(to_unsigned(nblk,16)));
when "wblks " => -- wblks seq addr nblk data stat
get_seq_ea(iline, c_rlink_cmd_wblk, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
read_ea(iline, nblk); -- nblk
readgen_ea(iline, idata, 2); -- start
readgen_ea(iline, istat, 2); -- stat
do_rxcds(icmd, -- rx: cmd dcl dch stat ccsr
slv(to_unsigned(nblk,16)),
istat);
do_txcad(icmd, iaddr, -- tx: cmd al ah cl ch ccrc
slv(to_unsigned(nblk,16)));
do_txblks(nblk, idata); -- nblk*(dl dh)
do_txcrc; -- dcrc
when "rblkd " => -- rblkd seq addr ndone stat
get_seq_ea(iline, c_rlink_cmd_rblk, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
read_ea(iline, ndone); -- ndone
readgen_ea(iline, istat, 2); -- stat
do_rxrbeg(icmd, ndatlist); --rx: cmd cl ch
for i in 0 to ndatlist-1 loop
do_rx16(datlist(i)); -- nblk*(dl dh)
end loop; -- i
do_rxrend(ndone, istat); -- dcl dch stat ccrc
do_txcad(icmd, iaddr, -- tx: cmd al ah cl ch ccrc
slv(to_unsigned(ndatlist,16)));
when "wblkd " => -- wblkd seq addr ndone stat
get_seq_ea(iline, c_rlink_cmd_wblk, icmd); -- seq
readgen_ea(iline, iaddr, 2); -- addr
read_ea(iline, ndone); -- ndone
readgen_ea(iline, istat, 2); -- stat
do_rxcds(icmd, -- rx: cmd dcl dch stat ccsr
slv(to_unsigned(ndone,16)),
istat);
do_txcad(icmd, iaddr, -- tx: cmd al ah cl ch ccrc
slv(to_unsigned(ndatlist,16)));
for i in 0 to ndatlist-1 loop
do_tx16(datlist(i)); -- nblk*(dl dh)
end loop; -- i
do_txcrc; -- dcrc
when ".dclr " => -- .dclr
ndatlist := 0;
when ".dwrd " => -- .dwrd data
readgen_ea(iline, idata, 2);
datlist(ndatlist) := idata;
ndatlist := ndatlist + 1;
when ".dseq " => -- .dseq nblk start
read_ea(iline, nblk);
readgen_ea(iline, idata, 2);
for i in 1 to nblk loop
datlist(ndatlist) := idata;
ndatlist := ndatlist + 1;
idata := slv(unsigned(idata) + 1);
end loop;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
next file_loop when ntxlist=0;
for i in 0 to ntxlist-1 loop
RL_DI <= txlist(i);
RL_ENA <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim");
write(oline, txlist(i)(d_f_cflag), right, 3);
write(oline, txlist(i)(d_f_data), right, 9);
if txlist(i)(d_f_cflag) = '1' then
case txlist(i) is
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
writeline(output, oline);
wait for clock_period;
while RL_BUSY = '1' loop
wait for clock_period;
end loop;
RL_ENA <= '0';
end loop; -- i
ntxlist := 0;
end loop; -- file fstim
wait for 50*clock_period;
checkmiss_rx;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RL_VAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni");
write(oline, RL_DO(d_f_cflag), right, 3);
write(oline, RL_DO(d_f_data), right, 9);
if RL_DO(d_f_cflag) = '1' then
case RL_DO is
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
if sv_nrxlist > 0 then
write(oline, string'(" CHECK"));
if sv_rxind < sv_nrxlist then
if RL_DO = sv_rxlist(sv_rxind) then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, sv_rxlist(sv_rxind)(d_f_cflag), right, 2);
write(oline, sv_rxlist(sv_rxind)(d_f_data), right, 9);
end if;
sv_rxind := sv_rxind + 1;
else
write(oline, string'(" FAIL, UNEXPECTED"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 4d07419baba708fa2e5bcdde95dce8cd | 0.465408 | 3.746297 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd | 1 | 9,458 | -- $Id: rlink_sp1c_fx2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - -
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.1 use rbaddr_ constants
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => '0', -- not used in FX2 enabled boards
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux -- rlink control mux -----------------
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
FX2CNTL : fx2_2fifoctl_ic -- FX2 interface ---------------------
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
| gpl-3.0 | 1237efd332a63f38965e5e58aabab7e6 | 0.506872 | 3.356281 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3_starterkit/spartan3_SRAM.vhd | 1 | 5,234 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
uart_support : string := "yes"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
int_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic;
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0);
ram_address: out std_logic_vector(31 downto 2);
ram_data: inout std_logic_vector(31 downto 0);
ram_ce1_n: out std_logic;
ram_ub1_n: out std_logic;
ram_lb1_n: out std_logic;
ram_ce2_n: out std_logic;
ram_ub2_n: out std_logic;
ram_lb2_n: out std_logic;
ram_we_n: out std_logic;
ram_oe_n: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_we, data_w_cpu: std_logic_vector(3 downto 0);
signal we_n_next : std_logic;
signal we_n_reg : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock, we_n_next)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
if reset_in = '1' then
we_n_reg <= '1';
elsif rising_edge(clk_in) then
we_n_reg <= we_n_next or not clock;
end if;
if reset_in = '1' then
data_read_ram <= (others => '0');
elsif rising_edge(clock) then
data_read_ram <= ram_data;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_access => data_access_cpu
);
-- peripherals / busmux logic
peripherals_busmux: entity work.busmux
generic map(
uart_support => uart_support
)
port map(
clock => clock,
reset => reset,
stall => stall,
stall_cpu => stall_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => address,
data_read_mem => data_read,
data_write_mem => data_write,
data_we_mem => data_we,
extio_in => extio_in,
extio_out => extio_out,
uart_read => uart_read,
uart_write => uart_write
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external SRAM)
-- very simple SRAM memory controller using both IS61LV25616AL chips.
-- these SRAMs have 16-bit words, so we use both chips and access each using low and
-- high banks. using this arrangement, we have byte addressable 32-bit words.
-- the address bus is controlled directly by the CPU.
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
ram_address <= address(31 downto 2);
ram_we_n <= we_n_reg;
ram_control:
process(clock, ram_enable_n, data_we, data_write)
begin
if ram_enable_n = '0' then --SRAM
ram_ce1_n <= '0';
ram_ce2_n <= '0';
if data_we = "0000" then -- read
ram_data <= (others => 'Z');
ram_ub1_n <= '0';
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
we_n_next <= '1';
ram_oe_n <= '0';
else -- write
if clock = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not data_we(3);
ram_lb1_n <= not data_we(2);
ram_ub2_n <= not data_we(1);
ram_lb2_n <= not data_we(0);
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
ram_data <= (others => 'Z');
ram_ce1_n <= '1';
ram_ub1_n <= '1';
ram_lb1_n <= '1';
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process;
end top_level;
| gpl-2.0 | 58407243f747b48e6e9f752b816d86b3 | 0.613871 | 2.551926 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_core8.vhd | 1 | 5,162 | -- $Id: rlink_core8.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_core8 - syn
-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
--
-- Dependencies: rlink_core
-- comlib/byte2cdata
-- comlib/cdata2byte
-- rlink_mon_sb [sim only, for 8bit level]
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-05 596 14.7 131013 xc6slx16-2 352 492 24 176 s 7.0 ver 4.0
-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-11 666 4.1 add ESCXON,ESCFILL in signals, for cdata2byte
-- 2014-10-12 596 4.0 now rlink v4 iface, 4 bit STAT
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core8 is -- rlink core with 8bit interface
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end entity rlink_core8;
architecture syn of rlink_core8 is
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RLB_BUSY_L : slbit := '0';
signal RLB_DO_L : slv8 := (others=>'0');
signal RLB_VAL_L : slbit := '0';
begin
RL : rlink_core
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
-- RLB -> RL converter (DI handling) -------------
B2CD : byte2cdata -- byte stream -> 9bit comma,data
port map (
CLK => CLK,
RESET => RESET,
DI => RLB_DI,
ENA => RLB_ENA,
ERR => '0',
BUSY => RLB_BUSY_L,
DO => RL_DI,
VAL => RL_ENA,
HOLD => RL_BUSY
);
-- RL -> RLB converter (DO handling) -------------
CD2B : cdata2byte -- 9bit comma,data -> byte stream
port map (
CLK => CLK,
RESET => RESET,
ESCXON => ESCXON,
ESCFILL => ESCFILL,
DI => RL_DO,
ENA => RL_VAL,
BUSY => RL_HOLD,
DO => RLB_DO_L,
VAL => RLB_VAL_L,
HOLD => RLB_HOLD
);
RLB_BUSY <= RLB_BUSY_L;
RLB_DO <= RLB_DO_L;
RLB_VAL <= RLB_VAL_L;
-- synthesis translate_off
RLBMON: if ENAPIN_RLBMON >= 0 generate
MON : rlink_mon_sb
generic map (
DWIDTH => RLB_DI'length,
ENAPIN => ENAPIN_RLBMON)
port map (
CLK => CLK,
RL_DI => RLB_DI,
RL_ENA => RLB_ENA,
RL_BUSY => RLB_BUSY_L,
RL_DO => RLB_DO_L,
RL_VAL => RLB_VAL_L,
RL_HOLD => RLB_HOLD
);
end generate RLBMON;
-- synthesis translate_on
end syn;
| gpl-3.0 | 374932919114407dea2f0d4c744a97b3 | 0.496319 | 3.376063 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_mem70.vhd | 1 | 5,930 | -- $Id: pdp11_mem70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mem70 - syn
-- Description: pdp11: 11/70 memory system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mem70;
architecture syn of pdp11_mem70 is
constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
subtype cntl_ibf_frep is integer range 5 downto 4;
subtype cntl_ibf_fmiss is integer range 3 downto 2;
constant cntl_ibf_disutrap : integer := 1;
constant cntl_ibf_distrap : integer := 0;
type regs_type is record -- state registers
ibsel_cr : slbit; -- ibus select cntl
ibsel_hm : slbit; -- ibus select hitmiss
ibsel_ls : slbit; -- ibus select losize
ibsel_nn : slbit; -- ibus select others
hm_data : slv6; -- hit/miss: data
cr_frep : slv2; -- cntl: force replacement bits
cr_fmiss : slv2; -- cntl: force miss bits
cr_disutrap: slbit; -- cntl: disable unibus trap
cr_distrap: slbit; -- cntl: disable traps
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- ibsel_*
(others=>'0'), -- hm_data
"00","00", -- cr_frep,_fmiss
'0','0' -- dis(u)trap
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_cr := '0';
n.ibsel_hm := '0';
n.ibsel_ls := '0';
n.ibsel_nn := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
n.ibsel_cr := '1';
end if;
if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
n.ibsel_hm := '1';
end if;
if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
n.ibsel_ls := '1';
end if;
if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
IB_MREQ.addr=ibaddr_maint(12 downto 1) or
IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
n.ibsel_nn := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_cr = '1' then
idout(cntl_ibf_frep) := r.cr_frep;
idout(cntl_ibf_fmiss) := r.cr_fmiss;
idout(cntl_ibf_disutrap) := r.cr_disutrap;
idout(cntl_ibf_distrap) := r.cr_distrap;
end if;
if r.ibsel_hm = '1' then
idout(r.hm_data'range) := r.hm_data;
end if;
if r.ibsel_ls = '1' then
idout := slv(to_unsigned(sys_conf_mem_losize,16));
end if;
if r.ibsel_cr='1' and ibw0='1' then
n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
end if;
if HM_ENA = '1' then
n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
r.ibsel_ls or r.ibsel_nn) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
end syn;
| gpl-3.0 | c0a0a1f8eb9258f723c5401f49d6d23c | 0.535245 | 3.254665 | false | false | false | false |
wfjm/w11 | rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd | 1 | 4,576 | -- $Id: tbd_nx_cram_memctl_as.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_nx_cram_memctl_as - syn
-- Description: Wrapper for nx_cram_memctl_as to avoid records & generics.
-- It has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: nx_cram_memctl_as
-- To test: nx_cram_memctl_as
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4
-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1
--
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-27 802 1.2.1 use cram_read0delay ect
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl
-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR
-- 2010-05-30 297 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity tbd_nx_cram_memctl_as is -- CRAM controller (async mode) [tb wrap]
-- generic: READ0=2;READ1=2;WRITE=3
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tbd_nx_cram_memctl_as;
architecture syn of tbd_nx_cram_memctl_as is
signal ADDR_X : slv22 := (others=>'0');
begin
-- Note: This is a hack to ensure that the IOB flops are on the O_MEM_ADDR
-- pins. Without par might choose to use IFF's on ADDR, causing varying
-- routing delays to O_MEM_ADDR. Didn't find a better way, setting
-- iob "false" attributes in ADDR didn't help.
-- This logic doesn't hurt, and prevents that IFFs for ADDR compete with
-- OFF's for O_MEM_ADDR.
ADDR_X <= ADDR when RESET='0' else (others=>'0');
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => cram_read0delay(50), -- assume 50 MHz system clock. Must be
READ1DELAY => cram_read1delay(50), -- modified when clock_period is
WRITEDELAY => cram_writedelay(50)) -- changed in tb_nx_cram_memctl !!
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR_X,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | 64e67945c5d795fdc57c0afe7c89678e | 0.515079 | 3.28972 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_uart_rxtx_ab.vhd | 1 | 3,940 | -- $Id: serport_uart_rxtx_ab.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx_ab - syn
-- Description: serial port UART - transmitter-receiver + autobauder
--
-- Dependencies: serport_uart_autobaud
-- serport_uart_rxtx
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-04-12 666 14.7 131013 xc6slx16-2 100 142 0 48 s 6.2
-- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-01 641 1.2 add CLKDIV_F for autobaud;
-- 2011-10-22 417 1.1.1 now numeric_std clean
-- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
ABDONE : out slbit; -- autobaud resync done
ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting
ABCLKDIV_F : out slv3 -- autobaud clock divider fraction
);
end serport_uart_rxtx_ab;
architecture syn of serport_uart_rxtx_ab is
signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH));
signal CLKDIV_F : slv3 := (others=>'0');
signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
signal UART_RESET : slbit := '0';
begin
AB : serport_uart_autobaud
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => CLKDIV,
CLKDIV_F => CLKDIV_F,
ACT => ABACT_L,
DONE => ABDONE
);
UART_RESET <= ABACT_L or RESET;
ABACT <= ABACT_L;
ABCLKDIV <= CLKDIV;
ABCLKDIV_F <= CLKDIV_F;
RXTX : serport_uart_rxtx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
| gpl-3.0 | efb94cec0734f4813f0c29071ecf921c | 0.536548 | 3.858962 | false | false | false | false |
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