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wfjm/w11 | rtl/bplib/s3board/tb/tb_s3board_fusp.vhd | 1 | 6,929 | -- $Id: tb_s3board_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_fusp - sim
-- Description: Test bench for s3board (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_fusp_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_fusp is
end tb_s3board_fusp;
architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_fusp_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 8d20a18a3a2bc1b846ce176295e6d0e3 | 0.525328 | 3.059161 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/nexys4d/tb/sys_conf_sim.vhd | 1 | 1,912 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_nexys4d (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 6de860ef692f2138740ba54ab3e8622f | 0.608787 | 3.698259 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_UART_Device.vhdl | 1 | 5,929 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze UART Adapter
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_UART_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
UART_TX_put : out STD_LOGIC;
UART_TX_Data : out T_SLV_8;
UART_TX_Empty_n : in STD_LOGIC;
UART_TX_HalfFull : in STD_LOGIC;
UART_TX_Full : in STD_LOGIC;
UART_RX_got : out STD_LOGIC;
UART_RX_Data : in T_SLV_8;
UART_RX_Empty_n : in STD_LOGIC;
UART_RX_HalfFull : in STD_LOGIC;
UART_RX_Full : in STD_LOGIC
);
end entity;
architecture rtl of pb_UART_Device is
CONSTANT REG_WO_INT_ENABLE : UNSIGNED(0 downto 0) := "0";
CONSTANT REG_RO_STATUS : UNSIGNED(0 downto 0) := "0";
CONSTANT REG_RW_FIFO : UNSIGNED(0 downto 0) := "1";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant REG_INT_ENABLE_DEFAULT : T_SLV_8 := x"88"; -- interrupt on TX/RX_DataLoss
signal Reg_Int_Enable : T_SLV_8 := REG_INT_ENABLE_DEFAULT;
signal Reg_Status : T_SLV_8 := (others => '0');
signal UART_TX_put_i : STD_LOGIC;
signal UART_TX_DataLoss : STD_LOGIC;
signal UART_RX_DataLoss : STD_LOGIC;
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_Int_Enable <= REG_INT_ENABLE_DEFAULT;
Reg_Status <= (others => '0');
else
if (AdrDec_we = '1') THEN
case unsigned(AdrDec_WriteAddress(0 downto 0)) is
when REG_WO_INT_ENABLE => Reg_Int_Enable <= AdrDec_Data;
when others => null;
end case;
end if;
Reg_Status <= UART_TX_DataLoss & UART_TX_Full & UART_TX_HalfFull & UART_TX_Empty_n &
UART_RX_DataLoss & UART_RX_Full & UART_RX_HalfFull & UART_RX_Empty_n;
end if;
end if;
end process;
UART_TX_put_i <= to_sl(unsigned(AdrDec_WriteAddress(0 downto 0)) = REG_RW_FIFO) and AdrDec_we;
UART_TX_DataLoss <= UART_TX_Full and UART_TX_put_i;
UART_RX_DataLoss <= UART_RX_Full and '1'; -- TODO:
UART_TX_put <= UART_TX_put_i;
UART_TX_Data <= AdrDec_Data;
process(AdrDec_re, AdrDec_ReadAddress, Reg_Status, UART_RX_Data)
begin
DataOut <= Reg_Status;
UART_RX_got <= '0';
case unsigned(AdrDec_ReadAddress(0 downto 0)) is
when REG_RO_STATUS =>
DataOut <= Reg_Status;
when REG_RW_FIFO =>
DataOut <= UART_RX_Data;
UART_RX_got <= AdrDec_re;
when others =>
null;
end case;
end process;
Interrupt <= slv_or(Reg_Int_Enable and Reg_Status);
Message <= Reg_Status;
end;
| apache-2.0 | 71ea303a53fe161853ba4ad34f8f97d2 | 0.530275 | 3.120526 | false | false | false | false |
sjohann81/hf-risc | mips/platform/virtex4_ml403/virtex4ml403.vhd | 1 | 4,646 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '0') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | ac8ed55fd8eca6c5ab52ea5da00a3edb | 0.626345 | 2.602801 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/rams/ram.vhd | 2 | 1,229 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end bram;
architecture memory of bram is
type ram is array(2 ** address_width -1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
begin
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
| gpl-2.0 | 110d79028a1fe75812379f4d03d0bb79 | 0.639544 | 2.737194 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/arty/tb/sys_conf_sim.vhd | 1 | 1,910 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 4bf9962b01efa5cf449306d3ae194508 | 0.608377 | 3.708738 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/tst_sram.vhd | 1 | 40,498 | -- $Id: tst_sram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_sram - syn
-- Description: test of sram (s3,c7) and cram (n2,n3,n4) and its controller
--
-- Dependencies: vlib/memlib/ram_1swsr_wfirst_gen
-- vlib/memlib/ram_2swsr_wfirst_gen
--
-- Test bench: arty/tb/tb_tst_sram_arty (with ddr3 via mig)
-- nexys4d/tb/tb_tst_mig_n4d (with ddr2 via mig)
-- cmoda7/tb/tb_tst_sram_c7 (with sram)
-- nexys4/tb/tb_tst_sram_n4 (with cram)
-- nexys3/tb/tb_tst_sram_n3 (with cram)
-- nexys2/tb/tb_tst_sram_n2 (with cram)
-- s3board/tb/tb_tst_sram_s3 (with sram)
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-02 1116 1.6.1 define init_rbf_*
-- 2017-06-25 917 1.6 allow AWIDTH=17; sstat_rbf_awidth instead of _wide
-- 2016-07-10 785 1.5.1 std SWI layout: now (7:4) disp select, SWI(1)->XON
-- 2016-07-09 784 1.5 AWIDTH generic, add 22bit support for cram
-- 2016-05-22 767 1.4.1 don't init N_REGS (vivado fix for fsm inference)
-- 2014-09-05 591 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-11-21 432 1.2.0 now numeric_std clean
-- 2010-12-31 352 1.2 port to rbv3
-- 2010-10-23 335 1.1.3 rename RRI_LAM->RB_LAM;
-- 2010-06-18 306 1.1.2 rename rbus data fields to _rbf_
-- 2010-06-03 299 1.1.1 correct rbus init logic (use we, RB_ADDR)
-- 2010-05-24 294 1.1 Correct _al->_dl logic, remove BUSY=0 condition
-- 2010-05-21 292 1.0.1 move memory controller to top level entity
-- 2010-05-16 291 1.0 Initial version (extracted from sys_tst_sram)
-- now RB_SRES only driven when selected
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbb00000 15:00 mdih r/w/- Memory data input register, high word
-- bbb00001 15:00 mdil r/w/- Memory data input register, low word
-- bbb00010 15:00 mdoh r/-/- Memory data output register, high word
-- bbb00011 15:00 mdol r/-/- Memory data output register, low word
-- bbb00100 01:00 maddrh r/w/- Memory address register, high word
-- bbb00101 15:00 maddrl r/w/- Memory address register, low word
--
-- bbb00110 mcmd -/-/f Immediate memory command register
-- 14 ld -/-/f if 1 load addrh field to maddr high word
-- 13 inc -/-/f if 1 post-increment maddr
-- 12 we -/-/f if 1 do write cycle, otherwise read
-- 11:08 be -/-/f byte enables (used for writes)
-- *:00 addrh -/-/f maddr high word (loaded of ld=1)
--
-- bbb00111 15:00 mblk r/w/- Memory block read/write
-- pairs of r/w to access memory directly
-- read access logic:
-- than mdo is read from mem(maddr)
-- 1st read gives mdoh, 2nd loads mdol
-- maddr is post-incrememted
-- write access logic:
-- 1st write loads mdih, 2nd loads mdil
-- than mdi is written to mem(maddr)
-- maddr is post-incrememted
--
-- bbb01000 10:00 slim r/w/- Sequencer range register
-- bbb01001 10:00 saddr r/w/- Sequencer address register
-- bbb01010 15:00 sblk r/w/- Sequencer memory block read/write
-- groups of 4 r/w to access sequencer mem
-- access order: 11,10,01,00
-- bbb01011 15:00 sblkc r/w/- Like sblk, access to command part
-- groups of 2 r/w to access sequencer mem
-- access order: 11,10
-- bbb01100 15:00 sblkd r/w/- Like sblk, access to data part
-- groups of 2 r/w to access sequencer mem
-- access order: 01,00
-- bbb01101 sstat r/w/- Sequencer status register
-- 15 wide r/-/- 1 if AWIDTH=22
-- 09 wswap r/w/- enable swap of upper 4 addr bits
-- 08 wloop r/w/- enable wide (22bit) loop (default 18bit)
-- 07 loop r/w/- loop till maddr=<all-ones>
-- 06 xord r/w/- xor memory address with maddr
-- 05 xora r/w/- xor memory data with mdi
-- 04 veri r/w/- verify memory reads
-- 01 fail r/-/- 1 if sequencer stopped after failure
-- 00 run r/-/- 1 if sequencer running
-- bbb01110 sstart -/-/f Start sequencer (sstat.run=1, .fail=0)
-- bbb01111 sstop -/-/f Stop sequencer (sstat.run=0)
-- bbb10000 10:00 seaddr r/-/- Current sequencer address
-- bbb10001 15:00 sedath r/-/- Current sequencer data (high word)
-- bbb10010 15:00 sedatl r/-/- Current sequencer data ( low word)
--
-- Sequencer memory format
-- 64 bit wide, upper 32 bits sequencer command, lower 32 bits data
-- Item Bits Name Function
-- scmd 31:28 wait number of wait cycles
-- 24 we write enable
-- 23:20 be byte enables
-- 17:00 addr address
--
------------------------------------------------------------------------------
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
-- BTN(3:0): unused
--
-- SWI(7:4): determine data displayed
-- SWI 3210
-- 0000 mdil
-- 0001 mdih
-- 0010 mem_do.l
-- 0011 mem_do.h
-- 0100 maddr.l
-- 0101 maddr.h
-- 0110 slim
-- 0111 saddr
-- 1000 sstat
-- 1001 seaddr
-- 1010 sedatl
-- 1011 sedath
-- 1100 smem_b0 data.l
-- 1101 smem_b1 data.h
-- 1110 smem_b2 cmd.l
-- 1111 smem_b3 cmd.h
-- SWI(3:2): unused
-- SWI(1): 1 enable XON
-- SWI(0): RS232 port select (on some boards)
--
-- LED(7): or of all unused BTNs and SWI
-- LED(6): R_REGS.sloop
-- LED(5): R_REGS.sveri
-- LED(4): R_REGS.sfail
-- LED(3): R_REGS.srun
-- LED(2): MEM_ACT_W
-- LED(1): MEM_ACT_R
-- LED(0): MEM_BUSY
--
-- DSP: data as selected by SWI(7..4)
--
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rutil.all;
use work.memlib.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity tst_sram is -- tester for sram memctl
generic (
RB_ADDR : slv16 := slv(to_unsigned(2#0000000000000000#,16));
AWIDTH : natural := 18);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv4; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
SWI : in slv8; -- hio switches
BTN : in slv4; -- hio buttons
LED : out slv8; -- hio leds
DSP_DAT : out slv16; -- hio display data
MEM_RESET : out slbit; -- mem: reset
MEM_REQ : out slbit; -- mem: request
MEM_WE : out slbit; -- mem: write enable
MEM_BUSY : in slbit; -- mem: controller busy
MEM_ACK_R : in slbit; -- mem: acknowledge read
MEM_ACK_W : in slbit; -- mem: acknowledge write
MEM_ACT_R : in slbit; -- mem: signal active read
MEM_ACT_W : in slbit; -- mem: signal active write
MEM_ADDR : out slv(AWIDTH-1 downto 0); -- mem: address
MEM_BE : out slv4; -- mem: byte enable
MEM_DI : out slv32; -- mem: data in (memory view)
MEM_DO : in slv32 -- mem: data out (memory view)
);
end tst_sram;
architecture syn of tst_sram is
constant IWIDTH : natural := imin(18, AWIDTH);
signal SEQ_RESET : slbit := '0';
signal SMEM_CEA : slbit := '0';
signal SMEM_B3_WE : slbit := '0';
signal SMEM_B2_WE : slbit := '0';
signal SMEM_B1_WE : slbit := '0';
signal SMEM_B0_WE : slbit := '0';
signal SMEM_WEB : slbit := '0';
signal SMEM_CMD : slv32 := (others=>'0');
signal SMEM_DATA : slv32 := (others=>'0');
type state_type is (
s_idle, -- s_idle: wait for input
s_mcmd, -- s_mcmd: immediate memory r/w
s_mcmd_read, -- s_mcmd_read: wait for read completion
s_mblk_wr1, -- s_mblk_wr1: mem blk write, get datal
s_mblk_wr2, -- s_mblk_wr2: mem blk write, do write
s_mblk_rd1, -- s_mblk_rd1: mem blk read, wait, datah
s_mblk_rd2, -- s_mblk_rd2: mem blk read, datal
s_sblk_rd, -- s_sblk_rd: read smem for sblk
s_sblk, -- s_sblk: process sblk transfers
s_sstart, -- s_sstart: sequencer startup
s_sload, -- s_sload: sequencer load data
s_srun, -- s_srun: run sequencer commands
s_sloop -- s_sloop: stop or loop
);
type regs_type is record
state : state_type; -- state
rbsel : slbit; -- rbus select
maddr : slv(AWIDTH-1 downto 0); -- memory address
mdi : slv32; -- memory data input
saddr : slv11; -- sequencer address
slim : slv11; -- sequencer range
sbank : slv2; -- current sblk bank
srun : slbit; -- seq: run flag
slast : slbit; -- seq: last cmd flag
sfail : slbit; -- seq: fail flag
swcnt : slv4; -- seq: wait counter
scaddr : slv11; -- seq: current address
sveri : slbit; -- seq: verify mode (check data)
sxora : slbit; -- seq: xor maddr into address
sxord : slbit; -- seq: xor mdi into data
sloop : slbit; -- seq: loop over maddr
swloop : slbit; -- seq: enable wide loop (22bit)
swswap : slbit; -- seq: enable top 4 bit addr swap
mrp_val_al : slbit; -- mrp: valid flag, addr latch stage
mrp_adr_al : slv11; -- mrp: seq address, addr latch stage
mrp_dat_al : slv32; -- mrp: exp mem data, addr latch stage
mrp_val_dl : slbit; -- mrp: valid flag, data latch stage
mrp_adr_dl : slv11; -- mrp: seq address, data latch stage
mrp_dat_dl : slv32; -- mrp: exp mem data, data latch stage
se_addr : slv11; -- seq err: seq address
se_data : slv32; -- seq err: memory data
dispval : slv16; -- data for display
end record regs_type;
constant maddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
maddrzero, -- maddr
(others=>'0'), -- mdi
(others=>'0'), -- saddr
(others=>'0'), -- slim
(others=>'0'), -- sbank
'0','0','0', -- srun, slast, sfail
(others=>'0'), -- swcnt
(others=>'0'), -- scaddr
'0','0','0', -- sveri,sxora,sxord
'0','0','0', -- sloop,swloop,swswap
'0', -- mrp_val_al
(others=>'0'), -- mrp_adr_al
(others=>'0'), -- mrp_dat_al
'0', -- mrp_val_dl
(others=>'0'), -- mrp_adr_dl
(others=>'0'), -- mrp_dat_dl
(others=>'0'), -- se_addr
(others=>'0'), -- se_data
(others=>'0') -- dispval
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
subtype maddr_f_wh is integer range AWIDTH-1 downto 16;
subtype maddr_f_wl is integer range 15 downto 0;
subtype maddr_f_scmd is integer range IWIDTH-1 downto 0;
subtype maddr_f_top4 is integer range AWIDTH-1 downto AWIDTH-1-3;
subtype maddr_f_mid4 is integer range AWIDTH-1-4 downto AWIDTH-1-7;
subtype maddr_f_bot is integer range AWIDTH-1-8 downto 0;
subtype df_word0 is integer range 15 downto 0;
subtype df_word1 is integer range 31 downto 16;
constant init_rbf_seq: integer := 0;
constant init_rbf_mem: integer := 1;
subtype maddrh_rbf_h is integer range AWIDTH-1-16 downto 0;
constant mcmd_rbf_ld: integer := 14;
constant mcmd_rbf_inc: integer := 13;
constant mcmd_rbf_we: integer := 12;
subtype mcmd_rbf_be is integer range 11 downto 8;
subtype mcmd_rbf_addrh is integer range AWIDTH-1-16 downto 0;
subtype sstat_rbf_awidth is integer range 15 downto 13;
constant sstat_rbf_wswap: integer := 9;
constant sstat_rbf_wloop: integer := 8;
constant sstat_rbf_loop: integer := 7;
constant sstat_rbf_xord: integer := 6;
constant sstat_rbf_xora: integer := 5;
constant sstat_rbf_veri: integer := 4;
constant sstat_rbf_fail: integer := 1;
constant sstat_rbf_run: integer := 0;
subtype scmd_rbf_wait is integer range 31 downto 28;
constant scmd_rbf_we: integer := 24;
subtype scmd_rbf_be is integer range 23 downto 20;
subtype scmd_rbf_addr is integer range IWIDTH-1 downto 0;
constant rbaddr_mdih: slv5 := "00000"; -- 0 -/r/w
constant rbaddr_mdil: slv5 := "00001"; -- 1 -/r/w
constant rbaddr_mdoh: slv5 := "00010"; -- 2 -/r/-
constant rbaddr_mdol: slv5 := "00011"; -- 3 -/r/-
constant rbaddr_maddrh: slv5 := "00100"; -- 4 -/r/w
constant rbaddr_maddrl: slv5 := "00101"; -- 5 -/r/w
constant rbaddr_mcmd: slv5 := "00110"; -- 6 -/-/w
constant rbaddr_mblk: slv5 := "00111"; -- 7 -/r/w
constant rbaddr_slim: slv5 := "01000"; -- 8 -/r/w
constant rbaddr_saddr: slv5 := "01001"; -- 9 -/r/w
constant rbaddr_sblk: slv5 := "01010"; -- 10 -/r/w
constant rbaddr_sblkc: slv5 := "01011"; -- 11 -/r/w
constant rbaddr_sblkd: slv5 := "01100"; -- 12 -/r/w
constant rbaddr_sstat: slv5 := "01101"; -- 13 -/r/w
constant rbaddr_sstart: slv5 := "01110"; -- 14 f/-/-
constant rbaddr_sstop: slv5 := "01111"; -- 15 f/-/-
constant rbaddr_seaddr: slv5 := "10000"; -- 16 -/r/-
constant rbaddr_sedath: slv5 := "10001"; -- 17 -/r/-
constant rbaddr_sedatl: slv5 := "10010"; -- 18 -/r/-
constant omux_mdil: slv4 := "0000";
constant omux_mdih: slv4 := "0001";
constant omux_memdol: slv4 := "0010";
constant omux_memdoh: slv4 := "0011";
constant omux_maddrl: slv4 := "0100";
constant omux_maddrh: slv4 := "0101";
constant omux_slim: slv4 := "0110";
constant omux_saddr: slv4 := "0111";
constant omux_sstat: slv4 := "1000";
constant omux_seaddr: slv4 := "1001";
constant omux_sedatl: slv4 := "1010";
constant omux_sedath: slv4 := "1011";
constant omux_smemb0: slv4 := "1100";
constant omux_smemb1: slv4 := "1101";
constant omux_smemb2: slv4 := "1110";
constant omux_smemb3: slv4 := "1111";
begin
assert AWIDTH=17 or AWIDTH=18 or AWIDTH=22
report "assert(AWIDTH=17 or AWIDTH=18 or AWIDTH=22): unsupported AWIDTH"
severity failure;
SMEM_B3 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 16)
port map (
CLK => CLK,
EN => SMEM_CEA,
WE => SMEM_B3_WE,
ADDR => R_REGS.saddr,
DI => RB_MREQ.din,
DO => SMEM_CMD(df_word1)
);
SMEM_B2 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 16)
port map (
CLK => CLK,
EN => SMEM_CEA,
WE => SMEM_B2_WE,
ADDR => R_REGS.saddr,
DI => RB_MREQ.din,
DO => SMEM_CMD(df_word0)
);
SMEM_B1 : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 16)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => SMEM_CEA,
ENB => SMEM_WEB,
WEA => SMEM_B1_WE,
WEB => SMEM_WEB,
ADDRA => R_REGS.saddr,
ADDRB => R_REGS.mrp_adr_dl,
DIA => RB_MREQ.din,
DIB => MEM_DO(df_word1),
DOA => SMEM_DATA(df_word1),
DOB => open
);
SMEM_B0 : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 16)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => SMEM_CEA,
ENB => SMEM_WEB,
WEA => SMEM_B0_WE,
WEB => SMEM_WEB,
ADDRA => R_REGS.saddr,
ADDRB => R_REGS.mrp_adr_dl,
DIA => RB_MREQ.din,
DIB => MEM_DO(df_word0),
DOA => SMEM_DATA(df_word0),
DOB => open
);
-- look for init's against the rbus base address
-- generate subsystem resets depending in data bits
proc_reset: process (RESET, RB_MREQ)
begin
SEQ_RESET <= RESET;
MEM_RESET <= RESET;
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then
SEQ_RESET <= RB_MREQ.din(init_rbf_seq);
MEM_RESET <= RB_MREQ.din(init_rbf_mem);
end if;
end process proc_reset;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if SEQ_RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ,
MEM_BUSY, MEM_ACT_R, MEM_ACK_R, MEM_DO,
SMEM_CMD, SMEM_DATA,
SWI)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0'; -- re or we -> rbus request
variable irbact : slbit := '0'; -- sel and (re or we) -> device active
variable imem_reqr : slbit := '0';
variable imem_reqw : slbit := '0';
variable imem_be : slv4 := (others=>'0');
variable imem_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable imem_di : slv32 := (others=>'0');
variable ixor_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable ixor_data : slv32 := (others=>'0');
variable imaddr_chk: slv(AWIDTH-1 downto 0) := (others=>'0');
variable isblk_ok : slbit := '0';
variable isbank : slv2 := "11";
variable maddr_inc : slbit := '0';
variable saddr_inc : slbit := '0';
variable saddr_next : slbit := '0';
variable saddr_last : slbit := '0';
variable swcnt_inc : slbit := '0';
variable ilam : slbit := '0';
variable omux_sel : slv4 := "0000";
variable omux_dat : slv16 := (others=>'0');
constant c_maddr_ones : slv(AWIDTH-1 downto 0) := (others=>'1');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
irbact := '0';
imem_reqr := '0';
imem_reqw := '0';
imem_be := (others=>'1');
imem_addr := r.maddr;
imem_di := r.mdi;
ixor_addr := (others=>'0');
ixor_data := (others=>'0');
isblk_ok := '0';
isbank := "11";
maddr_inc := '0';
saddr_inc := '0';
saddr_next := '0';
saddr_last := '0';
swcnt_inc := '0';
ilam := '0';
omux_sel := omux_mdil;
omux_dat := (others=>'0');
SMEM_CEA <= '0';
SMEM_B3_WE <= '0';
SMEM_B2_WE <= '0';
SMEM_B1_WE <= '0';
SMEM_B0_WE <= '0';
SMEM_WEB <= '0';
if r.saddr = r.slim then
saddr_last := '1';
end if;
if r.mrp_val_dl='1' and MEM_ACK_R='1' then
n.mrp_val_dl := '0';
if r.sveri = '1' then
if r.mrp_dat_dl /= MEM_DO and -- mismatch
r.sfail='0' then -- and no fail set yet
ilam := '1';
n.sfail := '1';
n.srun := '0';
n.se_addr := r.mrp_adr_dl;
n.se_data := MEM_DO;
end if;
else
SMEM_WEB <= '1';
end if;
end if;
if r.mrp_val_al='1' and MEM_ACT_R='1' then
n.mrp_val_al := '0';
n.mrp_val_dl := r.mrp_val_al;
n.mrp_adr_dl := r.mrp_adr_al;
n.mrp_dat_dl := r.mrp_dat_al;
end if;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 5)=RB_ADDR(15 downto 5) then
n.rbsel := '1';
end if;
if r.rbsel='1' and irbena='1' then
irb_ack := '1'; -- ack all (maybe rejected later)
irbact := '1'; -- signal device active
end if;
case r.state is
when s_idle => -- s_idle: wait for rbus requests ----
if r.rbsel = '1' then -- rbus select
case RB_MREQ.addr(4 downto 0) is -- rbus address decoder
when rbaddr_mdih =>
omux_sel := omux_mdih;
if RB_MREQ.we = '1' then
n.mdi(df_word1) := RB_MREQ.din;
end if;
when rbaddr_mdil =>
omux_sel := omux_mdil;
if RB_MREQ.we = '1' then
n.mdi(df_word0) := RB_MREQ.din;
end if;
when rbaddr_mdoh =>
omux_sel := omux_memdoh;
if RB_MREQ.we = '1' then
irb_err := '1'; -- read-only reg
end if;
when rbaddr_mdol =>
omux_sel := omux_memdol;
if RB_MREQ.we = '1' then
irb_err := '1'; -- read-only reg
end if;
when rbaddr_maddrh =>
omux_sel := omux_maddrh;
if RB_MREQ.we = '1' then
n.maddr(maddr_f_wh) := RB_MREQ.din(maddrh_rbf_h);
end if;
when rbaddr_maddrl =>
omux_sel := omux_maddrl;
if RB_MREQ.we = '1' then
n.maddr(maddr_f_wl) := RB_MREQ.din;
end if;
when rbaddr_mcmd =>
if RB_MREQ.we = '1' then
if RB_MREQ.din(mcmd_rbf_ld) = '1' then
n.maddr(maddr_f_wh) := RB_MREQ.din(mcmd_rbf_addrh);
end if;
irb_busy := '1';
n.state := s_mcmd;
end if;
if RB_MREQ.re = '1' then
irb_err := '1'; -- write-only reg
end if;
when rbaddr_mblk =>
imem_addr := r.maddr;
if RB_MREQ.we = '1' then
n.mdi(df_word1) := RB_MREQ.din;
n.state := s_mblk_wr1;
end if;
if RB_MREQ.re = '1' then
irb_busy := '1';
imem_reqr := '1';
if MEM_BUSY = '0' then
maddr_inc := '1';
n.state := s_mblk_rd1;
end if;
end if;
when rbaddr_slim =>
omux_sel := omux_slim;
if RB_MREQ.we = '1' then
n.slim := RB_MREQ.din(r.slim'range);
end if;
when rbaddr_saddr =>
omux_sel := omux_saddr;
if RB_MREQ.we = '1' then
n.saddr := RB_MREQ.din(r.saddr'range);
end if;
when rbaddr_sblk|rbaddr_sblkc|rbaddr_sblkd =>
if RB_MREQ.we = '1' then
n.sbank := "11";
irb_busy := '1';
n.state := s_sblk;
end if;
if RB_MREQ.re = '1' then
n.sbank := "11";
irb_busy := '1';
n.state := s_sblk_rd;
end if;
when rbaddr_sstat =>
omux_sel := omux_sstat;
if RB_MREQ.we = '1' then
n.swswap := RB_MREQ.din(sstat_rbf_wswap);
n.swloop := RB_MREQ.din(sstat_rbf_wloop);
n.sloop := RB_MREQ.din(sstat_rbf_loop);
n.sxord := RB_MREQ.din(sstat_rbf_xord);
n.sxora := RB_MREQ.din(sstat_rbf_xora);
n.sveri := RB_MREQ.din(sstat_rbf_veri);
end if;
when rbaddr_sstart =>
if RB_MREQ.we = '1' then
n.sfail := '0';
n.state := s_sstart;
end if;
if RB_MREQ.re = '1' then
irb_err := '1'; -- write-only reg
end if;
when rbaddr_sstop =>
if RB_MREQ.we = '1' then
n.srun := '0';
end if;
if RB_MREQ.re = '1' then
irb_err := '1'; -- write-only reg
end if;
when rbaddr_seaddr =>
omux_sel := omux_seaddr;
if RB_MREQ.we = '1' then
irb_err := '1'; -- read-only reg
end if;
when rbaddr_sedath =>
omux_sel := omux_sedath;
if RB_MREQ.we = '1' then
irb_err := '1'; -- read-only reg
end if;
when rbaddr_sedatl =>
omux_sel := omux_sedatl;
if RB_MREQ.we = '1' then
irb_err := '1'; -- read-only reg
end if;
when others =>
irb_ack := '0'; -- refuse ack in case of bad addr
end case;
else -- no rbus request (rb_mreq.ack='0')
if r.srun = '1' then
n.state := s_srun;
end if;
end if;
when s_mcmd=> -- s_mcmd: immediate memory r/w ------
if RB_MREQ.din(mcmd_rbf_we) = '1' then -- write command
imem_reqw := '1';
else -- read command
imem_reqr := '1';
end if;
imem_be := RB_MREQ.din(mcmd_rbf_be);
imem_addr := r.maddr;
imem_di := r.mdi;
if irbact = '0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if MEM_BUSY = '0' then -- command accepted ?
if RB_MREQ.din(mcmd_rbf_inc) = '1' then -- maddr inc requested
maddr_inc := '1';
end if;
if RB_MREQ.din(mcmd_rbf_we) = '1' then -- write command
n.state := s_idle;
else -- read command
irb_busy := '1';
n.state := s_mcmd_read;
end if;
else -- otherwise
irb_busy := '1'; -- hold and wait
end if;
end if;
when s_mcmd_read => -- s_mcmd_read: wait for read completion
if irbact = '0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if MEM_ACK_R = '1' then -- read acknowledge seen
n.state := s_idle;
else -- otherwise
irb_busy := '1'; -- hold and wait
end if;
end if;
when s_mblk_wr1 => -- s_mblk_wr1: mem blk write, get datal
if irbact = '1' then -- wait for rbus request
if RB_MREQ.we = '1' and -- write access and cmd ok ?
RB_MREQ.addr(4 downto 0)=rbaddr_mblk then
n.mdi(df_word0) := RB_MREQ.din; -- latch datal
irb_busy := '1';
n.state := s_mblk_wr2; -- next: issue mem write
else
irb_err := '1'; -- signal error
n.state := s_idle; -- return to dispatch
end if;
end if;
when s_mblk_wr2 => -- s_mblk_wr2: mem blk write, do write
n.state := s_mblk_wr2; -- needed to prevent vivado iSTATE
imem_reqw := '1';
imem_be := (others=>'1');
imem_addr := r.maddr;
imem_di := r.mdi;
if irbact = '0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if MEM_BUSY = '0' then -- command accepted ?
maddr_inc := '1';
n.state := s_idle;
else -- otherwise
irb_busy := '1'; -- hold and wait
end if;
end if;
when s_mblk_rd1 => -- s_mblk_rd1: mem blk read, wait, datah
omux_sel := omux_memdoh; -- return mem datah
if irbact = '0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if MEM_ACK_R = '1' then -- read acknowledge seen
n.state := s_mblk_rd2;
else -- otherwise
irb_busy := '1'; -- hold and wait
end if;
end if;
when s_mblk_rd2 => -- s_mblk_rd2: mem blk read, datal ---
omux_sel := omux_memdol; -- return mem datal
if irbact = '1' then -- wait for rbus request
if RB_MREQ.re = '1' and -- read access and cmd ok ?
RB_MREQ.addr(4 downto 0)=rbaddr_mblk then
n.state := s_idle;
else -- write if unexpected cmd addr
irb_err := '1'; -- signal error
n.state := s_idle; -- return to dispatch
end if;
end if;
when s_sblk_rd => -- s_sblk_rd: read smem for sblk -----
if irbact = '0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
irb_busy := '1';
SMEM_CEA <= '1';
n.state := s_sblk;
end if;
when s_sblk => -- s_sblk: process sblk transfers ----
isblk_ok := irbact;
case RB_MREQ.addr(4 downto 0) is
when rbaddr_sblk =>
isbank := r.sbank;
if r.sbank = "00" then
saddr_next := irbact;
end if;
when rbaddr_sblkc =>
isbank := '1' & r.sbank(0);
if r.sbank(0) = '0' then
saddr_next := irbact;
end if;
when rbaddr_sblkd =>
isbank := '0' & r.sbank(0);
if r.sbank(0) = '0' then
saddr_next := irbact;
end if;
when others =>
isblk_ok := '0';
end case;
if isblk_ok='1' and RB_MREQ.we='1' then
SMEM_CEA <= '1';
case isbank is
when "11" => SMEM_B3_WE <= '1';
when "10" => SMEM_B2_WE <= '1';
when "01" => SMEM_B1_WE <= '1';
when "00" => SMEM_B0_WE <= '1';
when others => null;
end case;
end if;
case isbank is
when "11" => omux_sel := omux_smemb3;
when "10" => omux_sel := omux_smemb2;
when "01" => omux_sel := omux_smemb1;
when "00" => omux_sel := omux_smemb0;
when others => null;
end case;
if isblk_ok = '1' then -- in active sblk cycle ?
n.sbank := slv(unsigned(r.sbank) - 1);
if saddr_next = '1' then
saddr_inc := '1';
if RB_MREQ.re = '1' then
n.state := s_sblk_rd;
end if;
end if;
else -- not in active sblk cycle
if irbact = '1' then -- if request than other address
irb_busy := '1'; -- hold interface and
n.state := s_idle; -- back to dispatcher to handle
end if;
end if;
when s_sstart => -- s_sstart: sequencer startup -------
irb_busy := irbact;
n.slast := '0';
n.srun := '1';
n.saddr := (others=>'0');
n.se_addr := (others=>'0');
n.se_data := (others=>'0');
n.state := s_sload;
when s_sload => -- s_sload: sequencer load data ------
irb_busy := irbact;
SMEM_CEA <= '1';
n.scaddr := r.saddr;
saddr_inc := '1';
if saddr_last = '1' then
n.slast := '1';
end if;
n.state := s_srun;
when s_srun => -- s_srun: run sequencer commands ----
irb_busy := irbact;
ixor_addr := r.maddr;
if r.sxora = '0' then
ixor_addr(maddr_f_scmd) := SMEM_CMD(scmd_rbf_addr);
else
ixor_addr(maddr_f_scmd) := SMEM_CMD(scmd_rbf_addr) xor
r.maddr(maddr_f_scmd);
end if;
if r.swswap = '1' then
ixor_addr := ixor_addr(maddr_f_mid4) & ixor_addr(maddr_f_top4) &
ixor_addr(maddr_f_bot);
end if;
if r.sxord = '0' then
ixor_data := SMEM_DATA;
else
ixor_data := SMEM_DATA xor r.mdi;
end if;
imem_addr := ixor_addr;
imem_be := SMEM_CMD(scmd_rbf_be);
imem_di := ixor_data;
if SMEM_CMD(scmd_rbf_wait) /= r.swcnt then
swcnt_inc := '1';
else
if SMEM_CMD(scmd_rbf_we) = '1' then
imem_reqw := '1';
else
imem_reqr := '1';
end if;
if MEM_BUSY = '0' then
if imem_reqr = '1' then
n.mrp_val_al := '1';
n.mrp_adr_al := r.scaddr;
n.mrp_dat_al := ixor_data;
end if;
if r.srun = '0' then
n.state := s_idle;
elsif r.slast = '1' then
n.state := s_sloop;
else
SMEM_CEA <= '1';
n.scaddr := r.saddr;
saddr_inc := '1';
if saddr_last = '1' then
n.slast := '1';
end if;
if irbact = '1' then -- pending rbus request ?
n.state := s_idle; -- than goto dispatcher
end if;
end if;
end if;
end if;
when s_sloop => -- s_sloop: stop or loop -------------
irb_busy := irbact;
imaddr_chk := r.maddr;
if AWIDTH = 22 and r.swloop = '0' then
imaddr_chk(maddr_f_top4) := (others=>'1');
end if;
if MEM_ACT_R='0' and MEM_ACK_R='0' then -- wait here till mem read done
if r.sfail='0' and r.sloop='1' and -- no fail and loop requested ?
imaddr_chk/=c_maddr_ones then -- and not wrapping
maddr_inc := '1'; -- increment maddr
n.state := s_sstart; -- and restart
else -- otherwise
ilam := not r.sfail; -- signal attention unless fail set
n.srun := '0'; -- stop sequencer
n.state := s_idle; -- goto dispatcher
end if;
end if;
when others => null;
end case;
if maddr_inc = '1' then
n.maddr := slv(unsigned(r.maddr) + 1);
end if;
if saddr_inc = '1' then
n.saddr := slv(unsigned(r.saddr) + 1);
end if;
if swcnt_inc = '1' then
n.swcnt := slv(unsigned(r.swcnt) + 1);
else
n.swcnt := (others=>'0');
end if;
if irbact = '0' then -- if no rbus request, use SWI for mux
omux_sel := SWI(7 downto 4);
end if;
case omux_sel is
when omux_mdil =>
omux_dat := r.mdi(df_word0);
when omux_mdih =>
omux_dat := r.mdi(df_word1);
when omux_memdoh =>
omux_dat := MEM_DO(df_word1);
when omux_memdol =>
omux_dat := MEM_DO(df_word0);
when omux_maddrh =>
omux_dat := (others=>'0');
omux_dat(maddrh_rbf_h) := r.maddr(maddr_f_wh);
when omux_maddrl =>
omux_dat := r.maddr(maddr_f_wl);
when omux_slim =>
omux_dat := (others=>'0');
omux_dat(r.slim'range) := r.slim;
when omux_saddr =>
omux_dat := (others=>'0');
omux_dat(r.saddr'range) := r.saddr;
when omux_sstat =>
omux_dat := (others=>'0');
omux_dat(sstat_rbf_awidth):= slv(to_unsigned(AWIDTH-16,3));
omux_dat(sstat_rbf_wswap) := r.swswap;
omux_dat(sstat_rbf_wloop) := r.swloop;
omux_dat(sstat_rbf_loop) := r.sloop;
omux_dat(sstat_rbf_xord) := r.sxord;
omux_dat(sstat_rbf_xora) := r.sxora;
omux_dat(sstat_rbf_veri) := r.sveri;
omux_dat(sstat_rbf_fail) := r.sfail;
omux_dat(sstat_rbf_run) := r.srun;
when omux_seaddr =>
omux_dat := (others=>'0');
omux_dat(r.se_addr'range) := r.se_addr;
when omux_sedath =>
omux_dat := r.se_data(df_word1);
when omux_sedatl =>
omux_dat := r.se_data(df_word0);
when omux_smemb0 =>
omux_dat := SMEM_DATA(df_word0);
when omux_smemb1 =>
omux_dat := SMEM_DATA(df_word1);
when omux_smemb2 =>
omux_dat := SMEM_CMD(df_word0);
when omux_smemb3 =>
omux_dat := SMEM_CMD(df_word1);
when others => null;
end case;
if irbact = '1' then
irb_dout := omux_dat; -- if rbus request, drive dout
else
n.dispval := omux_dat; -- if no rbus request, display mux value
end if;
N_REGS <= n;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
MEM_REQ <= imem_reqr or imem_reqw;
MEM_WE <= imem_reqw;
MEM_BE <= imem_be;
MEM_ADDR <= imem_addr;
MEM_DI <= imem_di;
RB_LAM <= ilam;
end process proc_next;
RB_STAT(3) <= '0';
RB_STAT(2) <= '0';
RB_STAT(1) <= R_REGS.sfail;
RB_STAT(0) <= R_REGS.srun;
DSP_DAT <= R_REGS.dispval;
LED(0) <= MEM_BUSY;
LED(1) <= MEM_ACT_R;
LED(2) <= MEM_ACT_W;
LED(3) <= R_REGS.srun;
LED(4) <= R_REGS.sfail;
LED(5) <= R_REGS.sveri;
LED(6) <= R_REGS.sloop;
LED(7) <= SWI(3) or SWI(2) or SWI(1) or SWI(0) or
BTN(0) or BTN(1) or BTN(2) or BTN(3);
end syn;
| gpl-3.0 | 9d8e3bf1ae2772d5d31a748e0fb395f8 | 0.454566 | 3.570937 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/instruction_memory.vhd | 1 | 1,912 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
immediate_data(0) <= x"0000002c";
immediate_data(1) <= x"00000041";
instruction_data(1) <= "010100111010";
instruction_data(2) <= "010100000111";
instruction_data(3) <= "010100000100";
instruction_data(4) <= "010100111101";
instruction_data(5) <= "000001000000";
instruction_data(6) <= "000001000000";
instruction_data(7) <= "000001000000";
instruction_data(8) <= "010100000000";
instruction_data(9) <= "010100000001";
instruction_data(10) <= "010011000000";
instruction_data(11) <= "010101000000";
instruction_data(12) <= "011001000000";
instruction_data(13) <= "010000000000";
instruction_data(14) <= "010001000000";
instruction_data(15) <= "011010000000";
instruction_data(16) <= "000001000000";
instruction_data(17) <= "010001000000";
instruction_data(18) <= "010000000000";
instruction_data(19) <= "010000000000";
end Behavioral; | mit | 0bdb8bfe4c00c5fce139e0356d2f0a5f | 0.708159 | 3.402135 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd | 1 | 4,885 | -- $Id: sys_tst_snhumanio_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n2 - syn
-- Description: snhumanio tester design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
architecture syn of sys_tst_snhumanio_n2 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | bc5b875d93062b7808701d5938b4d073 | 0.469191 | 3.32087 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdc_signal_s1_as.vhd | 1 | 1,744 | -- $Id: cdc_signal_s1_as.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdc_signal_s1_as - syn
-- Description: clock domain crossing for a signal, 2 stage, asyn input
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-10 774 1.0 Initial version (copy of cdc_signal_s1)
--
------------------------------------------------------------------------------
-- Logic is identical to cdc_signal_s1 !
-- but no scoped xdc with max_delay for input associated
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input
generic (
INIT : slbit := '0'); -- initial state
port (
CLKO : in slbit; -- O|output clock
DI : in slbit; -- I|input data
DO : out slbit -- O|output data
);
end entity cdc_signal_s1_as;
architecture syn of cdc_signal_s1_as is
signal R_DO_S0 : slbit := INIT;
signal R_DO_S1 : slbit := INIT;
attribute ASYNC_REG: string;
attribute ASYNC_REG of R_DO_S0 : signal is "true";
attribute ASYNC_REG of R_DO_S1 : signal is "true";
begin
proc_regs: process (CLKO)
begin
if rising_edge(CLKO) then
R_DO_S0 <= DI; -- synch 0: CLKI->CLKO
R_DO_S1 <= R_DO_S0; -- synch 1: CLKO
end if;
end process proc_regs;
DO <= R_DO_S1;
end syn;
| gpl-3.0 | d657972cee2e4cc626d5078c77141f4e | 0.53555 | 3.40625 | false | false | false | false |
nanomolina/vhdl_examples | sl2/sl2.vhd | 4 | 601 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY sl2 IS
PORT(a: IN std_logic_vector(0 TO 31);
y: OUT std_logic_vector(0 TO 31));
END Sl2;
ARCHITECTURE sl2_est OF sl2 IS
BEGIN
PROCESS(a)
VARIABLE temp: std_logic_vector(0 TO 31);
VARIABLE length: integer := 0;
BEGIN
length := a'LENGTH;
FOR i IN 0 TO length-3 LOOP --los primeros 29 bits
temp(i) := a(i+2);
END LOOP;
temp(length-2) := '0';
temp(length-1) := '0';
y <= temp;
END PROCESS;
END sl2_est;
| gpl-3.0 | 516b46733b413af1d83d2b84141ca6e7 | 0.545757 | 3.231183 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/tbd_rlink_direct.vhd | 1 | 5,105 | -- $Id: tbd_rlink_direct.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_direct - syn
-- Description: Wrapper for rlink_core to avoid records. It has a port
-- interface which will not be modified by xst synthesis
-- (no records, no generic port).
--
-- Dependencies: rlink_core
-- rbus/rb_mon
-- rlink/rlink_mon
--
-- To test: rlink_core
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-11-24 92 8.1.03 I27 xc3s1000-4 143 309 0 166 s 7.64
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 148 320 0 - t 8.34
-- 2007-10-27 92 9.1 J30 xc3s1000-4 148 315 0 - t 8.34
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 302 0 162 s 7.65
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 138 306 0 - s 7.64
--
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-19 594 4.0 now rlink v4.0 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2010-12-25 348 3.0.2 drop RL_FLUSH, add RL_MONI for rlink_core
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CP_FLUSH for rri_core, add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbd_rlink_direct is -- rlink_core only tb design
-- generic: ATOWIDTH=5; ITOWIDTH=6
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_direct;
architecture syn of tbd_rlink_direct is
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
begin
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
UUT : rlink_core
generic map (
BTOWIDTH => 5,
RTAWIDTH => 11,
SYSID => x"76543210",
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
TXRXACT <= '0';
end syn;
| gpl-3.0 | 0c807812cfa423aec01f8e56cb8ec21d | 0.515377 | 3.243329 | false | false | false | false |
nanomolina/vhdl_examples | datapath/dmem.vhd | 2 | 1,090 | -- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in std_logic;
rd: out std_logic_vector(31 downto 0));
end entity;
architecture arq_dmem of dmem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(clk)
variable my_mem: mem;
variable address: std_logic_vector(5 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop --Inicializo mi memoria
my_mem(pos) := std_logic_vector(to_unsigned(pos, 32));
end loop;
if clk'EVENT and clk='1' then
address := a(7 downto 2);
pos_a := to_integer(unsigned(address));
if we='1' then
my_mem(pos_a) := wd;
rd <= wd;
else
rd <= my_mem(pos_a);
end if;
end if;
end process;
end architecture;
| gpl-3.0 | a5b074f0dfb63fc6b096247d0e8c9184 | 0.547706 | 3.395639 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/sys_conf_sim.vhd | 1 | 1,033 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys2_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 2;
constant sys_conf_clkfx_multiply : positive := 3; -- ==> 75 MHz
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | c2c017500f1962efa0fe8b465ffecd3d | 0.575024 | 3.611888 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/spi_sram_ctrl.vhd | 1 | 7,662 | -- file: spi_sram_ctrl.vhd
-- description: Microchip SPI SRAM and EEPROM chip controller
-- date: 03/2018
-- author: Sergio Johann Filho <[email protected]>
--
-- A memory controller compatible with the 23lc1024 and similar SRAM chips.
-- For the 23lc512 chip, only two address bytes should be transmitted, and
-- this controller needs some small changes. The controller assumes that
-- the chip is configured to burst (sequential) data mode by default (which
-- is not true for the 23x256 family of chips.
-- In short address mode (sddr_i = '1'), this controller is also compatible with
-- EEPRROMs, which operate in burst mode by default but use the 16 bit address
-- format. Warning: this controller doesn't use page writes, so EEPROMs may
-- wear out faster than normal. To avoid this, hook the write protection pin.
-- Traffic to / from SRAM / EEPROM is performed in 32 bit words (4 SPI 8 bit words)
-- or multiple (burst) of 32 bit words. For single word access, a half word or
-- byte can be individually accessed. In this case burst mode must be deselected.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_sram_ctrl is
generic (
BURST_SIZE: integer := 4
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(23 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
burst_i: in std_logic; -- data in burst mode
bmode_i: in std_logic; -- byte access
hmode_i: in std_logic; -- half word access
wr_i: in std_logic;
rd_i: in std_logic;
saddr_i: in std_logic; -- 16 bit short address select
wren_i: in std_logic; -- EEPROM write enable latch
data_ack_o: out std_logic; -- signals the last byte of a word
cpu_stall_o: out std_logic;
-- SPI interface
spi_cs_n_o: out std_logic;
spi_clk_o: out std_logic; -- spi bus sck
spi_mosi_o: out std_logic; -- spi bus mosi output
spi_miso_i: in std_logic -- spi bus miso input
);
end spi_sram_ctrl;
architecture spi_sram_ctrl_arch of spi_sram_ctrl is
type states is (start, cmd_wren, cmd_write, cmd_read, addr_phase, data_phase, ready);
signal state: states;
signal data_o_reg: std_logic_vector(31 downto 0);
signal cmd_counter: std_logic;
signal addr_counter: std_logic_vector(1 downto 0);
signal data_counter: std_logic_vector(2**BURST_SIZE downto 0);
signal data_in, data_out: std_logic_vector(7 downto 0);
signal wren, data_valid, bmode, hmode, cpu_stall: std_logic;
begin
spi_core: entity work.spi_master
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => data_in,
data_o => data_out,
wren_i => wren,
data_valid_o => data_valid,
spi_clk_o => spi_clk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
data_o <= data_o_reg;
cpu_stall_o <= cpu_stall or wr_i or rd_i;
process(clk_i, rst_i, data_valid)
begin
if rst_i = '1' then
data_o_reg <= (others => '0');
cmd_counter <= '0';
addr_counter <= (others => '0');
data_counter <= (others => '0');
data_in <= (others => '0');
wren <= '0';
spi_cs_n_o <= '1';
data_ack_o <= '0';
cpu_stall <= '0';
bmode <= '0';
hmode <= '0';
elsif clk_i'event and clk_i = '1' then
case state is
when start =>
cmd_counter <= '0';
if (saddr_i = '0') then
addr_counter <= "00";
else
addr_counter <= "01";
end if;
data_o_reg <= (others => '0');
if (hmode_i = '1' and bmode_i = '0' and burst_i = '0') then
data_counter(1 downto 0) <= "10";
data_counter(2**BURST_SIZE downto 2) <= (others => '0');
bmode <= '0';
hmode <= '1';
elsif (hmode_i = '0' and bmode_i = '1' and burst_i = '0') then
data_counter(1 downto 0) <= "11";
data_counter(2**BURST_SIZE downto 2) <= (others => '0');
bmode <= '1';
hmode <= '0';
else
data_counter <= (others => '0');
bmode <= '0';
hmode <= '0';
end if;
wren <= '0';
spi_cs_n_o <= '0';
data_ack_o <= '0';
cpu_stall <= '1';
when cmd_wren =>
if (data_valid = '0') then
data_in <= x"06";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when cmd_write =>
if (data_valid = '0') then
data_in <= x"02";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when cmd_read =>
if (data_valid = '0') then
data_in <= x"03";
wren <= '1';
else
cmd_counter <= '1';
wren <= '0';
end if;
when addr_phase =>
if (data_valid = '0') then
case addr_counter is
when "00" => data_in <= addr_i(23 downto 16);
when "01" => data_in <= addr_i(15 downto 8);
when "10" => data_in <= addr_i(7 downto 0);
when others => null;
end case;
wren <= '1';
else
if (wren = '1') then
addr_counter <= addr_counter + 1;
end if;
wren <= '0';
end if;
when data_phase =>
if (data_valid = '0') then
case data_counter(1 downto 0) is
when "00" => data_in <= data_i(31 downto 24);
data_o_reg(31 downto 24) <= data_out;
data_ack_o <= '0';
when "01" => data_in <= data_i(23 downto 16);
data_o_reg(23 downto 16) <= data_out;
when "10" => data_in <= data_i(15 downto 8);
data_o_reg(15 downto 8) <= data_out;
when "11" => data_in <= data_i(7 downto 0);
if bmode = '1' then
data_o_reg <= data_out & data_out & data_out & data_out;
elsif hmode = '1' then
data_o_reg <= data_o_reg(15 downto 8) & data_out & data_o_reg(15 downto 8) & data_out;
else
data_o_reg(7 downto 0) <= data_out;
end if;
data_ack_o <= '1';
when others => null;
end case;
wren <= '1';
else
if (wren = '1') then
data_counter <= data_counter + 1;
end if;
wren <= '0';
end if;
when ready =>
spi_cs_n_o <= '1';
cpu_stall <= '0';
when others => null;
end case;
end if;
end process;
process(clk_i, rst_i, state, cmd_counter, addr_counter, data_counter, wr_i, rd_i)
begin
if rst_i = '1' then
state <= ready;
elsif clk_i'event and clk_i = '1' then
case state is
when start =>
if (wr_i = '1') then
if (wren_i = '1') then
state <= cmd_wren;
else
state <= cmd_write;
end if;
elsif (rd_i = '1') then
state <= cmd_read;
else
state <= start;
end if;
when cmd_wren =>
if (cmd_counter = '1') then
state <= ready;
else
state <= cmd_wren;
end if;
when cmd_write =>
if (cmd_counter = '1') then
state <= addr_phase;
else
state <= cmd_write;
end if;
when cmd_read =>
if (cmd_counter = '1') then
state <= addr_phase;
else
state <= cmd_read;
end if;
when addr_phase =>
if (addr_counter < 3) then
state <= addr_phase;
else
state <= data_phase;
end if;
when data_phase =>
if (burst_i = '1') then
if (data_counter < (4 * BURST_SIZE)) then
state <= data_phase;
else
state <= ready;
end if;
else
if (data_counter < 4) then
state <= data_phase;
else
state <= ready;
end if;
end if;
when ready =>
if (wr_i = '1' or rd_i = '1') then
state <= start;
else
state <= ready;
end if;
when others => null;
end case;
end if;
end process;
end spi_sram_ctrl_arch;
| gpl-2.0 | 3b9501220740946496eef4e581cd01d4 | 0.555991 | 2.852569 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vhd | 1 | 4,138 | -- $Id: sys_tst_snhumanio_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n4 - syn
-- Description: snhumanio tester design for nexys4
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-02-02 1108 2018.3 xc7a100t-1 154 187 0 0 69
-- 2019-02-02 1108 2017.2 xc7a100t-1 154 185 0 0 68
-- 2015-01-31 640 2014.4 xc7a100t-1 154 133 0 0 56
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.1 factor out memory
-- 2015-02-01 641 1.0.1 separate I_BTNRST_N
-- 2015-01-31 640 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 4 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n4 is -- top level
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_snhumanio_n4;
architecture syn of sys_tst_snhumanio_n4 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI(7 downto 0),
I_BTN => I_BTN,
O_LED => O_LED(7 downto 0),
O_ANO_N => O_ANO_N(3 downto 0),
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
O_RTS_N <= I_CTS_N;
O_LED(15 downto 8) <= not I_SWI(15 downto 8);
O_ANO_N(7 downto 4) <= (others=>'1');
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 7e71aa4e3b8c44dd818bfd5ff852b8d9 | 0.463751 | 3.377959 | false | false | false | false |
kb3gtn/fpga_edc | tb/mojo_top_tb/mojo_top_tb.vhd | 1 | 5,141 | --------------------------------------------------------
-- FPGA_EDC top level test bench
--
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
component mojo_top is
Port (
clk50m : in STD_LOGIC;
rst_n : in STD_LOGIC;
cclk : in STD_LOGIC; -- spi/fpga programming clock (not used).
led : out STD_LOGIC_VECTOR (7 downto 0); -- board LEDs
-- RS232
serial_tx : out STD_LOGIC; -- pin 7 on SV2
serial_rx : in STD_LOGIC; -- pin 5 on SV2
-- SPI1 signals
spi1_miso : in STD_LOGIC; -- pin 11 on SV2
spi1_mosi : out STD_LOGIC; -- pin 13 on SV2
spi1_sclk : out STD_LOGIC; -- pin 9 on SV2
spi1_cs_n : out STD_LOGIC_VECTOR( 3 downto 0) -- pins 10,12,14,16 on SV2
);
end component mojo_top;
-- signals
signal clk50m : std_logic;
signal rst_n : std_logic;
signal serial_tx : std_logic;
signal serial_rx : std_logic;
signal spi1_miso : std_logic;
signal spi1_mosi : std_logic;
signal spi1_sclk : std_logic;
signal spi1_cs_n : std_logic_vector( 3 downto 0);
constant tx_bit_period : time := 8.680555 us;
signal serial_ce : std_logic; -- clock enable for serial generation procedure
-- procedure to send a byte of data as a rs232 serial stream
procedure serial_send (
constant input_byte : in std_logic_vector(7 downto 0);
signal tx_out : out std_logic
) is
begin
tx_out <= '1'; -- idle state;
wait until rising_edge( serial_ce );
tx_out <= '0'; -- tx start bit.
wait until rising_edge( serial_ce );
tx_out <= input_byte(0);
wait until rising_edge( serial_ce );
tx_out <= input_byte(1);
wait until rising_edge( serial_ce );
tx_out <= input_byte(2);
wait until rising_edge( serial_ce );
tx_out <= input_byte(3);
wait until rising_edge( serial_ce );
tx_out <= input_byte(4);
wait until rising_edge( serial_ce );
tx_out <= input_byte(5);
wait until rising_edge( serial_ce );
tx_out <= input_byte(6);
wait until rising_edge( serial_ce );
tx_out <= input_byte(7);
wait until rising_edge( serial_ce );
tx_out <= '0'; -- stop bit
wait until rising_edge( serial_ce );
tx_out <= '1'; -- back to idle
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
end procedure;
BEGIN
serial_ce_gen : process
begin
serial_ce <= '0';
wait for tx_bit_period/2;
serial_ce <= '1';
wait for tx_bit_period/2;
end process;
-- clock and reset generation
clk50_gen : process
begin
clk50m <= '0';
wait for 10 ns; -- 1/2 50 MHz clock period
clk50m <= '1';
wait for 10 ns; -- 1/2 50 MHz clock period
end process;
-- Component Instantiation
mojo_unit : mojo_top
port map (
clk50m => clk50m,
rst_n => rst_n,
cclk => '1',
serial_tx => serial_tx,
serial_rx => serial_rx,
spi1_miso => spi1_miso,
spi1_mosi => spi1_mosi,
spi1_sclk => spi1_sclk,
spi1_cs_n => spi1_cs_n
);
tb_stim : process
begin
rst_n <= '0'; -- reset active
wait for 80 ns; -- wait for 4 clock cycles
rst_n <= '1'; -- reset de-asserted..
wait for 80 ns; -- wait for 4 clock cycles
-- turn LEDs on ( address 0x03 )
serial_send( x"03", serial_rx );
serial_send( x"55", serial_rx );
serial_send( x"03", serial_rx );
serial_send( x"AA", serial_rx );
-- read back value from led register
serial_send( x"83", serial_rx );
-- send a write to address 2 ( spi1_baud_reg )
-- cmd format (R/!W <7 bits of address> )
serial_send( x"02", serial_rx ); -- address 2 as a write
serial_send( x"19", serial_rx ); -- set spi baud register to 25 -> 500 KHz spi clock
-- now issue a serial read of the buad register (addr 02)
serial_send( x"82", serial_rx );
wait for tx_bit_period*10; -- should get a byte back from the data bus on the uart..
wait for 1 us;
rst_n <= '0'; -- assert reset
wait; -- stop simulation
end process;
END ARCHITECTURE;
| apache-2.0 | f9436d69cbe2e85f04adbc9e081d44c4 | 0.501459 | 3.802515 | false | false | false | false |
jasonpeng/cg3207-proj | CPU.vhd | 1 | 23,660 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CPU is
port (
-- debug
Control : IN std_logic_vector( 5 downto 0);
Operand1 : IN std_logic_vector(31 downto 0);
Operand2 : IN std_logic_vector(31 downto 0);
Result1 : OUT std_logic_vector(31 downto 0);
Result2 : OUT std_logic_vector(31 downto 0);
Debug : OUT std_logic_vector(31 downto 0);
-- cpu
REG1 : out std_logic_vector(31 downto 0);
REG2 : out std_logic_vector(31 downto 0);
REG3 : out std_logic_vector(31 downto 0);
REG4 : out std_logic_vector(31 downto 0);
REG5 : out std_logic_vector(31 downto 0);
REG6 : out std_logic_vector(31 downto 0);
REG7 : out std_logic_vector(31 downto 0);
REG8 : out std_logic_vector(31 downto 0);
ALU_OP : out std_logic_vector(2 downto 0);
Clk, Reset : IN std_logic
);
end CPU;
architecture Behavioral of CPU is
-- IFetch
component Fetch
PORT(
Clk : in std_logic;
Reset : in std_logic;
In_stall_if : in std_logic;
BEQ_PC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PCSrc : IN STD_LOGIC;
Jump : IN STD_LOGIC;
JumpPC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
IF_ID_Flush : out std_logic
);
end component;
-- IF_ID_BUFF
component IF_ID_REG
port(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ID_STALL : in std_logic;
IF_ID_FLUSH : in std_logic;
PC_ADDR_IN : in STD_LOGIC_VECTOR(31 downto 0);
INST_REG_IN : in STD_LOGIC_VECTOR(31 downto 0);
PC_ADDR_OUT : out STD_LOGIC_VECTOR(31 downto 0);
INST_REG_OUT : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
-- IDecode
component Decoder
Port (
Clk : in std_logic;
Reset : in std_logic;
In_PC : in std_logic_vector (31 downto 0);
In_Instr : in STD_LOGIC_VECTOR(31 downto 0);
-- Register Write In
Write_Address : in std_logic_vector(4 downto 0);
WriteData1 : in STD_LOGIC_VECTOR(31 downto 0);
WriteData2 : in STD_LOGIC_VECTOR(31 downto 0);
Mul_or_Div : in std_logic;
RegWrite_in : in std_logic;
-- Data Hazzard
ID_EX_MEM_READ : in std_logic;
ID_EX_REG_RT : in std_logic_vector(4 downto 0);
ID_STALL : out std_logic;
--WB
RegWrite : out std_logic;
MemtoReg : out std_logic;
--MEM
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
--EX
RegDst : OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
ALUSrc : OUT STD_LOGIC;
--JUMP
Jump : OUT STD_LOGIC;
JumpPC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0 );
BranchPC : OUT STD_LOGIC_VECTOR(31 downto 0);
--Decode
EX_MEM_REG_RD : in std_logic_vector(4 downto 0);
Branch_Sign_Extended : out std_logic_vector(31 downto 0);
PCSrc : OUT STD_LOGIC;
Read_data_1 : out std_logic_vector(31 downto 0);
Read_data_2 : out std_logic_vector(31 downto 0);
-- Check Registers
Reg_S1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S4 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S5 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S6 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S7 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S8 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instr_25to21 : out std_logic_vector(4 downto 0);
Instr_20to16 : out std_logic_vector(4 downto 0);
Instr_15to11 : out std_logic_vector(4 downto 0)
);
end component;
-- ID_EX_BUFF
component ID_EX_BUFF
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- IN --
IN_ID_ALUOp : in STD_LOGIC_VECTOR(2 downto 0);
IN_ID_SignExtended : in STD_LOGIC_VECTOR(31 downto 0);
IN_ID_ALUSrc : in STD_LOGIC;
IN_ID_Data1 : in STD_LOGIC_VECTOR(31 downto 0);
IN_ID_Data2 : in STD_LOGIC_VECTOR(31 downto 0);
-- register writeback
IN_ID_RegDst : in STD_LOGIC;
IN_ID_Instr_25_21 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_20_16 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_15_11 : in STD_LOGIC_VECTOR(4 downto 0);
-- states received
IN_ID_MemWrite : in STD_LOGIC;
IN_ID_MemToReg : in STD_LOGIC;
IN_ID_MemRead : in STD_LOGIC;
IN_ID_RegWrite : in STD_LOGIC;
-- OUT --
OUT_EX_ALUOp : out STD_LOGIC_VECTOR(2 downto 0);
OUT_EX_SignExtended : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_ALUSrc : out STD_LOGIC;
OUT_EX_Data1 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_Data2 : out STD_LOGIC_VECTOR(31 downto 0);
-- register writeback
OUT_EX_RegDst : out STD_LOGIC;
OUT_EX_Instr_25_21 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_20_16 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_15_11 : out STD_LOGIC_VECTOR(4 downto 0);
-- states received
OUT_EX_MemWrite : out STD_LOGIC;
OUT_EX_MemToReg : out STD_LOGIC;
OUT_EX_MemRead : out STD_LOGIC;
OUT_EX_RegWrite : out STD_LOGIC
);
end component;
-- IExecute
component Execute
Port (
IN_ID_EX_ALUOp : in STD_LOGIC_VECTOR(2 downto 0);
IN_ID_EX_SignExtended : in STD_LOGIC_VECTOR(31 downto 0);
IN_ID_EX_ALUSrc : in STD_LOGIC;
IN_ID_EX_Data1 : in STD_LOGIC_VECTOR(31 downto 0);
IN_ID_EX_Data2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_ID_EX_MemWrite : in STD_LOGIC;
IN_ID_EX_RegDst : in STD_LOGIC;
IN_ID_EX_Instr_25_21 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_EX_Instr_20_16 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_EX_Instr_15_11 : in STD_LOGIC_VECTOR(4 downto 0);
-- forward unit
IN_EX_MM_RegWrite : in STD_LOGIC;
IN_EX_MM_RD : in STD_LOGIC_VECTOR(4 downto 0);
IN_EX_MM_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_MM_WB_RegWrite : in STD_LOGIC;
IN_MM_WB_RD : in STD_LOGIC_VECTOR(4 downto 0);
IN_WB_Reg_Data : in STD_LOGIC_VECTOR(31 downto 0);
-- alu related
OUT_EX_MM_OVF : out STD_LOGIC;
OUT_EX_MM_Zero : out STD_LOGIC;
OUT_EX_MM_ALU_Result_1 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_Data_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_MULDIV : out STD_LOGIC;
OUT_EX_MM_RegWriteAddr : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
-- EX_MEM_BUFF
component EX_MEM_BUFF
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- states received from EX
-- state registers
IN_EX_MemWrite : in STD_LOGIC;
IN_EX_MemToReg : in STD_LOGIC;
IN_EX_MemRead : in STD_LOGIC;
IN_EX_RegWrite : in STD_LOGIC;
-- alu related
IN_EX_OVF : in STD_LOGIC;
IN_EX_Zero : in STD_LOGIC;
IN_EX_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_MULDIV : in STD_LOGIC;
IN_EX_Data2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
OUT_MEM_MemWrite : out STD_LOGIC;
OUT_MEM_MemToReg : out STD_LOGIC;
OUT_MEM_MemRead : out STD_LOGIC;
OUT_MEM_RegWrite : out STD_LOGIC;
-- alu related
OUT_MEM_OVF : out STD_LOGIC;
OUT_MEM_Zero : out STD_LOGIC;
OUT_MEM_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_MULDIV : out STD_LOGIC;
OUT_MEM_Data2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
-- MEM
component DataMemory
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- state registers
IN_EX_MM_MemWrite : in STD_LOGIC;
IN_EX_MM_MemRead : in STD_LOGIC;
-- alu related
IN_EX_MM_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_MM_Data2 : in STD_LOGIC_VECTOR(31 downto 0);
OUT_MM_WB_Data : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
-- MEM_WB_BUFF
component MEM_WB_BUFF
Port (
Clk, Reset : in std_logic;
IN_MemToReg : in STD_LOGIC;
IN_DataMemory_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_MUL_DIV : in STD_LOGIC;
IN_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
IN_RegWrite : in STD_LOGIC;
OUT_MemToReg : out STD_LOGIC;
OUT_DataMemory_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MUL_DIV : out STD_LOGIC;
OUT_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0);
OUT_RegWrite : out STD_LOGIC
);
end component;
-- WB
component WriteBack
Port (
IN_DataMemory_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_MemToReg : in STD_LOGIC;
IN_Reg_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
OUT_Reg_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0);
OUT_Reg_Data : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
-- Signals
-- IF
signal IFO_Instr : std_logic_vector(31 downto 0);
signal IFO_PC_Addr : std_logic_vector(31 downto 0);
signal IFO_Flush : std_logic;
-- IF/ID
signal DBO_IDI_Instr : std_logic_vector(31 downto 0);
signal DBO_IDI_PC_Addr : std_logic_vector(31 downto 0);
-- ID
signal IDO_BEI_RegWrite : std_logic;
signal IDO_BEI_MemToReg : std_logic;
signal IDO_BEI_MemRead : std_logic;
signal IDO_BEI_MemWrite : std_logic;
signal IDO_BEI_RegDst : std_logic;
signal IDO_BEI_ALU_Op : std_logic_vector(2 downto 0);
signal IDO_BEI_ALU_Src : std_logic;
signal IDO_IFI_Jump : std_logic;
signal IDO_IFI_Jump_Addr : std_logic_vector(31 downto 0);
signal IDO_BEI_Branch_Extend : std_logic_vector(31 downto 0);
signal IDO_BEI_PCSrc : std_logic;
signal IDO_BEI_Data_1 : std_logic_vector (31 downto 0);
signal IDO_BEI_Data_2 : std_logic_vector (31 downto 0);
signal IDO_BEI_Instr_25_21 : std_logic_vector(4 downto 0);
signal IDO_BEI_Instr_20_16 : std_logic_vector(4 downto 0);
signal IDO_BEI_Instr_15_11 : std_logic_vector (4 downto 0);
signal IDO_IFI_STALL : std_logic;
signal ID_REG1 : std_logic_vector(31 downto 0);
signal ID_REG2 : std_logic_vector(31 downto 0);
signal ID_REG3 : std_logic_vector(31 downto 0);
signal ID_REG4 : std_logic_vector(31 downto 0);
signal ID_REG5 : std_logic_vector(31 downto 0);
signal ID_REG6 : std_logic_vector(31 downto 0);
signal ID_REG7 : std_logic_vector(31 downto 0);
signal ID_REG8 : std_logic_vector(31 downto 0);
signal IDO_BranchPC : STD_LOGIC_VECTOR(31 downto 0);
-- ID/EX
signal BEO_EXI_ALU_Op : STD_LOGIC_VECTOR(2 downto 0);
signal BEO_EXI_ALU_Src : STD_LOGIC;
signal BEO_EXI_Data_1 : STD_LOGIC_VECTOR(31 downto 0);
signal BEO_EXI_Data_2 : STD_LOGIC_VECTOR(31 downto 0);
signal BEO_EXI_RegDst : STD_LOGIC;
signal BEO_EXI_Instru_25_21 : STD_LOGIC_VECTOR(4 downto 0);
signal BEO_EXI_Instru_20_16 : STD_LOGIC_VECTOR(4 downto 0);
signal BEO_EXI_Instru_15_11 : STD_LOGIC_VECTOR(4 downto 0);
signal BEO_EXI_Branch_Extend : STD_LOGIC_VECTOR(31 downto 0);
signal BEO_EXI_MemWrite : STD_LOGIC;
signal BEO_EXI_MemToReg : STD_LOGIC;
signal BEO_EXI_MemRead : STD_LOGIC;
signal BEO_BMI_RegWrite : STD_LOGIC;
-- EX
signal EXO_BMI_Overflow : STD_LOGIC;
signal EXO_BMI_Zero : STD_LOGIC;
signal EXO_BMI_Alu_Result : STD_LOGIC_VECTOR(31 downto 0);
signal EXO_BMI_Alu_Result_2 : STD_LOGIC_VECTOR(31 downto 0);
signal EXO_BMI_MULDIV : STD_LOGIC;
signal EXO_BMI_WriteAddr : STD_LOGIC_VECTOR( 4 downto 0);
signal EXO_BMI_Data_2 : STD_LOGIC_VECTOR(31 downto 0);
-- EX/MEM
signal BMO_MMI_MemWrite : STD_LOGIC;
signal BMO_MMI_MemToReg : STD_LOGIC;
signal BMO_MMI_MemRead : STD_LOGIC;
signal BMO_BWI_RegWrite : STD_LOGIC;
signal BMO_MMI_Alu_Result : STD_LOGIC_VECTOR(31 downto 0);
signal BMO_BWI_Alu_Result_2 : STD_LOGIC_VECTOR(31 downto 0);
signal BMO_BWI_MULDIV : STD_LOGIC;
signal BMO_MMI_Data : STD_LOGIC_VECTOR(31 downto 0);
signal BMO_MMI_Reg_WriteAddr : STD_LOGIC_VECTOR(4 downto 0);
-- MEM
signal MMO_BWI_Data : STD_LOGIC_VECTOR(31 downto 0);
-- MEM/WB
signal BWO_WBI_MemToReg : STD_LOGIC;
signal BWO_WBI_Data : STD_LOGIC_VECTOR(31 downto 0);
signal BWO_WBI_ALU_Result : STD_LOGIC_VECTOR(31 downto 0);
signal BWO_WBI_ALU_Result_2 : STD_LOGIC_VECTOR(31 downto 0);
signal BWO_WBI_MUL_DIV : std_logic;
signal BWO_WBI_Reg_WriteAddr : STD_LOGIC_VECTOR(4 downto 0);
signal BWO_IDI_RegWrite : std_logic;
-- WB
signal WBO_IDI_WriteAddr : std_logic_vector( 4 downto 0);
signal WBO_IDI_WriteData : std_logic_vector(31 downto 0);
begin
-- IFetch
IFF: Fetch Port MAP (
Clk => Clk,
Reset => Reset,
In_stall_if => IDO_IFI_STALL,
BEQ_PC => IDO_BranchPC,
PCSrc => IDO_BEI_PCSrc,
Jump => IDO_IFI_Jump,
JumpPC => IDO_IFI_Jump_Addr,
Instruction => IFO_Instr,
PC_out => IFO_PC_Addr,
IF_ID_Flush => IFO_Flush
);
-- IF_ID_BUFF
IFID: IF_ID_REG Port MAP (
Clk => Clk,
Reset => Reset,
ID_STALL => IDO_IFI_STALL,
IF_ID_FLUSH => IFO_Flush,
PC_ADDR_IN => IFO_PC_Addr,
INST_REG_IN => IFO_Instr,
PC_ADDR_OUT => DBO_IDI_PC_Addr,
INST_REG_OUT => DBO_IDI_Instr
);
-- IDecode
ID: Decoder Port MAP (
Clk => Clk,
Reset => Reset,
In_PC => DBO_IDI_PC_Addr,
In_Instr => DBO_IDI_Instr,
Write_Address => WBO_IDI_WriteAddr,
WriteData1 => WBO_IDI_WriteData,
WriteData2 => BWO_WBI_ALU_Result_2,
Mul_or_Div => BWO_WBI_MUL_DIV,
RegWrite_in => BWO_IDI_RegWrite,
-- Data Hazzard Detection
ID_EX_MEM_READ => BEO_EXI_MemRead,
ID_EX_REG_RT => BEO_EXI_Instru_20_16,
ID_STALL => IDO_IFI_STALL,
-- WB
RegWrite => IDO_BEI_RegWrite,
MemtoReg => IDO_BEI_MemToReg,
--MEM
MemRead => IDO_BEI_MemRead,
MemWrite => IDO_BEI_MemWrite,
--EX
RegDst => IDO_BEI_RegDst,
ALUop => IDO_BEI_ALU_Op,
ALUSrc => IDO_BEI_ALU_Src,
--JUMP
Jump => IDO_IFI_Jump,
JumpPC => IDO_IFI_Jump_Addr,
BranchPC => IDO_BranchPC,
EX_MEM_REG_RD => BMO_MMI_Reg_WriteAddr,
Branch_Sign_Extended => IDO_BEI_Branch_Extend,
PCSrc => IDO_BEI_PCSrc,
read_data_1 => IDO_BEI_Data_1,
read_data_2 => IDO_BEI_Data_2,
Reg_S1 => ID_REG1,
Reg_S2 => ID_REG2,
Reg_S3 => ID_REG3,
Reg_S4 => ID_REG4,
Reg_S5 => ID_REG5,
Reg_S6 => ID_REG6,
Reg_S7 => ID_REG7,
Reg_S8 => ID_REG8,
Instr_25to21 => IDO_BEI_Instr_25_21,
Instr_20to16 => IDO_BEI_Instr_20_16,
Instr_15to11 => IDO_BEI_Instr_15_11
);
-- ID_EX_BUFF
IDEX: ID_EX_BUFF Port Map (
CLK => Clk,
RESET => Reset,
-- IN --
IN_ID_ALUOp => IDO_BEI_ALU_Op,
IN_ID_SignExtended => IDO_BEI_Branch_Extend,
IN_ID_ALUSrc => IDO_BEI_ALU_Src,
IN_ID_Data1 => IDO_BEI_Data_1,
IN_ID_Data2 => IDO_BEI_Data_2,
-- register writeback
IN_ID_RegDst => IDO_BEI_RegDst,
IN_ID_Instr_25_21 => IDO_BEI_Instr_25_21,
IN_ID_Instr_20_16 => IDO_BEI_Instr_20_16,
IN_ID_Instr_15_11 => IDO_BEI_Instr_15_11,
-- states received
IN_ID_MemWrite => IDO_BEI_MemWrite,
IN_ID_MemToReg => IDO_BEI_MemToReg,
IN_ID_MemRead => IDO_BEI_MemRead,
IN_ID_RegWrite => IDO_BEI_RegWrite,
-- OUT --
OUT_EX_ALUOp => BEO_EXI_ALU_Op,
OUT_EX_SignExtended => BEO_EXI_Branch_Extend,
OUT_EX_ALUSrc => BEO_EXI_ALU_Src,
OUT_EX_Data1 => BEO_EXI_Data_1,
OUT_EX_Data2 => BEO_EXI_Data_2,
-- register writeback
OUT_EX_RegDst => BEO_EXI_RegDst,
OUT_EX_Instr_25_21 => BEO_EXI_Instru_25_21,
OUT_EX_Instr_20_16 => BEO_EXI_Instru_20_16,
OUT_EX_Instr_15_11 => BEO_EXI_Instru_15_11,
-- states received
OUT_EX_MemWrite => BEO_EXI_MemWrite,
OUT_EX_MemToReg => BEO_EXI_MemToReg,
OUT_EX_MemRead => BEO_EXI_MemRead,
OUT_EX_RegWrite => BEO_BMI_RegWrite
);
-- IExecute
IE: Execute Port Map (
IN_ID_EX_ALUOp => BEO_EXI_ALU_Op,
IN_ID_EX_SignExtended => BEO_EXI_Branch_Extend,
IN_ID_EX_ALUSrc => BEO_EXI_ALU_Src,
IN_ID_EX_Data1 => BEO_EXI_Data_1,
IN_ID_EX_Data2 => BEO_EXI_Data_2,
-- register writeback
IN_ID_EX_MemWrite => BEO_EXI_MemWrite,
IN_ID_EX_RegDst => BEO_EXI_RegDst,
IN_ID_EX_Instr_25_21 => BEO_EXI_Instru_25_21,
IN_ID_EX_Instr_20_16 => BEO_EXI_Instru_20_16,
IN_ID_EX_Instr_15_11 => BEO_EXI_Instru_15_11,
-- forward unit
IN_EX_MM_RegWrite => BMO_BWI_RegWrite,
IN_EX_MM_RD => BMO_MMI_Reg_WriteAddr,
IN_EX_MM_ALU_Result => BMO_MMI_Alu_Result,
IN_MM_WB_RegWrite => BWO_IDI_RegWrite,
IN_MM_WB_RD => BWO_WBI_Reg_WriteAddr,
IN_WB_Reg_Data => WBO_IDI_WriteData,
-- alu related
OUT_EX_MM_OVF => EXO_BMI_Overflow,
OUT_EX_MM_Zero => EXO_BMI_Zero,
OUT_EX_MM_ALU_Result_1 => EXO_BMI_Alu_Result,
OUT_EX_MM_ALU_Result_2 => EXO_BMI_Alu_Result_2,
OUT_EX_MM_Data_2 => EXO_BMI_Data_2,
OUT_EX_MM_MULDIV => EXO_BMI_MULDIV,
OUT_EX_MM_RegWriteAddr => EXO_BMI_WriteAddr
);
-- EX_MEM_BUFF
EXMM: EX_MEM_BUFF Port Map (
CLK => Clk,
RESET => Reset,
-- state registers
IN_EX_MemWrite => BEO_EXI_MemWrite,
IN_EX_MemToReg => BEO_EXI_MemToReg,
IN_EX_MemRead => BEO_EXI_MemRead,
IN_EX_RegWrite => BEO_BMI_RegWrite,
-- alu related
IN_EX_OVF => EXO_BMI_Overflow,
IN_EX_Zero => EXO_BMI_Zero,
IN_EX_ALU_Result => EXO_BMI_Alu_Result,
IN_EX_ALU_Result_2 => EXO_BMI_Alu_Result_2,
IN_EX_MULDIV => EXO_BMI_MULDIV,
IN_EX_Data2 => EXO_BMI_Data_2,
IN_EX_REG_WriteAddr => EXO_BMI_WriteAddr,
OUT_MEM_MemWrite => BMO_MMI_MemWrite,
OUT_MEM_MemToReg => BMO_MMI_MemToReg,
OUT_MEM_MemRead => BMO_MMI_MemRead,
OUT_MEM_RegWrite => BMO_BWI_RegWrite,
-- alu related
OUT_MEM_ALU_Result => BMO_MMI_Alu_Result,
OUT_MEM_ALU_Result_2 => BMO_BWI_Alu_Result_2,
OUT_MEM_MULDIV => BMO_BWI_MULDIV,
OUT_MEM_Data2 => BMO_MMI_Data,
OUT_MEM_REG_WriteAddr => BMO_MMI_Reg_WriteAddr
);
-- MEM
MM: DataMemory Port Map (
CLK => Clk,
RESET => Reset,
IN_EX_MM_MemWrite => BMO_MMI_MemWrite,
IN_EX_MM_MemRead => BMO_MMI_MemRead,
IN_EX_MM_ALU_Result => BMO_MMI_Alu_Result,
IN_EX_MM_Data2 => BMO_MMI_Data,
OUT_MM_WB_Data => MMO_BWI_Data
);
-- MEM_WB_BUFF
MMWB: MEM_WB_BUFF Port Map (
Clk => Clk,
Reset => Reset,
IN_MemToReg => BMO_MMI_MemToReg,
IN_DataMemory_Result => MMO_BWI_Data,
IN_ALU_Result => BMO_MMI_Alu_Result,
IN_ALU_Result_2 => BMO_BWI_Alu_Result_2,
IN_MUL_DIV => BMO_BWI_MULDIV,
IN_REG_WriteAddr => BMO_MMI_Reg_WriteAddr,
IN_RegWrite => BMO_BWI_RegWrite,
OUT_MemToReg => BWO_WBI_MemToReg,
OUT_DataMemory_Result => BWO_WBI_Data,
OUT_ALU_Result => BWO_WBI_Alu_Result,
OUT_ALU_Result_2 => BWO_WBI_ALU_Result_2,
OUT_MUL_DIV => BWO_WBI_MUL_DIV,
OUT_REG_WriteAddr => BWO_WBI_Reg_WriteAddr,
OUT_RegWrite => BWO_IDI_RegWrite
);
-- WB
WB: WriteBack Port Map (
IN_DataMemory_Result => BWO_WBI_Data,
IN_ALU_Result => BWO_WBI_Alu_Result,
IN_MemToReg => BWO_WBI_MemToReg,
IN_Reg_WriteAddr => BWO_WBI_Reg_WriteAddr,
OUT_Reg_WriteAddr => WBO_IDI_WriteAddr,
OUT_Reg_Data => WBO_IDI_WriteData
);
--
result1 <= ID_REG2;
result2 <= ID_REG3;
debug <= ID_REG8;
ALU_op <= IDO_BEI_ALU_Op;
REG1 <= ID_REG1;
REG2 <= ID_REG2;
REG3 <= ID_REG3;
REG4 <= ID_REG4;
REG5 <= ID_REG5;
REG6 <= ID_REG6;
REG7 <= ID_REG7;
REG8 <= ID_REG8;
end Behavioral;
| gpl-2.0 | ce1bd64eda35c535dd9ed4a220d2f18e | 0.519527 | 3.366055 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/ctl_unit.vhd | 1 | 12,549 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ctl_unit is
port(clk : in std_logic;
rst : in std_logic;
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : out std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
immediate_addr : out std_logic_vector(5 downto 0);
ctl_immediate : out std_logic_vector(31 downto 0);
PC_data_out : in std_logic_vector(31 downto 0);
ALU_flags : in std_logic_vector(3 downto 0);
stack_e0 : in std_logic_vector(31 downto 0);
stack_e1 : in std_logic_vector(31 downto 0);
--Control signals
ALU_sel : out std_logic_vector(3 downto 0);
stack_e0_sel : out std_logic_vector(1 downto 0);
stack_e1_sel : out std_logic_vector(1 downto 0);
stack_e2_sel : out std_logic_vector(1 downto 0);
stack_e0_en : out std_logic;
stack_e1_en : out std_logic;
stack_e2_en : out std_logic;
stack_push : out std_logic;
stack_pop : out std_logic;
stack_pop2 : out std_logic;
RS_push : out std_logic;
RS_pop : out std_logic;
mem_we : out std_logic;
PC_load : out std_logic;
PC_inc : out std_logic;
IO_oport_en : out std_logic;
IO_opins_en : out std_logic;
stack_MUX_sel : out std_logic_vector(2 downto 0);
PC_MUX_sel : out std_logic);
end ctl_unit;
architecture Behavioral of ctl_unit is
signal instruction : std_logic_vector(11 downto 0);
signal opcode : std_logic_vector(5 downto 0);
signal ALU_flags_r : std_logic_vector(3 downto 0);
signal ALU_flags_en, ALU_flags_en_r : std_logic;
signal stack_e0_r, stack_e1_r : std_logic_vector(31 downto 0);
begin
--Split the instruction and send addresses out
instruction_addr <= PC_data_out;
immediate_addr <= instruction(5 downto 0);
opcode <= instruction(11 downto 6);
ctl_immediate <= immediate_in;
--Latch in the instruction and other data
latch : process (clk, rst) is
begin
if rst = '1' then
instruction <= (others => '0');
ALU_flags_r <= (others => '0');
stack_e0_r <= (others => '0');
stack_e1_r <= (others => '0');
elsif rising_edge(clk) then
instruction <= instruction_in;
if ALU_flags_en_r = '1' then
ALU_flags_r <= ALU_flags;
end if;
stack_e0_r <= stack_e0;
stack_e1_r <= stack_e1;
end if;
end process;
--Latch the ALU_flags_en signal on falling
latch_fall : process(clk, rst) is
begin
if rst = '1' then
ALU_flags_en_r <= '0';
elsif falling_edge(clk) then
ALU_flags_en_r <= ALU_flags_en;
end if;
end process;
--Decode the instruction
decode : process (opcode, immediate_in, ALU_flags_r, stack_e0_r, stack_e1_r) is
begin
--Default outputs
ALU_sel <= (others => '0');
stack_e0_sel <= (others => '0');
stack_e1_sel <= (others => '0');
stack_e2_sel <= (others => '0');
stack_e0_en <= '0';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
RS_push <= '0';
RS_pop <= '0';
mem_we <= '0';
PC_load <= '0';
PC_inc <= '1';
IO_oport_en <= '0';
IO_opins_en <= '0';
stack_MUX_sel <= (others => '0');
PC_MUX_sel <= '0';
ALU_flags_en <= '0';
if opcode(5 downto 4) = "00" then --Arithmetic/Logic instruction
--Update the flags register
ALU_flags_en <= '1';
--Catch a couple special cases, nop and cp
if opcode(3 downto 0) = "0000" then --nop
--do nothing, leave the defaults as defaults
elsif opcode(3 downto 0) = "0110" then --cp
--send the operands to the ALU to generate condition flags, but don't manipulate the stack
ALU_sel <= opcode(3 downto 0) - 1;
elsif ((opcode(3 downto 0) >= "0001") and (opcode(3 downto 0) <= "0101"))
or (opcode(3 downto 0) = "1011") or (opcode(3 downto 0) = "1100") then --Two-operand instructions
ALU_sel <= opcode(3 downto 0) - 1;
stack_e0_sel <= (others => '0'); --e0 gets data_in
stack_e1_sel <= "01"; --e1 gets e2
stack_e2_sel <= "01"; --e2 gets the top of the storage elements
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1'; --Pop one off the storage elements
stack_pop2 <= '0';
stack_MUX_sel <= "001"; --Data_in gets ALU_result
elsif (opcode(3 downto 0) >= "0111") and (opcode(3 downto 0) <= "1010") then --Single-operand instructions
ALU_sel <= opcode(3 downto 0) - 1;
stack_e0_sel <= (others => '0'); --e0 gets data_in
stack_e1_sel <= (others => '0');
stack_e2_sel <= (others => '0');
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "001"; --Data_in gets ALU_result
end if;
elsif opcode(5 downto 4) = "01" then --Stack manipulation instruction
--This is just going to have to be brute-force, no real decoding here
case opcode(3 downto 0) is
when x"0" => --drop
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"1" => --swap
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"2" => --nrot
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "10";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"3" => --rot
stack_e0_sel <= "10";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
when x"4" => --push
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "000"; --Data_in gets ctl_immediate
when x"5" => --dup
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '0';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
when x"6" => --nrd
stack_e0_sel <= "10";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"7" => --rd
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '0';
stack_e1_en <= '0';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"8" => --nrds
stack_e0_sel <= "00";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '0';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"9" => --rds
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
when x"A" => --over
stack_e0_sel <= "01";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
when others =>
--do nothing
end case;
elsif opcode(5 downto 4) = "10" then --Program control instruction
if opcode(3 downto 0) = "0000" then --JP instruction
--Pop one from the stack
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
--Set up the PC to take the top element of the data stack
PC_MUX_sel <= '0';
PC_load <= '1';
PC_inc <= '0';
elsif opcode(3 downto 0) = "0001" then --BRN instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--Check the selected flag to see if it's true
if ALU_flags_r(conv_integer(unsigned(stack_e1_r))) = '1' then
--Set up the PC to take the top element of the data stack
PC_MUX_sel <= '0';
PC_load <= '1';
PC_inc <= '0';
end if;
elsif opcode(3 downto 0) = "0010" then --RET instruction
--Set up the PC to take the top element of the return stack and pop the return stack
PC_MUX_sel <= '1';
PC_load <= '1';
PC_inc <= '0';
RS_pop <= '1';
elsif opcode(3 downto 0) = "0011" then --PSHPC instruction
RS_push <= '1';
end if;
elsif opcode(5 downto 4) = "11" then --Memory and I/O instruction
if opcode(3 downto 0) = "0000" then --RD_MEM instruction
--Replace the top element of the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "100"; --Data_in gets mem_data_out
elsif opcode(3 downto 0) = "0001" then --WR_MEM instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--enable writing
mem_we <= '1';
elsif opcode(3 downto 0) = "0010" then --RD_PRT instruction
--Push data onto the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '1';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "011"; --Data_in gets IO_iport_data
elsif opcode(3 downto 0) = "0011" then --WR_PRT instruction
--Pop one from the stack
stack_e0_sel <= "01";
stack_e1_sel <= "01";
stack_e2_sel <= "01";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '1';
stack_pop2 <= '0';
--enable writing to the port
IO_oport_en <= '1';
elsif opcode(3 downto 0) = "0100" then --RD_PIN instruction
--Replace the top element of the stack
stack_e0_sel <= "00";
stack_e1_sel <= "00";
stack_e2_sel <= "00";
stack_e0_en <= '1';
stack_e1_en <= '0';
stack_e2_en <= '0';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '0';
stack_MUX_sel <= "010"; --Data_in gets IO_ipins_data
elsif opcode(3 downto 0) = "0101" then --WR_PIN instruction
--Pop two from the stack
stack_e0_sel <= "10";
stack_e1_sel <= "10";
stack_e2_sel <= "11";
stack_e0_en <= '1';
stack_e1_en <= '1';
stack_e2_en <= '1';
stack_push <= '0';
stack_pop <= '0';
stack_pop2 <= '1';
--enable writing to the pins
IO_opins_en <= '1';
end if;
end if;
end process;
end Behavioral;
| mit | 9dc481bdc0438ae37ceabae6c5be11b4 | 0.497171 | 2.814939 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys3/sys_conf.vhd | 1 | 5,561 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.8.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.8 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.7.6 drop iist
-- 2018-09-22 1050 1.7.5 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.7.4 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.7.3 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-03-04 858 1.7.2 enable deuna
-- 2017-01-29 847 1.7.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.7 use cram_*delay functions to determine delays
-- 2016-07-10 786 1.6 memctl with page mode, new read1delay
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth
-- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-06-21 692 1.4.1 use clksys=64 (no closure after rhrp fixes)
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions
-- 2015-02-15 647 1.3 drop bram and minisys options
-- 2014-12-26 621 1.2.2 use 68 MHz, get occasional problems with 72 MHz
-- 2014-12-22 619 1.2.1 add _rbmon_awidth
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore
-- 2013-04-21 509 1.1 add fx2 settings
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 16; -- dcm 64 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 64 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 34dbac7ae3859e2f3cb8c6e10dd65bf0 | 0.597734 | 3.382603 | false | true | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd | 1 | 6,928 | -- $Id: sys_tst_serloop1_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n4 - syn
-- Description: Tester serial link for nexys4 (serport_1clock case)
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-02-02 1108 2018.3 xc7a100t-1 409 454 16 0 190
-- 2019-02-02 1108 2017.2 xc7a100t-1 409 445 16 0 189
-- 2016-03-25 751 2015.4 xc7a100t-1 415 402 32 0 185
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-05 772 1.1.1 use CDUWIDTH=7, 120 MHz clock is natural choice
-- 2016-03-27 753 1.1 clock now from cmt and configurable
-- 2015-02-06 643 1.1 factor out memory
-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n3)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n4 is -- top level
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop1_n4;
architecture syn of sys_tst_serloop1_n4 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKSYS : s7_cmt_sfs -- clock generator -------------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => sys_conf_clkdiv_msecdiv)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 5b83af629ebdfc35b581422d09a57721 | 0.489752 | 3.342016 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd | 1 | 4,378 | -- $Id: s7_cmt_1ce1ce.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_1ce1ce - syn
-- Description: clocking block for 7-Series: 2 clk with CEs
--
-- Dependencies: s7_cmt_sfs
-- clkdivce
-- Test bench: -
-- Target Devices: generic 7-Series
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
entity s7_cmt_1ce1ce is -- clocking block: 2 clk with CEs
generic (
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
CLK0_OUTDIV : positive := 1; -- clk0: output divide
CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
CLK1_OUTDIV : positive := 1; -- clk1: output divide
CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse
port (
CLKIN : in slbit; -- clock input
CLK0 : out slbit; -- clk0: clock output
CE0_USEC : out slbit; -- clk0: usec pulse
CE0_MSEC : out slbit; -- clk0: msec pulse
CLK1 : out slbit; -- clk1: clock output
CE1_USEC : out slbit; -- clk1: usec pulse
CE1_MSEC : out slbit; -- clk1: msec pulse
LOCKED : out slbit -- all PLL/MMCM locked
);
end s7_cmt_1ce1ce;
architecture syn of s7_cmt_1ce1ce is
signal CLK0_L : slbit := '0';
signal CLK1_L : slbit := '0';
signal LOCKED0 : slbit := '0';
signal LOCKED1 : slbit := '0';
begin
GEN_CLK0 : s7_cmt_sfs -- clock generator 0 -----------------
generic map (
VCO_DIVIDE => CLK0_VCODIV,
VCO_MULTIPLY => CLK0_VCOMUL,
OUT_DIVIDE => CLK0_OUTDIV,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKIN_JITTER => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT,
GEN_TYPE => CLK0_GENTYPE)
port map (
CLKIN => CLKIN,
CLKFX => CLK0_L,
LOCKED => LOCKED0
);
DIV_CLK0 : clkdivce -- usec/msec clock divider 0 ---------
generic map (
CDUWIDTH => CLK0_CDUWIDTH,
USECDIV => CLK0_USECDIV,
MSECDIV => CLK0_MSECDIV)
port map (
CLK => CLK0_L,
CE_USEC => CE0_USEC,
CE_MSEC => CE0_MSEC
);
GEN_CLK1 : s7_cmt_sfs -- clock generator serport -----------
generic map (
VCO_DIVIDE => CLK1_VCODIV,
VCO_MULTIPLY => CLK1_VCOMUL,
OUT_DIVIDE => CLK1_OUTDIV,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKIN_JITTER => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT,
GEN_TYPE => CLK1_GENTYPE)
port map (
CLKIN => CLKIN,
CLKFX => CLK1_L,
LOCKED => LOCKED1
);
DIV_CLK1 : clkdivce -- usec/msec clock divider 1 ---------
generic map (
CDUWIDTH => CLK1_CDUWIDTH,
USECDIV => CLK1_USECDIV,
MSECDIV => CLK1_MSECDIV)
port map (
CLK => CLK1_L,
CE_USEC => CE1_USEC,
CE_MSEC => CE1_MSEC
);
CLK0 <= CLK0_L;
CLK1 <= CLK1_L;
LOCKED <= LOCKED0 and LOCKED1;
end syn;
| gpl-3.0 | a8b182a6c39b7666b9c1aa030c5990e3 | 0.52741 | 3.5278 | false | false | false | false |
mr-kenhoff/Bitmap-VHDL-Package | rtl/bmp_pkg.vhd | 1 | 8,879 | -------------------------------------------------------------------------------
-- File : bmp_pkg.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Low level access to bitmap files
--
-- Target: Simulator
-- Dependencies: none
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package bmp_pkg is
constant BMP_MAX_WIDTH : integer := 700;
constant BMP_MAX_HEIGHT : integer := 640;
subtype bmp_slv8_t is std_logic_vector(7 downto 0);
subtype bmp_slv16_t is std_logic_vector(15 downto 0);
subtype bmp_slv32_t is std_logic_vector(31 downto 0);
type bmp_meta is
record
width : integer;
height : integer;
end record;
type bmp_pix is
record
r: bmp_slv8_t;
g: bmp_slv8_t;
b: bmp_slv8_t;
end record;
type bmp_line is array (0 to BMP_MAX_WIDTH-1) of bmp_pix;
type bmp_data is array (0 to BMP_MAX_HEIGHT-1) of bmp_line;
type bmp is
record
meta : bmp_meta;
data: bmp_data;
end record;
type bmp_ptr is access bmp;
----------------------------------------------------------------------------
-- Public procedures and functions
----------------------------------------------------------------------------
procedure bmp_open ( ptr : inout bmp_ptr; filename : in string );
procedure bmp_save ( ptr : inout bmp_ptr; filename : in string );
procedure bmp_get_width ( ptr : inout bmp_ptr; width : out integer);
procedure bmp_get_height ( ptr : inout bmp_ptr; height : out integer);
procedure bmp_get_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : out bmp_pix );
procedure bmp_set_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : in bmp_pix );
end package bmp_pkg;
package body bmp_pkg is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type bmp_file is file of character;
type bmp_header_array is array (0 to 53) of bmp_slv8_t;
----------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------
constant BMP_STD_HEADER_ARRAY : bmp_header_array := (
"01000010", "01001101", "00110110", "00000000", "00001100", "00000000",
"00000000", "00000000", "00000000", "00000000", "00110110", "00000000",
"00000000", "00000000", "00101000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000001", "00000000", "00011000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "11000100", "00001110", "00000000", "00000000",
"11000100", "00001110", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000"
);
----------------------------------------------------------------------------
-- Procedures
----------------------------------------------------------------------------
procedure bmp_open ( ptr : inout bmp_ptr; filename : in string ) is
file fp : bmp_file open read_mode is filename;
variable header_array : bmp_header_array;
variable byte : character;
variable val : integer;
variable tmp_slv32 : bmp_slv32_t; -- Temporary variable
variable file_pos : integer := 0;
variable data_offset : integer;
begin
-- Read bitmap header into array
for i in 0 to 53 loop
read( fp, byte );
val := character'pos( byte );
header_array(i) := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
file_pos := file_pos + 1;
end loop;
-- TODO: Validate bitmap
-- Extract image width from array
tmp_slv32 := header_array(21) & header_array(20) & header_array(19) & header_array(18);
ptr.meta.width := to_integer(signed(tmp_slv32));
-- Extract image height from array
tmp_slv32 := header_array(25) & header_array(24) & header_array(23) & header_array(22);
ptr.meta.height := to_integer(signed(tmp_slv32));
-- Extract offset of image data from array
tmp_slv32 := header_array(13) & header_array(12) & header_array(11) & header_array(10);
data_offset := to_integer(signed(tmp_slv32)); -- HACK: actually the data offset is not signed
assert ptr.meta.width <= BMP_MAX_WIDTH report "Image height too big. Increase BMP_MAX_WIDTH!" severity error;
assert ptr.meta.height <= BMP_MAX_HEIGHT report "Image width too big. Increase BMP_MAX_HEIGHT!" severity error;
-- Fast forward to image data
while file_pos < data_offset loop
read( fp, byte );
file_pos := file_pos + 1;
end loop;
-- Extract image data
line : for y in ptr.meta.height-1 downto 0 loop
pix : for x in 0 to ptr.meta.width -1 loop
-- Blue pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).b := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
-- Green pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).g := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
-- Red pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).r := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
end loop;
end loop;
end bmp_open;
procedure bmp_save ( ptr : inout bmp_ptr; filename : in string ) is
file fp : bmp_file open write_mode is filename;
variable header_array : bmp_header_array := BMP_STD_HEADER_ARRAY;
variable byte : character;
variable val : integer;
variable tmp_slv32 : bmp_slv32_t; -- Temporary variable
begin
--Inject image width into bitmap header
tmp_slv32 := bmp_slv32_t(to_signed(ptr.meta.width, bmp_slv32_t'length));
header_array(21) := tmp_slv32(31 downto 24);
header_array(20) := tmp_slv32(23 downto 16);
header_array(19) := tmp_slv32(15 downto 8);
header_array(18) := tmp_slv32(7 downto 0);
--Inject image height into bitmap header
tmp_slv32 := bmp_slv32_t(to_signed(ptr.meta.height, bmp_slv32_t'length));
header_array(25) := tmp_slv32(31 downto 24);
header_array(24) := tmp_slv32(23 downto 16);
header_array(23) := tmp_slv32(15 downto 8);
header_array(22) := tmp_slv32(7 downto 0);
-- Write array into bitmap header
for i in 0 to 53 loop
val := to_integer(unsigned(header_array(i)));
byte := character'val(val);
write( fp, byte );
end loop;
-- Write image data
line : for y in ptr.meta.height-1 downto 0 loop
pix : for x in 0 to ptr.meta.width -1 loop
-- Blue pixel
val := to_integer(unsigned(ptr.data(y)(x).b));
byte := character'val(val);
write( fp, byte );
-- Green pixel
val := to_integer(unsigned(ptr.data(y)(x).g));
byte := character'val(val);
write( fp, byte );
-- Red pixel
val := to_integer(unsigned(ptr.data(y)(x).r));
byte := character'val(val);
write( fp, byte );
end loop;
end loop;
end bmp_save;
procedure bmp_get_width ( ptr : inout bmp_ptr; width : out integer) is
begin
width := ptr.meta.width;
end bmp_get_width;
procedure bmp_get_height ( ptr : inout bmp_ptr; height : out integer) is
begin
height := ptr.meta.height;
end bmp_get_height;
procedure bmp_get_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : out bmp_pix ) is
begin
pix := ptr.data(y)(x);
end bmp_get_pix;
procedure bmp_set_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : in bmp_pix ) is
begin
ptr.data(y)(x) := pix;
-- Increase image size if nessecary
if x+1 > ptr.meta.width then
ptr.meta.width := x+1;
end if;
if y+1 > ptr.meta.height then
ptr.meta.height := y+1;
end if;
end bmp_set_pix;
end bmp_pkg;
| mit | d5e7d758e9e6ecaf503b9a7f3ab46d25 | 0.508728 | 4.065476 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4d/sys_conf.vhd | 1 | 1,928 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | c14ff2693bdbe51459f9af4a8700b679 | 0.623444 | 3.590317 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/s3_sram_dummy.vhd | 1 | 1,588 | -- $Id: s3_sram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s3_sram_dummy - syn
-- Description: s3board: SRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-17 278 1.0.2 renamed from sram_dummy
-- 2007-12-09 101 1.0.1 use _N for active low
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s3_sram_dummy is -- SRAM protection dummy
port (
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3_sram_dummy;
architecture syn of s3_sram_dummy is
begin
O_MEM_CE_N <= "11"; -- disable sram chips
O_MEM_BE_N <= "1111";
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');
end syn;
| gpl-3.0 | 53d1d660881fb56b0a85609ca5eb41a7 | 0.517003 | 3.150794 | false | false | false | false |
nanomolina/vhdl_examples | RAM/test_dmem.vhd | 2 | 1,741 | library ieee;
use ieee.std_logic_1164.all;
entity test_dmem is
end entity;
architecture arq_test_dmem of test_dmem is
component dmem
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in bit;
rd: out std_logic_vector(31 downto 0));
end component;
signal a1, wd1, rd1: std_logic_vector(31 downto 0);
signal clk1, we1: bit;
begin
prueba0: dmem port map(a=>a1, wd=>wd1, clk=>clk1, we=>we1, rd=>rd1);
process
begin
a1 <= x"00010001";
wait for 5 ns;
a1 <= x"11100101";
wait for 5 ns;
a1 <= x"11104000";
wait for 5 ns;
a1 <= x"1121121F";
wait for 5 ns;
a1 <= x"AA0000AF";
wait for 5 ns;
a1 <= x"FFFFFFFF";
wait for 5 ns;
end process;
process
begin
wd1 <= x"AAAAAAAA";
wait for 5 ns;
wd1 <= x"BBBBBBBB";
wait for 6 ns;
wd1 <= x"CCCCCCCC";
wait for 7 ns;
wd1 <= x"DDDDDDDD";
wait for 8 ns;
wd1 <= x"EEEEEEEE";
wait for 9 ns;
wd1 <= x"FFFFFFFF";
wait for 10 ns;
wd1 <= x"99999999";
wait for 11 ns;
end process;
process
begin
clk1 <= '0';
wait for 5 ns;
clk1 <= '1';
wait for 5 ns;
end process;
process
begin
we1 <= '0';
wait for 6 ns;
we1 <= '1';
wait for 8 ns;
we1 <= '0';
wait for 12 ns;
we1 <= '1';
wait for 9 ns;
we1 <= '0';
wait for 7 ns;
we1 <= '1';
wait for 4 ns;
we1 <= '0';
wait for 8 ns;
end process;
end architecture;
| gpl-3.0 | cd7ec5062c0b2355857d813156e51a40 | 0.475589 | 3.440711 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_master_slave/spi_master_slave.vhd | 1 | 4,871 | -- file: spi_master_slave.vhd
-- description: SPI master slave interface
-- date: 01/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- This is a simple SPI master / slave interface that works in SPI MODE 0.
-- Chip select logic is not included and selects the operating mode (spi_ssn_i <= '0'
-- for slave mode and spi_ssn_i <= '1' for master mode). The usual terminology of the
-- clock and data buses (SCK, MISO and MOSI) is changed because the interface can act
-- in both modes. So, the SPI clock bus works in either direction and MISO, MOSI data
-- buses are changed to DI and DO respectively.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_master_slave is
generic (
BYTE_SIZE: integer := 8
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
data_i: in std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data in (clocked on rising spi_clk after last bit)
data_o: out std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data output (clocked on rising spi_clk after last bit)
data_valid_o: out std_logic; -- data valid (read / write finished)
wren_i: in std_logic; -- data write enable, starts transmission when interface is idle
clk_div_i: in std_logic_vector(8 downto 0); -- SPI clock divider
-- SPI interface
spi_ssn_i: in std_logic; -- spi slave select negated input
spi_clk_i: in std_logic; -- spi slave clock input
spi_clk_o: out std_logic; -- spi master clock output
spi_do_o: out std_logic; -- spi mosi (master mode) or miso (slave mode)
spi_di_i: in std_logic -- spi miso (master mode) or mosi (slave mode)
);
end spi_master_slave;
architecture spi_master_slave_arch of spi_master_slave is
type states is (idle, data1, clock1, data2, clock2, sdata1, sdata2, done);
signal state: states;
signal data_reg: std_logic_vector(BYTE_SIZE-1 downto 0);
signal clk_cnt: std_logic_vector(8 downto 0);
signal counter: std_logic_vector(8 downto 0);
signal fsm_trigger: std_logic;
begin
process(clk_i, rst_i)
begin
if rst_i = '1' then
clk_cnt <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if (clk_cnt < clk_div_i) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= (others => '0');
end if;
end if;
end process;
fsm_trigger <= '1' when clk_cnt = "000000000" or spi_ssn_i = '0' else '0';
process(clk_i, rst_i, spi_clk_i, fsm_trigger)
begin
if rst_i = '1' then
data_reg <= (others => '0');
counter <= (others => '0');
data_valid_o <= '0';
spi_clk_o <= '0';
spi_do_o <= '0';
elsif clk_i'event and clk_i = '1' then
if (fsm_trigger = '1') then
case state is
when idle =>
counter <= (others => '0');
spi_clk_o <= '0';
spi_do_o <= '0';
data_valid_o <= '0';
data_reg <= data_i;
when data1 =>
data_valid_o <= '0';
spi_do_o <= data_reg(BYTE_SIZE-1);
when clock1 =>
spi_clk_o <= '1';
when data2 =>
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_di_i;
when clock2 =>
spi_clk_o <= '0';
counter <= counter + 1;
when sdata1 =>
data_valid_o <= '0';
spi_do_o <= data_reg(BYTE_SIZE-1);
when sdata2 =>
if (spi_clk_i = '0') then
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_di_i;
spi_do_o <= data_reg(BYTE_SIZE-1);
counter <= counter + 1;
end if;
when done =>
counter <= (others => '0');
data_valid_o <= '1';
spi_do_o <= '0';
when others => null;
end case;
end if;
end if;
end process;
data_o <= data_reg;
process(clk_i, rst_i, state, counter, wren_i, spi_ssn_i, spi_clk_i, fsm_trigger)
begin
if rst_i = '1' then
state <= idle;
elsif clk_i'event and clk_i = '1' then
if (fsm_trigger = '1') then
case state is
when idle =>
if (spi_ssn_i = '1') then
if (wren_i = '1') then
state <= data1;
end if;
else
state <= sdata1;
end if;
when data1 =>
state <= clock1;
when clock1 =>
state <= data2;
when data2 =>
state <= clock2;
when clock2 =>
if (counter < BYTE_SIZE-1) then
state <= data1;
else
state <= done;
end if;
when sdata1 =>
if (spi_clk_i = '1') then
state <= sdata2;
end if;
when sdata2 =>
if (spi_clk_i = '0') then
if (counter < BYTE_SIZE-1) then
state <= sdata1;
else
state <= done;
end if;
end if;
when done =>
if (spi_ssn_i = '1') then
if (wren_i = '0') then
state <= idle;
end if;
else
if (spi_clk_i = '1') then
state <= sdata1;
end if;
end if;
when others => null;
end case;
end if;
end if;
end process;
end spi_master_slave_arch;
| gpl-2.0 | 9d43451df6b9cd0fae73bd727ce0de57 | 0.579758 | 2.84189 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty_bram/sys_conf.vhd | 1 | 5,234 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.3.7 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.6 add sys_conf_ibd_kw11p
-- 2017-03-04 858 1.3.5 enable deuna
-- 2017-01-29 847 1.3.4 add sys_conf_ibd_deuna
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@ 80 MHz)
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz)
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth
-- 2016-03-13 742 1.1 add sysmon_bus
-- 2016-02-27 736 1.0 Initial version (derived from _b3 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 11;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | bcbc2b48a2b5947d513721b6f8191f4e | 0.599924 | 3.501003 | false | true | false | false |
wfjm/w11 | rtl/ibus/ib_sel.vhd | 1 | 1,818 | -- $Id: ib_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sel - syn
-- Description: ibus: address select logic
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end ib_sel;
architecture syn of ib_sel is
signal R_SEL : slbit := '0';
begin
assert SAWIDTH<=10 -- at most 1k words devices
report "assert(SAWIDTH<=10)" severity failure;
proc_regs: process (CLK)
variable isel : slbit := '0';
begin
if rising_edge(CLK) then
isel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then
isel := '1';
end if;
R_SEL <= isel;
end if;
end process proc_regs;
SEL <= R_SEL;
end syn;
| gpl-3.0 | e1dd7fb7cc17dcd80b474e3b69b7f71e | 0.5022 | 3.779626 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/instruction_memory1.vhd | 1 | 3,592 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
--Assigning the immediate memory
immediate_data(0) <= x"00000001";
immediate_data(1) <= x"00000003";
immediate_data(2) <= x"40000000";
immediate_data(3) <= x"10000000";
immediate_data(4) <= x"0000007D";
--Assigning the instruction memory
instruction_data(0) <= "000000000000"; --Address zero is zero
instruction_data(1) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(2) <= "010101000000"; --DUP
instruction_data(3) <= "000001000000"; --ADD
instruction_data(4) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(5) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(6) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(7) <= "000001000000"; --ADD
instruction_data(8) <= "000001000000"; --ADD
instruction_data(9) <= "000001000000"; --ADD
instruction_data(10) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(11) <= "110001000000"; --WR_MEM
instruction_data(12) <= "010100000010"; --PUSH immediate at addr 2 (2.0)
instruction_data(13) <= "010100000011"; --PUSH immediate at addr 3 (0.5)
instruction_data(14) <= "001011000000"; --FPMUL
instruction_data(15) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(16) <= "110000000000"; --RD_MEM
instruction_data(17) <= "010000000000"; --DROP
instruction_data(18) <= "010000000000"; --DROP
instruction_data(19) <= "110010000000"; --RD_PRT
instruction_data(20) <= "110011000000"; --WR_PRT
instruction_data(21) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(22) <= "110100000000"; --RD_PIN
instruction_data(23) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(24) <= "110101000000"; --WR_PIN
instruction_data(25) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(26) <= "010100000100"; --PUSH immediate at addr 4 (125) --addr for jp
instruction_data(27) <= "100011000000"; --PSHPC
instruction_data(28) <= "100000000000"; --JP to 125
instruction_data(29) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(30) <= "000110000000"; --CP
instruction_data(31) <= "010100000001"; --PUSH immediate at addr 1 (3)
instruction_data(32) <= "010100000100"; --PUSH immediate at addr 4 (125)
instruction_data(33) <= "100001000000"; --BRN (if e0 is greater than e1)
instruction_data(125) <= "010100000000"; --PUSH immediate at addr 0 (1)
instruction_data(126) <= "000001000000"; --ADD
instruction_data(127) <= "100010000000"; --RET
end Behavioral;
| mit | 9802e0f24fc094d9f834cddd5d294889 | 0.687918 | 3.37277 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/rgbdrv_3x4mux.vhd | 1 | 3,744 | -- $Id: rgbdrv_3x4mux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_3x4mux - syn
-- Description: rgbled driver: mux three 4bit inputs
--
-- Dependencies: xlib/iob_reg_o_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-27 737 1.0 Initial version (re-write, new logic)
-- 2016-02-20 734 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv4; -- red data
DATG : in slv4; -- green data
DATB : in slv4; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3; -- pad-o: rgb led 1
O_RGBLED2 : out slv3; -- pad-o: rgb led 2
O_RGBLED3 : out slv3 -- pad-o: rgb led 3
);
end rgbdrv_3x4mux;
architecture syn of rgbdrv_3x4mux is
signal R_LED : slv4 := "0001";
signal R_COL : slv3 := "001";
signal R_DIM : slbit := '1';
signal RGB0 : slv3 := (others=>'0');
signal RGB1 : slv3 := (others=>'0');
signal RGB2 : slv3 := (others=>'0');
signal RGB3 : slv3 := (others=>'0');
begin
IOB_RGB0: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0);
IOB_RGB1: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1);
IOB_RGB2: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB2, PAD => O_RGBLED2);
IOB_RGB3: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB3, PAD => O_RGBLED3);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_LED <= "0001";
R_COL <= "001";
R_DIM <= '1';
else
if CE_USEC = '1' then
R_DIM <= not R_DIM;
if R_DIM = '1' then
R_COL <= R_COL(1) & R_COL(0) & R_COL(2);
if R_COL(2) = '1' then
R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3);
end if;
end if;
end if;
end if;
end if;
end process proc_regs;
proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB)
begin
RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0);
RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0);
RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0);
RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1);
RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1);
RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1);
RGB2(0) <= (not R_DIM) and R_COL(0) and R_LED(2) and DATR(2);
RGB2(1) <= (not R_DIM) and R_COL(1) and R_LED(2) and DATG(2);
RGB2(2) <= (not R_DIM) and R_COL(2) and R_LED(2) and DATB(2);
RGB3(0) <= (not R_DIM) and R_COL(0) and R_LED(3) and DATR(3);
RGB3(1) <= (not R_DIM) and R_COL(1) and R_LED(3) and DATG(3);
RGB3(2) <= (not R_DIM) and R_COL(2) and R_LED(3) and DATB(3);
end process proc_mux;
end syn;
| gpl-3.0 | e7d9241425d3089d9828cc95dca10ba4 | 0.504808 | 2.832073 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd | 1 | 18,702 | -- $Id: sys_w11a_n4.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n4 - syn
-- Description: w11a test design for nexys4
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_4line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/fx2rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_sys_w11a_n4
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.29-2.0.0 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2022-07-05 1247 2022.1 xc7a100t-1 3455 6137 279 17.5 2100 80
-- 2019-05-19 1150 2017.2 xc7a100t-1 3418 7272 285 17.5 2234 80 +dz11
-- 2019-05-01 1143 2017.2 xc7a100t-1 3295 6597 260 17.5 2107 80 +m9312
-- 2019-04-27 1140 2017.2 xc7a100t-1 3288 6574 260 17.0 2132 80 +dlbuf
-- 2019-04-24 1137 2017.2 xc7a100t-1 3251 6465 228 17.0 2043 80 +pcbuf
-- 2019-03-17 1123 2017.2 xc7a100t-1 3231 6403 212 17.0 2053 80 +lpbuf
-- 2019-03-02 1116 2017.2 xc7a100t-1 3200 6317 198 17.0 2032 80 +ibtst
-- 2019-02-02 1108 2018.3 xc7a100t-1 3165 6497 182 17.0 2054 80
-- 2019-02-02 1108 2017.2 xc7a100t-1 3146 6227 182 17.0 1982 80
-- 2018-10-13 1056 2017.2 xc7a100t-1 3146 6228 182 17.0 1979 80 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a100t-1 2926 5904 150 17.0 1884 80 +KW11P
-- 2017-04-22 885 2016.4 xc7a100t-1 2862 5859 150 12.0 1900 80 +dmcmon
-- 2017-04-16 881 2016.4 xc7a100t-1 2645 5621 138 12.0 1804 80 +DEUNA
-- 2017-01-29 846 2016.4 xc7a100t-1 2574 5496 138 12.0 1750 80 +int24
-- 2016-05-26 768 2016.1 xc7a100t-1 2777 5672 150 10.0 1763 90 dms=0
-- 2016-05-22 767 2016.1 xc7a100t-1 2790 5774 150 11.0 1812 75 fsm
-- 2016-03-29 756 2015.4 xc7a100t-1 2651 4955 150 11.0 1608 75 2clock
-- 2016-03-27 753 2015.4 xc7a100t-1 2545 4850 150 11.0 1576 80 meminf
-- 2016-03-27 752 2015.4 xc7a100t-1 2544 4875 178 13.0 1569 80 +TW=8
-- 2016-03-13 742 2015.4 xc7a100t-1 2536 4868 178 10.5 1542 80 +XADC
-- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11
-- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80
-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80
-- 2015-02-22 650 i 14.7 xc7a100t-1 1670 3564 124 1508 80
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 2.5 use s7_cmt_1ce1ce
-- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.1 define rlink SYSID
-- 2016-03-13 742 2.2 add sysmon_rbus
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-11 666 1.4.2 rearrange XON handling
-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and
-- minisys options;
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
-- 2014-12-24 620 1.2.1 relocate ibus window and hio rbus address
-- 2014-08-28 588 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-22 543 1.0 Initial version (derived from sys_w11a_n3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys4
-- w11a + rlink + serport
--
-- Usage of Nexys 4 Switches, Buttons, LEDs
--
-- SWI(15:5): no function (only connected to sn_humanio_rbus)
-- (5): select DSP(7:4) display
-- 0 abclkdiv & abclkdiv_f
-- 1 PC
-- (4): select DSP(3:0) display
-- 0 DISPREG
-- 1 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2): unused-reserved (USB port select)
-- (1): 1 enable XON
-- (0): unused-reserved (serial port select)
--
-- LEDs if SWI(3) = 1
-- (15:0) DR emulation; shows R0 during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5)
-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4)
-- DP(3:0) shows IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n4 is -- top level
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end sys_w11a_n4;
architecture syn of sys_w11a_n4 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"05"; -- nexys4
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP(3 downto 0)
);
DSP_DP(7 downto 4) <= "0010";
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | b9ee8ec8e57d69f60038312490d2e8fb | 0.50139 | 3.059382 | false | false | false | false |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/src/vgagraph_fifo/vgagraph_fifo_sim_netlist.vhdl | 1 | 241,986 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
-- Date : Sat Apr 1 16:02:47 2017
-- Host : g-tune2016 running 64-bit Ubuntu 16.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/minoru/FPGA/Zybo/Chapter9/vgagraph/vgagraph/src/vgagraph_fifo/vgagraph_fifo_sim_netlist.vhdl
-- Design : vgagraph_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end vgagraph_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => \gc0.count_d1_reg[10]\(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => din(15 downto 0),
DIADI(15 downto 0) => din(31 downto 16),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => dout(15 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_compare is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_compare : entity is "compare";
end vgagraph_fifo_compare;
architecture STRUCTURE of vgagraph_fifo_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(2 downto 0),
S(0) => v1_reg(0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_d1_reg[10]\,
S(0) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(3)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[10]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_compare_3 : entity is "compare";
end vgagraph_fifo_compare_3;
architecture STRUCTURE of vgagraph_fifo_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(2 downto 0),
S(0) => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gc0.count_reg[10]\,
S(0) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_compare__parameterized0\ is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_compare__parameterized0\ : entity is "compare";
end \vgagraph_fifo_compare__parameterized0\;
architecture STRUCTURE of \vgagraph_fifo_compare__parameterized0\ is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_compare__parameterized1\ is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_compare__parameterized1\ : entity is "compare";
end \vgagraph_fifo_compare__parameterized1\;
architecture STRUCTURE of \vgagraph_fifo_compare__parameterized1\ is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => wr_rst_busy,
I1 => comp2,
I2 => \out\,
I3 => wr_en,
I4 => comp1,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gc0.count_d1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end vgagraph_fifo_rd_bin_cntr;
architecture STRUCTURE of vgagraph_fifo_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \gc0.count[10]_i_2_n_0\ : STD_LOGIC;
signal \^gc0.count_d1_reg[9]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair9";
begin
Q(10 downto 0) <= \^q\(10 downto 0);
\gc0.count_d1_reg[9]_0\(7 downto 0) <= \^gc0.count_d1_reg[9]_0\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(6),
I1 => \^gc0.count_d1_reg[9]_0\(4),
I2 => \gc0.count[10]_i_2_n_0\,
I3 => \^gc0.count_d1_reg[9]_0\(5),
I4 => \^gc0.count_d1_reg[9]_0\(7),
I5 => rd_pntr_plus1(10),
O => plusOp(10)
);
\gc0.count[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(3),
I1 => \^gc0.count_d1_reg[9]_0\(1),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(0),
I4 => \^gc0.count_d1_reg[9]_0\(0),
I5 => \^gc0.count_d1_reg[9]_0\(2),
O => \gc0.count[10]_i_2_n_0\
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
I2 => \^gc0.count_d1_reg[9]_0\(0),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => \^gc0.count_d1_reg[9]_0\(0),
I3 => \^gc0.count_d1_reg[9]_0\(1),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(0),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => \^gc0.count_d1_reg[9]_0\(1),
I4 => \^gc0.count_d1_reg[9]_0\(2),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(1),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => \^gc0.count_d1_reg[9]_0\(0),
I4 => \^gc0.count_d1_reg[9]_0\(2),
I5 => \^gc0.count_d1_reg[9]_0\(3),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[10]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[9]_0\(4),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[10]_i_2_n_0\,
I1 => \^gc0.count_d1_reg[9]_0\(4),
I2 => \^gc0.count_d1_reg[9]_0\(5),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(4),
I1 => \gc0.count[10]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[9]_0\(5),
I3 => \^gc0.count_d1_reg[9]_0\(6),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^gc0.count_d1_reg[9]_0\(5),
I1 => \gc0.count[10]_i_2_n_0\,
I2 => \^gc0.count_d1_reg[9]_0\(4),
I3 => \^gc0.count_d1_reg[9]_0\(6),
I4 => \^gc0.count_d1_reg[9]_0\(7),
O => plusOp(9)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(0),
Q => \^q\(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(10),
Q => \^q\(10)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(1),
Q => \^q\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(0),
Q => \^q\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(1),
Q => \^q\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(2),
Q => \^q\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(3),
Q => \^q\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(4),
Q => \^q\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(5),
Q => \^q\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(6),
Q => \^q\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc0.count_d1_reg[9]_0\(7),
Q => \^q\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(10),
Q => rd_pntr_plus1(10)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^gc0.count_d1_reg[9]_0\(0)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^gc0.count_d1_reg[9]_0\(1)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => \^gc0.count_d1_reg[9]_0\(2)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(5),
Q => \^gc0.count_d1_reg[9]_0\(3)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(6),
Q => \^gc0.count_d1_reg[9]_0\(4)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(7),
Q => \^gc0.count_d1_reg[9]_0\(5)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(8),
Q => \^gc0.count_d1_reg[9]_0\(6)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => plusOp(9),
Q => \^gc0.count_d1_reg[9]_0\(7)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \^q\(0),
I1 => WR_PNTR_RD(0),
I2 => \^q\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => WR_PNTR_RD(0),
I2 => rd_pntr_plus1(1),
O => v1_reg_0(0)
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => WR_PNTR_RD(1),
O => ram_empty_fb_i_reg
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(10),
I1 => WR_PNTR_RD(1),
O => ram_empty_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_synchronizer_ff : entity is "synchronizer_ff";
end vgagraph_fifo_synchronizer_ff;
architecture STRUCTURE of vgagraph_fifo_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_synchronizer_ff_0 : entity is "synchronizer_ff";
end vgagraph_fifo_synchronizer_ff_0;
architecture STRUCTURE of vgagraph_fifo_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_synchronizer_ff_1 : entity is "synchronizer_ff";
end vgagraph_fifo_synchronizer_ff_1;
architecture STRUCTURE of vgagraph_fifo_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_synchronizer_ff_2 : entity is "synchronizer_ff";
end vgagraph_fifo_synchronizer_ff_2;
architecture STRUCTURE of vgagraph_fifo_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \vgagraph_fifo_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \vgagraph_fifo_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \vgagraph_fifo_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \vgagraph_fifo_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[10]\ : label is "yes";
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(10 downto 0) <= Q_reg(10 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(10),
Q => Q_reg(10)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \vgagraph_fifo_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \vgagraph_fifo_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \vgagraph_fifo_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[9]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 10 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \vgagraph_fifo_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \vgagraph_fifo_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \vgagraph_fifo_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[10]\ : label is "yes";
attribute msgon of \Q_reg_reg[10]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(10);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(10),
Q => Q_reg(10)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(3),
I3 => \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(0)
);
\gnxpm_cdc.rd_pntr_bin[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(4),
I2 => Q_reg(10),
O => \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(10),
I2 => Q_reg(4),
I3 => Q_reg(5),
I4 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I5 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(1)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I1 => Q_reg(5),
I2 => Q_reg(4),
I3 => Q_reg(10),
I4 => Q_reg(3),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(2)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(8),
I2 => Q_reg(7),
I3 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(10),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => \gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0\,
I4 => Q_reg(8),
I5 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(3)
);
\gnxpm_cdc.rd_pntr_bin[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(10),
I4 => Q_reg(8),
I5 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(4)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(6),
I2 => Q_reg(7),
I3 => Q_reg(10),
I4 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(5)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(10),
I3 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(6)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(8),
I2 => Q_reg(10),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(7)
);
\gnxpm_cdc.rd_pntr_bin[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(10),
O => \gnxpm_cdc.rd_pntr_bin_reg[9]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_wr_bin_cntr is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end vgagraph_fifo_wr_bin_cntr;
architecture STRUCTURE of vgagraph_fifo_wr_bin_cntr is
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair13";
begin
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
I4 => wr_pntr_plus2(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
I5 => wr_pntr_plus2(5),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(8),
O => \plusOp__0\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(7),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(6),
I3 => wr_pntr_plus2(8),
I4 => wr_pntr_plus2(9),
O => \plusOp__0\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => wr_pntr_plus2(3),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => wr_pntr_plus2(2),
I5 => wr_pntr_plus2(4),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_13_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_13_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_13_out(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => p_13_out(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => p_13_out(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(6),
Q => p_13_out(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(7),
Q => p_13_out(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(8),
Q => p_13_out(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => Q(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => Q(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => Q(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => Q(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(4),
Q => Q(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(5),
Q => Q(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(6),
Q => Q(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(7),
Q => Q(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(8),
Q => Q(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => Q(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => wr_pntr_plus2(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => wr_pntr_plus2(9)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(0),
I1 => RD_PNTR_WR(0),
I2 => p_13_out(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(2),
I1 => RD_PNTR_WR(2),
I2 => p_13_out(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus2(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(4),
I1 => RD_PNTR_WR(4),
I2 => p_13_out(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus2(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(6),
I1 => RD_PNTR_WR(6),
I2 => p_13_out(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus2(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(8),
I1 => RD_PNTR_WR(8),
I2 => p_13_out(9),
I3 => RD_PNTR_WR(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => RD_PNTR_WR(8),
I2 => wr_pntr_plus2(9),
I3 => RD_PNTR_WR(9),
O => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end vgagraph_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.vgagraph_fifo_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 1 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_clk_x_pntrs : entity is "clk_x_pntrs";
end vgagraph_fifo_clk_x_pntrs;
architecture STRUCTURE of vgagraph_fifo_clk_x_pntrs is
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 8 downto 1 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 10 to 10 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 10 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[9]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => Q(2),
I2 => p_22_out(2),
I3 => Q(3),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(2),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => Q(4),
I2 => p_22_out(4),
I3 => Q(5),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(4),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => Q(6),
I2 => p_22_out(6),
I3 => Q(7),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(6),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => Q(8),
I2 => p_22_out(8),
I3 => Q(9),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(8),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\vgagraph_fifo_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\vgagraph_fifo_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(10 downto 0) => p_4_out(10 downto 0),
Q(10 downto 0) => rd_pntr_gc(10 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\vgagraph_fifo_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\vgagraph_fifo_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(10 downto 0) => p_4_out(10 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[9]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[9]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(10),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(10),
Q => RD_PNTR_WR(9)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => RD_PNTR_WR(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => RD_PNTR_WR(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => RD_PNTR_WR(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => RD_PNTR_WR(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => RD_PNTR_WR(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => RD_PNTR_WR(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => RD_PNTR_WR(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => RD_PNTR_WR(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => RD_PNTR_WR(8)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => Q(10),
O => \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(10),
Q => rd_pntr_gc(10)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0\,
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => WR_PNTR_RD(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => WR_PNTR_RD(1)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[10]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_rd_status_flags_as : entity is "rd_status_flags_as";
end vgagraph_fifo_rd_status_flags_as;
architecture STRUCTURE of vgagraph_fifo_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.vgagraph_fifo_compare
port map (
comp1 => comp1,
\gc0.count_d1_reg[10]\ => \gc0.count_d1_reg[10]\,
\gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0),
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(0) => v1_reg(0)
);
c1: entity work.vgagraph_fifo_compare_3
port map (
comp1 => comp1,
\gc0.count_reg[10]\ => \gc0.count_reg[10]\,
\gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[7]_0\(3 downto 0),
v1_reg_0(0) => v1_reg_0(0)
);
\gc0.count_d1[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end vgagraph_fifo_reset_blk_ramfifo;
architecture STRUCTURE of vgagraph_fifo_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.vgagraph_fifo_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.vgagraph_fifo_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.vgagraph_fifo_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.vgagraph_fifo_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_wr_status_flags_as : entity is "wr_status_flags_as";
end vgagraph_fifo_wr_status_flags_as;
architecture STRUCTURE of vgagraph_fifo_wr_status_flags_as is
signal c2_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.\vgagraph_fifo_compare__parameterized0\
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.\vgagraph_fifo_compare__parameterized1\
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c2_n_0,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end vgagraph_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.vgagraph_fifo_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
\gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_rd_logic : entity is "rd_logic";
end vgagraph_fifo_rd_logic;
architecture STRUCTURE of vgagraph_fifo_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gras.rsts_n_2\ : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
signal rpntr_n_12 : STD_LOGIC;
begin
\gras.rsts\: entity work.vgagraph_fifo_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\gc0.count_d1_reg[10]\ => rpntr_n_0,
\gc0.count_reg[10]\ => rpntr_n_12,
\gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[7]_0\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[7]_0\(3 downto 0),
\out\ => \out\,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(0) => \c0/v1_reg\(0),
v1_reg_0(0) => \c1/v1_reg\(0)
);
rpntr: entity work.vgagraph_fifo_rd_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
Q(10 downto 0) => Q(10 downto 0),
WR_PNTR_RD(1 downto 0) => WR_PNTR_RD(1 downto 0),
\gc0.count_d1_reg[9]_0\(7 downto 0) => \gc0.count_d1_reg[9]\(7 downto 0),
ram_empty_fb_i_reg => rpntr_n_0,
ram_empty_fb_i_reg_0 => rpntr_n_12,
rd_clk => rd_clk,
v1_reg(0) => \c0/v1_reg\(0),
v1_reg_0(0) => \c1/v1_reg\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_wr_logic is
port (
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst_busy : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_wr_logic : entity is "wr_logic";
end vgagraph_fifo_wr_logic;
architecture STRUCTURE of vgagraph_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwas.wsts\: entity work.vgagraph_fifo_wr_status_flags_as
port map (
E(0) => \^wea\(0),
full => full,
\out\ => \out\,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.vgagraph_fifo_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end vgagraph_fifo_blk_mem_gen_top;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.vgagraph_fifo_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_v8_3_5_synth is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end vgagraph_fifo_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.vgagraph_fifo_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_blk_mem_gen_v8_3_5 is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
end vgagraph_fifo_blk_mem_gen_v8_3_5;
architecture STRUCTURE of vgagraph_fifo_blk_mem_gen_v8_3_5 is
begin
inst_blk_mem_gen: entity work.vgagraph_fifo_blk_mem_gen_v8_3_5_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_memory : entity is "memory";
end vgagraph_fifo_memory;
architecture STRUCTURE of vgagraph_fifo_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.vgagraph_fifo_blk_mem_gen_v8_3_5
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => \gc0.count_d1_reg[10]\(10 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end vgagraph_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of vgagraph_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 1 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 1 );
signal p_0_out : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 10 downto 1 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 2 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.vgagraph_fifo_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
Q(10 downto 0) => p_0_out(10 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(10 downto 1),
WR_PNTR_RD(1) => p_22_out(9),
WR_PNTR_RD(0) => p_22_out(0),
\gc0.count_reg[9]\(7 downto 0) => rd_pntr_plus1(9 downto 2),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
rd_clk => rd_clk,
v1_reg(3 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 1),
v1_reg_0(3 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 1),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.vgagraph_fifo_rd_logic
port map (
AR(0) => rd_rst_i(2),
Q(10 downto 0) => p_0_out(10 downto 0),
WR_PNTR_RD(1) => p_22_out(9),
WR_PNTR_RD(0) => p_22_out(0),
empty => empty,
\gc0.count_d1_reg[9]\(7 downto 0) => rd_pntr_plus1(9 downto 2),
\gnxpm_cdc.wr_pntr_bin_reg[7]\(3 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 1),
\gnxpm_cdc.wr_pntr_bin_reg[7]_0\(3 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 1),
\out\ => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.vgagraph_fifo_wr_logic
port map (
AR(0) => wr_rst_i(1),
Q(9 downto 0) => p_12_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(10 downto 1),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
full => full,
\out\ => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.vgagraph_fifo_memory
port map (
Q(9 downto 0) => p_12_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
\gc0.count_d1_reg[10]\(10 downto 0) => p_0_out(10 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.vgagraph_fifo_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_fifo_generator_top : entity is "fifo_generator_top";
end vgagraph_fifo_fifo_generator_top;
architecture STRUCTURE of vgagraph_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.vgagraph_fifo_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_fifo_generator_v13_1_3_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end vgagraph_fifo_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of vgagraph_fifo_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.vgagraph_fifo_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 2048;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 11;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of vgagraph_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vgagraph_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end vgagraph_fifo_fifo_generator_v13_1_3;
architecture STRUCTURE of vgagraph_fifo_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.vgagraph_fifo_fifo_generator_v13_1_3_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vgagraph_fifo is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 15 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vgagraph_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of vgagraph_fifo : entity is "vgagraph_fifo,fifo_generator_v13_1_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of vgagraph_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of vgagraph_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4";
end vgagraph_fifo;
architecture STRUCTURE of vgagraph_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 16;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 2048;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 11;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.vgagraph_fifo_fifo_generator_v13_1_3
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(15 downto 0) => dout(15 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(10 downto 0) => B"00000000000",
prog_empty_thresh_assert(10 downto 0) => B"00000000000",
prog_empty_thresh_negate(10 downto 0) => B"00000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(10 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(10 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| bsd-2-clause | 367bc3be548aa7caa1c917848eb6275c | 0.615168 | 2.922572 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01800_good.vhd | 1 | 2,997 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01800_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of falling edge detection signal: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01800_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D_fe : out std_logic -- Falling edge of i_D
);
end CNE_01800_good;
architecture Behavioral of CNE_01800_good is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D_fe <= not D_r1 and D_r2;
end Behavioral;
--CODE | gpl-3.0 | a6eda1d0f2b5252632530bb4157daa29 | 0.487154 | 4.362445 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01500_good.vhd | 1 | 3,610 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01500_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of custom type name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01500_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_Addr : in std_logic_vector(1 downto 0); -- Address to read from or write to
i_Rd : in std_logic; -- Read signal
i_Wr : in std_logic; -- Write signal
i_Data : in std_logic; -- Incoming data to write
o_Data : out std_logic -- Data read
);
end CNE_01500_good;
--CODE
architecture Behavioral of CNE_01500_good is
type t_register is array (0 to 3) of std_logic; -- Array for signal registration
signal D : t_register; -- Actual signal
signal Data : std_logic; -- Module output
begin
-- Describes a simple Register bank with Read and Write signals
P_Register_Bank:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D <= (others => '0');
Data <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Rd='1') then
-- Read memory
Data <= D(to_integer(unsigned(i_Addr)));
elsif (i_Wr='1') then
-- Write memory
D(to_integer(unsigned(i_Addr))) <= i_Data;
end if;
end if;
end process;
o_Data <= Data;
end Behavioral;
--CODE | gpl-3.0 | 84d3a34eca8fe382f7f6d5c9d9ba1556 | 0.473684 | 4.610473 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_tmu_sb.vhd | 1 | 1,902 | -- $Id: pdp11_tmu_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit; simbus wrapper
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-05 1053 1.0.2 use DM_STAT_CA instead of DM_STAT_SY
-- 2015-11-01 712 1.0.1 use sbcntl_sbf_tmu
-- 2009-05-10 214 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end pdp11_tmu_sb;
architecture sim of pdp11_tmu_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : pdp11_tmu
port map (
CLK => CLK,
ENA => ENA,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
end sim;
| gpl-3.0 | ba0d320bfd3aae373a2127f174f7db7c | 0.559937 | 3.20202 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s7_cmt_sfs_2_gsim.vhd | 1 | 5,366 | -- $Id: s7_cmt_sfs_2_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_2 - sim
-- Description: Series-7 CMT for dual-channel frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-18 1072 1.0 Initial version (derived from s7_cmt_sfs_3_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output 0 divide
OUT1_DIVIDE : positive := 1; -- output 1 divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs_2;
architecture sim of s7_cmt_sfs_2 is
signal LOCKED0 : slbit := '1';
signal LOCKED1 : slbit := '1';
begin
proc_init : process
-- currently frequency limits taken from Artix-7 speed grade -1
constant f_vcomin_pll : integer := 800;
constant f_vcomax_pll : integer := 1600;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 450;
constant f_vcomin_mmcm : integer := 600;
constant f_vcomax_mmcm : integer := 1200;
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or
OUT0_DIVIDE/=1 or OUT1_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>56 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT0_DIVIDE<1 or OUT0_DIVIDE>128 or
OUT1_DIVIDE<1 or OUT1_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "MMCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>106 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT0_DIVIDE<1 or OUT0_DIVIDE>128 or
OUT1_DIVIDE<1 or OUT1_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps;
end if; -- GEN_TYPE = "MMCM"
-- now common check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- one factor /= 1
wait;
end process proc_init;
-- generate clock
SFS0: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT0_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED0
);
SFS1: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT1_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT1,
LOCKED => LOCKED1
);
LOCKED <= LOCKED0 and LOCKED1;
end sim;
| gpl-3.0 | df60f1c85482e2dcc22524c1a24c1810 | 0.553671 | 3.527942 | false | false | false | false |
nsensfel/tabellion | data/test/combinational_processes/valid.vhd | 1 | 3,097 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of valid is
type enum_t is (V0, V1, V2, V3);
signal s0, s1, s2, s3: std_logic;
signal st0: enum_t;
signal n0, n1, n2, n3: natural range 0 to 3;
begin
s0 <= s1; -- $SOL:0:0$
s0 <= (s1 and s2); -- $SOL:1:0$
process (s0, s1) -- $SOL:2:0$
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:3:0$
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:4:0$
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
process (s0, s1, s2) -- $SOL:5:0$
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op0 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
with ip0 select -- $SOL:6:0$
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
with st0 select -- $SOL:7:0$
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when V2,
s1 when V3;
with st0 select -- $SOL:8:0$
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when others;
process (s0, s1, s2, s3) -- $SOL:9:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when V1 =>
op0 <= s2;
when V0 =>
op0 <= s3;
end case;
end process;
process (s0, s1, s2, s3) -- $SOL:10:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when others =>
op0 <= s2;
end case;
end process;
process (n0, n2) -- $SOL:11:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 to 2 =>
n1 <= n2;
when 3 =>
n1 <= 2;
end case;
end process;
process (n0, n2) -- $SOL:12:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 =>
n1 <= n3;
when 2 =>
n1 <= n2;
when 3 =>
n1 <= 2;
end case;
end process;
process (n0, n3) -- $SOL:13:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 =>
n1 <= n3;
when others =>
n1 <= n3;
end case;
end process;
end;
| apache-2.0 | 2e4f9621744e852f47ae86026f77ffc0 | 0.383274 | 3.078529 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_reg_i_gen.vhd | 1 | 1,626 | -- $Id: iob_reg_i_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i_gen - syn
-- Description: Registered IOB, input only, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_i_gen;
architecture syn of iob_reg_i_gen is
signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INIT);
attribute iob : string;
attribute iob of R_DI : signal is "true";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
R_DI <= PAD;
end if;
end if;
end process proc_regs;
DI <= R_DI;
end syn;
| gpl-3.0 | 32dd2ceb0c55a3baf34647b6c21d1f71 | 0.52706 | 3.394572 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_ubmap.vhd | 1 | 4,637 | -- $Id: pdp11_ubmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ubmap - syn
-- Description: pdp11: 11/70 unibus mapper
--
-- Dependencies: memlib/ram_1swar_gen
-- ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 use ib_sel
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_ubmap;
architecture syn of pdp11_ubmap is
constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16));
signal IBSEL_UBMAP : slbit := '0';
signal MAP_2_WE : slbit := '0';
signal MAP_1_WE : slbit := '0';
signal MAP_0_WE : slbit := '0';
signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
begin
MAP_2 : ram_1swar_gen -- bit 21:16 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 6)
port map (
CLK => CLK,
WE => MAP_2_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(5 downto 0),
DO => MAP_DOUT(21 downto 16));
MAP_1 : ram_1swar_gen -- bit 15:08 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MAP_1_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(15 downto 8),
DO => MAP_DOUT(15 downto 8));
MAP_0 : ram_1swar_gen -- bit 07:01 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 7)
port map (
CLK => CLK,
WE => MAP_0_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(7 downto 1),
DO => MAP_DOUT(7 downto 1));
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_ubmap,
SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_UBMAP
);
proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
variable ibusy : slbit := '0';
variable idout : slv16 := (others=>'0');
variable iwe2 : slbit := '0';
variable iwe1 : slbit := '0';
variable iwe0 : slbit := '0';
variable iaddr : slv5 := (others=>'0');
begin
ibusy := '0';
idout := (others=>'0');
iwe2 := '0';
iwe1 := '0';
iwe0 := '0';
iaddr := (others=>'0');
if IBSEL_UBMAP = '1' then
if IB_MREQ.addr(1) = '1' then
idout(5 downto 0) := MAP_DOUT(21 downto 16);
else
idout(15 downto 1) := MAP_DOUT(15 downto 1);
end if;
if MREQ = '1' then -- if map request, stall ib cycle
ibusy := '1';
end if;
end if;
if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
if IB_MREQ.addr(1)='1' then
if IB_MREQ.be0 = '1' then
iwe2 := '1';
end if;
else
if IB_MREQ.be1 = '1' then
iwe1 := '1';
end if;
if IB_MREQ.be0 = '1' then
iwe0 := '1';
end if;
end if;
end if;
if MREQ = '1' then
iaddr := ADDR_UB(17 downto 13);
else
iaddr := IB_MREQ.addr(6 downto 2);
end if;
MAP_ADDR <= iaddr;
MAP_2_WE <= iwe2;
MAP_1_WE <= iwe1;
MAP_0_WE <= iwe0;
ADDR_PM <= slv(unsigned(MAP_DOUT) +
unsigned("000000000"&ADDR_UB(12 downto 1)));
IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
IB_SRES.busy <= ibusy;
IB_SRES.dout <= idout;
end process proc_comb;
end syn;
| gpl-3.0 | e342e3eb717328714fd9f662378c10ef | 0.490619 | 3.267794 | false | false | false | false |
jsyk/spnsyn-demo | t/tslink00/tb1.vhd | 1 | 2,127 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
use work.comp_tslink_ct.all;
entity tb1 is
end entity;
architecture arch of tb1 is
signal eos : boolean := false;
signal clk : std_ulogic;
signal rst : std_ulogic;
signal LinkIn : std_ulogic;
signal IValid : std_ulogic;
signal QAck : std_ulogic;
signal IData : std_logic_vector(7 downto 0);
signal IAck : std_ulogic;
signal ShiftEnable : std_ulogic;
signal LinkOut : std_ulogic;
signal QValid : std_ulogic;
begin
dut: tslink_ct
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkIn, -- : in std_ulogic;
IValid, -- : in std_ulogic;
QAck, -- : in std_ulogic;
IData, -- : in std_logic_vector(7 downto 0);
IAck, -- : out std_ulogic;
ShiftEnable, -- : out std_ulogic;
LinkOut, -- : out std_ulogic;
QValid -- : out std_ulogic
);
clkgen: process
begin
clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0';
if eos then
wait;
end if;
end process;
tb: process
begin
rst <= '1';
LinkIn <= '0';
IValid <= '0';
QAck <= '0';
IData <= x"00";
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
IData <= x"A5";
IValid <= '1';
wait until rising_edge(clk);
-- LinkIn <= '1';
wait until rising_edge(clk);
LinkIn <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
eos <= true;
wait;
end process;
end architecture ; -- arch
| gpl-2.0 | ab480847e2dd8585a3a7c47959690b04 | 0.544429 | 3.592905 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/tb_cmoda7_core.vhd | 1 | 1,402 | -- $Id: tb_cmoda7_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cmoda7_core - sim
-- Description: Test bench for cmoda7 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any cmoda7 target
--
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from tb_arty_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_cmoda7_core is
port (
I_BTN : out slv2 -- c7 buttons
);
end tb_cmoda7_core;
architecture sim of tb_cmoda7_core is
signal R_BTN : slv2 := (others=>'0');
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | 7222f602133aa2dd661918b87f9b0ff3 | 0.562767 | 3.2529 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd | 1 | 4,245 | -- $Id: sys_tst_snhumanio_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_s3 - syn
-- Description: snhumanio tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_s3 is -- top level
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end sys_tst_snhumanio_s3;
architecture syn of sys_tst_snhumanio_s3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | 406a1c63af9e77888dbdb92470223028 | 0.467138 | 3.374404 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/reg_bank.vhd | 3 | 1,127 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg_bank is
port ( clock: in std_logic;
read_reg1: in std_logic_vector(4 downto 0);
read_reg2: in std_logic_vector(4 downto 0);
write_reg: in std_logic_vector(4 downto 0);
wreg: in std_logic;
write_data: in std_logic_vector(31 downto 0);
read_data1: out std_logic_vector(31 downto 0);
read_data2: out std_logic_vector(31 downto 0)
);
end reg_bank;
architecture arch_reg_bank of reg_bank is
type bank is array(0 to 31) of std_logic_vector(31 downto 0);
signal registers: bank := (others => (others => '0'));
begin
process(clock, write_reg, wreg, write_data, read_reg1, read_reg2, registers)
begin
if clock'event and clock = '1' then
if write_reg /= "00000" and wreg = '1' then
registers(conv_integer(write_reg)) <= write_data;
end if;
end if;
end process;
read_data1 <= registers(conv_integer(read_reg1)) when read_reg1 /= "00000" else (others => '0');
read_data2 <= registers(conv_integer(read_reg2)) when read_reg2 /= "00000" else (others => '0');
end arch_reg_bank;
| gpl-2.0 | 81402c0c4bb282476eef7fe61e0fc544 | 0.664596 | 2.762255 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_rlim_gen.vhd | 1 | 3,447 | -- $Id: ib_rlim_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_rlim_gen - syn
-- Description: ibus rate limter - master
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-14 1131 1.1 add CPUSUSP port; RLIM_CEV now slv8
-- 2019-03-17 1123 1.0 Initial version
-- 2019-03-15 1122 0.1 First draft
--
-- Notes:
-- cev scale rate in slv
-- (0) none 8 clock cycles
-- (1) 1: 1 8 usec 125.0 kHz
-- (2) 1: 2 16 usec 62.5 kHz
-- (3) 1: 4 32 usec 31.2 kHz
-- (4) 1: 8 64 usec 15.6 kHz
-- (5) 1: 32 256 usec 3.9 kHz
-- (6) 1: 64 512 usec 2.0 kHz
-- (7) 1:128 1024 usec 1.0 kHz
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
-- ----------------------------------------------------------------------------
entity ib_rlim_gen is -- ibus rate limter - master
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
CPUSUSP : in slbit; -- cpu suspended
RLIM_CEV : out slv8 -- clock enable vector
);
end ib_rlim_gen;
architecture syn of ib_rlim_gen is
type regs_type is record -- state registers
cnt : slv7; -- usec counter
cev : slv8; -- ce vector
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- cnt
(others=>'0') -- cev
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, CPUSUSP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
n.cev := (others=>'0');
if CPUSUSP = '0' then -- run timers if CPU not suspended
n.cev(0) := '1'; -- none
if CE_USEC = '1' then
n.cev(1) := '1'; -- 1: 1
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt(0 downto 0) = "1" then n.cev(2) := '1'; end if; -- 1: 2
if r.cnt(1 downto 0) = "11" then n.cev(3) := '1'; end if; -- 1: 4
if r.cnt(2 downto 0) = "111" then n.cev(4) := '1'; end if; -- 1: 8
if r.cnt(4 downto 0) = "11111" then n.cev(5) := '1'; end if; -- 1: 32
if r.cnt(5 downto 0) = "111111" then n.cev(6) := '1'; end if; -- 1: 64
if r.cnt(6 downto 0) = "1111111" then n.cev(7) := '1'; end if; -- 1:128
end if;
end if;
N_REGS <= n;
RLIM_CEV <= r.cev;
end process proc_next;
end syn;
| gpl-3.0 | ee6ae06c293013b818bee3429c7602f1 | 0.451407 | 3.295411 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/miglib.vhd | 1 | 7,370 | -- $Id: miglib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: miglib
-- Description: MIG interface components - generic
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-26 1094 1.0 Initial version
-- 2018-11-11 1067 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package miglib is
constant c_migui_cmd_read : slv3 := "001";
constant c_migui_cmd_write : slv3 := "000";
type sramif2migui_moni_type is record -- sramif2migui monitor port
rdrhit : slbit; -- read row hit
wrrhit : slbit; -- write row hit
wrflush : slbit; -- write row flush
migcbusy : slbit; -- mig not ready for command
migwbusy : slbit; -- mig not ready for data write
miguirst : slbit; -- mig UI_CLK_SYNC_RST asserted
migcacow : slbit; -- mig calibration complete wait
end record sramif2migui_moni_type;
constant sramif2migui_moni_init : sramif2migui_moni_type := (
'0','0','0', -- rdrhit,wrrhit,wrflush
'0','0','0','0' -- migcbusy,migwbusy,miguirst,migcacow
);
component sramif2migui_core is -- SRAM to MIG interface core
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28); -- memory address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
MONI : out sramif2migui_moni_type; -- monitor signals
UI_CLK : in slbit; -- MIGUI clock
UI_CLK_SYNC_RST : in slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : in slbit; -- MIGUI calibration done
APP_RDY : in slbit; -- MIGUI ready for cmd
APP_EN : out slbit; -- MIGUI command enable
APP_CMD : out slv3; -- MIGUI command
APP_ADDR : out slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : in slbit; -- MIGUI ready for data write
APP_WDF_WREN : out slbit; -- MIGUI data write enable
APP_WDF_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : out slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : out slbit; -- MIGUI write end
APP_RD_DATA_VALID : in slbit; -- MIGUI read valid
APP_RD_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : in slbit -- MIGUI read end
);
end component;
component migui2bram is -- MIG to BRAM adapter
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
RAWIDTH : positive := 19; -- BRAM memory address width
RDELAY : positive := 5; -- read response delay
CLKMUI_MUL : positive := 6; -- multiplier for MIG UI clock
CLKMUI_DIV : positive := 12; -- divider for MIG UI clock
CLKMSYS_PERIOD : real := 6.000); -- MIG SYS_CLK period
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit -- MIGUI read end
);
end component;
component migui_core_gsim is -- MIG interface simulation core
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
SAWIDTH : positive := 24; -- simulator memory address width
CLKMUI_MUL : positive := 6; -- multiplier for MIG UI clock
CLKMUI_DIV : positive := 12; -- divider for MIG UI clock
CACO_WAIT : positive := 50); -- UI_CLK cycles till CALIB_COMP = 1
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit -- MIGUI ZQ calibrate acknowledge
);
end component;
end package miglib;
| gpl-3.0 | 19fb5b696035f33336cf6c85f7e491b7 | 0.51479 | 3.996746 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_mon.vhd | 1 | 8,777 | -- $Id: rb_mon.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_mon - sim
-- Description: rbus monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 4.1.2 fix for ghdl V0.36 -Whide warnings
-- 2014-10-25 599 4.1.1 use writeoptint()
-- 2014-09-03 591 4.1 add burst counter; add state checker
-- 2014-08-30 589 4.0 use hex for addr; 4 bit STAT; monitor ACK=0
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rblib.all;
entity rb_mon is -- rbus monitor (for tb's)
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end rb_mon;
architecture sim of rb_mon is
begin
proc_moni: process
variable oline : line;
variable nhold : integer := 0;
variable nburst : integer := 0;
variable data : slv16 := (others=>'0');
variable tag : string(1 to 8) := (others=>' ');
variable err : slbit := '0';
variable r_sel : slbit := '0';
procedure write_data(L: inout line;
ptag: in string;
pdata: in slv16;
pnhold: in integer := 0;
pnburst: in integer := 0;
pcond: in boolean := false;
pctxt: in string := " ") is
begin
writetimestamp(L, CLK_CYCLE, ptag);
writehex(L, RB_MREQ.addr, right, 4);
write(L, string'(" "));
writegen(L, pdata, right, 0, DBASE);
write(L, string'(" "));
write(L, RB_STAT, right, 4);
writeoptint(L, " hold=", pnhold, 2);
writeoptint(L, " b=", pnburst, 2);
if pcond then
write(L, pctxt);
end if;
writeline(output, L);
end procedure write_data;
begin
loop
if ENA = '0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RB_MREQ.aval='1' and r_sel='0' then
nburst := 0;
end if;
if RB_MREQ.re='1' or RB_MREQ.we='1' then
if RB_SRES.err = '1' then
err := '1';
end if;
if RB_SRES.busy = '1' then
nhold := nhold + 1;
else
data := (others=>'0');
tag := ": ???? ";
if RB_MREQ.re = '1' then
data := RB_SRES.dout;
tag := ": rbre ";
end if;
if RB_MREQ.we = '1' then
data := RB_MREQ.din;
tag := ": rbwe ";
end if;
if RB_SRES.ack = '1' then
write_data(oline, tag, data, nhold, nburst, err='1', " ERR='1'");
else
write_data(oline, tag, data, nhold, nburst, true, " ACK='0'");
end if;
nburst := nburst + 1;
nhold := 0;
end if;
else
if nhold > 0 then
write_data(oline, tag, data, nhold, nburst, true, " TIMEOUT");
end if;
nhold := 0;
err := '0';
end if;
if RB_MREQ.init = '1' then -- init
write_data(oline, ": rbini ", RB_MREQ.din);
end if;
if unsigned(RB_LAM) /= 0 then
write_data(oline, ": rblam ", RB_LAM, 0, 0, true, " RB_LAM active");
end if;
r_sel := RB_MREQ.aval;
end loop;
end process proc_moni;
proc_check: process (CLK)
variable r_sel : slbit := '0';
variable r_addr : slv16 := (others=>'0');
variable idump : boolean := false;
variable oline : line;
begin
if rising_edge(CLK) then
idump := false;
-- check that addr doesn't change after 1st aval cycle
if r_sel='1' and RB_MREQ.addr /= r_addr then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: addr changed after aval; initial addr=");
writehex(oline, r_addr, right, 4);
writeline(output, oline);
idump := true;
end if;
-- check that we,re don't come together in core select time
-- (aval and r_sel) and not at all outside
if RB_MREQ.aval='1' and r_sel='1' then
if RB_MREQ.we='1' and RB_MREQ.re='1' then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: we and re both active");
writeline(output, oline);
idump := true;
end if;
if RB_MREQ.init='1' then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: init seen inside select");
writeline(output, oline);
idump := true;
end if;
else
if RB_MREQ.we='1' or RB_MREQ.re='1' then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: no select and we,re seen");
writeline(output, oline);
idump := true;
end if;
end if;
-- check that init not seen when aval or select is active
if RB_MREQ.aval='1' or r_sel='1' then
if RB_MREQ.init='1' then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: init seen inside aval or select");
writeline(output, oline);
idump := true;
end if;
end if;
-- check that SRES isn't touched unless aval or select is active
if RB_MREQ.aval='0' and r_sel='0' then
if RB_SRES.dout/=x"0000" or RB_SRES.busy='1' or
RB_SRES.ack='1' or RB_SRES.err='1' then
writetimestamp(oline, CLK_CYCLE,
": FAIL rb_mon: SRES driven outside aval or select");
writeline(output, oline);
idump := true;
end if;
end if;
-- dump rbus state in case of any error seen above
if idump then
write(oline, string'(" FAIL: MREQ aval="));
write(oline, RB_MREQ.aval, right, 1);
write(oline, string'(" re="));
write(oline, RB_MREQ.re , right, 1);
write(oline, string'(" we="));
write(oline, RB_MREQ.we , right, 1);
write(oline, string'(" init="));
write(oline, RB_MREQ.init, right, 1);
write(oline, string'(" sel="));
write(oline, r_sel , right, 1);
write(oline, string'(" addr="));
writehex(oline, RB_MREQ.addr, right, 4);
write(oline, string'(" din="));
writehex(oline, RB_MREQ.din, right, 4);
writeline(output, oline);
write(oline, string'(" FAIL: SRES ack="));
write(oline, RB_SRES.ack , right, 1);
write(oline, string'(" busy="));
write(oline, RB_SRES.busy, right, 1);
write(oline, string'(" err="));
write(oline, RB_SRES.err , right, 1);
write(oline, string'(" dout="));
writehex(oline, RB_SRES.dout, right, 4);
writeline(output, oline);
end if;
-- keep track of select state and latch current addr
if RB_MREQ.aval='1' and r_sel='0' then -- if 1st cycle of aval
r_addr := RB_MREQ.addr; -- latch addr
end if;
-- select simply aval if last cycle (assume all addr are valid)
r_sel := RB_MREQ.aval;
end if;
end process proc_check;
end sim;
| gpl-3.0 | 9829c6b2b53787d5a3f7539d80babf90 | 0.513387 | 3.546263 | false | false | false | false |
mr-kenhoff/Bitmap-VHDL-Package | rtl/bmp_sink.vhd | 1 | 3,142 | -------------------------------------------------------------------------------
-- File : bmp_sink.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Takes a data stream and saves it to a bitmap image
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bmp_pkg.all;
entity bmp_sink is
generic (
FILENAME : string;
SEQUENCE : string := "TRUE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
val_i : in std_logic;
dat_i : in std_logic_vector(23 downto 0);
rdy_o : out std_logic := '1';
eol_i : in std_logic;
eof_i : in std_logic;
halt_i : in std_logic
);
end entity;
architecture behavioural of bmp_sink is
signal x : natural := 0;
signal y : natural := 0;
signal iteration : integer := 0;
begin
rdy_o <= not halt_i when rising_edge(clk_i);
sink_process : process( clk_i )
variable sink_bmp : bmp_ptr;
variable sink_pix : bmp_pix;
variable is_bmp_created : boolean := false;
variable is_bmp_saved : boolean := false;
begin
-- Create bitmap on startup
if is_bmp_created = false then
sink_bmp := new bmp;
is_bmp_created := true;
end if;
if rising_edge( clk_i ) then
if rst_i = '1' then
x <= 0;
y <= 0;
else
if val_i = '1' and halt_i = '0' then
sink_pix.r := dat_i(23 downto 16);
sink_pix.g := dat_i(15 downto 8);
sink_pix.b := dat_i(7 downto 0);
bmp_set_pix( sink_bmp, x, y, sink_pix );
if eol_i = '1' then
x <= 0;
if eof_i = '1' then
y <= 0;
-- Frame completed. Save to bitmap..
if SEQUENCE = "FALSE" then
if is_bmp_saved = false then
bmp_save( sink_bmp, FILENAME & ".bmp" );
is_bmp_saved := true;
end if;
elsif SEQUENCE = "TRUE" then
bmp_save( sink_bmp, FILENAME & "_" & INTEGER'IMAGE(iteration) & ".bmp" );
is_bmp_saved := true;
end if;
iteration <= iteration + 1;
else
y <= y + 1;
end if;
else
x <= x + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
| mit | ec0b6cd22d5862d0d6c444669aff3ac7 | 0.370783 | 4.573508 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd | 1 | 11,798 | -- $Id: sys_tst_rlink_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n4 - syn
-- Description: rlink tester design for nexys4
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_4line_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/bpgen/rgbdrv_master
-- bplib/bpgen/rgbdrv_analog_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_2
-- vlib/rbus/rb_sres_or_6
--
-- Test bench: tb/tb_tst_rlink_n4
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-02-02 1108 2018.3 xc7a100t-1 1179 1725 36 3.0 606
-- 2019-02-02 1108 2017.2 xc7a100t-1 1179 1813 36 3.0 627
-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc
-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf
-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC
-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB
-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice
-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access)
-- 2016-03-19 748 1.5.1 define rlink SYSID
-- 2016-03-12 741 1.5 add sysmon_rbus
-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2015-02-06 643 1.4 factor out memory
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-09-28 535 1.0 Initial version (derived from sys_tst_rlink_n3)
------------------------------------------------------------------------------
-- Usage of Nexys 4 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): -unused-
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n4 is -- top level
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_rlink_n4;
architecture syn of sys_tst_rlink_n4 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RGBCNTL : slv3 := (others=>'0');
signal DIMCNTL : slv12 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"05"; -- nexys4
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good up to 127 MHz
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RGBMSTR : rgbdrv_master
generic map (
DWIDTH => DIMCNTL'length)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL
);
RGB0 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB0,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED0
);
RGB1 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb1)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB1,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED1
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_ORRGB : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_RGB0,
RB_SRES_2 => RB_SRES_RGB1,
RB_SRES_OR => RB_SRES_RGB
);
RB_SRES_OR1 : rb_sres_or_6
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_3 => RB_SRES_RGB,
RB_SRES_4 => RB_SRES_SYSMON,
RB_SRES_5 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(15 downto 0) <= (others=>'0');
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(15 downto 8) <= SWI(15 downto 8);
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | dc7415c5ff3f656f9c2a4e00ac642be5 | 0.507628 | 3.130273 | false | false | false | false |
jsyk/spnsyn-demo | t/ftlbase.vhd | 1 | 1,126 | library ieee;
use ieee.std_logic_1164.all;
package ftlbase is
constant ZERO_std_ulogic : std_ulogic := '0';
constant UNDEF_std_ulogic : std_ulogic := 'U';
function to_bool(x: std_ulogic) return boolean;
function to_stdulogic(x: boolean) return std_ulogic;
function zero_std_logic_vector(hi: integer; lo: integer) return std_logic_vector;
function undef_std_logic_vector(hi: integer; lo: integer) return std_logic_vector;
end;
package body ftlbase is
function to_bool(x: std_ulogic) return boolean is
begin
return (x = '1');
end function to_bool;
function to_stdulogic(x: boolean) return std_ulogic is
begin
if x then
return '1';
else
return '0';
end if;
end function;
function zero_std_logic_vector(hi: integer; lo: integer) return std_logic_vector is
variable v : std_logic_vector(hi downto lo) := (others => '0');
begin
return v;
end function zero_std_logic_vector;
function undef_std_logic_vector(hi: integer; lo: integer) return std_logic_vector is
variable v : std_logic_vector(hi downto lo) := (others => 'U');
begin
return v;
end function undef_std_logic_vector;
end;
| gpl-2.0 | 714131d82ebbf235ecbe8b1344499ba5 | 0.711368 | 3.189802 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/UART6_RX.unconstrained.vhdl | 1 | 17,373 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_rx6_unconstrained is
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_rx6_unconstrained;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_rx6
--
architecture rtl of uart_rx6_unconstrained is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_rx6
--
-------------------------------------------------------------------------------------------
--
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sample_value : std_logic;
signal sample : std_logic;
signal sample_dly_value : std_logic;
signal sample_dly : std_logic;
signal stop_bit_value : std_logic;
signal stop_bit : std_logic;
signal data_value : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal run_value : std_logic;
signal run : std_logic;
signal start_bit_value : std_logic;
signal start_bit : std_logic;
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal div_carry : std_logic;
signal sample_input_value : std_logic;
signal sample_input : std_logic;
signal buffer_write_value : std_logic;
signal buffer_write : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
-- attribute hblknm of pointer3_lut : label is "uart_rx6_1";
-- attribute hblknm of pointer3_flop : label is "uart_rx6_1";
-- attribute hblknm of pointer2_lut : label is "uart_rx6_1";
-- attribute hblknm of pointer2_flop : label is "uart_rx6_1";
-- attribute hblknm of pointer01_lut : label is "uart_rx6_1";
-- attribute hblknm of pointer1_flop : label is "uart_rx6_1";
-- attribute hblknm of pointer0_flop : label is "uart_rx6_1";
-- attribute hblknm of data_present_lut : label is "uart_rx6_1";
-- attribute hblknm of data_present_flop : label is "uart_rx6_1";
-- --
-- attribute hblknm of data01_lut : label is "uart_rx6_2";
-- attribute hblknm of data0_flop : label is "uart_rx6_2";
-- attribute hblknm of data1_flop : label is "uart_rx6_2";
-- attribute hblknm of data23_lut : label is "uart_rx6_2";
-- attribute hblknm of data2_flop : label is "uart_rx6_2";
-- attribute hblknm of data3_flop : label is "uart_rx6_2";
-- attribute hblknm of data45_lut : label is "uart_rx6_2";
-- attribute hblknm of data4_flop : label is "uart_rx6_2";
-- attribute hblknm of data5_flop : label is "uart_rx6_2";
-- attribute hblknm of data67_lut : label is "uart_rx6_2";
-- attribute hblknm of data6_flop : label is "uart_rx6_2";
-- attribute hblknm of data7_flop : label is "uart_rx6_2";
-- --
-- attribute hblknm of div01_lut : label is "uart_rx6_3";
-- attribute hblknm of div23_lut : label is "uart_rx6_3";
-- attribute hblknm of div0_flop : label is "uart_rx6_3";
-- attribute hblknm of div1_flop : label is "uart_rx6_3";
-- attribute hblknm of div2_flop : label is "uart_rx6_3";
-- attribute hblknm of div3_flop : label is "uart_rx6_3";
-- attribute hblknm of sample_input_lut : label is "uart_rx6_3";
-- attribute hblknm of sample_input_flop : label is "uart_rx6_3";
-- attribute hblknm of full_lut : label is "uart_rx6_3";
-- --
-- attribute hblknm of sample_lut : label is "uart_rx6_4";
-- attribute hblknm of sample_flop : label is "uart_rx6_4";
-- attribute hblknm of sample_dly_flop : label is "uart_rx6_4";
-- attribute hblknm of stop_bit_lut : label is "uart_rx6_4";
-- attribute hblknm of stop_bit_flop : label is "uart_rx6_4";
-- attribute hblknm of buffer_write_flop : label is "uart_rx6_4";
-- attribute hblknm of start_bit_lut : label is "uart_rx6_4";
-- attribute hblknm of start_bit_flop : label is "uart_rx6_4";
-- attribute hblknm of run_lut : label is "uart_rx6_4";
-- attribute hblknm of run_flop : label is "uart_rx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_rx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_rx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
sample_lut: LUT6_2
generic map (INIT => X"CCF00000AACC0000")
port map( I0 => serial_in,
I1 => sample,
I2 => sample_dly,
I3 => en_16_x_baud,
I4 => '1',
I5 => '1',
O5 => sample_value,
O6 => sample_dly_value);
sample_flop: FD
port map ( D => sample_value,
Q => sample,
C => clk);
sample_dly_flop: FD
port map ( D => sample_dly_value,
Q => sample_dly,
C => clk);
stop_bit_lut: LUT6_2
generic map (INIT => X"CAFFCAFF0000C0C0")
port map( I0 => stop_bit,
I1 => sample,
I2 => sample_input,
I3 => run,
I4 => data(0),
I5 => '1',
O5 => buffer_write_value,
O6 => stop_bit_value);
buffer_write_flop: FD
port map ( D => buffer_write_value,
Q => buffer_write,
C => clk);
stop_bit_flop: FD
port map ( D => stop_bit_value,
Q => stop_bit,
C => clk);
data01_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(0),
O6 => data_value(1));
data0_flop: FD
port map ( D => data_value(0),
Q => data(0),
C => clk);
data1_flop: FD
port map ( D => data_value(1),
Q => data(1),
C => clk);
data23_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(2),
I1 => data(3),
I2 => data(4),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(2),
O6 => data_value(3));
data2_flop: FD
port map ( D => data_value(2),
Q => data(2),
C => clk);
data3_flop: FD
port map ( D => data_value(3),
Q => data(3),
C => clk);
data45_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(4),
O6 => data_value(5));
data4_flop: FD
port map ( D => data_value(4),
Q => data(4),
C => clk);
data5_flop: FD
port map ( D => data_value(5),
Q => data(5),
C => clk);
data67_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(6),
I1 => data(7),
I2 => stop_bit,
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(6),
O6 => data_value(7));
data6_flop: FD
port map ( D => data_value(6),
Q => data(6),
C => clk);
data7_flop: FD
port map ( D => data_value(7),
Q => data(7),
C => clk);
run_lut: LUT6
generic map (INIT => X"2F2FAFAF0000FF00")
port map( I0 => data(0),
I1 => start_bit,
I2 => sample_input,
I3 => sample_dly,
I4 => sample,
I5 => run,
O => run_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
start_bit_lut: LUT6
generic map (INIT => X"222200F000000000")
port map( I0 => start_bit,
I1 => sample_input,
I2 => sample_dly,
I3 => sample,
I4 => run,
I5 => '1',
O => start_bit_value);
start_bit_flop: FD
port map ( D => start_bit_value,
Q => start_bit,
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => run,
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"6CCC00005AAA0000")
port map( I0 => div(2),
I1 => div(3),
I2 => div_carry,
I3 => en_16_x_baud,
I4 => run,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
sample_input_lut: LUT6_2
generic map (INIT => X"0080000088888888")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_carry,
O6 => sample_input_value);
sample_input_flop: FD
port map ( D => sample_input_value,
Q => sample_input,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_rx6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | e6115f04c6112a6f94f68975adeeb74e | 0.499108 | 3.796547 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/OZ4_top.vhd | 2 | 10,210 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity OZ4_top is
port(clk : in std_logic;
rst : in std_logic;
--Basic IO
iport : in std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
oport : out std_logic_vector(31 downto 0);
opins : out std_logic_vector(7 downto 0);
--Instruction Memory
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : out std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
immediate_addr : out std_logic_vector(5 downto 0);
--Data Memory
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we_out : out std_logic;
mem_clk : out std_logic);
end OZ4_top;
architecture Behavioral of OZ4_top is
component ctl_unit is
port(clk : in std_logic;
rst : in std_logic;
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : out std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
immediate_addr : out std_logic_vector(5 downto 0);
ctl_immediate : out std_logic_vector(31 downto 0);
PC_data_out : in std_logic_vector(31 downto 0);
ALU_flags : in std_logic_vector(3 downto 0);
stack_e0 : in std_logic_vector(31 downto 0);
stack_e1 : in std_logic_vector(31 downto 0);
--Control signals
ALU_sel : out std_logic_vector(3 downto 0);
stack_e0_sel : out std_logic_vector(1 downto 0);
stack_e1_sel : out std_logic_vector(1 downto 0);
stack_e2_sel : out std_logic_vector(1 downto 0);
stack_e0_en : out std_logic;
stack_e1_en : out std_logic;
stack_e2_en : out std_logic;
stack_push : out std_logic;
stack_pop : out std_logic;
stack_pop2 : out std_logic;
RS_push : out std_logic;
RS_pop : out std_logic;
mem_we : out std_logic;
PC_load : out std_logic;
PC_inc : out std_logic;
IO_oport_en : out std_logic;
IO_opins_en : out std_logic;
stack_MUX_sel : out std_logic_vector(2 downto 0);
PC_MUX_sel : out std_logic);
end component;
component ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0);
flags : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component data_stack is
port(
clk : in std_logic;
rst : in std_logic;
e0_sel : in std_logic_vector(1 downto 0);
e1_sel : in std_logic_vector(1 downto 0);
e2_sel : in std_logic_vector(1 downto 0);
e0_en : in std_logic;
e1_en : in std_logic;
e2_en : in std_logic;
push : in std_logic;
pop : in std_logic;
pop2 : in std_logic;
data_in : in std_logic_vector(31 downto 0);
e0_out : out std_logic_vector(31 downto 0);
e1_out : out std_logic_vector(31 downto 0)
);
end component;
component return_stack is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
push : in std_logic;
pop : in std_logic
);
end component;
component prog_counter is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
load : in std_logic;
increment : in std_logic
);
end component;
component memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic;
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we : out std_logic;
mem_clk : out std_logic
);
end component;
component IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
ipins_data : out std_logic_vector(31 downto 0);
ipins_sel : in std_logic_vector(2 downto 0);
oport : out std_logic_vector(31 downto 0);
oport_data : in std_logic_vector(31 downto 0);
oport_en : in std_logic;
opins : out std_logic_vector(7 downto 0);
opins_data : in std_logic_vector(31 downto 0);
opins_sel : in std_logic_vector(2 downto 0);
opins_en : in std_logic
);
end component;
component stack_in_MUX is
port(sel : in std_logic_vector(2 downto 0);
ctl_immediate : in std_logic_vector(31 downto 0);
ALU_result : in std_logic_vector(31 downto 0);
IO_ipins_data : in std_logic_vector(31 downto 0);
IO_iport_data : in std_logic_vector(31 downto 0);
mem_data_out : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end component;
component PC_MUX is
port(sel : in std_logic;
RS_top : in std_logic_vector(31 downto 0);
stack_e0 : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end component;
--Signals
--From the control unit
signal ctl_immediate : std_logic_vector(31 downto 0);
--ALU
signal ALU_sel : std_logic_vector(3 downto 0);
signal ALU_result : std_logic_vector(31 downto 0);
signal ALU_flags : std_logic_vector(3 downto 0);
--Data Stack
signal stack_e0_sel, stack_e1_sel, stack_e2_sel: std_logic_vector(1 downto 0);
signal stack_e0_en, stack_e1_en, stack_e2_en : std_logic;
signal stack_push, stack_pop, stack_pop2 : std_logic;
signal stack_e0, stack_e1 : std_logic_vector(31 downto 0);
--Return Stack
signal RS_top : std_logic_vector(31 downto 0);
signal RS_push, RS_pop : std_logic;
--Memory Controller
signal mem_data_out : std_logic_vector(31 downto 0);
signal mem_we : std_logic;
--Program Counter
signal PC_data_out, PC_data_out_2 : std_logic_vector(31 downto 0);
signal PC_load, PC_inc : std_logic;
--I/O Controller
signal IO_iport_data, IO_ipins_data : std_logic_vector(31 downto 0);
signal IO_oport_en, IO_opins_en : std_logic;
--Multiplexers
signal stack_MUX_sel : std_logic_vector(2 downto 0);
signal stack_MUX_out : std_logic_vector(31 downto 0);
signal PC_MUX_sel : std_logic;
signal PC_MUX_out : std_logic_vector(31 downto 0);
begin
--The control unit
ctl : ctl_unit
port map(
clk => clk,
rst => rst,
instruction_in => instruction_in,
instruction_addr => instruction_addr,
immediate_in => immediate_in,
immediate_addr => immediate_addr,
ctl_immediate => ctl_immediate,
PC_data_out => PC_data_out,
ALU_flags => ALU_flags,
stack_e0 => stack_e0,
stack_e1 => stack_e1,
ALU_sel => ALU_sel,
stack_e0_sel => stack_e0_sel,
stack_e1_sel => stack_e1_sel,
stack_e2_sel => stack_e2_sel,
stack_e0_en => stack_e0_en,
stack_e1_en => stack_e1_en,
stack_e2_en => stack_e2_en,
stack_push => stack_push,
stack_pop => stack_pop,
stack_pop2 => stack_pop2,
RS_push => RS_push,
RS_pop => RS_pop,
mem_we => mem_we,
PC_load => PC_load,
PC_inc => PC_inc,
IO_oport_en => IO_oport_en,
IO_opins_en => IO_opins_en,
stack_MUX_sel => stack_MUX_sel,
PC_MUX_sel => PC_MUX_sel
);
--The ALU
arith : ALU
port map(
A => stack_e0,
B => stack_e1,
sel => ALU_sel,
result => ALU_result,
flags => ALU_flags
);
--The data stack
DS : data_stack
port map(
clk => clk,
rst => rst,
e0_sel => stack_e0_sel,
e1_sel => stack_e1_sel,
e2_sel => stack_e2_sel,
e0_en => stack_e0_en,
e1_en => stack_e1_en,
e2_en => stack_e2_en,
push => stack_push,
pop => stack_pop,
pop2 => stack_pop2,
data_in => stack_MUX_out,
e0_out => stack_e0,
e1_out => stack_e1
);
--The return stack
RS : return_stack
port map(
clk => clk,
rst => rst,
data_in => PC_data_out_2,
data_out => RS_top,
push => RS_push,
pop => RS_pop
);
--The memory controller
mem_ctl : memory_control
port map(
clk => clk,
rst => rst,
address => stack_e0,
data_in => stack_e1,
data_out => mem_data_out,
we => mem_we,
mem_addr => mem_addr,
mem_write_data => mem_write_data,
mem_read_data => mem_read_data,
mem_we => mem_we_out,
mem_clk => mem_clk
);
--The program counter
PC : prog_counter
port map(
clk => clk,
rst => rst,
data_in => PC_MUX_out,
data_out => PC_data_out,
load => PC_load,
increment => PC_inc
);
PC_data_out_2 <= PC_data_out + 2; --For pushing the program counter
--I/O controller
IO : IO_ctl
port map(
clk => clk,
rst => rst,
iport => iport,
iport_data => IO_iport_data,
ipins => ipins,
ipins_data => IO_ipins_data,
ipins_sel => stack_e0(2 downto 0),
oport => oport,
oport_data => stack_e0,
oport_en => IO_oport_en,
opins => opins,
opins_data => stack_e1,
opins_sel => stack_e0(2 downto 0),
opins_en => IO_opins_en
);
--MUX that selects which bus goes onto the stack
DS_MUX : stack_in_MUX
port map(
sel => stack_MUX_sel,
ctl_immediate => ctl_immediate,
ALU_result => ALU_result,
IO_ipins_data => IO_ipins_data,
IO_iport_data => IO_iport_data,
mem_data_out => mem_data_out,
output => stack_MUX_out
);
--MUX that selects whether the top of the return stack or data stack goes to the PC
prog_MUX : PC_MUX
port map(
sel => PC_MUX_sel,
RS_top => RS_top,
stack_e0 => stack_e0,
output => PC_MUX_out
);
end Behavioral;
| mit | 886b44e1ad878843a811927b2641f7ee | 0.597943 | 2.950014 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swar_1ar_gen.vhd | 1 | 3,060 | -- $Id: ram_1swar_1ar_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- The code is inspired by Xilinx example rams_09.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2010-06-03 (r123) with ise 11.4 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm RAM16X1D MUXF5 MUXF6 MUXF7
-- 4 16 - 32 16 0 0 0
-- 5 16 34 64 32 0 0 0
-- 6 16 68 128 64 32 0 0
-- 7 16 136 256 128 64 32 0
-- 8 16 292 512 256 144 64 32
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- {same results as above for AW=4 and 6}
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
architecture syn of ram_1swar_1ar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDRA))) <= DI;
end if;
end if;
end process proc_clk;
DOA <= RAM(to_integer(unsigned(ADDRA)));
DOB <= RAM(to_integer(unsigned(ADDRB)));
end syn;
| gpl-3.0 | 190234de3ae4f3851baa1298ea664167 | 0.544118 | 3.388704 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | reg.vhd | 1 | 624 | library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic(
DATA_WIDTH : natural := 32
);
port(
clk, rst, en : in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end reg;
architecture rtl of reg is
signal Temp: std_logic_vector((DATA_WIDTH-1) downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
Temp <= (others => '0');
elsif (clk'event and clk='0')then -- ver a borda!
if (en='1') then
Temp <= D;
end if;
end if;
end process;
Q <= Temp;
end rtl; | mit | 84919089d23e3be71921bc584b5cb243 | 0.5625 | 2.773333 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd | 1 | 7,461 | -- $Id: tb_nexys4_cram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_cram - sim
-- Description: Test bench for nexys4 (base+cram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.2 use sfs_gsim_core
-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
-- 2016-07-20 791 1.3 use simbididly
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4_cram is
end tb_nexys4_cram;
architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_BE_N : slv2 := (others=>'1');
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADV_N : slbit := '1';
signal TB_MEM_CLK : slbit := '0';
signal TB_MEM_CRE : slbit := '0';
signal TB_MEM_WAIT : slbit := '0';
signal TB_MEM_ADDR : slv23 := (others=>'Z');
signal TB_MEM_DATA : slv16 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_cram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_BE_N => TB_MEM_BE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADV_N => TB_MEM_ADV_N,
O_MEM_CLK => TB_MEM_CLK,
O_MEM_CRE => TB_MEM_CRE,
I_MEM_WAIT => TB_MEM_WAIT,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= TB_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= TB_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= TB_MEM_CLK after pcb_delay;
MM_MEM_CRE <= TB_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
TB_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | d2369a50fdc40c7b39410f7c0dcc96b3 | 0.534781 | 2.970143 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd | 1 | 3,655 | -- $Id: sys_tst_snhumanio_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_b3 - syn
-- Description: snhumanio tester design for basys3
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022--7-05 1247 2022.1 xc7a35t-1 154 161 0 0 67
-- 2019-02-02 1108 2018.3 xc7a35t-1 154 187 0 0 75
-- 2019-02-02 1108 2017.2 xc7a35t-1 154 184 0 0 69
-- 2015-01-30 636 2014.4 xc7a35t-1 154 133 0 0 63
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-16 636 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Basys 3 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_b3 is -- top level
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_snhumanio_b3;
architecture syn of sys_tst_snhumanio_b3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI(7 downto 0),
I_BTN => I_BTN,
O_LED => O_LED(7 downto 0),
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
O_LED(15 downto 8) <= not I_SWI(15 downto 8);
end syn;
| gpl-3.0 | 610fea6f1799231f3d90ce464559a9b8 | 0.45855 | 3.444863 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/migui_artys7_gsim.vhd | 1 | 5,386 | -- $Id: migui_artys7_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui_artys7 - sim
-- Description: MIG generated for artys7 - simple simulator
--
-- Dependencies: bplib/mig/migui_core_gsim
-- Test bench: tb_tst_sram_artys7
-- Target Devices: artys7 board
-- Tool versions: viv 2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (cloned from migui_arty_gsim)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.miglib.all;
use work.miglib_artys7.all;
entity migui_artys7 is -- MIG generated for artys7
port (
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end migui_artys7;
architecture sim of migui_artys7 is
begin
MIG_SIM : migui_core_gsim
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth,
SAWIDTH => 24,
CLKMUI_MUL => 7,
CLKMUI_DIV => 14)
port map (
SYS_CLK => SYS_CLK_I,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK
);
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
APP_SR_ACTIVE <= '0';
end sim;
| gpl-3.0 | 36bde607e00735d6bbf92558e1bd10ce | 0.495173 | 3.353674 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd | 1 | 2,926 | -- $Id: ram_1swsr_wfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_rfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- The 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Notes: For xst 8.1.03i: can be written with a signal or a shared
-- variable declared at the architecture level. Use variable
-- because this seemed better for simulation. Using a simple
-- variable declared at process level leads to an array of
-- registers and a big mux.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swsr_wfirst_gen;
architecture syn of ram_1swsr_wfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DO : slv(DWIDTH-1 downto 0) := datzero;
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if EN = '1' then
if WE = '1' then
sv_ram(to_integer(unsigned(ADDR))) := DI;
end if;
R_DO <= sv_ram(to_integer(unsigned(ADDR)));
end if;
end if;
end process proc_clk;
DO <= R_DO;
end syn;
| gpl-3.0 | 8fe14a2b4e45ef34065e9d36b24ffeec | 0.566644 | 3.599016 | false | false | false | false |
sjohann81/hf-risc | devices/peripherals/basic_soc.vhd | 1 | 13,162 | -- file: basic_soc.vhd
-- description: basic SoC with peripherals
-- date: 07/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Basic SoC configuration template for prototyping. Dual GPIO ports,
-- a counter, a timer and a UART are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal paaltcfg0: std_logic_vector(23 downto 0);
signal s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(15 downto 0);
signal pbddr, pbout, pbin, pbin_inv, pbin_mask: std_logic_vector(15 downto 0);
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_gpiob, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal paalt0, paalt2, paalt8, paalt10: std_logic;
signal int_uart, uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "0000" else '0';
s0cause <= int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "00" & int_gpiob & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_gpiob <= '1' when ((pbin xor pbin_inv) and pbin_mask) /= "0000" else '0';
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
pain <= gpioa_in(15 downto 0);
gpioa_out <= paout(15 downto 11) & paalt10 & paout(9) & paalt8 & paout(7 downto 3) & paalt2 & paout(1) & paalt0;
gpioa_ddr <= paddr;
pbin <= gpiob_in(15 downto 0);
gpiob_out <= pbout;
gpiob_ddr <= pbddr;
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= "00" & uart0_write_busy & uart0_data_avail;
paalt0 <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt2 <= uart0_tx when paaltcfg0(5 downto 4) = "01" else paout(2);
paalt8 <= int_timer1_ctc when paaltcfg0(17 downto 16) = "01" else int_timer1_ocr when paaltcfg0(17 downto 16) = "10" else paout(8);
paalt10 <= uart0_tx when paaltcfg0(21 downto 20) = "01" else paout(10);
uart0_rx <= gpioa_in(3) when paaltcfg0(7 downto 6) = "01" else gpioa_in(11) when paaltcfg0(23 downto 22) = "01" else '1';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"0000000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= x"00" & paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"0000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"0000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"0000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"0000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"0000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
data_o <= x"0000" & pbddr;
when "0001" => -- PBOUT (RW)
data_o <= x"0000" & pbout;
when "0010" => -- PBIN (RO)
data_o <= x"0000" & pbin;
when "0011" => -- PBIN_INV (RW)
data_o <= x"0000" & pbin_inv;
when "0100" => -- PBIN_MASK (RW)
data_o <= x"0000" & pbin_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
pbout <= (others => '0');
pbin_inv <= (others => '0');
pbin_mask <= (others => '0');
pbddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(23 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(15 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(15 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(15 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
pbddr <= data_i(15 downto 0);
when "0001" => -- PBOUT (RW)
pbout <= data_i(15 downto 0);
when "0011" => -- PBIN_INV (RW)
pbin_inv <= data_i(15 downto 0);
when "0100" => -- PBIN_MASK (RW)
pbin_mask <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
end peripherals_arch;
| gpl-2.0 | 51c7d0832f427323b4c7e877268bbc23 | 0.54361 | 2.795073 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_dl11_buf.vhd | 1 | 15,868 | -- $Id: ibdr_dl11_buf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11_buf - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-31 1156 1.0.1 size->fuse rename; re-organize rlim handling
-- 2019-04-26 1139 1.0 Initial version (derived from ibdr_{dl11,pc11_buf})
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11_buf is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16));
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11_buf;
architecture syn of ibdr_dl11_buf is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
subtype rcsr_ibf_type is integer range 10 downto 8;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_rlb : integer := 4;
constant rcsr_ibf_fclr : integer := 1;
subtype rbuf_ibf_rfuse is integer range AWIDTH-1+8 downto 8;
subtype rbuf_ibf_xfuse is integer range AWIDTH-1 downto 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
subtype xcsr_ibf_xrlim is integer range 14 downto 12;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xir : integer := 5;
constant xcsr_ibf_rlb : integer := 4;
constant xcsr_ibf_fclr : integer := 1;
constant xbuf_ibf_xval : integer := 15;
subtype xbuf_ibf_fuse is integer range AWIDTH-1+8 downto 8;
subtype xbuf_ibf_data is integer range 7 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rintreq : slbit; -- rx interrupt request
xrlim : slv3; -- xcsr: transmitter rate limit
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"000", -- rrlim
'0','0','0', -- rdone,rie,rintreq
"000", -- xrlim
'1', -- xrdy !! is set !!
'0', -- xie
'0' -- xintreq
);
constant c_fuse1 : slv(AWIDTH-1 downto 0) := slv(to_unsigned(1,AWIDTH));
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RBUF_CE : slbit := '0';
signal RBUF_WE : slbit := '0';
signal RBUF_DO : slv8 := (others=>'0');
signal RBUF_RESET : slbit := '0';
signal RBUF_EMPTY : slbit := '0';
signal RBUF_FULL : slbit := '0';
signal RBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal XBUF_CE : slbit := '0';
signal XBUF_WE : slbit := '0';
signal XBUF_DO : slv8 := (others=>'0');
signal XBUF_RESET : slbit := '0';
signal XBUF_EMPTY : slbit := '0';
signal XBUF_FULL : slbit := '0';
signal XBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
signal XRLIM_START : slbit := '0';
signal XRLIM_BUSY : slbit := '0';
begin
assert AWIDTH>=4 and AWIDTH<=7
report "assert(AWIDTH>=4 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
RBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RBUF_RESET,
CE => RBUF_CE,
WE => RBUF_WE,
DI => IB_MREQ.din(rbuf_ibf_data),
DO => RBUF_DO,
EMPTY => RBUF_EMPTY,
FULL => RBUF_FULL,
SIZE => RBUF_FUSE
);
XBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => XBUF_RESET,
CE => XBUF_CE,
WE => XBUF_WE,
DI => IB_MREQ.din(xbuf_ibf_data),
DO => XBUF_DO,
EMPTY => XBUF_EMPTY,
FULL => XBUF_FULL,
SIZE => XBUF_FUSE
);
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
XRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.xrlim,
START => XRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => XRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- keep RRLIM field
R_REGS.xrlim <= N_REGS.xrlim; -- keep XRLIM field
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RESET,
RBUF_DO, RBUF_EMPTY, RBUF_FULL, RBUF_FUSE, RRLIM_BUSY,
XBUF_DO, XBUF_EMPTY, XBUF_FULL, XBUF_FUSE, XRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irbufce : slbit := '0';
variable irbufwe : slbit := '0';
variable irbufrst : slbit := '0';
variable irrlimsta : slbit := '0';
variable ixbufce : slbit := '0';
variable ixbufwe : slbit := '0';
variable ixbufrst : slbit := '0';
variable ixrlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irbufce := '0';
irbufwe := '0';
irbufrst := RESET;
irrlimsta := '0';
ixbufce := '0';
ixbufwe := '0';
ixbufrst := RESET;
ixrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then -- rcsr write
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rdone='1' and r.rie='0' then -- ie 0->1 while done=1
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupt
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
idout(rcsr_ibf_type) := slv(to_unsigned(AWIDTH,3));
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_rlb) := RRLIM_BUSY;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
if ibw0 = '1' then
if IB_MREQ.din(rcsr_ibf_fclr) = '1' then -- 1 written to FCLR
irbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := RBUF_DO;
if ibrd = '1' then -- rbuf read
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- cancel interrupt
if r.rdone='1' then -- data available ?
irbufce := '1'; -- read next from fifo
irbufwe := '0';
if RBUF_FUSE = c_fuse1 then -- last value (fuse=1) ?
ilam := '1'; -- rri lam
end if;
end if;
end if;
else -- rri ---------------------
idout(rbuf_ibf_rfuse) := RBUF_FUSE;
idout(rbuf_ibf_xfuse) := XBUF_FUSE;
if ibw0 = '1' then
if RBUF_FULL = '0' then -- fifo not full
irbufce := '1'; -- write to fifo
irbufwe := '1';
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then-- set IE to 1
if r.xrdy='1' and r.xie='0' then -- ie 0->1 while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.xintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(xcsr_ibf_xrlim) := r.xrlim;
idout(xcsr_ibf_xir) := r.xintreq;
idout(xcsr_ibf_rlb) := XRLIM_BUSY;
if ibw1 = '1' then
n.xrlim := IB_MREQ.din(xcsr_ibf_xrlim); -- set XRLIM field
end if;
if ibw0 = '1' then
if IB_MREQ.din(xcsr_ibf_fclr) = '1' then -- 1 written to FCLR
ixbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.xrdy = '1' then -- ignore buf write when rdy=0
n.xrdy := '0'; -- clear ready
n.xintreq := '0'; -- cancel interrupt
if XBUF_FULL = '0' then -- fifo not full
ixbufce := '1'; -- write to fifo
ixbufwe := '1';
if XBUF_EMPTY = '1' then -- first write to empty fifo
ilam := '1'; -- request attention
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(xbuf_ibf_xval) := not XBUF_EMPTY;
idout(xbuf_ibf_fuse) := XBUF_FUSE;
idout(xbuf_ibf_data) := XBUF_DO;
if ibrd = '1' then
if XBUF_EMPTY = '0' then -- fifo not empty
ixbufce := '1'; -- read from fifo
ixbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when others => null;
end case;
else -- ibus not selected -----------------
-- handle rx done, timer and interrupt
if RBUF_EMPTY='0' and RRLIM_BUSY='0' then -- not empty and not busy ?
if r.rdone = '0' then -- done not set ?
n.rdone := '1'; -- set done
irrlimsta := '1'; -- start timer
if r.rie = '1' then -- irupts enabled ?
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
end if;
-- handle tx ready, timer and interrupt
if XBUF_FULL='0' and XRLIM_BUSY='0' then -- not full and not busy ?
if r.xrdy = '0' then -- ready not set ?
n.xrdy := '1'; -- set ready
ixrlimsta := '1'; -- start timer
if r.xie = '1' then -- irupts enabled ?
n.xintreq := '1'; -- request tx interrupt
end if;
end if;
end if;
end if; -- else r.ibsel='1'
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
RBUF_RESET <= irbufrst;
RBUF_CE <= irbufce;
RBUF_WE <= irbufwe;
RRLIM_START <= irrlimsta;
XBUF_RESET <= ixbufrst;
XBUF_CE <= ixbufce;
XBUF_WE <= ixbufwe;
XRLIM_START <= ixrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
| gpl-3.0 | 90bfb8820c11f88dd25bf9e771561d8f | 0.449143 | 3.915125 | false | false | false | false |
wfjm/w11 | rtl/bplib/nxcramlib/nxcramlib.vhd | 1 | 5,343 | -- $Id: nxcramlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: nxcramlib
-- Description: Nexys 2/3 CRAM controllers
--
-- Dependencies: -
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.1 add cram_(read0|read1|write)delay functions
-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nxcramlib is
pure function cram_delay(clk_mhz : positive;
delay_ps : positive) return positive;
pure function cram_read0delay(clk_mhz : positive) return positive;
pure function cram_read1delay(clk_mhz : positive) return positive;
pure function cram_writedelay(clk_mhz : positive) return positive;
constant cram_read0delay_ps : positive := 80000; -- initial read delay
constant cram_read1delay_ps : positive := 30000; -- page read delay
constant cram_writedelay_ps : positive := 75000; -- write delay
component nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
component nx_cram_memctl_as is -- CRAM controller (async+page mode)
generic (
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
end package nxcramlib;
-- ----------------------------------------------------------------------------
package body nxcramlib is
-- -------------------------------------
pure function cram_delay( -- calculate delay in clock cycles
clk_mhz : positive; -- clock frequency in MHz
delay_ps : positive) -- delay in ps
return positive is
variable period_ps : natural := 0; -- clk period in ps
begin
period_ps := 1000000 / clk_mhz;
return (delay_ps + period_ps - 10) / period_ps;
end function cram_delay;
-- -------------------------------------
pure function cram_read0delay( -- read0 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read0delay_ps);
end function cram_read0delay;
-- -------------------------------------
pure function cram_read1delay( -- read1 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read1delay_ps);
end function cram_read1delay;
-- -------------------------------------
pure function cram_writedelay( -- write delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_writedelay_ps);
end function cram_writedelay;
end package body nxcramlib;
| gpl-3.0 | b59490cd67accd17b68edf1e21787034 | 0.533595 | 3.978407 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | MIPS.vhd | 1 | 10,021 | library ieee;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
entity MIPS is
Port (
outs: out std_logic_vector(31 downto 0);
clk, rst: in std_logic
);
end MIPS;
architecture rtl of MIPS is
signal sig_OUT_PCP4_2, sig_OUT_jump, sig_OUT_memI_1, sig_inst, sig_regData, sig_dadoLido1, sig_dadoLido2,
sig_imediate_ext, sig_dadoLido1_1,sig_dadoLido2_1, sig_imediate_ext_1, sig_somInPC,
sig_IN2_ULA, sig_ULA_result, sig_OUT_PCP4_3, sig_in_PC, sig_out_PC,
sig_OUT_jump_1, sig_ULA_result_1, sig_dadoLido2_2, sig_OUT_memD,
sig_OUT_memD_1, sig_ULA_result_2, sig_OUT_PCP4_1: std_logic_vector(31 downto 0);
signal in_PIPE1, out_PIPE1: std_logic_vector(63 downto 0);
signal sig_opcode, sig_function : std_logic_vector(5 downto 0);
signal sig_ReadReg1, sig_ReadReg2, sig_regDest, sig_RegEsc, sig_ReadReg2_1, sig_regDest_1,
sig_RegEsc_1, sig_RegEsc_0, sig_RegEsc_2 : std_logic_vector (4 downto 0);
signal sig_imediate: std_logic_vector(15 downto 0);
signal sig_ulaOp, sig_ulaOp_1: std_logic_vector(1 downto 0);
signal sig_ulaFonte, sig_ulaFonte_1, sig_escMem, sig_escMem_1, sig_lerMem,
sig_lerMem_1, sig_DvC, sig_DvC_1, sig_memParaReg, sig_memParaReg_1, sig_fontePC, we3,
sig_escReg_1, sig_ULA_zero, sig_RegDST, sig_escMem_2, sig_lerMem_2,
sig_DvC_2, sig_memParaReg_2, sig_escReg_2, sig_ULA_zero_1, sig_memParaReg_3, sig_escReg_3, sig_escReg, sig_RegDST_1 : STD_LOGIC;
signal in_PIPE2, out_pipe2: std_logic_vector( 146 downto 0);
signal sig_operULA: std_logic_vector(3 downto 0);
signal in_PIPE3, out_PIPE3: std_logic_vector (106 downto 0);
signal in_PIPE4, out_PIPE4: std_logic_vector(70 downto 0);
component reg
generic(
DATA_WIDTH : natural := 8
);
port(
clk, rst, en : in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
END component ;
component memInst
PORT(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component memInst2
generic (
wlength: integer := 32;
words : integer := 10
);
Port(
data: IN std_logic_vector(wlength-1 downto 0);
address: IN std_logic_vector(words-1 downto 0);
clock, wren: IN std_logic;
q: OUT std_logic_vector(wlength-1 downto 0)
);
end component;
component memData
PORT(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component addSub
generic(
DATA_WIDTH : natural := 8
);
port(
a : in std_logic_vector ((DATA_WIDTH-1) downto 0);
b : in std_logic_vector ((DATA_WIDTH-1) downto 0);
add_sub : in std_logic;
result : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end component;
component mux2to1
generic(
DATA_WIDTH : natural := 32
);
port (
SEL : in STD_LOGIC;
A, B : in STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
X : out STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0)
);
end component;
component PC
generic(
DATA_WIDTH : natural := 5
);
port(
clk, rst: in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end component;
component regbank
port (
A1, A2, A3: in std_logic_vector(4 downto 0);
clk, rst, we3: in std_logic;
wd3: in std_logic_vector(31 downto 0);
out1, out2 : out std_logic_vector(31 downto 0)
);
end component;
component signalExtensor
Port (
in16: in std_logic_vector(15 downto 0);
out32: out std_logic_vector(31 downto 0)
);
end component;
component controller
PORT (
opcode : IN std_logic_vector(5 downto 0);
ulaOp : out std_logic_vector(1 downto 0);
RegDst, ulaFonte, escMem, lerMem, DvC, memParaReg, escReg : out std_logic
);
END component;
component flipflop
generic(
DATA_WIDTH : natural := 32
);
port(
clk, rst : in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end component;
component ULA
port (
in0, in1: in std_logic_vector(31 downto 0);
oper: in std_logic_vector(3 downto 0);
zero: out std_logic;
output : out std_logic_vector(31 downto 0)
);
end component;
component opULA
PORT (
ULAop :in std_logic_vector(1 downto 0);
funct :in std_logic_vector(5 downto 0);
oper :out std_logic_vector(3 downto 0)
);
END component;
begin
-- PRIMEIRO ESTÁGIO --
PC1: PC GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
clk => clk,
rst => rst,
D => sig_in_PC,
Q => sig_out_PC
);
mux_IN_PC: mux2to1 GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
sel => sig_fontePC,
A => sig_OUT_PCP4_1,
B => sig_OUT_jump_1,
X => sig_in_PC
);
PCP4: addSub GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
a => sig_out_PC,
b => "00000000000000000000000000000100", -- 4
add_sub => '1',
result => sig_OUT_PCP4_1
);
memI: memInst2 PORT MAP (
address => sig_out_PC(11 downto 2),
clock => clk,
data => (others => '0'),
wren => '0',
q => sig_OUT_memI_1
);
in_PIPE1 <= sig_OUT_PCP4_1 & sig_OUT_memI_1;
PIPE1: flipflop GENERIC MAP (DATA_WIDTH => 64) PORT MAP (
clk => clk,
rst => rst,
D => in_PIPE1,
Q => out_PIPE1
);
-- SEGUNDO ESTÁGIO --
sig_OUT_PCP4_2 <= out_PIPE1(63 downto 32);
sig_inst <= out_PIPE1(31 downto 0);
sig_opcode <= sig_inst(31 downto 26);
sig_ReadReg1 <= sig_inst(25 downto 21);
sig_ReadReg2 <= sig_inst(20 downto 16);
sig_imediate <= sig_inst(15 downto 0);
sig_regDest <= sig_inst(15 downto 11);
controle: controller PORT MAP (
opcode => sig_opcode,
ulaOp => sig_ulaOp,
RegDST => sig_RegDST,
ulaFonte => sig_ulaFonte,
escMem => sig_escMem,
lerMem => sig_lerMem,
DvC => sig_DvC,
memParaReg => sig_memParaReg,
escReg => sig_escReg
);
registradores: regbank PORT MAP (
A1 => sig_ReadReg1,
A2 => sig_ReadReg2,
A3 => sig_RegEsc_2,
clk => clk,
rst => rst,
we3 => sig_escReg_3,
wd3 => sig_regData,
out1 => sig_dadoLido1,
out2 => sig_dadoLido2
);
ExtSinal: signalExtensor PORT MAP (
in16 => sig_imediate,
out32 => sig_imediate_ext
);
in_PIPE2 <= sig_ulaOp & sig_RegDST & sig_ulaFonte & sig_escMem & sig_lerMem & sig_DvC & sig_memParaReg & sig_escReg & sig_OUT_PCP4_2 & sig_dadoLido1 & sig_dadoLido2 & sig_imediate_ext & sig_ReadReg2 & sig_regDest;
PIPE2: flipflop GENERIC MAP (DATA_WIDTH => 147) PORT MAP (
clk => clk,
rst => rst,
D => in_PIPE2,
Q => out_PIPE2
);
-- TERCEIRO ESTÁGIO --
sig_ulaOp_1 <= out_PIPE2(146 downto 145);
sig_RegDST_1 <= out_PIPE2(144);
sig_ulaFonte_1 <= out_PIPE2(143);
sig_escMem_1 <= out_PIPE2(142);
sig_lerMem_1 <= out_PIPE2(141);
sig_DvC_1 <= out_PIPE2(140);
sig_memParaReg_1 <= out_PIPE2(139);
sig_escReg_1 <= out_PIPE2(138);
sig_OUT_PCP4_3 <= out_PIPE2(137 downto 106);
sig_dadoLido1_1 <= out_PIPE2(105 downto 74);
sig_dadoLido2_1 <= out_PIPE2(73 downto 42);
sig_imediate_ext_1 <= out_PIPE2(41 downto 10);
sig_function <= sig_imediate_ext_1(5 downto 0);
sig_ReadReg2_1 <= out_PIPE2(9 downto 5);
sig_regDest_1 <= out_PIPE2(4 downto 0);
sig_somInPC <= sig_imediate_ext_1(29 downto 0) & "00";
inPC: addSub GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
a => sig_OUT_PCP4_3,
b => sig_somInPC, --b de 10 recebe de 32 --
add_sub => '1',
result => sig_OUT_jump
);
mux_IN_ULA_2: mux2to1 GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
sel => sig_ulaFonte_1,
A => sig_dadoLido2_1,
B => sig_imediate_ext_1,
X => sig_IN2_ULA
);
operaULA: opULA PORT MAP (
ULAop => sig_ulaOp_1,
funct => sig_function,
oper => sig_operULA
);
ULA1: ULA PORT MAP (
in0 => sig_dadoLido1_1,
in1 => sig_IN2_ULA,
oper => sig_operULA,
zero => sig_ULA_zero,
output => sig_ULA_result
);
muxEscReg: mux2to1 GENERIC MAP (DATA_WIDTH => 5) PORT MAP (
sel => sig_RegDST_1,
A => sig_ReadReg2_1,
B => sig_regDest_1,
X => sig_RegEsc_0
);
in_PIPE3 <= sig_escMem_1 & sig_lerMem_1 & sig_DvC_1 & sig_memParaReg_1 & sig_escReg_1 & sig_OUT_jump & sig_ULA_zero & sig_ULA_result & sig_dadoLido2_1 & sig_RegEsc_0;
PIPE3: flipflop GENERIC MAP (DATA_WIDTH => 107) PORT MAP (
clk => clk,
rst => rst,
D => in_PIPE3,
Q => out_PIPE3
);
-- QUARTO ESTÁGIO --
sig_escMem_2 <= out_PIPE3(106);
sig_lerMem_2 <= out_PIPE3(105);
sig_DvC_2 <= out_PIPE3(104);
sig_memParaReg_2 <= out_PIPE3(103);
sig_escReg_2 <= out_PIPE3(102);
sig_OUT_jump_1 <= out_PIPE3(101 downto 70);
sig_ULA_zero_1 <= out_PIPE3(69);
sig_ULA_result_1 <= out_PIPE3(68 downto 37);
sig_dadoLido2_2 <= out_PIPE3(36 downto 5);
sig_RegEsc_1 <= out_PIPE3(4 downto 0);
sig_fontePC <= sig_DvC_2 and sig_ULA_zero_1;
memD: memData PORT MAP (
address => sig_ULA_result_1(11 downto 2),
clock => clk,
data => sig_dadoLido2_2,
wren => sig_escMem_2,
q => sig_OUT_memD
);
in_PIPE4 <= sig_memParaReg_2 & sig_escReg_2 & sig_OUT_memD & sig_ULA_result_1 & sig_RegEsc_1;
PIPE4: flipflop GENERIC MAP (DATA_WIDTH => 71) PORT MAP (
clk => clk,
rst => rst,
D => in_PIPE4,
Q => out_PIPE4
);
-- QUINTO ESTÁGIO --
sig_memParaReg_3 <= out_PIPE4(70);
sig_escReg_3 <= out_PIPE4(69);
sig_OUT_memD_1 <= out_PIPE4(68 downto 37);
sig_ULA_result_2 <= out_PIPE4(36 downto 5);
sig_RegEsc_2 <= out_PIPE4(4 downto 0);
muxEscReg2: mux2to1 GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
sel => sig_memParaReg_3,
A => sig_ULA_result_2,
B => sig_OUT_memD_1,
X => sig_regData
);
outs <= sig_regData;
end rtl; | mit | dfb81d66041b1f440ad6bf7eff15baf5 | 0.61272 | 2.661706 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop2_n2.vhd | 1 | 8,280 | -- $Id: sys_tst_serloop2_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x
-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-09 437 1.0.4 rename serport stat->moni port
-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-12 423 1.0 Initial version
-- 2011-11-09 422 0.5 First draft
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop2_n2;
architecture syn of sys_tst_serloop2_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
DCM_U : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLKS,
LOCKED => open
);
CLKDIV_S : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLKS,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_2clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 5b510911d9311c5dbdad8c5c4eb4b6cd | 0.481039 | 3.208059 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | shifter.vhd | 1 | 6,149 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shifter is
port(
in_vec : in std_logic_vector (31 downto 0);
number : in std_logic_vector(4 downto 0);
dir : in std_logic;
out_vec : out std_logic_vector (31 downto 0)
);
end shifter;
architecture rtl of shifter is
begin
process (in_vec, number, dir)
begin
case number is
when "00001" =>
if dir = '1' then
out_vec <= in_vec(30 downto 0) & '0';
else
out_vec <= '1' & in_vec(31 downto 1);
end if;
when "00010" =>
if dir = '1' then
out_vec <= in_vec(29 downto 0) & "00";
else
out_vec <= "11" & in_vec(31 downto 2);
end if;
when "00011" =>
if dir = '1' then
out_vec <= in_vec(28 downto 0) & "000";
else
out_vec <= "111" & in_vec(31 downto 3);
end if;
when "00100" =>
if dir = '1' then
out_vec <= in_vec(27 downto 0) & "0000";
else
out_vec <= "1111" & in_vec(31 downto 4);
end if;
when "00101" =>
if dir = '1' then
out_vec <= in_vec(26 downto 0) & "00000";
else
out_vec <= "11111" & in_vec(31 downto 5);
end if;
when "00110" =>
if dir = '1' then
out_vec <= in_vec(25 downto 0) & "000000";
else
out_vec <= "111111" & in_vec(31 downto 6);
end if;
when "00111" =>
if dir = '1' then
out_vec <= in_vec(24 downto 0) & "0000000";
else
out_vec <= "1111111" & in_vec(31 downto 7);
end if;
when "01000" =>
if dir = '1' then
out_vec <= in_vec(23 downto 0) & "00000000";
else
out_vec <= "11111111" & in_vec(31 downto 8);
end if;
when "01001" =>
if dir = '1' then
out_vec <= in_vec(22 downto 0) & "000000000";
else
out_vec <= "111111111" & in_vec(31 downto 9);
end if;
when "01010" =>
if dir = '1' then
out_vec <= in_vec(21 downto 0) & "0000000000";
else
out_vec <= "1111111111" & in_vec(31 downto 10);
end if;
when "01011" =>
if dir = '1' then
out_vec <= in_vec(20 downto 0) & "00000000000";
else
out_vec <= "11111111111" & in_vec(31 downto 11);
end if;
when "01100" =>
if dir = '1' then
out_vec <= in_vec(19 downto 0) & "000000000000";
else
out_vec <= "111111111111" & in_vec(31 downto 12);
end if;
when "01101" =>
if dir = '1' then
out_vec <= in_vec(18 downto 0) & "0000000000000";
else
out_vec <= "1111111111111" & in_vec(31 downto 13);
end if;
when "01110" =>
if dir = '1' then
out_vec <= in_vec(17 downto 0) & "00000000000000";
else
out_vec <= "11111111111111" & in_vec(31 downto 14);
end if;
when "01111" =>
if dir = '1' then
out_vec <= in_vec(16 downto 0) & "000000000000000";
else
out_vec <= "111111111111111" & in_vec(31 downto 15);
end if;
when "10000" =>
if dir = '1' then
out_vec <= in_vec(15 downto 0) & "0000000000000000";
else
out_vec <= "1111111111111111" & in_vec(31 downto 16);
end if;
when "10001" =>
if dir = '1' then
out_vec <= in_vec(14 downto 0) & "00000000000000000";
else
out_vec <= "11111111111111111" & in_vec(31 downto 17);
end if;
when "10010" =>
if dir = '1' then
out_vec <= in_vec(13 downto 0) & "000000000000000000";
else
out_vec <= "111111111111111111" & in_vec(31 downto 18);
end if;
when "10011" =>
if dir = '1' then
out_vec <= in_vec(12 downto 0) & "0000000000000000000";
else
out_vec <= "1111111111111111111" & in_vec(31 downto 19);
end if;
when "10100" =>
if dir = '1' then
out_vec <= in_vec(11 downto 0) & "00000000000000000000";
else
out_vec <= "11111111111111111111" & in_vec(31 downto 20);
end if;
when "10101" =>
if dir = '1' then
out_vec <= in_vec(10 downto 0) & "000000000000000000000";
else
out_vec <= "111111111111111111111" & in_vec(31 downto 21);
end if;
when "10110" =>
if dir = '1' then
out_vec <= in_vec(9 downto 0) & "0000000000000000000000";
else
out_vec <= "1111111111111111111111" & in_vec(31 downto 22);
end if;
when "10111" =>
if dir = '1' then
out_vec <= in_vec(8 downto 0) & "00000000000000000000000";
else
out_vec <= "11111111111111111111111" & in_vec(31 downto 23);
end if;
when "11000" =>
if dir = '1' then
out_vec <= in_vec(7 downto 0) & "000000000000000000000000";
else
out_vec <= "111111111111111111111111" & in_vec(31 downto 24);
end if;
when "11001" =>
if dir = '1' then
out_vec <= in_vec(6 downto 0) & "0000000000000000000000000";
else
out_vec <= "1111111111111111111111111" & in_vec(31 downto 25);
end if;
when "11010" =>
if dir = '1' then
out_vec <= in_vec(5 downto 0) & "00000000000000000000000000";
else
out_vec <= "11111111111111111111111111" & in_vec(31 downto 26);
end if;
when "11011" =>
if dir = '1' then
out_vec <= in_vec(4 downto 0) & "000000000000000000000000000";
else
out_vec <= "111111111111111111111111111" & in_vec(31 downto 27);
end if;
when "11100" =>
if dir = '1' then
out_vec <= in_vec(3 downto 0) & "0000000000000000000000000000";
else
out_vec <= "1111111111111111111111111111" & in_vec(31 downto 28);
end if;
when "11101" =>
if dir = '1' then
out_vec <= in_vec(2 downto 0) & "00000000000000000000000000000";
else
out_vec <= "11111111111111111111111111111" & in_vec(31 downto 29);
end if;
when "11110" =>
if dir = '1' then
out_vec <= in_vec(1 downto 0) & "000000000000000000000000000000";
else
out_vec <= "111111111111111111111111111111" & in_vec(31 downto 30);
end if;
when "11111" =>
if dir = '1' then
out_vec <= in_vec(0 downto 0) & "0000000000000000000000000000000";
else
out_vec <= "1111111111111111111111111111111" & in_vec(31 downto 31);
end if;
when others =>
if dir = '1' then
out_vec <= in_vec(0 downto 0) & "0000000000000000000000000000000";
else
out_vec <= "1111111111111111111111111111111" & in_vec(31 downto 31);
end if;
end case;
end process;
end rtl; | mit | 8b4b56e71999427b4a244e28f120ddb2 | 0.572776 | 2.971967 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd | 1 | 8,552 | -- $Id: sn_humanio_emu_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_emu_rbus - syn
-- Description: sn_humanio rbus emulator
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2017.1-2019,1; ghdl 0.34-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version (derived from sn_humanio_rbus
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 stat r/-/- Status register
-- 15 emu r/-/- emulation (always 1)
-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1
-- 11:08 hled r/-/- led size as LWIDTH-1
-- 7:04 hbtn r/-/- button size as BWIDTH-1
-- 3:00 hswi r/-/- switch size as SWIDTH-1
--
-- 001 cntl r/w/- Control register
-- 4 dsp1_en r/-/- always 0
-- 3 dsp0_en r/-/- always 0
-- 2 dp_en r/-/- always 0
-- 1 led_en r/-/- always 0
-- 0 swi_en r/-/- always 1: SWI will be driven by rbus
--
-- 010 x:00 btn -/-/f w: will pulse BTN
-- 011 x:00 swi r/w/- SWI status
-- 100 x:00 led r/-/- LED status
-- 101 x:00 dp r/-/- DSP_DP status
-- 110 15:00 dsp0 r/-/- DSP_DAT lsb status
-- 111 15:00 dsp1 r/-/- DSP_DAT msb status
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_emu_rbus is -- sn_humanio rbus emulator
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings
BTN : out slv(BWIDTH-1 downto 0); -- button settings
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points
);
end sn_humanio_emu_rbus;
architecture syn of sn_humanio_emu_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv(SWIDTH-1 downto 0); -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv(LWIDTH-1 downto 0); -- hio led
dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- hio dsp_dat
dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- hio dsp_dp
end record regs_type;
constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0');
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0');
constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
swizero, -- swi
btnzero, -- btn
ledzero, -- led
datzero, -- dsp_dat
dpzero -- dsp_dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
constant stat_rbf_emu: integer := 15;
subtype stat_rbf_hdig is integer range 14 downto 12;
subtype stat_rbf_hled is integer range 11 downto 8;
subtype stat_rbf_hbtn is integer range 7 downto 4;
subtype stat_rbf_hswi is integer range 3 downto 0;
constant cntl_rbf_dsp1_en: integer := 4;
constant cntl_rbf_dsp0_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
constant rbaddr_stat: slv3 := "000"; -- 0 r/-/-
constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/-
constant rbaddr_btn: slv3 := "010"; -- 1 -/-/f
constant rbaddr_swi: slv3 := "011"; -- 1 r/w/-
constant rbaddr_led: slv3 := "100"; -- 2 r/-/-
constant rbaddr_dp: slv3 := "101"; -- 3 r/-/-
constant rbaddr_dsp0: slv3 := "110"; -- 4 r/-/-
constant rbaddr_dsp1: slv3 := "111"; -- 5 r/-/-
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
begin
assert SWIDTH<=16
report "assert (SWIDTH<=16)"
severity failure;
assert BWIDTH<=8
report "assert (BWIDTH<=8)"
severity failure;
assert LWIDTH<=16
report "assert (LWIDTH<=16)"
severity failure;
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input registers
n.led := LED;
n.dsp_dat := DSP_DAT;
n.dsp_dp := DSP_DP;
-- clear btn register --> cause single cycle pulses
n.btn := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_emu) := '1';
irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3));
irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4));
irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4));
irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4));
if RB_MREQ.we = '1' then
irb_ack := '0';
end if;
when rbaddr_cntl =>
irb_dout(cntl_rbf_dsp1_en) := '0';
irb_dout(cntl_rbf_dsp0_en) := '0';
irb_dout(cntl_rbf_dp_en) := '0';
irb_dout(cntl_rbf_led_en) := '0';
irb_dout(cntl_rbf_swi_en) := '1';
when rbaddr_btn =>
irb_dout(r.btn'range) := r.btn;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(n.btn'range);
end if;
when rbaddr_swi =>
irb_dout(r.swi'range) := r.swi;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(r.led'range) := r.led;
when rbaddr_dp =>
irb_dout(r.dsp_dp'range) := r.dsp_dp;
when rbaddr_dsp0 =>
irb_dout := r.dsp_dat(dspdat_lsb);
when rbaddr_dsp1 =>
irb_dout := r.dsp_dat(dspdat_msb);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= R_REGS.btn;
SWI <= R_REGS.swi;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | b6d8f535cf5e30de7d5ccdf12d414653 | 0.501286 | 3.348473 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/rlink_tba.vhd | 1 | 21,834 | -- $Id: rlink_tba.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_tba - syn
-- Description: rlink test bench adapter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic [synthesizable, but only used in tb's]
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 4.0 now full rlink v4 iface
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add state r_txal;
-- 2011-11-22 432 3.0.2 now numeric_std clean
-- 2011-11-19 427 3.0.1 fix crc8_update usage;
-- 2010-12-24 347 3.0 rename rritba->rlink_tba, CP_*->RL_*; rbus v3 port;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-05-05 289 1.0.3 drop dead snooper code and unneeded unsigned casts
-- 2008-03-02 121 1.0.2 remove snoopers
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
entity rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end entity rlink_tba;
architecture syn of rlink_tba is
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_data is integer range 7 downto 0; -- d9: data field
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
type txstate_type is (
s_txidle, -- s_txidle: wait for ENA
s_txsop, -- s_txsop: send sop
s_txeop, -- s_txeop: send eop
s_txcmd, -- s_txcmd: send cmd
s_txal, -- s_txal: send addr lsb
s_txah, -- s_txah: send addr msb
s_txcl, -- s_txcl: send blk count lsb
s_txch, -- s_txcl: send blk count msb
s_txdl, -- s_txdl: send data lsb
s_txdh, -- s_txdh: send data msb
s_txcrcl1, -- s_txcrcl1: send cmd crc lsb in wblk
s_txcrch1, -- s_txcrch1: send cmd crc msb in wblk
s_txwbld, -- s_txwbld: wblk data load
s_txwbdl, -- s_txwbdl: wblk send data lsb
s_txwbdh, -- s_txwbdh: wblk send data msb
s_txcrcl2, -- s_txcrcl2: send final crc lsb
s_txcrch2 -- s_txcrch2: send final crc msb
);
type txregs_type is record
state : txstate_type; -- state
ccmd : slv3; -- current command
snum : slv5; -- command sequence number
crc : slv16; -- crc (cmd and data)
braddr : slv16; -- block read address
bdata : slv16; -- block data
bloop : slbit; -- block loop flag
tcnt : slv16; -- tcnt (down count for wblk)
sopdone : slbit; -- sop send
eoppend : slbit; -- eop pending
end record txregs_type;
constant txregs_init : txregs_type := (
s_txidle, -- state
"000", -- ccmd
"00000", -- snum
(others=>'0'), -- crc
(others=>'0'), -- braddr
(others=>'0'), -- bdata
'0', -- bloop
(others=>'0'), -- tcnt
'0','0' -- sopdone, eoppend
);
type rxstate_type is (
s_rxidle, -- s_rxidle: wait for ENA
s_rxcmd, -- s_rxcmd: wait cmd
s_rxcl, -- s_rxcl: wait cnt lsb
s_rxch, -- s_rxcl: wait cnt msb
s_rxbabo, -- s_rxbabo: wait babo
s_rxdcl, -- s_rxdcl: wait dcnt lsb
s_rxdch, -- s_rxdch: wait dcnt msb
s_rxdl, -- s_rxdl: wait data lsb
s_rxdh, -- s_rxdh: wait data msb
s_rxstat, -- s_rxstat: wait status
s_rxcrcl, -- s_rxcrcl: wait crc lsb
s_rxcrch, -- s_rxcrch: wait crc msb
s_rxapl, -- s_rxapl: wait attn pat lsb
s_rxaph, -- s_rxaph: wait attn pat msb
s_rxacl, -- s_rxapl: wait attn crc lsb
s_rxach -- s_rxaph: wait attn crc msb
);
type rxregs_type is record
state : rxstate_type; -- state
ccmd : slv3; -- current command
crc : slv16; -- crc
bwaddr : slv16; -- block write address
data : slv16; -- received data
dcnt : slv16; -- done count
tcnt : slv16; -- tcnt (down count for rblk)
ack : slbit; -- ack flag
err : slbit; -- crc error flag
stat : slv8; -- stat
apend : slbit; -- attn pending
ano : slbit; -- attn notify seen
apat : slv16; -- attn pat
end record rxregs_type;
constant rxregs_init : rxregs_type := (
s_rxidle, -- state
"000", -- ccmd
(others=>'0'), -- crc
(others=>'0'), -- bwaddr
(others=>'0'), -- data
(others=>'0'), -- dcnt
(others=>'0'), -- tcnt
'0','0', -- ack, err
(others=>'0'), -- stat
'0','0', -- apend, ano
(others=>'0') -- attn pat
);
signal R_TXREGS : txregs_type := txregs_init; -- TX state registers
signal N_TXREGS : txregs_type := txregs_init; -- TX next value state regs
signal R_RXREGS : rxregs_type := rxregs_init; -- RX state registers
signal N_RXREGS : rxregs_type := rxregs_init; -- RX next value state regs
signal TXBUSY : slbit := '0';
signal RXBUSY : slbit := '0';
signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_TXREGS <= txregs_init;
R_RXREGS <= rxregs_init;
else
R_TXREGS <= N_TXREGS;
R_RXREGS <= N_RXREGS;
end if;
end if;
end process proc_regs;
-- tx FSM ==================================================================
proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)
variable r : txregs_type := txregs_init;
variable n : txregs_type := txregs_init;
variable itxbusy : slbit := '0';
variable icpdi : slv9 := (others=>'0');
variable iena : slbit := '0';
variable ibre : slbit := '0';
variable do_crc : slbit := '0';
begin
r := R_TXREGS;
n := R_TXREGS;
itxbusy := '1';
icpdi := (others=>'0');
iena := '0';
ibre := '0';
do_crc := '0';
if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy
n.eoppend := '1'; -- queue it
end if;
case r.state is
when s_txidle => -- s_txidle: wait for ENA ------------
itxbusy := '0';
if CNTL.ena = '1' then -- cmd requested
n.ccmd := CNTL.cmd;
if CNTL.eop = '1' then -- if eop requested with ENA
n.eoppend := '1'; -- queue it, eop after this cmd
end if;
if r.sopdone = '0' then -- if not in active packet
n.snum := (others=>'0'); -- set snum=0
n.state := s_txsop; -- send sop
else
n.state := s_txcmd;
end if;
else -- no cmd requested
if CNTL.eop='1' and r.sopdone='1' then -- if eop req and in packet
n.state := s_txeop; -- send eop
end if;
end if;
when s_txsop => -- s_txsop: send sop -----------------
n.sopdone := '1';
icpdi := c_rlink_dat_sop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txcmd;
end if;
when s_txeop => -- s_txeop: send eop -----------------
n.sopdone := '0';
n.eoppend := '0';
icpdi := c_rlink_dat_eop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txidle;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
n.tcnt := CNTL.cnt;
n.braddr := (others=>'0');
icpdi(c_rlink_cmd_rbf_seq) := r.snum;
icpdi(c_rlink_cmd_rbf_code) := r.ccmd;
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum
case r.ccmd is
when c_rlink_cmd_labo => n.state := s_txcrcl2;
when c_rlink_cmd_attn => n.state := s_txcrcl2;
when others => n.state := s_txal;
end case;
end if;
when s_txal => -- s_txal: send addr lsb -------------
icpdi := '0' & CNTL.addr(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txah;
end if;
when s_txah => -- s_txah: send addr msb -------------
icpdi := '0' & CNTL.addr(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
case r.ccmd is
when c_rlink_cmd_rreg => n.state := s_txcrcl2;
when c_rlink_cmd_rblk => n.state := s_txcl;
when c_rlink_cmd_wblk => n.state := s_txcl;
when others => n.state := s_txdl;
end case;
end if;
when s_txcl => -- s_txcl: send blk count lsb -------
icpdi := '0' & CNTL.cnt(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txch;
end if;
when s_txch => -- s_txch: send blk count msb -------
icpdi := '0' & CNTL.cnt(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.ccmd = c_rlink_cmd_wblk then
n.state := s_txcrcl1;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txdl => -- s_txdl: send data lsb -------------
icpdi := '0' & DI(d_f_data);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txdh;
end if;
when s_txdh => -- s_txdh: send data msb -------------
icpdi := '0' & DI(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txcrcl2;
end if;
when s_txcrcl1 => -- s_txcrcl1: send cmd crc lsb in wblk
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch1;
end if;
when s_txcrch1 => -- s_txcrch1: send cmd crc msb in wblk
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txwbld;
end if;
when s_txwbld => -- s_txwbld: wblk data load ----------
-- this state runs when s_wreg is
-- executed in rlink, thus doesn't cost
-- an extra cycle in 2nd+ iteration.
ibre := '1';
n.bdata := DI;
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.braddr := slv(unsigned(r.braddr) + 1);
if unsigned(r.tcnt) = 1 then
n.bloop := '0';
else
n.bloop := '1';
end if;
n.state := s_txwbdl;
when s_txwbdl => -- s_txwbdl: wblk send data lsb ------
icpdi := '0' & r.bdata(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txwbdh;
end if;
when s_txwbdh => -- s_txwbdh: wblk send data msb ------
icpdi := '0' & r.bdata(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.bloop = '1' then
n.state := s_txwbld;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txcrcl2 => -- s_txcrcl2: send final crc lsb -----
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch2;
end if;
when s_txcrch2 => -- s_txcrch2: send final crc msb -----
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
if r.eoppend = '1' or unsigned(r.snum)=31 then
n.state := s_txeop;
else
n.state := s_txidle;
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, icpdi(d_f_data));
end if;
N_TXREGS <= n;
TXBUSY <= itxbusy;
STAT_L.braddr <= r.braddr;
STAT_L.bre <= ibre;
RL_DI <= icpdi;
RL_ENA <= iena;
end process proc_txnext;
-- rx FSM ==================================================================
proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)
variable r : rxregs_type := rxregs_init;
variable n : rxregs_type := rxregs_init;
variable irxbusy : slbit := '0';
variable ibwe : slbit := '0';
variable do_crc : slbit := '0';
variable ido : slv16 := (others=>'0');
begin
r := R_RXREGS;
n := R_RXREGS;
n.ack := '0';
n.ano := '0';
irxbusy := '1';
ibwe := '0';
do_crc := '0';
ido := r.data;
case r.state is
when s_rxidle => -- s_rxidle: wait --------------------
n.crc := (others=>'0');
n.err := '0';
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_attn then -- attn seen ?
n.state := s_rxapl;
elsif RL_DO = c_rlink_dat_sop then
n.state := s_rxcmd;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcmd => -- s_rxcmd: wait cmd ----------------
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_eop then
n.state := s_rxidle;
else
n.bwaddr := (others=>'0');
do_crc := '1';
n.ccmd := RL_DO(n.ccmd'range);
case RL_DO(n.ccmd'range) is
when c_rlink_cmd_rreg => n.state := s_rxdl;
when c_rlink_cmd_rblk => n.state := s_rxcl;
when c_rlink_cmd_wreg => n.state := s_rxstat;
when c_rlink_cmd_wblk => n.state := s_rxdcl;
when c_rlink_cmd_labo => n.state := s_rxbabo;
when c_rlink_cmd_attn => n.state := s_rxdl;
when c_rlink_cmd_init => n.state := s_rxstat;
when others => null;
end case;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcl => -- s_rxcl: wait cnt lsb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxch;
end if;
when s_rxch => -- s_rxch: wait cnt msb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxdl;
end if;
when s_rxbabo => -- s_rxbabo: wait babo ---------------
if RL_VAL = '1' then
do_crc := '1';
n.data(15 downto 0) := (others=>'0');
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxdl => -- s_rxdl: wait data lsb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdh;
end if;
when s_rxdh => -- s_rxdh: wait data msb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte1) := RL_DO(d_f_data);
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.bwaddr := slv(unsigned(r.bwaddr) + 1);
if r.ccmd = c_rlink_cmd_rblk then
ido(f_byte1) := RL_DO(d_f_data);
ibwe := '1';
end if;
if r.ccmd /= c_rlink_cmd_rblk then
n.state := s_rxstat;
elsif unsigned(r.tcnt) = 1 then
n.state := s_rxdcl;
else
n.state := s_rxdl;
end if;
end if;
when s_rxdcl => -- s_rxdcl: wait dcnt lsb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdch;
end if;
when s_rxdch => -- s_rxdch: wait dcnt msb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxstat => -- s_rxstat: wait status -------------
if RL_VAL = '1' then
do_crc := '1';
n.stat := RL_DO(d_f_data);
n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status
n.state := s_rxcrcl;
end if;
when s_rxcrcl => -- s_rxcrcl: wait crc lsb ------------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxcrch;
end if;
when s_rxcrch => -- s_rxcrch: wait crc msb ------------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ack := '1';
n.state := s_rxcmd;
end if;
when s_rxapl => -- s_rxapl: wait attn pat lsb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte0) := RL_DO(d_f_data);
n.state := s_rxaph;
end if;
when s_rxaph => -- s_rxaph: wait attn pat msb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte1) := RL_DO(d_f_data);
n.state := s_rxacl;
end if;
when s_rxacl => -- s_rxacl: wait attn crc lsb --------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxach;
end if;
when s_rxach => -- s_rxach: wait attn crc msb --------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ano := '1';
n.state := s_rxidle;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, RL_DO(d_f_data));
end if;
N_RXREGS <= n;
RXBUSY <= irxbusy;
DO <= ido;
STAT_L.stat <= r.stat;
STAT_L.ack <= r.ack;
STAT_L.err <= r.err;
STAT_L.bwaddr <= r.bwaddr;
STAT_L.bwe <= ibwe;
STAT_L.dcnt <= r.dcnt;
STAT_L.apend <= r.apend;
STAT_L.ano <= r.ano;
STAT_L.apat <= r.apat;
RL_HOLD <= '0';
end process proc_rxnext;
STAT_L.busy <= RXBUSY or TXBUSY;
STAT <= STAT_L;
end syn;
| gpl-3.0 | 5723894e872b02edbb00b5e39cb4b910 | 0.407896 | 3.688799 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd | 1 | 1,343 | -- $Id: sys_conf_ba4_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=4;btyp=bram)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 4; -- 128 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_bram;
end package sys_conf;
| gpl-3.0 | a5c874609961de936cc28a89f7daaff4 | 0.521221 | 3.881503 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/artys7_dummy.vhd | 1 | 1,703 | -- $Id: artys7_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: artys7_dummy - syn
-- Description: artys7 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_artys7
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-05 1038 1.0 Initial version (cloned from artya7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity artys7_dummy is -- ARTY S7 dummy (base; loopback)
-- implements artys7_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3 -- artys7 rgb-led 1
);
end artys7_dummy;
architecture syn of artys7_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
end syn;
| gpl-3.0 | 8928ca2af649cb61f42e114297bb2a88 | 0.492073 | 3.767699 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/rgbdrv_master.vhd | 1 | 2,466 | -- $Id: rgbdrv_master.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_master - syn
-- Description: rgbled driver: master
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity rgbdrv_master is -- rgbled driver: master
generic (
DWIDTH : positive := 8); -- dimmer width (must be >= 1)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
RGBCNTL : out slv3; -- rgb control
DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
);
end rgbdrv_master;
architecture syn of rgbdrv_master is
type regs_type is record
rgbena : slv3; -- rgb enables
dimcnt : slv(DWIDTH-1 downto 0); -- dim counter
end record regs_type;
constant dimones : slv(DWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
"001", -- rgbena
dimones -- dimcnt
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if CE_USEC = '1' then
n.dimcnt := slv(unsigned(r.dimcnt) + 1);
if r.dimcnt = dimones then
n.rgbena(2) := r.rgbena(1);
n.rgbena(1) := r.rgbena(0);
n.rgbena(0) := r.rgbena(2);
end if;
end if;
N_REGS <= n;
end process proc_next;
RGBCNTL <= R_REGS.rgbena;
DIMCNTL <= R_REGS.dimcnt;
end syn;
| gpl-3.0 | 79b8eb151a0e7252c8b7b84a8867e1c6 | 0.517843 | 3.558442 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swar_gen.vhd | 1 | 2,589 | -- $Id: ram_1swar_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- The code is inspired by Xilinx example rams_04.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 16 16*RAM16X1S
-- 5 16 - 32 16*RAM32X1S
-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
architecture syn of ram_1swar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
DO <= RAM(to_integer(unsigned(ADDR)));
end syn;
| gpl-3.0 | 873bc97fda86fdfc46a04dc1c3b1a427 | 0.559289 | 3.433687 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/tb/tb_s3board.vhd | 1 | 5,971 | -- $Id: tb_s3board.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board - sim
-- Description: Test bench for s3board (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-21 432 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 2.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 2.0.2 use serport_uart_rxtx
-- 2010-05-01 286 2.0.1 use rritb_core as component again (rriv1 is gone..)
-- 2010-04-25 283 2.0 factor out basic device handling to tb_s3board_core
-- and_conf/_stim file processing to rri/tb/rritb_core
-- 2010-04-24 281 1.3.2 use serport_uart_[tr]x directly again
-- 2007-12-16 101 1.3.1 use _N for active low, add sram memory model
-- 2007-12-09 100 1.3 add sram memory signals
-- 2007-11-23 97 1.2 use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-10-26 92 1.1.1 use DONE timestamp at end of execution
-- 2007-10-19 90 1.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- use CLKDIV="00 --> sim with max. serport speed
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board is
end tb_s3board;
architecture sim of tb_s3board is
signal CLK : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | cbb6d6e08733a09d319489cdf8186679 | 0.540613 | 3.077835 | false | false | false | false |
RP7/R7-min-system | src/R7MS_top.vhd | 1 | 8,240 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
--Date : Sat Feb 21 09:53:18 2015
--Host : dodo-PC running 64-bit Service Pack 1 (build 7601)
--Command : generate_target miniarm_wrapper.bd
--Design : miniarm_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_top is
port (
------------------- global clock input
SYS_CLK : IN STD_LOGIC ;
--------------------------------------
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
------------------- GE interface
GMII_TX_EN : out std_logic;
GMII_TX_ER : out std_logic;
GMII_TXD : out std_logic_vector(7 downto 0);
GMII_TXCLK : in STD_LOGIC ;
GMII_GTXCLK : out STD_LOGIC ;
GMII_RXD : in std_logic_vector(7 downto 0);
GMII_RX_ER : in std_logic;
GMII_RX_DV : in std_logic;
GMII_RXCLK : in std_logic;
GMII_MDIO : inout std_logic;
GMII_MDIO_MDC : out std_logic;
GMII_GE_IND : in std_logic;
------------------- test interface
TEST_LED : out std_logic_vector(3 downto 0) );
end led_top;
architecture top of led_top is
component miniarm_wrapper is
port (
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 17 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC_VECTOR ( 0 to 0 );
ENET0_GMII_TX_ER : out STD_LOGIC_VECTOR ( 0 to 0 );
ENET0_MDIO_I : in STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
test_led_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component miniarm_wrapper;
component IOBUF is
port(
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component;
component clk_wiz_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
reset : in STD_LOGIC
);
end component clk_wiz_0;
signal clk_125M : std_logic := '0';
signal pll_reset : std_logic := '0';
signal pll_locked : std_logic := '0';
signal ENET0_MDIO_O : std_logic := '0';
signal ENET0_MDIO_T : std_logic := '0';
signal ENET0_MDIO_I : std_logic := '0';
signal BRAM_PORTA_addr : STD_LOGIC_VECTOR ( 17 downto 0 );
signal BRAM_PORTA_clk : STD_LOGIC;
signal BRAM_PORTA_din : STD_LOGIC_VECTOR ( 31 downto 0 );
signal BRAM_PORTA_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal BRAM_PORTA_en : STD_LOGIC;
signal BRAM_PORTA_rst : STD_LOGIC;
signal BRAM_PORTA_we : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ENET0_GMII_TX_CLK : STD_LOGIC;
signal GMII_GE_IND_reg : std_logic := '0';
signal GMII_GE_TIMER : std_logic_vector( 27 downto 0 );
begin
miniarm: component miniarm_wrapper
port map (
BRAM_PORTA_addr(17 downto 0) => BRAM_PORTA_addr(17 downto 0),
BRAM_PORTA_clk => BRAM_PORTA_clk,
BRAM_PORTA_din(31 downto 0) => BRAM_PORTA_din(31 downto 0),
BRAM_PORTA_dout(31 downto 0) => BRAM_PORTA_dout(31 downto 0),
BRAM_PORTA_en => BRAM_PORTA_en,
BRAM_PORTA_rst => BRAM_PORTA_rst,
BRAM_PORTA_we(3 downto 0) => BRAM_PORTA_we(3 downto 0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
ENET0_GMII_RXD(7 downto 0) => GMII_RXD(7 downto 0),
ENET0_GMII_RX_CLK => GMII_RXCLK,
ENET0_GMII_RX_DV => GMII_RX_DV,
ENET0_GMII_RX_ER => GMII_RX_ER,
ENET0_GMII_TXD(7 downto 0) => GMII_TXD(7 downto 0),
ENET0_GMII_TX_CLK => ENET0_GMII_TX_CLK,
ENET0_GMII_TX_EN(0) => GMII_TX_EN,
ENET0_GMII_TX_ER(0) => GMII_TX_ER,
ENET0_MDIO_I => ENET0_MDIO_I,
ENET0_MDIO_MDC => GMII_MDIO_MDC,
ENET0_MDIO_O => ENET0_MDIO_O,
ENET0_MDIO_T => ENET0_MDIO_T,
TEST_LED_tri_o(3 downto 0) => TEST_LED(3 downto 0)
);
-- GMII_MDIOµÄÈý̬¼Ä´æÆ÷Íø¿Ú-----
GMII_MDIO_iobuf : IOBUF
port map (
I => ENET0_MDIO_O,
IO => GMII_MDIO,
O => ENET0_MDIO_I,
T => ENET0_MDIO_T
);
clk_125M_i: component clk_wiz_0
port map (
clk_out1 => clk_125M,
clk_in1 => SYS_CLK,
locked => pll_locked,
reset => pll_reset
);
Reg_GMII_GE_IND : process(clk_125M)
begin
if rising_edge(clk_125M) then
if GMII_GE_IND = '1' then
GMII_GE_IND_reg <= '1';
GMII_GE_TIMER <= X"0000000";
else
if GMII_GE_TIMER = X"fffffff" then
GMII_GE_IND_reg <= '0';
else
GMII_GE_TIMER <= GMII_GE_TIMER+1;
end if;
end if;
end if;
end process;
GMII_GTXCLK <= clk_125M;
ENET0_GMII_TX_CLK <= clk_125M when GMII_GE_IND_reg = '1' else GMII_TXCLK;
end top;
| apache-2.0 | 8af07fb717901e41f3a5bb873a765658 | 0.564806 | 3.012797 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd | 1 | 20,864 | -- $Id: sys_w11a_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n3 - syn
-- Description: w11a test design for nexys3
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/fx2rlink/rlink_sp1c_fx2
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_sys_w11a_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2019-05-19 1150 14.7 131013 xc6slx16-2 3167 6052 248 2130 ok: +dz11 93%
-- 2019-05-01 1143 14.7 131013 xc6slx16-2 3062 5761 232 2057 ok: +m9312 90%
-- 2019-04-27 1140 14.7 131013 xc6slx16-2 3053 5742 232 2050 ok: +dlbuf 89%
-- 2019-04-24 1137 14.7 131013 xc6slx16-2 3049 5727 223 2045 ok: +pcbuf 89%
-- 2019-03-17 1123 14.7 131013 xc6slx16-2 3059 5722 212 2041 ok: +lpbuf 89%
-- 2019-03-02 1116 14.7 131013 xc6slx16-2 3048 5741 212 2030 ok: +ibtst 89%
-- 2019-01-27 1108 14.7 131013 xc6slx16-2 2979 5542 201 2018 ok: -iist 88%
-- 2018-10-13 1055 14.7 131013 xc6slx16-2 3057 5822 201 2064 ok: +dmpcnt 90%
-- 2018-09-15 1045 14.7 131013 xc6slx16-2 2851 5453 177 1932 ok: +KW11P 84%
-- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85%
-- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82%
-- 2017-01-29 846 14.7 131013 xc6slx16-2 2680 5208 177 1860 ok: +int24 81%
-- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
-- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
-- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
-- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes
-- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67%
-- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67%
-- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65%
-- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61%
-- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon
-- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4
-- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11
-- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51%
-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-24 668 1.8.3 added ibd_ibmon
-- 2015-04-11 666 1.8.2 rearrange XON handling
-- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-15 647 1.8 drop bram and minisys options
-- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address
-- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon
-- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT
-- 2014-08-15 583 1.6 rb_mreq addr now 16 bit
-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.4 added fx2 (cuff) support
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.0.1 fixup PPCM handling
-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
------------------------------------------------------------------------------
--
-- w11a test design for nexys3
-- w11a + rlink + serport
--
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:6): select LED display mode
-- 0x w11 sys70 LED display (further controlled by SWI(3))
-- 10 FX2 debug: fx2 fifo states
-- 11 FX2 debug: fx2 fsm states
-- (5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LEDs if SWI(7) = 0 and SWI(3) = 1
-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
--
-- LEDs if SWI(7) = 0 and SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- LEDs if SWI(7) = 1
-- (7) fifo_ep4
-- (6) fifo_ep6
-- (5) fsm_rx
-- (4) fsm_tx
-- LEDs if SWI(7) = 1 and SWI(6) = 0
-- (3) flag_ep4_empty
-- (2) flag_ep4_almost
-- (1) flag_ep6_full
-- (0) flag_ep6_almost
-- LEDs if SWI(7) = 1 and SWI(6) = 1
-- (3) fsm_idle
-- (2) fsm_prep
-- (1) fsm_disp
-- (0) fsm_pipe
--
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back pressure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back pressure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back pressure)
-- (2): RLB_TXBUSY (shows tx back pressure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n3 is -- top level
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n3;
architecture syn of sys_w11a_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal LED70 : slv8 := (others=>'0');
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"03"; -- nexys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs -- clock generator -------------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce -- usec/msec clock divider -----------
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => (others=>'0'),
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => GRESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
if SWI(7) = '0' then
iled := LED70;
else
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fsm_rx;
iled(4) := FX2_MONI.fsm_tx;
if SWI(6) = '0' then
iled(3) := FX2_MONI.flag_ep4_empty;
iled(2) := FX2_MONI.flag_ep4_almost;
iled(1) := FX2_MONI.flag_ep6_full;
iled(0) := FX2_MONI.flag_ep6_almost;
else
iled(3) := FX2_MONI.fsm_idle;
iled(2) := FX2_MONI.fsm_prep;
iled(1) := FX2_MONI.fsm_disp;
iled(0) := FX2_MONI.fsm_pipe;
end if;
end if;
LED <= iled;
end process proc_fx2leds;
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | f572a85b19554e2da2efdf9eea129855 | 0.498275 | 3.0264 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_Divider_Device.vhdl | 1 | 6,567 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Divider 8/16/24/32 bit) Device for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_Divider_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_Divider_Device is
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant REQUIRED_REG_BYTES : POSITIVE := div_ceil(BITS, 8);
constant BIT_AB : NATURAL := log2ceil(REQUIRED_REG_BYTES);
signal Reg_Start : STD_LOGIC := '0';
signal Reg_Operand_A : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_Operand_B : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_Result : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Div_Result : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal Div_Done_d : STD_LOGIC := '0';
signal Div_Done_re : STD_LOGIC;
begin
assert ((BITS = 8) or (BITS = 16) or (BITS = 24) or (BITS = 32))
report "Divider size is not supported. Supported sizes: 8, 16, 24, 32. BITS=" & INTEGER'image(BITS)
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
Reg_Start <= '0';
if (Reset = '1') then
Reg_Operand_A <= (others => (others => '0'));
Reg_Operand_B <= (others => (others => '0'));
Reg_Result <= (others => (others => '0'));
else
if (AdrDec_we = '1') then
if (AdrDec_WriteAddress(BIT_AB) = '0') then
Reg_Operand_A(to_index(AdrDec_WriteAddress(BIT_AB - 1 downto 0))) <= AdrDec_Data;
else
Reg_Operand_B(to_index(AdrDec_WriteAddress(BIT_AB - 1 downto 0))) <= AdrDec_Data;
end if;
if (slv_and(AdrDec_WriteAddress(BIT_AB downto 0)) = '1') then
Reg_Start <= '1';
end if;
end if;
if (Div_Done_re = '1') then
Reg_Result <= to_slvv_8(Div_Result);
end if;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_Result, Div_Done_d)
begin
DataOut <= Reg_Result(to_index(AdrDec_ReadAddress(BIT_AB - 1 downto 0), Reg_Result'length - 1));
if (slv_and(AdrDec_ReadAddress(BIT_AB downto 0)) = '1') then
DataOut <= "0000000" & Div_Done_d;
end if;
end process;
Interrupt <= Div_Done_re;
Message <= x"00";
blkDiv : block
signal Operand_A_slv : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal Operand_B_slv : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal Div_Done : STD_LOGIC;
begin
Operand_A_slv <= to_slv(Reg_Operand_A);
Operand_B_slv <= to_slv(Reg_Operand_B);
Div : entity PoC.arith_div
generic map (
N => BITS, -- Operand /Result bit widths
RAPOW => 2, -- Power of Radix used (2**RAPOW)
REGISTERED => FALSE
)
port map (
clk => Clock,
rst => Reset,
start => Reg_Start,
arg1 => Operand_A_slv,
arg2 => Operand_B_slv,
rdy => Div_Done,
res => Div_Result
);
Div_Done_d <= Div_Done when rising_edge(Clock);
Div_Done_re <= not Div_Done_d and Div_Done;
end block;
end;
| apache-2.0 | ec54aadd4f3942dbdeb51a9bffd71dc6 | 0.523984 | 3.203415 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/tb_c7_sram_memctl.vhd | 1 | 9,263 | -- $Id: tb_c7_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_c7_sram_memctl - sim
-- Description: Test bench for c7_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61wv5128bll
-- c7_sram_memctl [UUT]
--
-- To test: c7_sram_memctl
--
-- Verified (with tb_c7_sram_memctl_stim.dat):
-- Date Rev Code ghdl viv Target Comment
-- 2017-06-11 912 _ssim 0.34 2017.1 xx xx
--
-- Target Devices: generic
-- Tool versions: viv 2017.1; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-13 913 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.cmoda7lib.all;
use work.simlib.all;
entity tb_c7_sram_memctl is
end tb_c7_sram_memctl;
architecture sim of tb_c7_sram_memctl is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv17 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADDR : slv19 := (others=>'0');
signal IO_MEM_DATA : slv8 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv17 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv17 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv17 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.is61wv5128bll
port map (
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : c7_sram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_c7_sram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv17 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
wait for clock_period;
REQ <= '0';
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
wait for clock_period;
REQ <= '0';
WE <= '0';
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 5, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 8, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
| gpl-3.0 | ddb7bb09c1ff2b499ea94e3750aadab6 | 0.489582 | 3.565435 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/pb.comp.vhdl | 1 | 8,917 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: PicoBlaze component declarations
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.utils.all;
package pb_comp is
component main_Page0 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page1 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page2 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page3 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page4 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page5 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page6 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component main_Page7 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end component;
component JTAGLoader6 is
generic (
C_NUM_PICOBLAZE : integer := 1;
C_JTAG_CHAIN : INTEGER := 2;
C_ADDR_WIDTH : T_INTVEC(0 to 7) := (others => 10)
);
port (
picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE - 1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE - 1 downto 0);
jtag_din : out std_logic_vector(17 downto 0);
jtag_addr : out std_logic_vector(imax(C_ADDR_WIDTH) - 1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in std_logic_vector(17 downto 0);
jtag_dout_1 : in std_logic_vector(17 downto 0);
jtag_dout_2 : in std_logic_vector(17 downto 0);
jtag_dout_3 : in std_logic_vector(17 downto 0);
jtag_dout_4 : in std_logic_vector(17 downto 0);
jtag_dout_5 : in std_logic_vector(17 downto 0);
jtag_dout_6 : in std_logic_vector(17 downto 0);
jtag_dout_7 : in std_logic_vector(17 downto 0)
);
end component;
component uart_tx6 is
port (
clk : in std_logic;
en_16_x_baud : in std_logic;
data_in : in std_logic_vector(7 downto 0);
buffer_reset : in std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
serial_out : out std_logic
);
end component;
component uart_tx6_unconstrained is
port (
clk : in std_logic;
en_16_x_baud : in std_logic;
data_in : in std_logic_vector(7 downto 0);
buffer_reset : in std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
serial_out : out std_logic
);
end component;
component uart_rx6 is
port (
clk : in std_logic;
en_16_x_baud : in std_logic;
serial_in : in std_logic;
buffer_reset : in std_logic;
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
component uart_rx6_unconstrained is
port (
clk : in std_logic;
en_16_x_baud : in std_logic;
serial_in : in std_logic;
buffer_reset : in std_logic;
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
end package;
package body pb_comp is
end package body;
| apache-2.0 | c53c8b91d39a53f5084db9194e402ba7 | 0.575193 | 3.060055 | false | false | false | false |
wfjm/w11 | rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd | 1 | 27,540 | -- $Id: nx_cram_memctl_as.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nx_cram_memctl_as - syn
-- Description: nexys2/3/4: CRAM controller - async and page mode
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3
-- sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2019.1; ghdl 0.26-0.36
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2016-07-03 783 2016.3 xc7a100t-1 91 87 0 0 43
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-07-03 767 14.7 131013 xc6slx16-2 100 134 0 60 s 4.2
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 2.1.1 fix for ghdl V0.36 -Whide warnings
-- 2016-07-16 788 2.1 change *DELAY generics, now absolute delay cycles
-- add s_init1; drop "KEEP" for data (better for dbg)
-- 2016-07-10 786 2.0 add page mode support
-- 2016-05-22 767 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
-- 2011-11-19 427 1.0.5 now numeric_std clean
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
-- cycle;
-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
-- 2010-05-23 293 1.0 Initial version
--
-- Notes:
-- 1. There is no 'bus-turn-around' cycle needed for a write->read change
-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
-- transition simultaneously. The FPGA will go high-Z quickly, the memory
-- low-Z delay by the IOB and internal memory delays. No clash.
-- 2. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
-- some delay. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
-- Again no clash due to the 1 cycle delay.
--
-- Nominal timings:
-- READ0 = (T_aa + ext_read_delay) in cycles
-- READ1 = (T_pa + ext_read_delay) in cycles
-- WRITE = (T_aa + ext_write_delay) in cycles
-- with
-- ext_read_delay: output_IOB + 2*PCB_delay + input_IOB + skew
-- ext_write_delay: skew
--
--
-- Timing of some signals:
--
-- single read request:
--
-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
-- 0 20 40 60 80 100 120
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
--
-- REQ _______|^^^^^|_____________________________________________
-- WE ___________________________________________________________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
--
-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
-- ACK_R ___________________________________________________________|^^^^^^^|_
--
-- single write request:
--
-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
-- 0 20 40 60 80 100 120
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
--
-- REQ _______|^^^^^|______________________________________
-- WE _______|^^^^^|______________________________________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_OE ____________________________________________________
-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
--
-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
-- ACK_W __________________________________________|^^^^^^^|_
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity nx_cram_memctl_as is -- CRAM controller (async+page mode)
generic (
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nx_cram_memctl_as;
architecture syn of nx_cram_memctl_as is
type state_type is (
s_init, -- s_init: startup state
s_init1, -- s_init1: reset released
s_wcinit, -- s_wcinit: write rcr init
s_wcwait, -- s_wcwait: write rcr wait
s_wcput, -- s_wcput: write rcr done
s_rainit, -- s_rainit: read array init
s_rawait, -- s_rawait: wait read array
s_idle, -- s_idle: wait for req
s_rdinit, -- s_rdinit: read init cycle
s_rdwait0, -- s_rdwait0: read wait low word
s_rdget0, -- s_rdget0: read get low word
s_rdwait1, -- s_rdwait1: read wait high word
s_rdget1, -- s_rdget1: read get high word
s_wrinit, -- s_wrinit: write init cycle
s_wrwait0, -- s_rdwait0: write wait 1st word
s_wrput0, -- s_rdput0: write put 1st word
s_wrini1, -- s_wrini1: write init 2nd word
s_wrwait1, -- s_wrwait1: write wait 2nd word
s_wrput1 -- s_wrput1: write put 2nd word
);
type regs_type is record
state : state_type; -- state
ackr : slbit; -- signal ack_r
addr0 : slbit; -- current addr0
be2nd : slv2; -- be's of 2nd write cycle
cntdly : slv3; -- wait delay counter
cntce : slv7; -- ce counter
fidle : slbit; -- force idle flag
memdo0 : slv16; -- mem data out, low word
memdi : slv32; -- mem data in
end record regs_type;
constant regs_init : regs_type := (
s_init, -- state
'0', -- ackr
'0', -- addr0
"00", -- be2nd
(others=>'0'), -- cntdly
(others=>'0'), -- cntce
'0', -- fidle
(others=>'0'), -- memdo0
(others=>'0') -- memdi
);
constant c_addrh_rcr_setup : slv22 :=
"000" & -- 22:20 reserved MBZ
"00" & -- 19:18 reg sel 00=RCR
"0000000000" & -- 17: 8 reserved MBZ
'1' & -- 7 page mode enable (1=enable)
"00" & -- 6: 5 reserved MBZ
'1' & -- 4 dpd disaable (1=disable)
"000"; -- 3: 1 rest is reserved or PAR, which should be 0
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CLK_180 : slbit := '0';
signal MEM_CE_N : slbit := '1';
signal MEM_BE_N : slv2 := "11";
signal MEM_WE_N : slbit := '1';
signal MEM_OE_N : slbit := '1';
signal MEM_CRE : slbit := '0';
signal BE_CE : slbit := '0';
signal ADDRH_CE : slbit := '0';
signal ADDR0_CE : slbit := '0';
signal ADDRH : slv22 := (others=>'0');
signal ADDR0 : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
signal DATA_OE : slbit := '0';
signal MEM_DO : slv16 := (others=>'0');
signal MEM_DI : slv16 := (others=>'0');
begin
-- Notes:
-- used READ0DELAY-2 and READ0DELAY-3
-- used READ1DELAY-2
-- used WRITEDELAY-2
assert READ0DELAY-2 < 2**R_REGS.cntdly'length and
READ1DELAY-2 < 2**R_REGS.cntdly'length and
WRITEDELAY-2 < 2**R_REGS.cntdly'length
report "assert( (READ0,READ1,WRITE)DELAY-2 < 2**cntdly'length)"
severity failure;
assert READ0DELAY >= 3 and
READ1DELAY >= 2 and
WRITEDELAY >= 2
report "assert( (READ0,READ1,WRITE)DELAY-2 >= 2 or 3)"
severity failure;
CLK_180 <= not CLK;
IOB_MEM_CE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CE_N,
PAD => O_MEM_CE_N
);
IOB_MEM_BE : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '1')
port map (
CLK => CLK,
CE => BE_CE,
DO => MEM_BE_N,
PAD => O_MEM_BE_N
);
IOB_MEM_WE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK_180,
CE => '1',
DO => MEM_WE_N,
PAD => O_MEM_WE_N
);
IOB_MEM_OE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_OE_N,
PAD => O_MEM_OE_N
);
IOB_MEM_CRE : iob_reg_o
generic map (
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CRE,
PAD => O_MEM_CRE
);
IOB_MEM_ADDRH : iob_reg_o_gen
generic map (
DWIDTH => 22)
port map (
CLK => CLK,
CE => ADDRH_CE,
DO => ADDRH,
PAD => O_MEM_ADDR(22 downto 1)
);
IOB_MEM_ADDR0 : iob_reg_o
port map (
CLK => CLK,
CE => ADDR0_CE,
DO => ADDR0,
PAD => O_MEM_ADDR(0)
);
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 16,
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
CEO => DATA_CEO,
OE => DATA_OE,
DI => MEM_DO,
DO => MEM_DI,
PAD => IO_MEM_DATA
);
O_MEM_ADV_N <= '0';
O_MEM_CLK <= '0';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, REQ, WE, BE, DI, ADDR, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibusy : slbit := '0';
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_cre : slbit := '0';
variable ibe_ce : slbit := '0';
variable iaddrh_ce : slbit := '0';
variable iaddr0_ce : slbit := '0';
variable iaddrh : slv22 := (others=>'0');
variable iaddr0 : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
procedure do_dispatch(pnstate : out state_type;
piaddrh_ce : out slbit;
piaddr0_ce : out slbit;
piaddr0 : out slbit;
pibe_ce : out slbit;
pimem_be : out slv2;
pimem_ce : out slbit;
pimem_oe : out slbit;
pnbe2nd : out slv2) is
begin
piaddrh_ce := '1'; -- latch address (high part)
piaddr0_ce := '1'; -- latch address 0 bit
pibe_ce := '1'; -- latch be's
pimem_ce := '1'; -- ce CRAM next cycle
pnbe2nd := "00"; -- assume no 2nd write cycle
if WE = '0' then -- if READ requested
piaddr0 := '0'; -- go first for low word
pimem_be := "11"; -- on read always on
pimem_oe := '1'; -- oe CRAM next cycle
pnstate := s_rdinit; -- next: read init part
else -- if WRITE requested
if BE(1 downto 0) /= "00" then -- low word write
piaddr0 := '0'; -- access word 0
pimem_be := BE(1 downto 0); -- set be's for 1st cycle
pnbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
else -- high word write
piaddr0 := '1'; -- access word 1
pimem_be := BE(3 downto 2); -- set be's for 1st cycle
end if;
pimem_oe := '0'; -- oe=0
pnstate := s_wrinit; -- next: write init part
end if;
end procedure do_dispatch;
begin
r := R_REGS;
n := R_REGS;
n.ackr := '0';
ibusy := '0';
iackw := '0';
iactr := '0';
iactw := '0';
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_cre := '0';
ibe_ce := '0';
iaddrh_ce := '0';
iaddr0_ce := '0';
iaddrh := ADDR;
iaddr0 := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
if unsigned(r.cntdly) /= 0 then
n.cntdly := slv(unsigned(r.cntdly) - 1);
end if;
case r.state is
when s_init => -- s_init: startup state
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_init1;
when s_init1 => -- s_init1: reset released
ibusy := '1'; -- signal busy, unable to handle req
iaddrh := c_addrh_rcr_setup;
iaddr0 := '0';
iaddrh_ce := '1';
iaddr0_ce := '1';
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
n.state := s_wcinit;
when s_wcinit => -- s_wcinit: write rcr init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
n.cntdly := slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wcwait;
when s_wcwait => -- s_wcinit: write rcr wait
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wcput; -- next: write rcr done
end if;
when s_wcput => -- s_wcput: write rcr done
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_rainit; -- next: read array init
when s_rainit => -- s_rainit: read array init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-2, n.cntdly'length));
n.state := s_rawait ; -- next: wait read array
when s_rawait => -- s_rawait: wait read array
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_idle; -- next: wait for req
end if;
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
when s_rdinit => -- s_rdinit: read init cycle
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-3, n.cntdly'length));
n.state := s_rdwait0; -- next: wait low word
when s_rdwait0 => -- s_rdwait0: read wait low word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget0; -- next: get low word
end if;
when s_rdget0 => -- s_rdget0: read get low word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= slv(to_unsigned(READ1DELAY-2, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
when s_rdwait1 => -- s_rdwait1: read wait high word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget1; -- next: get high word
end if; --
when s_rdget1 => -- s_rdget1: read get high word
iactr := '1'; -- signal mem read
n.memdo0:= MEM_DO; -- save low word data
idata_cei := '1'; -- latch input data
n.ackr := '1'; -- ACK_R next cycle
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy, unable to handle req
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
when s_wrinit => -- s_wrinit: write init cycle
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
iackw := '1'; -- signal write done (all latched)
idata_ceo:= '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
when s_wrwait0 => -- s_rdput0: write wait 1st word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wrput0; -- next: put 1st word
end if;
when s_wrput0 => -- s_rdput0: write put 1st word
iactw := '1'; -- signal mem write
imem_we := '0'; -- deassert we CRAM in half cycle
if r.be2nd /= "00" then
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
ibe_ce := '1'; -- latch be's
imem_be := r.be2nd; -- now be's of high word
n.state := s_wrini1; -- next: start 2nd write
else
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
end if;
when s_wrini1 => -- s_wrini1: write init 2nd word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_ceo:= '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wrput1; -- next: put 2nd word
end if;
when s_wrput1 => -- s_wrput1: write put 2nd word
iactw := '1'; -- signal mem write
imem_we := '0'; -- deassert we CRAM in half cycle
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy, unable to handle req
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
when others => null;
end case;
if imem_ce = '0' then -- if cmem not active
n.cntce := (others=>'0'); -- clear counter
n.fidle := '0'; -- clear force idle flag
else -- if cmem active
if unsigned(r.cntce) >= 127 then -- if max ce count expired
n.fidle := '1'; -- set forced idle flag
else -- if max ce count not yet reached
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
end if;
end if;
if iaddrh_ce = '1' then -- if addresses are latched
n.memdi := DI; -- latch data too...
end if;
if iaddr0_ce = '1' then -- if address bit 0 changed
n.addr0 := iaddr0; -- mirror it in state regs
end if;
N_REGS <= n;
MEM_CE_N <= not imem_ce;
MEM_WE_N <= not imem_we;
MEM_BE_N <= not imem_be;
MEM_OE_N <= not imem_oe;
MEM_CRE <= imem_cre;
if r.addr0 = '0' then
MEM_DI <= r.memdi(15 downto 0);
else
MEM_DI <= r.memdi(31 downto 16);
end if;
BE_CE <= ibe_ce;
ADDRH_CE <= iaddrh_ce;
ADDR0_CE <= iaddr0_ce;
ADDRH <= iaddrh;
ADDR0 <= iaddr0;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;
DATA_OE <= idata_oe;
BUSY <= ibusy;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= iactr;
ACT_W <= iactw;
DO <= MEM_DO & r.memdo0;
end process proc_next;
end syn;
| gpl-3.0 | 8bbd639fb929410b31ea3e29b85ce49b | 0.429484 | 3.781409 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/gray_cnt_n.vhd | 1 | 3,042 | -- $Id: gray_cnt_n.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
-- Description: Genric width Gray code counter
--
-- Dependencies: -
-- Test bench: tb/tb_gray_cnt_n
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2016-03-25 ise 14.7 for xc6slx16-csg324-2:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 5 5 421MHz/ 2.37ns
-- 5 6 6 414MHz/ 2.41ns
-- 6 8 7 361MHz/ 2.77ns
-- 8 10 9 321MHz/ 3.11ns
-- 16 29 17 252MHz/ 3.96ns
-- 32 70 33 214MHz/ 4.65ns
-- 64 173 65 176MHz/ 5.66ns
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 6 5 305MHz/ 3.28ns
-- 5 8 6 286MHz/ 2.85ns
-- 8 13 9 234MHz/ 4.26ns
-- 16 56 17 149MHz/ 6.67ns
-- 32 95 33 161MHz/ 6.19ns
-- 64 188 68 126MHz/ 7.90ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_n;
architecture syn of gray_cnt_n is
signal R_AUX : slbit := '1';
signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
assert DWIDTH>=3
report "assert(DWIDTH>=3): only 3 bit or larger supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_AUX <= '1';
R_DATA <= (others=>'0');
elsif CE = '1' then
R_AUX <= not R_AUX;
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_AUX, R_DATA)
variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
variable s : slbit := '0';
begin
r := R_DATA;
n := R_DATA;
s := '1';
if R_AUX = '1' then
n(0) := not r(0);
else
for i in 1 to DWIDTH-2 loop
if s='1' and r(i-1)='1' then
n(i) := not r(i);
end if;
s := s and not r(i-1);
end loop;
if s = '1' then
n(DWIDTH-1) := r(DWIDTH-2);
end if;
end if;
N_DATA <= n;
end process proc_next;
DATA <= R_DATA;
end syn;
| gpl-3.0 | 4866dc258098ffe8fa5b6adc952797c5 | 0.488494 | 3.069627 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04900_good.vhd | 1 | 2,959 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04900_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of clock signal: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_04900_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_04900_good;
--CODE
architecture Behavioral of CNE_04900_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop:process(i_Clock, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable='1') then -- D Flip-Flop enabled
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE | gpl-3.0 | 9e97c68dbc38637f9ccbd4f79df15af7 | 0.48023 | 4.49696 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/tst_mig.vhd | 1 | 28,047 | -- $Id: tst_mig.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_mig - syn
-- Description: test of mig
--
-- Dependencies: -
--
-- Test bench: arty/tb/tb_tst_mig_arty (with ddr3 via mig)
-- nexys4d/tb/tb_tst_mig_n4d (with ddr2 via mig)
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-12-23 1092 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00000 cntl -/-/f Control register
-- 15:13 cmd 0/w/- commmand code for func=cmd
-- 12 wren 0/w/- wren option for func=cmd
-- 11 dwend 0/w/- disable wend for func=cmd,wren
-- 03:00 func 0/-/f function command
-- 0000 noop
-- 0001 rd read memory
-- 0010 wr write memory
-- 0011 pat sample rdy pattern
-- 0100 ref refresh
-- 0101 cal ZQ cal
-- 0110 cmd send command to mem
-- 0111 wren send wren strobe to mem
-- 00001 stat r/-/- Status register
-- 06 zqpend r/-/- ZQ cal req pending
-- 05 refpend r/-/- refresh req pending
-- 04 rdend r/-/- RD_DATA_END seen
-- 03 uirst r/-/- reset from ui
-- 02 caco r/-/- calibration complete
-- 01 wrdy r/-/- write ready
-- 00 crdy r/-/- cmd ready
-- 00010 conf r/-/- Configuration register
-- 9:05 mawidth r/-/- MAWIDTH
-- 4:00 mwidth r/-/- MWIDTH
-- 00011 15:00 mask r/w/- Mask register
-- 00100 15:00 addrl r/w/- Address register (low part)
-- 00101 15:00 addrh r/w/- Address register (high part)
-- 00110 15:00 temp r/-/- Device temperature
-- 00111 15:00 dvalcnt r/-/- Data valid counter
-- 01000 15:00 crpat r/-/- Command ready pattern
-- 01001 15:00 wrpat r/-/- Write ready pattern
-- 01010 15:00 cwait r/-/- Command wait
-- 01011 15:00 rwait r/-/- Read wait
-- 01100 15:00 xwait r/-/- Request wait
-- 01101 ircnt r/-/- Init/Reset count
-- 15:08 rstcnt r/-/- reset count
-- 7:00 inicnt r/-/- init count
-- 01110 15:00 rsttime r/-/- length of last reset
-- 01111 15:00 initime r/-/- length of last init
-- 10xxx datrd[0-7] r/-/- Data read register
-- 11xxx datwr[0-7] r/w/- Data write register
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rutil.all;
use work.memlib.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity tst_mig is -- tester for mig
generic (
RB_ADDR : slv16 := slv(to_unsigned(2#0000000000000000#,16));
MAWIDTH : natural := 28;
MWIDTH : natural := 16);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv4; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
APP_ADDR : out slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_CMD : out slv3; -- MIGUI command
APP_EN : out slbit; -- MIGUI command enable
APP_WDF_DATA : out slv(8*MWIDTH-1 downto 0);-- MIGUI write data
APP_WDF_END : out slbit; -- MIGUI write end
APP_WDF_MASK : out slv(MWIDTH-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : out slbit; -- MIGUI write enable
APP_RD_DATA : in slv(8*MWIDTH-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : in slbit; -- MIGUI read end
APP_RD_DATA_VALID : in slbit; -- MIGUI read valid
APP_RDY : in slbit; -- MIGUI ready for cmd
APP_WDF_RDY : in slbit; -- MIGUI ready for data write
APP_SR_REQ : out slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : out slbit; -- MIGUI refresh request
APP_ZQ_REQ : out slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : in slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : in slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : in slbit; -- MIGUI ZQ calibrate acknowledge
MIG_UI_CLK_SYNC_RST : in slbit; -- MIGUI reset
MIG_INIT_CALIB_COMPLETE : in slbit; -- MIGUI calibration done
MIG_DEVICE_TEMP_I : in slv12 -- MIGUI xadc temperature
);
end tst_mig;
architecture syn of tst_mig is
type state_type is (
s_idle, -- s_idle: wait for input
s_rdcwait, -- s_rdcwait: read cmd wait
s_rdrwait, -- s_rdrwait: read res wait
s_wrcwait, -- s_wrcwait: write cmd wait
s_cmdwait, -- s_cmdwait: cmd wait
s_wrenwait -- s_wrenwait: wren wait
);
type regs_type is record
state : state_type; -- state
rbsel : slbit; -- rbus select
mask : slv16; -- memory mask
addr : slv32; -- memory address
datrd : slv(127 downto 0); -- memory data read
datwr : slv(127 downto 0); -- memory data write
dvalcnt : slv16; -- data valid counter
crpat : slv16; -- command ready pattern
wrpat : slv16; -- write ready pattern
cwait : slv16; -- command wait counter
rwait : slv16; -- read wait counter
xwait : slv16; -- request wait counter
rstcnt : slv8; -- reset counter
inicnt : slv8; -- init counter
rsttime : slv16; -- reset time counter
initime : slv16; -- init time counter
crsreg : slv15; -- command ready shift register
wrsreg : slv15; -- write ready shift register
rdend : slbit; -- RD_DATA_END capture
refpend : slbit; -- ref req pending
zqpend : slbit; -- zq req pending
caco_1 : slbit; -- last caco
uirst_1 : slbit; -- last uirst
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
(others=>'0'), -- mask
(others=>'0'), -- addr
(others=>'0'), -- datrd
(others=>'0'), -- datwr
(others=>'0'), -- dvalcnt
(others=>'0'), -- crpat
(others=>'0'), -- wrpat
(others=>'0'), -- cwait
(others=>'0'), -- rwait
(others=>'0'), -- xwait
(others=>'0'), -- rstcnt
(others=>'0'), -- inicnt
(others=>'0'), -- rsttime
(others=>'0'), -- initime
(others=>'0'), -- crsreg
(others=>'0'), -- wrsreg
'0','0','0', -- rdend,refpend,zqpend
'0','0' -- caco_1,uirst_1
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
constant rbaddr_cntl: slv5 := "00000"; -- 0 -/-/f
constant rbaddr_stat: slv5 := "00001"; -- 1 r/-/-
constant rbaddr_conf: slv5 := "00010"; -- 2 r/-/-
constant rbaddr_mask: slv5 := "00011"; -- 3 r/w/-
constant rbaddr_addrl: slv5 := "00100"; -- 4 r/w/-
constant rbaddr_addrh: slv5 := "00101"; -- 5 r/w/-
constant rbaddr_temp: slv5 := "00110"; -- 6 r/-/-
constant rbaddr_dvalcnt: slv5 := "00111"; -- 7 r/-/-
constant rbaddr_crpat: slv5 := "01000"; -- 8 r/-/-
constant rbaddr_wrpat: slv5 := "01001"; -- 9 r/-/-
constant rbaddr_cwait: slv5 := "01010"; -- 10 r/-/-
constant rbaddr_rwait: slv5 := "01011"; -- 11 r/-/-
constant rbaddr_xwait: slv5 := "01100"; -- 12 r/-/-
constant rbaddr_ircnt: slv5 := "01101"; -- 13 r/-/-
constant rbaddr_rsttime: slv5 := "01110"; -- 14 r/-/-
constant rbaddr_initime: slv5 := "01111"; -- 15 r/-/-
constant rbaddr_datrd0: slv5 := "10000"; -- 16 r/-/-
constant rbaddr_datrd1: slv5 := "10001"; -- 17 r/-/-
constant rbaddr_datrd2: slv5 := "10010"; -- 18 r/-/-
constant rbaddr_datrd3: slv5 := "10011"; -- 19 r/-/-
constant rbaddr_datrd4: slv5 := "10100"; -- 20 r/-/-
constant rbaddr_datrd5: slv5 := "10101"; -- 21 r/-/-
constant rbaddr_datrd6: slv5 := "10110"; -- 22 r/-/-
constant rbaddr_datrd7: slv5 := "10111"; -- 23 r/-/-
constant rbaddr_datwr0: slv5 := "11000"; -- 14 r/w/-
constant rbaddr_datwr1: slv5 := "11001"; -- 15 r/w/-
constant rbaddr_datwr2: slv5 := "11010"; -- 16 r/w/-
constant rbaddr_datwr3: slv5 := "11011"; -- 17 r/w/-
constant rbaddr_datwr4: slv5 := "11100"; -- 28 r/w/-
constant rbaddr_datwr5: slv5 := "11101"; -- 29 r/w/-
constant rbaddr_datwr6: slv5 := "11110"; -- 30 r/w/-
constant rbaddr_datwr7: slv5 := "11111"; -- 31 r/w/-
subtype cntl_rbf_cmd is integer range 15 downto 13;
constant cntl_rbf_wren : integer := 12;
constant cntl_rbf_dwend : integer := 11;
subtype cntl_rbf_func is integer range 3 downto 0;
constant stat_rbf_zqpend : integer := 6;
constant stat_rbf_refpend : integer := 5;
constant stat_rbf_rdend : integer := 4;
constant stat_rbf_uirst : integer := 3;
constant stat_rbf_caco : integer := 2;
constant stat_rbf_wrdy : integer := 1;
constant stat_rbf_crdy : integer := 0;
subtype conf_rbf_mawidth is integer range 9 downto 5;
subtype conf_rbf_mwidth is integer range 4 downto 0;
subtype ircnt_rbf_rstcnt is integer range 15 downto 8;
subtype ircnt_rbf_inicnt is integer range 7 downto 0;
constant func_noop : slv4 := "0000"; -- func: noop
constant func_rd : slv4 := "0001"; -- func: rd read memory
constant func_wr : slv4 := "0010"; -- func: wr write memory
constant func_pat : slv4 := "0011"; -- func: pat sample rdy pattern
constant func_ref : slv4 := "0100"; -- func: ref refresh
constant func_cal : slv4 := "0101"; -- func: cal ZQ cal
constant func_cmd : slv4 := "0110"; -- func: cmd send command to mem
constant func_wren : slv4 := "0111"; -- func: wren send wren strobe to mem
subtype df_word0 is integer range 15 downto 0;
subtype df_word1 is integer range 31 downto 16;
subtype df_word2 is integer range 47 downto 32;
subtype df_word3 is integer range 63 downto 48;
subtype df_word4 is integer range 79 downto 64;
subtype df_word5 is integer range 95 downto 80;
subtype df_word6 is integer range 111 downto 96;
subtype df_word7 is integer range 127 downto 112;
constant migui_cmd_read : slv3 := "001";
constant migui_cmd_write : slv3 := "000";
begin
assert MAWIDTH <= 32
report "assert(MAWIDTH <= 32): unsupported MAWIDTH"
severity failure;
assert MWIDTH = 8 or MWIDTH = 16
report "assert(MWIDTH = 8 or 16): unsupported MWIDTH"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, CE_USEC,
APP_RD_DATA, APP_RD_DATA_END, APP_RD_DATA_VALID,
APP_RDY, APP_WDF_RDY, APP_REF_ACK, APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST, MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0'; -- re or we -> rbus request
variable iappcmd : slv3 := (others=>'0');
variable iappen : slbit := '0';
variable iappwren : slbit := '0';
variable iappwend : slbit := '0';
variable iappref : slbit := '0';
variable iappzq : slbit := '0';
variable ncrpat : slv16 := (others=>'0');
variable nwrpat : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
iappcmd := migui_cmd_read;
iappen := '0';
iappwren := '0';
iappwend := '0';
iappref := '0';
iappzq := '0';
ncrpat := r.crsreg & APP_RDY; -- current ready patterns
nwrpat := r.wrsreg & APP_WDF_RDY;
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 5)=RB_ADDR(15 downto 5) then
n.rbsel := '1';
end if;
if r.rbsel='1' and irbena='1' then
irb_ack := '1'; -- ack all (maybe rejected later)
end if;
case r.state is
when s_idle => -- s_idle: ---------------------------
-- rbus transactions
if r.rbsel = '1' then
case RB_MREQ.addr(4 downto 0) is
when rbaddr_cntl => -- cntl ---------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_noop => null; -- func: noop -----
when func_rd => -- func: rd -------
n.rdend := '0';
n.cwait := (others=>'0');
n.rwait := (others=>'0');
irb_busy := '1';
n.state := s_rdcwait;
when func_wr => -- func: wr -------
n.cwait := (others=>'0');
n.rwait := (others=>'0');
irb_busy := '1';
n.state := s_wrcwait;
when func_pat => -- func: pat ------
n.crpat := ncrpat;
n.wrpat := nwrpat;
when func_ref => -- func: ref ------
n.xwait := (others=>'0');
if r.refpend = '0' then
n.refpend := '1';
iappref := '1';
else
irb_err := '1';
end if;
when func_cal => -- func: cal ------
n.xwait := (others=>'0');
if r.zqpend = '0' then
n.zqpend := '1';
iappzq := '1';
else
irb_err := '1';
end if;
when func_cmd => -- func: cmd ------
n.cwait := (others=>'0');
n.rwait := (others=>'0');
irb_busy := '1';
n.state := s_cmdwait;
when func_wren => -- func: wren -----
n.cwait := (others=>'0');
n.rwait := (others=>'0');
irb_busy := '1';
n.state := s_wrenwait;
when others => -- <> not yet defined codes
irb_err := '1';
end case;
end if;
when rbaddr_stat => irb_err := RB_MREQ.we;
when rbaddr_conf => irb_err := RB_MREQ.we;
when rbaddr_mask => -- mask ---------------
if RB_MREQ.we = '1' then
n.mask := RB_MREQ.din;
end if;
when rbaddr_addrl => -- addrl --------------
if RB_MREQ.we = '1' then n.addr(df_word0) := RB_MREQ.din; end if;
when rbaddr_addrh => -- addrh --------------
if RB_MREQ.we = '1' then n.addr(df_word1) := RB_MREQ.din; end if;
when rbaddr_temp => irb_err := RB_MREQ.we;
when rbaddr_dvalcnt => irb_err := RB_MREQ.we;
when rbaddr_crpat => irb_err := RB_MREQ.we;
when rbaddr_wrpat => irb_err := RB_MREQ.we;
when rbaddr_cwait => irb_err := RB_MREQ.we;
when rbaddr_rwait => irb_err := RB_MREQ.we;
when rbaddr_xwait => irb_err := RB_MREQ.we;
when rbaddr_ircnt => irb_err := RB_MREQ.we;
when rbaddr_rsttime => irb_err := RB_MREQ.we;
when rbaddr_initime => irb_err := RB_MREQ.we;
when rbaddr_datrd0|rbaddr_datrd1| -- datrd* ----------------
rbaddr_datrd2|rbaddr_datrd3|
rbaddr_datrd4|rbaddr_datrd5|
rbaddr_datrd6|rbaddr_datrd7 => irb_err := RB_MREQ.we;
when rbaddr_datwr0 => -- datwr* ----------------
if RB_MREQ.we = '1' then n.datwr(df_word0) := RB_MREQ.din; end if;
when rbaddr_datwr1 =>
if RB_MREQ.we = '1' then n.datwr(df_word1) := RB_MREQ.din; end if;
when rbaddr_datwr2 =>
if RB_MREQ.we = '1' then n.datwr(df_word2) := RB_MREQ.din; end if;
when rbaddr_datwr3 =>
if RB_MREQ.we = '1' then n.datwr(df_word3) := RB_MREQ.din; end if;
when rbaddr_datwr4 =>
if RB_MREQ.we = '1' then n.datwr(df_word4) := RB_MREQ.din; end if;
when rbaddr_datwr5 =>
if RB_MREQ.we = '1' then n.datwr(df_word5) := RB_MREQ.din; end if;
when rbaddr_datwr6 =>
if RB_MREQ.we = '1' then n.datwr(df_word6) := RB_MREQ.din; end if;
when rbaddr_datwr7 =>
if RB_MREQ.we = '1' then n.datwr(df_word7) := RB_MREQ.din; end if;
when others => -- <> --------------------
irb_ack := '0';
end case;
end if;
when s_rdcwait => -- s_rdcwait -------------------------
iappcmd := migui_cmd_read; -- setup cmd
n.crpat := ncrpat; -- follow RDY patterns
n.wrpat := nwrpat;
if r.rbsel='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle;
else
if APP_RDY = '1' then
iappen := '1';
irb_busy := '1';
n.state := s_rdrwait;
else
n.cwait := slv(unsigned(r.cwait) + 1);
irb_busy := '1';
end if;
end if;
when s_rdrwait => -- s_rdrwait -------------------------
n.rwait := slv(unsigned(r.rwait) + 1);
if r.rbsel='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle;
else
if APP_RD_DATA_VALID = '1' then
n.state := s_idle;
else
irb_busy := '1';
end if;
end if;
when s_wrcwait => -- s_wrcwait -------------------------
iappcmd := migui_cmd_write; -- setup cmd
n.crpat := ncrpat; -- follow RDY patterns
n.wrpat := nwrpat;
if r.rbsel='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle;
else
if APP_RDY = '1' and APP_WDF_RDY = '1' then
iappen := '1';
iappwren := '1';
iappwend := '1';
n.state := s_idle;
else
n.cwait := slv(unsigned(r.cwait) + 1);
irb_busy := '1';
end if;
end if;
when s_cmdwait => -- s_cmdwait -------------------------
iappcmd := RB_MREQ.din(cntl_rbf_cmd); -- setup cmd
n.crpat := ncrpat; -- follow RDY pattern
if r.rbsel='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle;
else
if APP_RDY = '1' then
iappen := '1';
iappwren := RB_MREQ.din(cntl_rbf_wren);
iappwend := RB_MREQ.din(cntl_rbf_wren) and
not RB_MREQ.din(cntl_rbf_dwend);
n.state := s_idle;
else
n.cwait := slv(unsigned(r.cwait) + 1);
irb_busy := '1';
end if;
end if;
when s_wrenwait => -- s_wrenwait ------------------------
n.wrpat := nwrpat; -- follow RDY pattern
if r.rbsel='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle;
else
if APP_WDF_RDY = '1' then
iappwren := '1';
iappwend := not RB_MREQ.din(cntl_rbf_dwend);
n.state := s_idle;
else
n.cwait := slv(unsigned(r.cwait) + 1);
irb_busy := '1';
end if;
end if;
when others => null;
end case;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(4 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_zqpend) := r.zqpend;
irb_dout(stat_rbf_refpend) := r.refpend;
irb_dout(stat_rbf_rdend) := r.rdend;
irb_dout(stat_rbf_uirst) := MIG_UI_CLK_SYNC_RST;
irb_dout(stat_rbf_caco) := MIG_INIT_CALIB_COMPLETE;
irb_dout(stat_rbf_wrdy) := APP_WDF_RDY;
irb_dout(stat_rbf_crdy) := APP_RDY;
when rbaddr_conf =>
irb_dout(conf_rbf_mawidth) := slv(to_unsigned(MAWIDTH,5));
irb_dout(conf_rbf_mwidth) := slv(to_unsigned(MWIDTH,5));
when rbaddr_mask => irb_dout := r.mask;
when rbaddr_addrl => irb_dout := r.addr(df_word0);
when rbaddr_addrh => irb_dout := r.addr(df_word1);
when rbaddr_temp =>
irb_dout(MIG_DEVICE_TEMP_I'range) := MIG_DEVICE_TEMP_I;
when rbaddr_dvalcnt => irb_dout := r.dvalcnt;
when rbaddr_crpat => irb_dout := r.crpat;
when rbaddr_wrpat => irb_dout := r.wrpat;
when rbaddr_cwait => irb_dout := r.cwait;
when rbaddr_rwait => irb_dout := r.rwait;
when rbaddr_xwait => irb_dout := r.xwait;
when rbaddr_ircnt =>
irb_dout(ircnt_rbf_rstcnt) := r.rstcnt;
irb_dout(ircnt_rbf_inicnt) := r.inicnt;
when rbaddr_rsttime => irb_dout := r.rsttime;
when rbaddr_initime => irb_dout := r.initime;
when rbaddr_datrd0 => irb_dout := r.datrd(df_word0);
when rbaddr_datrd1 => irb_dout := r.datrd(df_word1);
when rbaddr_datrd2 => irb_dout := r.datrd(df_word2);
when rbaddr_datrd3 => irb_dout := r.datrd(df_word3);
when rbaddr_datrd4 => irb_dout := r.datrd(df_word4);
when rbaddr_datrd5 => irb_dout := r.datrd(df_word5);
when rbaddr_datrd6 => irb_dout := r.datrd(df_word6);
when rbaddr_datrd7 => irb_dout := r.datrd(df_word7);
when rbaddr_datwr0 => irb_dout := r.datwr(df_word0);
when rbaddr_datwr1 => irb_dout := r.datwr(df_word1);
when rbaddr_datwr2 => irb_dout := r.datwr(df_word2);
when rbaddr_datwr3 => irb_dout := r.datwr(df_word3);
when rbaddr_datwr4 => irb_dout := r.datwr(df_word4);
when rbaddr_datwr5 => irb_dout := r.datwr(df_word5);
when rbaddr_datwr6 => irb_dout := r.datwr(df_word6);
when rbaddr_datwr7 => irb_dout := r.datwr(df_word7);
when others => null;
end case;
end if;
-- update ready shift registers
n.crsreg := ncrpat(n.crsreg'range);
n.wrsreg := nwrpat(n.wrsreg'range);
-- ready data capture
if APP_RD_DATA_VALID = '1' then
n.rdend := APP_RD_DATA_END;
n.datrd(APP_RD_DATA'range) := APP_RD_DATA;
n.dvalcnt := slv(unsigned(r.dvalcnt) + 1);
end if;
-- REF and ZQ handling
if r.refpend = '1' or r.zqpend = '1' then
n.xwait := slv(unsigned(r.xwait) + 1);
end if;
if APP_REF_ACK = '1' then -- REF done
n.refpend := '0';
n.crpat := ncrpat; -- record RDY patterns too
n.wrpat := nwrpat;
end if;
if APP_ZQ_ACK = '1' then -- ZQ done
n.zqpend := '0';
n.crpat := ncrpat; -- record RDY patterns too
n.wrpat := nwrpat;
end if;
-- CACO monitor (length in CE_USEC)
n.caco_1 := MIG_INIT_CALIB_COMPLETE;
if MIG_INIT_CALIB_COMPLETE = '0' then
if r.caco_1 = '1' then
n.initime := (others => '0');
if r.inicnt /= x"ff" then
n.inicnt := slv(unsigned(r.inicnt) + 1);
end if;
else
if r.initime /= x"ffff" then
if CE_USEC = '1' then
n.initime := slv(unsigned(r.initime) + 1);
end if;
end if;
end if;
end if;
-- UIRST monitor (length in CE_USC)
n.uirst_1 := MIG_UI_CLK_SYNC_RST;
if MIG_UI_CLK_SYNC_RST = '1' then
if r.uirst_1 = '0' then
n.rsttime := (others => '0');
if r.rstcnt /= x"ff" then
n.rstcnt := slv(unsigned(r.rstcnt) + 1);
end if;
else
if r.rsttime /= x"ffff" then
if CE_USEC = '1' then
n.rsttime := slv(unsigned(r.rsttime) + 1);
end if;
end if;
end if;
end if;
N_REGS <= n;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
RB_LAM <= '0';
APP_ADDR <= r.addr(APP_ADDR'range);
APP_CMD <= iappcmd;
APP_EN <= iappen;
APP_WDF_DATA <= r.datwr(APP_WDF_DATA'range);
APP_WDF_END <= iappwend;
APP_WDF_MASK <= r.mask(APP_WDF_MASK'range);
APP_WDF_WREN <= iappwren;
APP_REF_REQ <= iappref;
APP_ZQ_REQ <= iappzq;
APP_SR_REQ <= '0';
end process proc_next;
RB_STAT(3) <= '0';
RB_STAT(2) <= '0';
RB_STAT(1) <= '0';
RB_STAT(0) <= '0';
end syn;
| gpl-3.0 | fe5ee210d7d829833dbd063754b9eae1 | 0.453132 | 3.677813 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_reg_i.vhd | 1 | 1,412 | -- $Id: iob_reg_i.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
| gpl-3.0 | 0c5ee4b985e7d1d0f9bea6c2e430659e | 0.475212 | 3.512438 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys4/sys_conf.vhd | 1 | 6,004 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.3; ghdl 0.29-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.6.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.6 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.5.6 add sys_conf_dmpcnt
-- 2018-09-09 1044 1.5.5 use _cache_twidth TW=7 (32 kByte), timing issues
-- 2018-09-08 1043 1.5.4 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.5.3 re-enable dmcmon
-- 2017-03-04 858 1.5.2 enable deuna
-- 2017-01-29 847 1.5.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.5 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt
-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz)
-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser (@75 MHz)
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth, use TW=8 (16 kByte)
-- 2016-03-13 742 1.2.2 add sysmon_bus
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2015-02-07 643 1.1 drop bram and minisys options
-- 2013-09-22 534 1.0 Initial version (derived from _n3 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 013d562fb0b61446bca01e8e9c3a509d | 0.598268 | 3.436749 | false | true | false | false |
Paebbels/PicoBlaze-Library | vhdl/KCPSM6.unconstrained.vhdl | 2 | 109,641 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
--
-- 4th July 2012 - ** SPECIAL VERSION **
--
-- Only use this version if problems are encountered during MAP and all
-- other workarounds described in the 'READ_ME_FIRST.txt' file have been
-- considered.
--
-- In this version all the Slice packing attributes have been commented out
-- and it should be expected that the implementation will be larger than the
-- 26-30 Slices normally achieved. Lower performance may also result.
--
-- Version 1.3 - 21st May 2014.
-- Addition of WebTalk information.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
-- attribute hblknm : string;
-- attribute hblknm of reset_lut : label is "kcpsm6_control";
-- attribute hblknm of run_flop : label is "kcpsm6_control";
-- attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state_lut : label is "kcpsm6_control";
-- attribute hblknm of t_state1_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state2_flop : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
-- attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
-- attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
-- attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
-- attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
-- attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
-- attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
-- attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
-- attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
-- attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
-- attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
-- attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
-- attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_flop : label is "kcpsm6_stack1";
-- attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
-- attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
-- attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
-- attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
-- attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
-- attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
-- attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | c316adabb3baf9f5e9d5aa65b3ecccb4 | 0.497305 | 3.60958 | false | false | false | false |
jasonpeng/cg3207-proj | Decoder_test.vhd | 1 | 8,979 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:07:27 11/13/2013
-- Design Name:
-- Module Name: Y:/cg3207-proj/decoder_test.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Decoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY decoder_test IS
END decoder_test;
ARCHITECTURE behavior OF decoder_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Decoder
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
In_PC : IN std_logic_vector(31 downto 0);
In_Instr : IN std_logic_vector(31 downto 0);
write_address : IN std_logic_vector(4 downto 0);
WriteData1 : IN std_logic_vector(31 downto 0);
WriteData2 : IN std_logic_vector(31 downto 0);
Mul_or_Div : IN std_logic;
RegWrite_in : IN std_logic;
ID_EX_MEM_READ : IN std_logic;
ID_EX_REG_RT : IN std_logic_vector(4 downto 0);
ID_STALL : OUT std_logic;
RegWrite : OUT std_logic;
MemtoReg : OUT std_logic;
MemRead : OUT std_logic;
MemWrite : OUT std_logic;
RegDst : OUT std_logic;
ALUop : OUT std_logic_vector(2 downto 0);
ALUSrc : OUT std_logic;
Jump : OUT std_logic;
JumpPC : OUT std_logic_vector(31 downto 0);
EX_MEM_REG_RD : IN std_logic_vector(4 downto 0);
Branch_Sign_Extended : OUT std_logic_vector(31 downto 0);
PCSrc : OUT std_logic;
read_data_1 : OUT std_logic_vector(31 downto 0);
read_data_2 : OUT std_logic_vector(31 downto 0);
Reg_S1 : OUT std_logic_vector(31 downto 0);
Reg_S2 : OUT std_logic_vector(31 downto 0);
Reg_S3 : OUT std_logic_vector(31 downto 0);
Reg_S4 : OUT std_logic_vector(31 downto 0);
Reg_S5 : OUT std_logic_vector(31 downto 0);
Reg_S6 : OUT std_logic_vector(31 downto 0);
Reg_S7 : OUT std_logic_vector(31 downto 0);
Reg_S8 : OUT std_logic_vector(31 downto 0);
Reg_S31 : OUT std_logic_vector(31 downto 0);
Instr_25to21 : OUT std_logic_vector(4 downto 0);
Instr_20to16 : OUT std_logic_vector(4 downto 0);
Instr_15to11 : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal In_PC : std_logic_vector(31 downto 0) := (others => '0');
signal In_Instr : std_logic_vector(31 downto 0) := (others => '0');
signal write_address : std_logic_vector(4 downto 0) := (others => '0');
signal WriteData1 : std_logic_vector(31 downto 0) := (others => '0');
signal WriteData2 : std_logic_vector(31 downto 0) := (others => '0');
signal Mul_or_Div : std_logic := '0';
signal RegWrite_in : std_logic := '0';
signal ID_EX_MEM_READ : std_logic := '0';
signal ID_EX_REG_RT : std_logic_vector(4 downto 0) := (others => '0');
signal EX_MEM_REG_RD : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal ID_STALL : std_logic;
signal RegWrite : std_logic;
signal MemtoReg : std_logic;
signal MemRead : std_logic;
signal MemWrite : std_logic;
signal RegDst : std_logic;
signal ALUop : std_logic_vector(2 downto 0);
signal ALUSrc : std_logic;
signal Jump : std_logic;
signal JumpPC : std_logic_vector(31 downto 0);
signal Branch_Sign_Extended : std_logic_vector(31 downto 0);
signal PCSrc : std_logic;
signal read_data_1 : std_logic_vector(31 downto 0);
signal read_data_2 : std_logic_vector(31 downto 0);
signal Reg_S1 : std_logic_vector(31 downto 0);
signal Reg_S2 : std_logic_vector(31 downto 0);
signal Reg_S3 : std_logic_vector(31 downto 0);
signal Reg_S4 : std_logic_vector(31 downto 0);
signal Reg_S5 : std_logic_vector(31 downto 0);
signal Reg_S6 : std_logic_vector(31 downto 0);
signal Reg_S7 : std_logic_vector(31 downto 0);
signal Reg_S8 : std_logic_vector(31 downto 0);
signal Reg_S31 : std_logic_vector(31 downto 0);
signal Instr_25to21 : std_logic_vector(4 downto 0);
signal Instr_20to16 : std_logic_vector(4 downto 0);
signal Instr_15to11 : std_logic_vector(4 downto 0);
-- Clock period definitions
constant Clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Decoder PORT MAP (
Clk => Clk,
Reset => Reset,
In_PC => In_PC,
In_Instr => In_Instr,
write_address => write_address,
WriteData1 => WriteData1,
WriteData2 => WriteData2,
Mul_or_Div => Mul_or_Div,
RegWrite_in => RegWrite_in,
ID_EX_MEM_READ => ID_EX_MEM_READ,
ID_EX_REG_RT => ID_EX_REG_RT,
ID_STALL => ID_STALL,
RegWrite => RegWrite,
MemtoReg => MemtoReg,
MemRead => MemRead,
MemWrite => MemWrite,
RegDst => RegDst,
ALUop => ALUop,
ALUSrc => ALUSrc,
Jump => Jump,
JumpPC => JumpPC,
EX_MEM_REG_RD => EX_MEM_REG_RD,
Branch_Sign_Extended => Branch_Sign_Extended,
PCSrc => PCSrc,
read_data_1 => read_data_1,
read_data_2 => read_data_2,
Reg_S1 => Reg_S1,
Reg_S2 => Reg_S2,
Reg_S3 => Reg_S3,
Reg_S4 => Reg_S4,
Reg_S5 => Reg_S5,
Reg_S6 => Reg_S6,
Reg_S7 => Reg_S7,
Reg_S8 => Reg_S8,
Reg_S31 => Reg_S31,
Instr_25to21 => Instr_25to21,
Instr_20to16 => Instr_20to16,
Instr_15to11 => Instr_15to11
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Reset <= '1';
wait for 100 ns;
Reset <= '0';
IN_PC <= X"10000000";
In_Instr <= X"34010064";
write_address <= "00001";
Writedata1 <= X"00000008";
RegWrite_in <= '1';
wait for 100 ns;
IN_PC <= X"10000004";
In_Instr <= X"34020014";
write_address <= "00010";
Writedata1 <= X"0000000A";
RegWrite_in <= '1';
wait for 100 ns;
IN_PC <= X"10000008";
In_Instr <= X"00221827";
write_address <= "00011";
Writedata1 <= X"00000010";
RegWrite_in <= '1';
-- insert stimulus here
wait for 100 ns;
IN_PC <= X"1000000C";
In_Instr <= X"34080064";
write_address <= "00100";
Writedata1 <= X"00000000";
RegWrite_in <= '1';
wait for 100 ns;
IN_PC <= X"1000000C";
In_Instr <= x"1022fffd";
write_address <= "00101";
Writedata1 <= X"000000FF";
RegWrite_in <= '1';
wait for 100 ns;
EX_MEM_REG_RD <= "00001";
In_Instr <= X"1022fffd"; -- case BEQ, $1,$2
wait for 100 ns;
EX_MEM_REG_RD <= "00001";
In_Instr <= x"0481fffb";
wait for 100 ns;
EX_MEM_REG_RD <= "00001";
In_Instr <= x"0421fffa";
wait for 100 ns;
EX_MEM_REG_RD <= "00001";
In_Instr <=x"0431fff9";
wait for 100 ns;
EX_MEM_REG_RD <= "00100";
In_Instr <= X"0491fff8";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | 0aae276145bb79d6564e1fad19ba1dcf | 0.516984 | 3.67841 | false | false | false | false |
abcsds/Micros | RS232Write_16/FSM16_control.vhd | 2 | 2,454 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FSM16_control is
port(
RST : in std_logic;
CLK : in std_logic;
START : in std_logic;
EOT : in std_logic;
RDY : out std_logic;
SEL : out std_logic;
STR : out std_logic
);
end FSM16_control;
architecture simple of FSM16_control is
signal Qp,Qn : std_logic_vector(2 downto 0);
begin
combinacional: process(EOT,START,Qp)
begin
case Qp is
when "000"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "001";
end if;
SEL <= '0';
STR <= '0';
RDY <= '1';
when "001"=>
Qn <= "010";
SEL <= '0';
STR <= '1';
RDY <= '0';
when "010"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "011";
end if;
SEL <= '0';
STR <= '0';
RDY <= '0';
when "011"=>
Qn <= "100";
SEL <= '1';
STR <= '0';
RDY <= '0';
when "100"=>
Qn <= "101";
SEL <= '1';
STR <= '1';
RDY <= '0';
when "101"=>
if(EOT = '0') then
Qn <= Qp;
else
Qn <= "110";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when "110"=>
if(START = '0') then
Qn <= Qp;
else
Qn <= "000";
end if;
SEL <= '1';
STR <= '0';
RDY <= '0';
when others=>
Qn <= "000";
SEL <= '0';
STR <= '0';
RDY <= '1';
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>"000");
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process secuencial;
end simple;
| gpl-3.0 | 11c0542422641bd9ba48c4894a461771 | 0.310921 | 4.267826 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/rlinktblib.vhd | 1 | 6,888 | -- $Id: rlinktblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rlinktblib
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 4.1 drop tbcore_rlink component definition
-- 2014-08-28 588 4.0 now full rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.1 new clock iface for tbcore_rlink; drop .._dcm
-- 2010-12-29 351 3.0.1 add rbtba_aif;
-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
-- many rri->rlink renames; drop rbus parts;
-- 2010-11-13 338 2.5.2 add rritb_core_dcm
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
-- drop RP_IINT signal from interfaces
-- add sbcntl_sbf_(cp|rp)mon defs
-- 2010-04-24 282 2.1 add rritb_core
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb)
-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb)
-- 2007-09-01 78 1.1.2 add rricp_rp
-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb
-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes
-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon
-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors
-- 2007-07-15 66 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rlinklib.all;
package rlinktblib is
type rlink_tba_cntl_type is record -- rlink_tba control
cmd : slv3; -- command code
ena : slbit; -- command enable
addr : slv16; -- address
cnt : slv16; -- block size
eop : slbit; -- end packet after current command
end record rlink_tba_cntl_type;
constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
(others=>'0'), -- cmd
'0', -- ena
(others=>'0'), -- addr
(others=>'0'), -- cnt
'0'); -- eop
type rlink_tba_stat_type is record -- rlink_tba status
busy : slbit; -- command busy
ack : slbit; -- command acknowledge
err : slbit; -- command error flag
stat : slv8; -- status flags
braddr : slv16; -- block read address (for wblk)
bre : slbit; -- block read enable (for wblk)
bwaddr : slv16; -- block write address (for rblk)
bwe : slbit; -- block write enable (for rblk)
dcnt : slv16; -- block done count
apend : slbit; -- attn pending (from stat)
ano : slbit; -- attn notify seen
apat : slv16; -- attn pattern
end record rlink_tba_stat_type;
constant rlink_tba_stat_init : rlink_tba_stat_type := (
'0','0','0', -- busy, ack, err
(others=>'0'), -- stat
(others=>'0'), -- braddr
'0', -- bre
(others=>'0'), -- bwaddr
'0', -- bwe
(others=>'0'), -- dcnt
'0','0', -- apend, ano
(others=>'0') -- apat
);
component rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end component;
component rbtba_aif is -- rbus tba, abstract interface
-- no generics, no records
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end component;
-- FIXME after this point !!
component rricp_rp is -- rri comm->reg port aif forwarder
-- implements rricp_aif, uses rrirp_aif
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit := '0' -- rlink: data hold
);
end component;
end package rlinktblib;
| gpl-3.0 | 0975ca4210f55e23f02e929bb351c4b3 | 0.469222 | 3.863152 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd | 1 | 2,142 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | c83d7c8bc9af675800486258b8a349ec | 0.63212 | 3.540496 | false | false | false | false |
wfjm/w11 | rtl/bplib/basys3/tb/tb_basys3.vhd | 1 | 5,103 | -- $Id: tb_basys3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_basys3 - sim
-- Description: Test bench for basys3 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_basys3_core
-- serport/tb/serport_master_tb
-- basys3_aif [UUT]
--
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.1.5 use sfs_gsim_core
-- 2016-09-02 805 1.1.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.basys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_basys3 is
end tb_basys3;
architecture sim of tb_basys3 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv16 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
B3CORE : entity work.tb_basys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : basys3_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most basys3 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 1f324404dccc4f491ba70ce4fc26eec0 | 0.546345 | 3.368317 | false | false | false | false |
nsensfel/tabellion | data/test/CNE_01200/valid.vhd | 1 | 3,084 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of valid is
type enum_t is (V0, V1, V2, V3);
signal s0, s1, s2, s3: std_logic;
signal st0: enum_t;
signal n0, n1, n2, n3: natural range 0 to 3;
begin
process (s0, s1) -- $SOL:0:0$
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:1:0$
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:2:0$
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
process (s0, s1, s2) -- $SOL:3:0$
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op0 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
with ip0 select
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
with st0 select
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when V2,
s1 when V3;
P_e: with st0 select
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when others;
process (s0, s1, s2, s3) -- $SOL:4:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when V1 =>
op0 <= s2;
when V0 =>
op0 <= s3;
end case;
end process;
Inprocess: process (s0, s1, s2, s3) -- $SOL:5:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when others =>
op0 <= s2;
end case;
end process;
My_Process: process (n0, n2) -- $SOL:6:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 to 2 =>
n1 <= n2;
when 3 =>
n1 <= 2;
end case;
end process;
nothing: process (n0, n2) -- $SOL:7:0$
begin
case n0 is
when 0 =>
P_I0: n1 <= 0;
when 1 =>
P_I1: n1 <= n3;
when 2 =>
P_I2: n1 <= n2;
when 3 =>
P_I3: n1 <= 2;
end case;
end process;
Still: process (n0, n3) -- $SOL:8:0$
begin
What: case n0 is
when 0 =>
May: n1 <= 0;
when 1 =>
Be: n1 <= n3;
when others =>
Caught: n1 <= n3;
end case;
end process;
end;
| apache-2.0 | 655fc62e555707de2b3e1713b2e91e0f | 0.390402 | 3.10574 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd | 1 | 1,343 | -- $Id: sys_conf_ba4_msim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=4;btyp=msim)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 4; -- 128 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_msim;
end package sys_conf;
| gpl-3.0 | 9f79e5d749aa4f2b500864f2cbe370d7 | 0.521221 | 3.881503 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/UART6_TX.vhdl | 1 | 15,376 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6 - constrained
--
architecture rtl of uart_tx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_tx6_1";
attribute hblknm of pointer3_flop : label is "uart_tx6_1";
attribute hblknm of pointer2_lut : label is "uart_tx6_1";
attribute hblknm of pointer2_flop : label is "uart_tx6_1";
attribute hblknm of pointer01_lut : label is "uart_tx6_1";
attribute hblknm of pointer1_flop : label is "uart_tx6_1";
attribute hblknm of pointer0_flop : label is "uart_tx6_1";
attribute hblknm of data_present_lut : label is "uart_tx6_1";
attribute hblknm of data_present_flop : label is "uart_tx6_1";
--
attribute hblknm of sm0_lut : label is "uart_tx6_2";
attribute hblknm of sm0_flop : label is "uart_tx6_2";
attribute hblknm of sm1_lut : label is "uart_tx6_2";
attribute hblknm of sm1_flop : label is "uart_tx6_2";
attribute hblknm of sm2_lut : label is "uart_tx6_2";
attribute hblknm of sm2_flop : label is "uart_tx6_2";
attribute hblknm of sm3_lut : label is "uart_tx6_2";
attribute hblknm of sm3_flop : label is "uart_tx6_2";
--
attribute hblknm of div01_lut : label is "uart_tx6_3";
attribute hblknm of div23_lut : label is "uart_tx6_3";
attribute hblknm of div0_flop : label is "uart_tx6_3";
attribute hblknm of div1_flop : label is "uart_tx6_3";
attribute hblknm of div2_flop : label is "uart_tx6_3";
attribute hblknm of div3_flop : label is "uart_tx6_3";
attribute hblknm of next_lut : label is "uart_tx6_3";
attribute hblknm of next_flop : label is "uart_tx6_3";
attribute hblknm of read_flop : label is "uart_tx6_3";
--
attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
attribute hblknm of msb_data_lut : label is "uart_tx6_4";
attribute hblknm of serial_lut : label is "uart_tx6_4";
attribute hblknm of serial_flop : label is "uart_tx6_4";
attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_tx6_5";
attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | 629f9baf56ed8b6b6b4be6af3baa0ebd | 0.492456 | 3.853634 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_uart_tx.vhd | 1 | 3,761 | -- $Id: serport_uart_tx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_tx - syn
-- Description: serial port UART - transmitter
--
-- Dependencies: -
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this)
-- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_tx is -- serial port uart: transmit part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_tx;
architecture syn of serport_uart_tx is
type regs_type is record
ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
bcnt : slv4; -- bit counter
sreg : slv9; -- output shift register
busy : slbit;
end record regs_type;
constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
cntzero,
(others=>'0'),
(others=>'1'), -- sreg to all 1 !!
'0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ld_ccnt : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ld_ccnt := '0';
if r.busy = '0' then
ld_ccnt := '1';
n.bcnt := (others=>'0');
if TXENA = '1' then
n.sreg := TXDATA & '0'; -- add start (0) bit
n.busy := '1';
end if;
else
if unsigned(r.ccnt) = 0 then
ld_ccnt := '1';
n.sreg := '1' & r.sreg(8 downto 1);
n.bcnt := slv(unsigned(r.bcnt) + 1);
if unsigned(r.bcnt) = 9 then -- if 10 bits send
n.busy := '0'; -- declare all done
end if;
end if;
end if;
if RESET = '1' then
ld_ccnt := '1';
n.busy := '0';
end if;
if ld_ccnt = '1' then
n.ccnt := CLKDIV;
else
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
N_REGS <= n;
TXBUSY <= r.busy;
TXSD <= r.sreg(0);
end process proc_next;
end syn;
| gpl-3.0 | e1cbe1a9ded579cb7f51b67eb10de8f8 | 0.523265 | 3.544769 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd | 1 | 10,216 | -- $Id: tb_nexys3_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp_cuff - sim
-- Description: Test bench for nexys3 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tbcore/tbcore_rlink
-- tb_nexys3_core
-- serport/tb/serport_master_tb
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp_cuff is
end tb_nexys3_fusp_cuff;
architecture sim of tb_nexys3_fusp_cuff is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_cuff_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 2cb10aac4f693c5af1cf73f2b556924d | 0.519283 | 3.013569 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd | 1 | 5,766 | -- $Id: tbu_rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbu_rlink_sp1c - syn
-- Description: Wrapper for rlink_sp1c to avoid records.
-- It has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: rlink_sp1c
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-22 442 13.1 O40d xc3s1000-4 348 704 64 473 s 9.08
-- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65
-- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL
-- 2014-08-31 590 4.0 now full rlink v4 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-22 442 3.2 renamed and retargeted to test rlink_sp1c
-- 2011-11-19 427 3.1.2 now numeric_std clean
-- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport
-- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end entity tbu_rlink_sp1c;
architecture syn of tbu_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbd_rlink_sp1c !!
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
begin
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 5,
RTAWIDTH => 11,
SYSID => x"76543210",
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RLBMON=> sbcntl_sbf_rlbmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => c_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_INT,
RESET => RESET,
ENAXON => '0',
ESCFILL => '0',
RXSD => RXSD,
TXSD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open
-- SER_MONI => open -- ISE 13.1 err's when a second record is mapped open
);
end syn;
| gpl-3.0 | 3071fc820f062217b13b0bbd87cb51b8 | 0.53642 | 3.121819 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd | 1 | 1,343 | -- $Id: sys_conf_ba3_msim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=3;btyp=msim)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 3; -- 64 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_msim;
end package sys_conf;
| gpl-3.0 | da569ca0d79a01aab083d021ed17a78c | 0.520477 | 3.870317 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_ConverterBCD24_Device.vhdl | 1 | 6,455 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Binary to BCD converter (24 bit) for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_ConverterBCD24_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_ConverterBCD24_Device is
constant REG_WO_A0 : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant REG_WO_A1 : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant REG_WO_A2 : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant REG_RO_R0 : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant REG_RO_R1 : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant REG_RO_R2 : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant REG_RO_STATUS : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_Start : STD_LOGIC := '0';
signal Flag_IsSigned : STD_LOGIC := '0';
signal Reg_Operand_a : T_SLV_24 := (OTHERS => '0');
signal Reg_Result : T_SLV_32 := (OTHERS => '0');
signal Conv_Busy : STD_LOGIC;
signal Conv_Busy_d : STD_LOGIC := '0';
signal Conv_Busy_fe : STD_LOGIC;
signal Conv_Sign : STD_LOGIC;
signal Conv_Result : T_BCD_VECTOR(6 downto 0);
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
Reg_Start <= '0';
Flag_IsSigned <= '0';
if (Reset = '1') then
Reg_Operand_A <= (others => '0');
Reg_Result <= (others => '0');
else
if (AdrDec_we = '1') then
case AdrDec_WriteAddress(1 downto 0) IS
when REG_WO_A0 => Reg_Operand_A(7 downto 0) <= AdrDec_Data;
when REG_WO_A1 => Reg_Operand_A(15 downto 8) <= AdrDec_Data;
when REG_WO_A2 => Reg_Operand_A(23 downto 16) <= AdrDec_Data;
Reg_Start <= '1';
when others => null;
end case;
elsif (Conv_Busy_fe = '1') then
Reg_Result(31 downto 28) <= "0000";
for i in 0 to 6 loop
Reg_Result((i * 4) + 3 downto (i * 4)) <= std_logic_vector(Conv_Result(i));
end loop;
end if;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_Result, Conv_Sign, Conv_Busy)
variable Reg_Result_slvv : T_SLVV_8(3 downto 0);
begin
Reg_Result_slvv := to_slvv_8(Reg_Result);
DataOut <= Reg_Result_slvv(to_index(AdrDec_ReadAddress(1 downto 0), Reg_Result_slvv'length - 1));
if (AdrDec_ReadAddress(1 downto 0) = REG_RO_STATUS) then
DataOut <= (not Conv_Busy) & "00" & Conv_Sign & Reg_Result_slvv(Reg_Result_slvv'high)(3 downto 0);
end if;
end process;
Interrupt <= Conv_Busy_fe;
Message <= to_slv(0, Message'length);
Conv : entity PoC.arith_convert_bin2bcd
generic map (
BITS => 24,
DIGITS => 7,
RADIX => 4
)
port map (
Clock => Clock,
Reset => Reset,
Start => Reg_Start,
Busy => Conv_Busy,
Binary => Reg_Operand_A,
IsSigned => Flag_IsSigned,
BCDDigits => Conv_Result,
Sign => Conv_Sign
);
Conv_Busy_d <= Conv_Busy when rising_edge(Clock);
Conv_Busy_fe <= Conv_Busy_d and not Conv_Busy;
end;
| apache-2.0 | 8598e3aa05ab8e45395263bb5c62978d | 0.529512 | 3.112343 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty/sys_conf.vhd | 1 | 4,499 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-05 1159 1.1.2 down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.0.1 down-rate to 75 MHz, viv 2018.3 fails with 80 MHz
-- 2018-11-17 1071 1.0 Initial version (derived from _br_arty version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5;
constant sys_conf_clksys_vcomultiply : positive := 54; -- vco 1080 MHz
constant sys_conf_clksys_outdivide : positive := 15; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | a4dd869415f256eff281f4136d19329f | 0.591687 | 3.663681 | false | true | false | false |
hubertokf/VHDL-MIPS-Pipeline | opULA.vhd | 1 | 1,259 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY opULA IS
PORT (
ULAop :in std_logic_vector(1 downto 0);
funct :in std_logic_vector(5 downto 0);
oper :out std_logic_vector(3 downto 0)
);
END opULA;
ARCHITECTURE rtl OF opULA IS
BEGIN
process(ULAop,funct)
begin
CASE ULAop IS
WHEN "00" =>
oper <= "0010";
WHEN "01" =>
oper <= "0110";
WHEN "10" =>
CASE funct IS
WHEN "100000" => --add
oper <= "0010";
WHEN "100001" => --addu
oper <= "0010";
WHEN "100100" => --and
oper <= "0000";
WHEN "100111" => --nor
oper <= "0101";
WHEN "100101" => --or
oper <= "0001";
WHEN "000000" => --sll
oper <= "1001";
WHEN "000010" => --srl
oper <= "1010";
WHEN "000011" => --sra
oper <= "1011";
WHEN "100010" => --sub
oper <= "0110";
WHEN "100110" => --xor
oper <= "1000";
WHEN "101010" => --slt
oper <= "1100";
WHEN "101011" => --sltu
oper <= "1101";
WHEN OTHERS =>
oper <= "0010";
END CASE;
WHEN OTHERS =>
oper <= "0010";
END CASE;
end process;
END rtl;
| mit | 162e64f7fc75a6bb11ed4976d777eb47 | 0.492454 | 3.055825 | false | false | false | false |
nanomolina/vhdl_examples | datapath/datapath.vhd | 2 | 2,281 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.components.all;
entity datapath is
port (MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump,
dump, reset, clk: in std_logic;
AluControl: in std_logic_vector(2 downto 0);
pc, instr: out std_logic_vector(31 downto 0));
end entity;
architecture arq_datapath of datapath is
--signal MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump,
-- dump, reset, clk,: std_logic;
--signal AluControl: std_logic_vector(2 downto 0);
--signal pc, instr: std_logic_vector(31 downto 0));
signal PCSrc: std_logic;
signal PCPlus4, PCBranch, PCNext, PCJump, PC1,
Instr1, Result, SrcA, WriteData, SrcB,
SignImm, SignImms2, ALUResult,
ReadData: std_logic_vector(31 downto 0);
signal WriteReg: std_logic_vector(4 downto 0);
signal zero: std_logic;
begin
PCSrc <= Branch and '0';
a0: mux2 port map(d0=>PCNext, d1=>PCBranch, s=>PCSrc, y=>PCNext);
PCJump <= PCPlus4(31 downto 28) and Instr1(25 downto 0) and "00";
a1: mux2 port map(d0=>PCNext, d1=>PCJump, s=>Jump, y=>PC1);
a2: flopr port map(d=>PC1, clk=>clk, reset=>reset, q=>PC1);
a3: adder port map(a=>PC1, b=>x"00000100", y=>PCPlus4);
a4: imem port map(a=>PC1(7 downto 2), y=>Instr1);
a5: regfile port map(ra1=>Instr1(25 downto 21), ra2=>Instr1(20 downto 16),
wa3=>WriteReg, wd3=>Result, we3=>RegWrite, clk=>clk,
rd1=>SrcA, rd2=>WriteData);
a6: mux2 port map(d0=>WriteData, d1=>SignImm, s=>AluSrc, y=>SrcB);
a7: signext port map(a=>Instr1(15 downto 0), y=>SignImm);
a8: mux2 generic map(N=>5) port map(d0=>Instr1(20 downto 16),
d1=>Instr1(15 downto 11), s=>RegDst, y=>WriteReg);
a9: sl2 port map(a=>SignImm, y=>SignImms2);
a10: adder port map(a=>SignImms2, b=>PCPlus4, y=>PCBranch);
a11: ALU port map(a=>SrcA, b=>SrcB, alucontrol=>AluControl, zero=>zero,
result=>ALUResult);
a12: dmem port map(a=>ALUResult, wd=>WriteData, clk=>clk, we=>MemWrite,
rd=>ReadData);
a13: mux2 port map(d0=>ALUResult, d1=>ReadData, s=>MemToReg, y=>Result);
pc <= PC1;
instr <= Instr1;
end architecture;
| gpl-3.0 | 57b48ae232936a33b1e95740c49feea2 | 0.61815 | 3.168056 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32i/cpu.vhd | 3 | 2,184 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity processor is
port ( clk_i: in std_logic;
rst_i: in std_logic;
stall_i: in std_logic;
addr_o: out std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
data_w_o: out std_logic_vector(3 downto 0);
data_mode_o: out std_logic_vector(2 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end processor;
architecture arch_processor of processor is
signal stall_cpu, mwait_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_b_cpu, data_h_cpu, data_access_cpu: std_logic;
signal irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_w_cpu: std_logic_vector(3 downto 0);
begin
data_mode_o <= data_b_cpu & data_h_cpu & data_access_cpu;
-- HF-RISC core
core: entity work.datapath
port map( clock => clk_i,
reset => rst_i,
stall => stall_cpu,
mwait => mwait_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_b => data_b_cpu,
data_h => data_h_cpu,
data_access => data_access_cpu
);
-- interrupt controller
int_control: entity work.interrupt_controller
port map(
clock => clk_i,
reset => rst_i,
stall => stall_i,
stall_cpu => stall_cpu,
mwait_cpu => mwait_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => addr_o,
data_read_mem => data_i,
data_write_mem => data_o,
data_we_mem => data_w_o,
extio_in => extio_in,
extio_out => extio_out
);
end arch_processor;
| gpl-2.0 | 824688b22ede5c5bd7c707a3616bdb63 | 0.651099 | 2.519031 | false | false | false | false |
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