repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
xdsopl/vhdl | test2.vhd | 1 | 1,743 | -- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
generic (
NUM_LEDS : positive := 5
);
port (
clock : in std_logic;
reset : in std_logic;
rotary : in std_logic_vector (1 downto 0);
leds : out std_logic_vector (NUM_LEDS-1 downto 0);
dclock : out std_logic
);
end test2;
architecture rtl of test2 is
signal pulse : std_logic;
signal direction : std_logic;
signal divided : std_logic;
signal divider : integer range 0 to 2**NUM_LEDS-1 := 0;
signal counter : integer range 0 to 2**NUM_LEDS-1 := 0;
begin
leds <= std_logic_vector(to_unsigned(divider, NUM_LEDS));
dclock <= divided;
quadrature_decoder_inst: entity work.quadrature_decoder
port map (clock, rotary, direction, pulse);
process (reset, clock)
begin
if reset = '1' then
counter <= 0;
divided <= '0';
elsif rising_edge(clock) then
if counter = 0 then
counter <= divider;
divided <= not divided;
else
counter <= counter - 1;
end if;
end if;
end process;
process (reset, pulse)
begin
if reset = '1' then
divider <= 0;
elsif rising_edge(pulse) then
if direction = '0' then
divider <= divider + 1;
else
divider <= divider - 1;
end if;
end if;
end process;
end rtl;
| cc0-1.0 | 2c2ae0cc8cae8b71685465c27b98b533 | 0.69191 | 3.282486 | false | true | false | false |
xdsopl/vhdl | pulse_generator.vhd | 1 | 1,100 | -- pulse_generator - create one clock cycle lasting pulse
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity pulse_generator is
port (
clock : in std_logic;
reset : in std_logic;
input : in std_logic;
pulse : out std_logic
);
end pulse_generator;
architecture rtl of pulse_generator is
signal state : std_logic;
begin
process (reset, clock)
begin
if reset = '1' then
state <= '0';
pulse <= '0';
elsif rising_edge(clock) then
if input = '1' then
if state = '0' then
state <= '1';
pulse <= '1';
else
pulse <= '0';
end if;
else
state <= '0';
pulse <= '0';
end if;
end if;
end process;
end rtl;
| cc0-1.0 | dbbc90f80c42cb92d958c78256cb3228 | 0.677273 | 3.353659 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_init_3.vhd | 2 | 15,102 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | bb646faa824116995ef3d773f93de08a | 0.537478 | 3.846663 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/wrpfifo_dp_cntl.vhd | 3 | 51,701 | -------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_counter_top;
Use opb_v20_v1_10_d.pf_occ_counter_top;
Use opb_v20_v1_10_d.pf_adder;
Use opb_v20_v1_10_d.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_v20_v1_10_d.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
| bsd-3-clause | 80f43bd299f86ee6eb88955cbb0c149b | 0.359316 | 5.06972 | false | false | false | false |
jevinskie/aes-over-pcie | source/mix_columns.vhd | 1 | 1,683 | -- File name: mix_columns.vhd
-- Created: 2009-03-29
-- Author: Matt Swanson
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael MixColumns
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mix_columns is
port (
d_in : in col;
d_out : out col
);
end entity mix_columns;
architecture behavioral of mix_columns is
begin
-- Rijndael mix columns matrix
-- [ r0 ] = [ 2 3 1 1 ] [ a0 ]
-- [ r1 ] = [ 1 2 3 1 ] [ a1 ]
-- [ r2 ] = [ 1 1 2 3 ] [ a2 ]
-- [ r3 ] = [ 3 1 1 2 ] [ a3 ]
--
-- Note: addition -> XOR
-- r0 = 2a0 + a3 + a2 + 3a1
-- r1 = 2a1 + a0 + a3 + 3a2
-- r2 = 2a2 + a1 + a0 + 3a3
-- r3 = 2a3 + a2 + a1 + 3a0
process(d_in)
variable b : col; --temp calculation variable
begin
--multiply by 2 is done with a left shift
--need Galois field correction for b here; i.e. b(i) must be 8-bits still
--Algo: check if upper nibble of d_in(1) = 0x80, if so b(i) = b(i) XOR 0x1b
for i in index loop
b(i) := d_in(i) sll 1;
if d_in(i)(7) = '1' then
b(i) := (b(i) xor x"1b");
end if;
end loop;
--when multiply by 3 is needed, we can break that into x*(2x)
d_out(0) <= b(0) xor d_in(3) xor d_in(2) xor b(1) xor d_in(1);
d_out(1) <= b(1) xor d_in(0) xor d_in(3) xor b(2) xor d_in(2);
d_out(2) <= b(2) xor d_in(1) xor d_in(0) xor b(3) xor d_in(3);
d_out(3) <= b(3) xor d_in(2) xor d_in(1) xor b(0) xor d_in(0);
end process;
end architecture behavioral;
| bsd-3-clause | 5349095e43844e1bec00af323c812b50 | 0.510992 | 2.569466 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/abc.vhd | 9 | 24,027 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_a;
use fsl_v20_v2_11_a.all;
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
entity user_logic is
generic
(
C_THREAD_MANAGER_BASEADDR : std_logic_vector := x"11000000";
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
);
port
(
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
);
end entity user_logic;
architecture IMP of user_logic is
-- Define the memory map for each command register, Address[13 to 14], This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals, FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_THREAD_MANAGER_BASEADDR or mask;
end function;
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 5d0b75352f053f438c85aace6fb0ee79 | 0.551671 | 3.244261 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_plbv46_bridge_v1_01_a/hdl/vhdl/opb_slave.vhd | 3 | 45,692 | -------------------------------------------------------------------------------
-- $Id: opb_slave.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: opb_slave.vhd
--
-- Description: This block maintains state about the current status of
-- plbv46 write operations, the state of plbv46 read
-- operations and the availability of prefetch data in the
-- LocalLink read buffer. It also provides a transaction
-- timeout timer in the event that read data is never claimed
-- or write data can't make it onto the PLBv46 bus.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated and Changelog
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
-------------------------------------------------------------------------------
ENTITY opb_slave IS
GENERIC (
-- OPB Address range definition
C_NUM_ADDR_RNG : integer RANGE 1 TO 4 := 1; -- Number of Address Ranges
C_RNG0_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG0_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG1_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG1_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG2_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG2_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG3_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG3_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
-- PLB I/O Specification
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-- OPB slave to Bridge Interface
brdg_block : IN std_logic; -- bridge block
brdg_prefetch_cmplt : IN std_logic; -- bridge prefetch complete
brdg_prefetch_status : IN std_logic; -- bridge prefetch status
opbs_prefetch_req : OUT std_logic; -- opb slave prefetch request
opbs_type : OUT std_logic; -- opb slave transaction request type
opbs_prefetch_clr : OUT std_logic; -- opb slave prefetch clear
opbs_postedwr_clr : OUT std_logic; -- opb slave posted write clear
opbs_trans_addr : OUT std_logic_vector(0 TO 31); -- opb slave transaction address
opbs_length : OUT std_logic_vector(0 TO 11); -- opb slave transaction length
opbs_postedwrt_req : OUT std_logic; -- opb slave posted write request
opbs_be : OUT std_logic_vector(0 TO 3); -- opb slave byte enable
-- Local Link Read Buffer
bfs_data : IN std_logic_vector(0 TO 31); -- Read data output to user logic
bfs_sof_n : IN std_logic; -- Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n : IN std_logic; -- Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n : IN std_logic; -- Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n : IN std_logic; -- Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n : OUT std_logic; -- Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n : OUT std_logic; -- Active low signal that the read local link destination needs to discontinue the transfer.
-- Local Link Write Buffer
bfd_data : OUT std_logic_vector(0 TO 31);
bfd_sof_n : OUT std_logic;
bfd_eof_n : OUT std_logic;
bfd_src_rdy_n : OUT std_logic;
bfd_src_dsc_n : OUT std_logic;
bfd_dst_rdy_n : IN std_logic;
bfd_dst_dsc_n : IN std_logic;
-- OPB Slave Interface
OPB_Select : IN std_logic; -- OPB Master select
OPB_RNW : IN std_logic; -- OPB Read not Write
OPB_BE : IN std_logic_vector(0 TO (32/8)-1); -- OPB transaction byte enables
OPB_seqAddr : IN std_logic; -- OPB sequential address
OPB_DBus : IN std_logic_vector(0 TO 32-1); -- OPB master data bus
OPB_ABus : IN std_logic_vector(0 TO 32-1); -- OPB Slave address bus
Sl_xferAck : OUT std_logic; -- OPB Slave transfer acknowledgement
Sl_errAck : OUT std_logic; -- OPB Slave transaction error acknowledgement
Sl_retry : OUT std_logic; -- OPB Slave transaction retry
Sl_ToutSup : OUT std_logic; -- OPB Slave timeout suppress
Sl_DBus : OUT std_logic_vector(0 TO 32-1); -- OPB Slave data bus
-- System Interface
MPLB_rst : IN std_logic; -- plb reset
MPLB_clk : IN std_logic; -- plb clock
SOPB_rst : IN std_logic; -- OPB reset
SOPB_clk : IN std_logic -- OPB clock
);
END ENTITY opb_slave;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
ARCHITECTURE syn OF opb_slave IS
-- Asserts high when OPB_ABus matches one of the proscribed address ranges
SIGNAL arng_match_ns : std_logic; -- address range match
-- Max Number of words that can be read or written in PLBv46 master burst
-- transaction. This becomes the ack_count as the burst is processed.
SIGNAL max_words_ns : unsigned(0 TO 5-1);
SIGNAL ack_count_ns, ack_count_cs : unsigned(0 TO 5-1);
SIGNAL transaction_addr_cs : std_logic_vector(0 TO 31);
SIGNAL transaction_be_cs : std_logic_vector(0 TO 3);
SIGNAL capture_transaction_addr_ns : std_logic;
SIGNAL prefetch_match_ns : std_logic;
SIGNAL post_writedata_ns : std_logic;
SIGNAL accept_trans_ns : std_logic; -- accept transaction
SIGNAL deny_trans_ns : std_logic; -- deny transaction
SIGNAL retry_read_prefetch_ns, retry_read_prefetch_cs : std_logic;
SIGNAL opbs_postedwrt_req_ns, opbs_postedwrt_req_cs : std_logic;
SIGNAL opbs_prefetch_clr_ns , opbs_prefetch_clr_cs : std_logic;
SIGNAL opbs_postedwr_clr_ns , opbs_postedwr_clr_cs : std_logic;
SIGNAL opbs_prefetch_req_ns , opbs_prefetch_req_cs : std_logic;
SIGNAL opbs_type_ns , opbs_type_cs : std_logic;
SIGNAL opbs_length_ns , opbs_length_cs : unsigned(0 TO 11);
SIGNAL Sl_xferAck_ns, Sl_xferAck_cs : std_logic;
SIGNAL Sl_errAck_ns , Sl_errAck_cs : std_logic;
SIGNAL Sl_retry_ns , Sl_retry_cs : std_logic;
SIGNAL bfs_dst_rdy_n_ns, bfs_dst_rdy_n_cs : std_logic;
SIGNAL bfs_data_cs : std_logic_vector(0 TO 32-1);
SIGNAL bfd_sof_n_ns, bfd_sof_n_cs : std_logic;
SIGNAL bfd_eof_n_ns, bfd_eof_n_cs : std_logic;
SIGNAL bfd_src_rdy_n_ns, bfd_src_rdy_n_cs : std_logic;
SIGNAL bfd_data_cs : std_logic_vector(0 TO 32-1);
BEGIN
----------------------------------------------------------------------------
-- ABUS_DECODE
--
-- An internal block rather then an external block (entity+arch) makes good
-- sense here because the internal workings are relevant to the state
-- machine operation. Placing the logic externally makes the guts harder to
-- reference. Plus we get a new namespace for the necessary
-- functions+signals.
----------------------------------------------------------------------------
abus_decode : BLOCK IS
--
-- 0 31
-- | |
-- +---------------------------------+
-- | j | k | OPB_Abus breakdown
-- +---------------------------------+
-- | Bits to | memory range |
-- | Compare | block size |
FUNCTION Addr_Bits (x, y : std_logic_vector(0 TO 32-1))
-- Find the number of unique address bits necessary for an address range.
-- This is equal to (32 - block size). For example baseaddr=0x0f00_0000 and
-- highaddr=0x0fff_ffff then the first '1' bit of the xor operation is found at
-- bit index 8. The block size is therefore 2**(32-8) = 2**24.
RETURN integer IS
VARIABLE addr_nor : std_logic_vector(0 TO 32-1);
BEGIN
addr_nor := x XOR y;
FOR i IN 0 TO 32-1 LOOP
IF addr_nor(i) = '1' THEN
RETURN i;
END IF;
END LOOP;
--coverage off
RETURN(32);
--coverage on
END FUNCTION Addr_Bits;
FUNCTION min_j (
CONSTANT j0, j1, j2, j3 : integer RANGE 0 TO 32;
CONSTANT C_NUM_ADDR_RNG : IN integer)
RETURN integer IS
VARIABLE m : integer := 33;
-- The min_j function returns the minimum number of bits used in an address
-- range size calculation amongst the four address ranges. A given "J"
-- value can only participate in the MIN operation if it is enabled. That
-- means C_NUM_ADDR_RNG is high enough to include the given J sub n.
BEGIN
IF (j0 < m AND C_NUM_ADDR_RNG >= 1) THEN m := j0; END IF;
--coverage off
IF (j1 < m AND C_NUM_ADDR_RNG >= 2) THEN m := j1; END IF;
IF (j2 < m AND C_NUM_ADDR_RNG >= 3) THEN m := j2; END IF;
IF (j3 < m AND C_NUM_ADDR_RNG >= 4) THEN m := j3; END IF;
--coverage on
RETURN m;
END FUNCTION min_j;
FUNCTION abus_match (
SIGNAL opb_abus : std_logic_vector;
CONSTANT baseaddr : std_logic_vector;
CONSTANT j : integer RANGE 0 TO 32;
CONSTANT num_addr_rng : integer RANGE 1 TO 4;
CONSTANT rng_num : integer RANGE 0 TO 3)
RETURN std_logic IS
BEGIN
IF (rng_num < num_addr_rng) THEN
-- The baseaddr is valid and can be used in matching. This is
-- necessary because if the address pair isn't used the baseaddr and
-- highaddr don't require values that make sense. This condition
-- protects the elaboration from bad vector ranges.
IF (j = 0) THEN
-- This is the degenerate matching case. it implies that the
-- range is the entire 32-bits so any address will be in the
-- baseaddr to highaddr range.
--coverage off
RETURN '1';
--coverage on
ELSE
IF (OPB_ABus(0 TO j-1) = baseaddr(0 TO J-1)) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END IF;
ELSE
-- baseaddr+highaddr pair isn't in use so no match possible.
RETURN '0';
END IF;
END FUNCTION abus_match;
CONSTANT j0 : integer := addr_bits(C_RNG0_BASEADDR, C_RNG0_HIGHADDR);
CONSTANT j1 : integer := addr_bits(C_RNG1_BASEADDR, C_RNG1_HIGHADDR);
CONSTANT j2 : integer := addr_bits(C_RNG2_BASEADDR, C_RNG2_HIGHADDR);
CONSTANT j3 : integer := addr_bits(C_RNG3_BASEADDR, C_RNG3_HIGHADDR);
CONSTANT minimum_j : integer := min_j(j0, j1, j2, j3, C_NUM_ADDR_RNG);
CONSTANT maximum_k : integer := 32-minimum_j;
CONSTANT d : std_logic_vector(0 TO 32*4-1) := C_RNG0_HIGHADDR & C_RNG1_HIGHADDR & C_RNG2_HIGHADDR & C_RNG3_HIGHADDR;
SIGNAL highaddr_ns, highaddr_cs : std_logic_vector(0 TO 32-1); -- selected high addr range value
SIGNAL s : std_logic_vector(0 TO 4-1);
-- Max K size is when rng is 0 to FFFFFFFF. So the max number of words is
-- 2^(32-2). However, the length is 1-based. IE 1 to 16 not 0 to 15. So we
-- need one more bit to represent the actual number of words. (The decimal
-- value 16 requires 5-bits to represent 10000=16). So the expression for the
-- width must be 2^(32-2+1)
SIGNAL words_to_highaddr : unsigned(1 TO maximum_k-2+1); -- Dealing in words so need -2
SIGNAL OPB_ABus_dly1 : std_logic_vector(0 TO 31);
BEGIN
ASSERT FALSE REPORT "C_NUM_ADDR_RNG = " & integer'image(C_NUM_ADDR_RNG) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 1 REPORT "rng0 bits to match j0 = " & integer'image(j0) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 2 REPORT "rng1 bits to match j1 = " & integer'image(j1) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 3 REPORT "rng2 bits to match j2 = " & integer'image(j2) SEVERITY NOTE;
ASSERT C_NUM_ADDR_RNG < 4 REPORT "rng3 bits to match j3 = " & integer'image(j3) SEVERITY NOTE;
ASSERT FALSE REPORT "minimum j = " & integer'image(minimum_j) SEVERITY NOTE;
ASSERT FALSE REPORT "maximum k = " & integer'image(maximum_k) SEVERITY NOTE;
--coverage off
ASSERT (maximum_k >= 6)
REPORT "The smallest address range must be greater then or equal to 64 bytes in size"
SEVERITY error;
--coverage on
abus_reg : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
OPB_ABus_dly1 <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
OPB_ABus_dly1 <= OPB_ABus;
END IF;
END PROCESS abus_reg;
-- The address ranges are supposed to be non-overlapping so these
-- comparisons result in a one-hot (or no-hot) signal.
s(0) <= abus_match(OPB_ABus_dly1, C_RNG0_BASEADDR, J0, C_NUM_ADDR_RNG, 0);
s(1) <= abus_match(OPB_ABus_dly1, C_RNG1_BASEADDR, J1, C_NUM_ADDR_RNG, 1);
s(2) <= abus_match(OPB_ABus_dly1, C_RNG2_BASEADDR, J2, C_NUM_ADDR_RNG, 2);
s(3) <= abus_match(OPB_ABus_dly1, C_RNG3_BASEADDR, J3, C_NUM_ADDR_RNG, 3);
arng_match_ns <= s(0) OR s(1) OR s(2) OR s(3);
x_mux_onehot_f : ENTITY proc_common_v3_00_a.mux_onehot_f
GENERIC MAP (
C_DW => 32, -- [integer]
C_NB => 4, -- [integer]
C_FAMILY => C_FAMILY) -- [string]
PORT MAP (
D => D, -- [in std_logic_vector(0 to C_DW*C_NB-1)]
S => S, -- [in std_logic_vector(0 to C_NB-1)]
Y => highaddr_ns); -- [out std_logic_vector(0 to C_DW-1)]
wha_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
words_to_highaddr <= (OTHERS => '0');
highaddr_cs <= (others => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
-- This is kind of a mystical expression. The goal is to count the number
-- of words using the smallest size subtractor that will work
-- irrespective of the size of the address range block of the address
-- range that matched the incoming OPB_ABus value. The one hot mux
-- selects amongst the high addr range constants based on which addr
-- range matched. The "-2" in the express insures that words are
-- counted and not bytes. The "+ 1" is because the count is used in the
-- command request to the plbv46_master and it requires a non-zero based count.
words_to_highaddr <= unsigned('0'&highaddr_cs(minimum_j TO (32-1) -2))
- unsigned('0'&OPB_ABus_dly1(minimum_j TO (32-1) -2))
+ 1;
-- Pipelineing added to meet spartan3e timing requirements.
highaddr_cs <= highaddr_ns;
END IF;
END PROCESS wha_reg;
-- Now, the length of the desired read or write operation that will not
-- overrun the end of the address range is given by min(16,
-- words_to_highaddr). It is a min 16 operation because that is the
-- largest prefetch read or posted write that can be done.
-- Irregardless of the vector width of words_to_highaddr only the least
-- significant 5 bits are needed.
max_words_ns <= words_to_highaddr(maximum_k-2+1-4 TO maximum_k-2+1) WHEN 16 > words_to_highaddr ELSE
to_unsigned(16, 5) AFTER 1 NS;
transAdr_reg : PROCESS (SOPB_clk, SOPB_rst) IS
-- The transaction address register does double duty. It gets captured
-- at a read prefetch or at the start of a write.
BEGIN
IF (SOPB_rst = '1') THEN
transaction_addr_cs <= (OTHERS => '0');
ELSIF (rising_edge(SOPB_clk)) THEN
IF (capture_transaction_addr_ns = '1') THEN
transaction_addr_cs <= OPB_ABus;
transaction_be_cs <= OPB_BE;
END IF;
END IF;
END PROCESS transAdr_reg;
prefetch_match_ns <= '1' WHEN (OPB_ABus_dly1 = transaction_addr_cs)
AND brdg_prefetch_cmplt = '1' ELSE
'0';
post_writedata_ns <= arng_match_ns AND NOT brdg_block AND NOT OPB_RNW;
accept_trans_ns <= post_writedata_ns OR prefetch_match_ns;
deny_trans_ns <= arng_match_ns AND brdg_block AND NOT brdg_prefetch_cmplt;
retry_read_prefetch_ns <= arng_match_ns AND NOT brdg_block AND OPB_RNW;
END BLOCK abus_decode;
-------------------------------------------------------------------------
--
-------------------------------------------------------------------------
sm : BLOCK IS
TYPE state_type IS (IDLE, DECODE, PIPEDLY1, PIPEDLY2, BURST1, BURST, SINGLE, RETRY);
SIGNAL slave_ns, slave_cs : state_type;
BEGIN
NS : PROCESS (
OPB_RNW, OPB_Select, OPB_seqAddr, Sl_errAck_cs, Sl_retry_cs,
Sl_xferAck_cs, accept_trans_ns, ack_count_cs, bfd_dst_rdy_n,
bfs_src_rdy_n, brdg_prefetch_status, brdg_prefetch_cmplt,
deny_trans_ns, max_words_ns,
opbs_length_cs, opbs_postedwr_clr_cs, opbs_postedwrt_req_cs,
opbs_prefetch_clr_cs, opbs_prefetch_req_cs, opbs_type_cs,
retry_read_prefetch_cs, retry_read_prefetch_ns, slave_cs) IS
VARIABLE terminal_ack_count : std_logic;
BEGIN
slave_ns <= slave_cs; -- Always hold state by default
-- Always hold output state by default
opbs_postedwrt_req_ns <= opbs_postedwrt_req_cs;
opbs_prefetch_clr_ns <= opbs_prefetch_clr_cs;
opbs_postedwr_clr_ns <= opbs_postedwr_clr_cs;
opbs_prefetch_req_ns <= opbs_prefetch_req_cs;
opbs_type_ns <= opbs_type_cs;
opbs_length_ns <= opbs_length_cs;
ack_count_ns <= ack_count_cs;
capture_transaction_addr_ns <= '0';
Sl_xferAck_ns <= Sl_xferAck_cs;
Sl_errAck_ns <= Sl_errAck_cs;
Sl_retry_ns <= Sl_retry_cs;
bfs_dst_rdy_n_ns <= '1';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_sof_n_ns <= '1';
bfd_eof_n_ns <= '1';
CASE slave_cs IS
WHEN IDLE =>
opbs_postedwrt_req_ns <= '0';
opbs_prefetch_clr_ns <= '0';
opbs_postedwr_clr_ns <= '0';
opbs_prefetch_req_ns <= '0';
Sl_xferAck_ns <= '0';
Sl_errAck_ns <= '0';
Sl_retry_ns <= '0';
IF (OPB_Select = '1') THEN
slave_ns <= DECODE;
END IF;
WHEN DECODE =>
-- This state is a pipeline delay to match the registering of OPB_ABus
-- (which is necessary to allow enough cycle time for the
-- combinatorial decode logic.)
slave_ns <= PIPEDLY1;
WHEN PIPEDLY1 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range. It also represents the
-- delay on the pipeline stage on the input data bus OPB_data
bfd_sof_n_ns <= '0'; -- will be first word if this is a write
IF (NOT OPB_Select) = '1' THEN
-- Better luck next time
slave_ns <= IDLE;
ELSIF (deny_trans_ns = '1') THEN
-- Better luck next time
Sl_retry_ns <= '1';
slave_ns <= RETRY;
ELSE
capture_transaction_addr_ns <= '1';
IF (retry_read_prefetch_ns = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters.
Sl_retry_ns <= '1';
opbs_type_ns <= OPB_seqAddr;
slave_ns <= PIPEDLY2;
ELSE
IF (accept_trans_ns = '1') THEN
-- Bridge is ready with prefetch data or waiting for a
-- full write buffer.
Sl_retry_ns <= '0';
-- Pass on read prefetch error status
Sl_errAck_ns <= brdg_prefetch_status;
-- The expression should reduce to a '1' but is not
-- strictly reducible to a '1' at all time. This
-- might be a little overkill in trying to be too
-- precise but it exactly matches the necessary
-- LocalLink semantics. Note that the expression
-- should read (not bfd_dst_rdy_n and not
-- bfd_src_rdy_n) or (not bfs_dst_rdy_n and not
-- bfs_srcy_rdy_n). (Ignore the "nots" which are
-- appropriate for the active low signals when
-- reading this to understand.) Both terms just
-- state that a source & destination are ready so
-- the transfer can occur. That is what we need for
-- the acknowledgement!
-- Also, the OPB_seqAddr term is necessary for writes
-- to prevent early assertion of the xferAck. This is a
-- nasty corner case protection term. When a burst
-- write is requested at the last word of a range the
-- only way to know is by checking the max transfer
-- count. That won't be available until after the
-- pipedly state (max_words is pipelined)
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW AND NOT OPB_seqAddr)
OR (OPB_RNW AND NOT bfs_src_rdy_n AND NOT OPB_seqAddr);
slave_ns <= PIPEDLY2;
ELSE
-- Just hang tight waiting for an address match or a
-- de-select or a prefetch match.
NULL;
END IF;
END IF;
END IF;
WHEN PIPEDLY2 =>
-- This state is a pipeline delay to match the registering
-- of the length calculation used in computing the number of
-- words to the highaddr of the range.
capture_transaction_addr_ns <= '0';
IF (OPB_RNW = '1') THEN
-- The plbv46_master_burst ignores the IP2Bus_Mst_length WHEN
-- IP2Bus_Mst_type=0 indicating a single.
opbs_length_ns <= "00000" & max_words_ns & "00";
ELSE
-- Pipelined, so starting with zero insures the proper count
-- at the end of the burst when the posted_wrt_req is made.
opbs_length_ns <= X"000";
END IF;
ack_count_ns <= max_words_ns;
--keep--bfd_src_rdy_n_ns <= '1';
-- Use of the retry_read_prefetch_cs (registered) version of
-- the combinatorial (_ns) signal eliminates a critical path on
-- bfs_dst_rdy_n_ns which becomes a fifo read signal.
IF (retry_read_prefetch_cs = '1') THEN
-- We have a winner. Issue the prefetch request to the
-- bridge and retry the transaction to the OPB master.
-- If the OPB read request was issued with seqAddr de-asserted
-- then only request the plbv46_master_burst get a single
-- word as well. This is a fairly high probability
-- asssumption about the behaviour of Xilinx OPB masters. The
-- prefetch request must assert here rather then in DECODE to
-- avoid a problem in 1:2 clock ratio mode where the
-- assertion caused the brdg_block to assert prematurely
-- (from the faster clock domain) thus cutting off
-- opbs_prefetch_req_ns before the PIPEDLY state was entered.
Sl_retry_ns <= '0';
opbs_type_ns <= OPB_seqAddr;
-- Don't issue the prefetch request if master aborts
-- transaction in this clock. (IE OPB_Select='0')
opbs_prefetch_req_ns <= OPB_Select;
slave_ns <= IDLE;
ELSE
-- For OPB Master aborts
-- 1) the state transition must be to idle
-- 2) the read prefetch buffer must not be touched and the
-- master must still come back and claim the data
-- 3) Nothing has been written to the posted write buffer (bfd)
-- yet so it doesn't have to be cleared
-- 4) prefetch buffer should be cleared since it has data in
-- it.
IF (OPB_seqAddr = '1') THEN
opbs_type_ns <= '1'; -- specify a "burst"
-- Sl_xferAck_cs is qualified by opb_select for the abort
-- case elsewhere.
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
IF (opb_select='1') THEN
slave_ns <= BURST1;
ELSE
slave_ns <= IDLE;
END IF;
ELSE
opbs_type_ns <= '0'; -- specify a "single"
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
bfd_sof_n_ns <= '0'; -- Is first since this is a single
bfd_eof_n_ns <= '0'; -- Is last since this is a single
opbs_postedwrt_req_ns <= NOT OPB_RNW AND OPB_Select;
opbs_prefetch_clr_ns <= '1';
Sl_xferAck_ns <= '0';
IF (opb_select='1') THEN
slave_ns <= SINGLE;
ELSE
slave_ns <= IDLE;
END IF;
END IF;
END IF;
WHEN BURST1 =>
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ack_count_ns <= ack_count_cs - 1;
IF (NOT OPB_Select) = '1' THEN
-- Burst terminated prematurely (Master abort?)
Sl_retry_ns <= '0';
Sl_xferAck_ns <= '0';
opbs_prefetch_clr_ns <= OPB_RNW;
opbs_postedwr_clr_ns <= NOT OPB_RNW;
--keep--bfd_src_rdy_n_ns <= '1'; -- clean shutdown of writes
bfs_dst_rdy_n_ns <= '1'; -- although who cares! buffer is reset momentarily
slave_ns <= IDLE;
ELSE
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '0';
slave_ns <= burst;
END IF;
WHEN BURST =>
ack_count_ns <= ack_count_cs - 1;
IF (ack_count_cs = 1) THEN
terminal_ack_count := '1';
ELSE
terminal_ack_count := '0';
END IF;
-- issue a retry if there isn't enough data in the fifo to
-- satisfy the request. This might happen if a read meant to
-- claim prefetch data has OPB_seqAddr asserted but the
-- original read had OPB_seqAddr deasserted.
Sl_retry_ns <= '0';
Sl_xferAck_ns <= (NOT bfd_dst_rdy_n AND NOT OPB_RNW)
OR (OPB_RNW AND NOT bfs_src_rdy_n);
bfs_dst_rdy_n_ns <= NOT OPB_RNW; -- ready to read data
--keep--bfd_src_rdy_n_ns <= OPB_RNW; -- ready to write
bfd_sof_n_ns <= '1';
IF (terminal_ack_count='1' OR OPB_SeqAddr = '0' OR OPB_Select = '0') THEN
-- Since xferAck is pipelined (Sl_xferAck<=Sl_xferAck_cs)
-- the ack must turn off here for a burst otherwise it
-- will clobber the next back-to-back transaction.
-- (Supposedly the Xilinx OPB doesn't permit these type of
-- b2b transactions but they fail in simulation without
-- this.) The condition of OPB_Select=0 (master
-- abort) must be handled elsewhere by gating the registered
-- xferAck with OPB_Select.
Sl_xferAck_ns <= '0';
-- HEY! This will be the last ack so make sure the Local Link
-- EOF is set properly. This only works for the lookahead
-- conditions (terminal_ack_count=1 or OPB_seqAddr=0). The
-- condition of OPB_Select=0 (master abort if no xferAcks
-- accepted yet) must be handled elsewhere by gating the
-- registered bfd_eof_n with OPB_Select.
bfd_eof_n_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1'; -- done w/ writing (using pipelined sig)
opbs_postedwrt_req_ns <=
-- brdg_prefetch_complete=1 would indicate that a read
-- burst was being satisfied. An opb master abort
-- typically causes OPB_RNW -> 0 which can cause an
-- unintentional opbs_postedwrt_req assertion in this
-- state because it thinks a write to the buffer is done.
-- The qualification by brdg_prefetch_complete rather then
-- opb_rnw will prevent that.
NOT brdg_prefetch_cmplt
AND (
-- Make request because
-- ... end of burst
(NOT OPB_seqAddr AND OPB_select)
-- ... master abort. Write data
-- already xferAck'd
OR (NOT OPB_Select)
-- ... buffer will
-- overflow if anymore accepted
OR (terminal_ack_count)
);
opbs_prefetch_clr_ns <= '1';
slave_ns <= IDLE;
IF (OPB_select)='1' THEN
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
ELSE
-- master abort occured (IE OPB_Select dropped prior to
-- first xferAck) or the Master simply dropped OPB_Select
-- without first dropping OPB_seqAddr so the very last xferAck IS
-- disabled, and the last word is not written to the local
-- link destination buffer (bfd). So length should not get
-- incremented.
null;
END IF;
ELSE
opbs_length_ns <= opbs_length_cs + 4; -- 1 word = 4 bytes
END IF;
WHEN SINGLE =>
opbs_prefetch_clr_ns <= '1';
opbs_postedwrt_req_ns <= '0';
--keep--bfd_src_rdy_n_ns <= '1';
bfd_eof_n_ns <= '0';
bfs_dst_rdy_n_ns <= '1';
Sl_xferAck_ns <= '0';
Sl_retry_ns <= '0';
slave_ns <= IDLE;
WHEN RETRY =>
-- This state is different then the SINGLE state in that the
-- prefetch buffer is not cleared. A retry acknowledgement
-- ends a transaction just like an xferAck does -- just
-- nothing was transfered.
Sl_retry_ns <= '0';
slave_ns <= IDLE;
--coverage off
WHEN OTHERS => NULL;
--coverage on
END CASE;
END PROCESS NS;
cs : PROCESS (SOPB_clk, SOPB_rst) IS
BEGIN
IF (SOPB_rst = '1') THEN
slave_cs <= IDLE;
ack_count_cs <= (OTHERS => '0');
opbs_length_cs <= (OTHERS => '0');
opbs_prefetch_clr_cs <= '0';
opbs_prefetch_req_cs <= '0';
opbs_postedwrt_req_cs <= '0';
opbs_type_cs <= '0';
Sl_xferAck_cs <= '0';
Sl_errAck_cs <= '0';
Sl_retry_cs <= '0';
bfd_sof_n_cs <= '1';
bfd_eof_n_cs <= '1';
bfd_src_rdy_n_cs <= '1';
retry_read_prefetch_cs <= '0';
ELSIF (rising_edge(SOPB_clk)) THEN
slave_cs <= slave_ns;
ack_count_cs <= ack_count_ns;
opbs_length_cs <= opbs_length_ns;
opbs_prefetch_clr_cs <= opbs_prefetch_clr_ns;
opbs_postedwr_clr_cs <= opbs_postedwr_clr_ns;
opbs_prefetch_req_cs <= opbs_prefetch_req_ns;
opbs_postedwrt_req_cs <= opbs_postedwrt_req_ns;
opbs_type_cs <= opbs_type_ns;
Sl_xferAck_cs <= Sl_xferAck_ns;
Sl_errAck_cs <= Sl_errAck_ns;
Sl_retry_cs <= Sl_retry_ns;
bfd_sof_n_cs <= bfd_sof_n_ns;
bfd_eof_n_cs <= bfd_eof_n_ns;
-- bfd_src_rdy_n_cs began to track the Sl_xferAck directly
-- to avoid having the state machine manage it. A later bug
-- fix identified the need to have xferAck drop with OPB_select
-- deasserting (thus signaling an OPB master abort). This necessitated
-- the addition of the OPB_select qualifier here as well. Otherwise,
-- a bug is introduced where a word gets written into the
-- destination buffer even though the xferAck got cut off. That
-- extra word gums up the works for the next transfer.
--keep--bfd_src_rdy_n_cs <= bfd_src_rdy_n_ns;
bfd_src_rdy_n_cs <= NOT (Sl_xferAck_cs AND OPB_Select) OR OPB_RNW;
-- Use of the registered version of the retry_read_prefetch SIGNAL
-- eliminates a critical path inside the PIPEDLY state for reading
-- data out of the Local Link buffer source (prefetch buffer).
retry_read_prefetch_cs <= retry_read_prefetch_ns;
END IF;
END PROCESS cs;
END BLOCK sm;
bfs_dly1 : PROCESS (SOPB_clk) IS
BEGIN
-- The data from local link is registered here and qualified by the
-- combinatorial slave xfer ack condition so that zero is driven when
-- invalid data is present. bfs_data_cs drives the Sl_DBus directly so it
-- must be zero at all other times to avoid clobbering data on the
-- OPB_Dbus distributed to all other opb peripherals (including this one
-- during write operations!) Note that the qualifier expression is
-- redundant. sl_xferack_ns is already conditioned on opb_rnw but for
-- both the read and write case. This redundancy will be removed during
-- synthesis but is convienient here as the concept of sl_xferack as the
-- qualifier is more clear then the underlying expression is.
IF (rising_edge(SOPB_clk)) THEN
IF ( (sl_xferack_ns AND OPB_rnw)='1') THEN
bfs_data_cs <= bfs_data;
ELSE
bfs_data_cs <= (others => '0');
END IF;
END IF;
END PROCESS bfs_dly1;
bfd_dly1 : PROCESS (SOPB_clk) IS
BEGIN
IF (rising_edge(SOPB_clk)) THEN
bfd_data_cs <= OPB_DBus;
END IF;
END PROCESS bfd_dly1;
----------------------------------------------------------------------------
-- Final output assignments from internal combinatorial or registered,
-- control or data paths.
----------------------------------------------------------------------------
-- The slave acknowledgements must be registed by Xilinx convention.
-- Unfortunately, to cover the Master abort case the ack's must be
-- qualified by OPB_Select combinatorially. No way around this.
Sl_xferAck <= Sl_xferAck_cs AND OPB_Select;
Sl_errAck <= Sl_errAck_cs AND OPB_Select;
Sl_retry <= Sl_retry_cs AND OPB_Select;
-- Since the Xilinx implementation of the OPB BUS arbiter and bus structure
-- differs then the true IBM implementation (in order to save on resources)
-- the Sl_DBus must be qualified such that it is all '0' when this slave
-- is not actively outputing data. The primary qualifier is thus Sl_xferAck.
-- The qualification must include OPB_Select as well to account for the CASE
-- of a master abort. bfs_data_cs includes a synchronous reset in the case
-- that Sl_xferAck is deasserted or OPB_rnw=write.
Sl_DBus <= bfs_data_cs WHEN (OPB_Select)='1'
ELSE (OTHERS => '0');
Sl_ToutSup <= '0';
-- The clr signal doesn't need clock domain transition pulse conditioning
-- because remaining on for two MPLB_clk periods (in 1:2 clock period ratio
-- situation) is not a problem. No read transaction can be activated in that
-- time period.
opbs_prefetch_req <= opbs_prefetch_req_cs;
-- pass through - no cross domain conditioning required.
opbs_trans_addr <= transaction_addr_cs;
opbs_be <= transaction_be_cs;
opbs_prefetch_clr <= opbs_prefetch_clr_cs;
opbs_postedwr_clr <= opbs_postedwr_clr_cs;
opbs_type <= opbs_type_cs;
opbs_length <= std_logic_vector(opbs_length_cs);
opbs_postedwrt_req <= opbs_postedwrt_req_cs;
-- LocalLink buffer destination (the posted write buffer) connections
bfd_sof_n <= bfd_sof_n_cs;
-- This "or" gate ensures that, on occasion of na OPB master abort, the last
-- word of data put into the fifo has its end of frame flag set.
bfd_eof_n <= bfd_eof_n_cs AND OPB_select ;
bfd_data <= bfd_data_cs;
bfd_src_dsc_n <= '1'; -- never DISCONNECT
bfd_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- The registered version of src_rdy is used to track the registered
-- version of OPB_xferAck
bfd_src_rdy_n <= bfd_src_rdy_n_cs;
END GENERATE bfd_gen1;
bfd_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfd_src_rdy_n_cs;
END IF;
bfd_src_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfd_gen2;
-- LocalLink buffer source (the read prefetch buffer) connections
bfs_dst_dsc_n <= '1'; -- never DISCONNECT
bfs_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
bfs_dst_rdy_n <= bfs_dst_rdy_n_ns;
END GENERATE bfs_gen1;
bfs_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This flip flop toggles for one MPLB_clk period whenver the SOPB_clk
-- domain signal is asserted. Note that both signals are active low so an
-- "OR" is used to be an active low input/output AND function.
reg : PROCESS (MPLB_clk) IS
VARIABLE reg_n : std_logic := '0';
BEGIN
IF (rising_edge(MPLB_clk)) THEN
reg_n := NOT reg_n OR bfs_dst_rdy_n_ns;
END IF;
bfs_dst_rdy_n <= reg_n;
END PROCESS reg;
END GENERATE bfs_gen2;
END ARCHITECTURE syn;
| bsd-3-clause | 75650d52200d9e5da50d6d3b0cb87c4d | 0.535126 | 4.160626 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_init_3.vhd | 2 | 15,009 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- condattr_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * condattr = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- retVal = hthread_condattr_init( cond_attr );
when STATE_2 =>
-- Push data->cond_attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 29c1f24b2e4574a00e2741a3458921f6 | 0.537744 | 3.856372 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ld_arith_reg.vhd | 3 | 15,160 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| bsd-3-clause | b97bcd3cc44e472ec379e59cb31e246d | 0.384037 | 4.94133 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/sync_fifo_fg.vhd | 2 | 68,298 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.coregen_comp_defs.all;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
use proc_common_v3_00_a.family_support.all;
-- synopsys translate_off
library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IfGen implements the fifo using FIFO Generator 4.3
-- when the designated FPGA Family is Spartan3, Virtex4, or
-- Virtex5.
--
------------------------------------------------------------
V5_AND_EARLIER: if(FAM_IS_S3_V4_V5) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : fifo_generator_v4_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1
)
port map (
CLK => Clk, -- : IN std_logic := '0';
BACKUP => '0', -- : IN std_logic := '0';
BACKUP_MARKER => '0', -- : IN std_logic := '0';
DIN => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK => '0', -- : IN std_logic := '0';
RD_EN => Rd_en, -- : IN std_logic := '0';
RD_RST => '0', -- : IN std_logic := '0';
RST => '0', -- : IN std_logic := '0';
SRST => Sinit, -- : IN std_logic := '0';
WR_CLK => '0', -- : IN std_logic := '0';
WR_EN => Wr_en, -- : IN std_logic := '0';
WR_RST => '0', -- : IN std_logic := '0';
INT_CLK => '0', -- : IN std_logic := '0';
ALMOST_EMPTY => open, -- : OUT std_logic;
ALMOST_FULL => Almost_full, -- : OUT std_logic;
DATA_COUNT => sig_prim_fg_datacnt, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY => Empty, -- : OUT std_logic;
FULL => sig_full, -- : OUT std_logic;
OVERFLOW => Wr_err, -- : OUT std_logic;
PROG_EMPTY => open, -- : OUT std_logic;
PROG_FULL => open, -- : OUT std_logic;
VALID => Rd_ack, -- : OUT std_logic;
RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW => Rd_err, -- : OUT std_logic;
WR_ACK => Wr_ack, -- : OUT std_logic;
WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR => open, -- : OUT std_logic;
DBITERR => open -- : OUT std_logic
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
V6_S6_AND_LATER: if(FAM_IS_NOT_S3_V4_V5) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : fifo_generator_v9_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => Clk,
RST => '0',
SRST => Sinit,
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => Din,
WR_EN => Wr_en,
RD_EN => Rd_en,
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0', -- new FG 5.1/5.2
INJECTSBITERR => '0', -- new FG 5.1/5.2
DOUT => Dout,
FULL => sig_full,
ALMOST_FULL => Almost_full,
WR_ACK => Wr_ack,
OVERFLOW => Wr_err,
EMPTY => Empty,
ALMOST_EMPTY => open,
VALID => Rd_ack,
UNDERFLOW => Rd_err,
DATA_COUNT => sig_prim_fg_datacnt,
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end implementation;
| bsd-3-clause | a3dc9d401dc8012a37ee7ad14d570597 | 0.38559 | 4.054016 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/yield_1.vhd | 2 | 14,448 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- yield_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- retVal = hthread_yield();
when FUNCTION_START =>
-- Call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_1;
next_state <= WAIT_STATE;
when STATE_1 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fbc3bee5651a6d14d0b84857af5b30d8 | 0.534953 | 3.878658 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/common/blockdram.vhd | 1 | 1,219 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
entity blockdram is
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := ( others => '0' ) );
end blockdram;
architecture arch_blockdram of blockdram is
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
(Dwidth-1 downto 0);
signal mem : ram_memtype:=(others=>(others=>'0'));
--attribute syn_ramstyle of mem : signal is "block_ram,area";
signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
begin
wr: process( clka )
begin
if rising_edge(clka) then
if wea = '1' then
mem(conv_integer(addra)) <= dia;
end if;
end if;
end process wr;
rd: process( clkb )
begin
if rising_edge(clkb) then
addrb_reg <= addrb;
end if;
end process rd;
dob <= mem(conv_integer(addrb_reg));
end arch_blockdram;
| gpl-2.0 | b5589cca5f5e849a0c06b56eb42dc37e | 0.665299 | 2.909308 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/fifo_d1.vhd | 1 | 4,291 | ---------------------------------------------------------------
-- Title : FIFO with depth one word
-- Project :
---------------------------------------------------------------
-- File : fifo_d1.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 23/06/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- This module describes a fifo with depth one word.
-- No EAB-Block is required, just registers.
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: fifo_d1.vhd,v $
-- Revision 1.3 2015/09/08 17:22:58 AGeissler
-- R1: Missing reset for second clock domain
-- M1: Replaced rstn with rst_a and rst_b
--
-- Revision 1.2 2015/06/15 16:40:08 AGeissler
-- R1: Clearness
-- M1: Replaced tabs with spaces
--
-- Revision 1.1 2005/05/06 12:06:49 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/11/02 11:29:27 mmiehling
-- added regs for full/empty signals
--
-- Revision 1.1 2004/07/27 17:15:22 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_d1 IS
GENERIC (
width : IN integer:=8
);
PORT (
rst_a : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
rst_b : IN std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END fifo_d1;
ARCHITECTURE fifo_d1_arch OF fifo_d1 IS
SIGNAL wr_ptr : std_logic;
SIGNAL rd_ptr : std_logic;
SIGNAL wr_ptr_b : std_logic;
SIGNAL rd_ptr_a : std_logic;
SIGNAL full_a_int : std_logic;
SIGNAL full_b_int : std_logic;
SIGNAL data_a_q : std_logic_vector(width-1 DOWNTO 0);
BEGIN
full_a_int <= '1' WHEN (wr_ptr = '1' AND rd_ptr_a = '0') OR (wr_ptr = '0' AND rd_ptr_a = '1') ELSE '0';
full_a <= full_a_int;
full_b_int <= '1' WHEN (wr_ptr_b = '1' AND rd_ptr = '0') OR (wr_ptr_b = '0' AND rd_ptr = '1') ELSE '0';
full_b <= full_b_int;
proca : PROCESS (clk_a, rst_a)
BEGIN
IF rst_a = '1' THEN
data_a_q <= (OTHERS => '0');
wr_ptr <= '0';
rd_ptr_a <= '0';
ELSIF clk_a'EVENT AND clk_a = '1' THEN
rd_ptr_a <= rd_ptr;
IF wr_a = '1' AND full_a_int = '0' THEN
data_a_q <= data_a;
wr_ptr <= NOT wr_ptr;
END IF;
END IF;
END PROCESS proca;
procb : PROCESS (clk_b, rst_b)
BEGIN
IF rst_b = '1' THEN
data_b <= (OTHERS => '0');
rd_ptr <= '0';
wr_ptr_b <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
wr_ptr_b <= wr_ptr;
IF rd_b = '1' AND full_b_int = '1' THEN
data_b <= data_a_q;
rd_ptr <= NOT rd_ptr;
END IF;
END IF;
END PROCESS procb;
END fifo_d1_arch;
| gpl-3.0 | ce183d1eb3b4bf549eddb2b4b26665e9 | 0.487765 | 3.581803 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/burst_size_calc.vhd | 3 | 15,480 | -------------------------------------------------------------------------------
-- $Id: burst_size_calc.vhd,v 1.5 2003/10/22 15:06:35 ostlerf Exp $
-------------------------------------------------------------------------------
-- Burst Size Calculation
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: burst_size_calc.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: This module calculates the size to use for a dma transfer.
-- The main complications are that for Rx channels the minimum
-- of LENGTH and PLENGTH must be used instead of LENGTH and
-- that for the last transfer there may be a need to round up
-- to include bytes that are insufficient to reach a unit of
-- C_BYTES_PER_SINGLE_TRANSFER.
--
-------------------------------------------------------------------------------
-- Structure:
-- burst_size_calc.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 05/09/2003 -- First version
--
-- FLO 05/14/2003
-- ^^^^^^
-- Removed the pipe stage between LENGTH_cco comparison to
-- PLENGTH_cco and thre rest of the logic.
-- Corrected the high-order bits of MstNum from '1' to '0'.
-- ~~~~~~
-- FLO 05/14/2003
-- ^^^^^^
-- Removed C_DMA_ALLOW_BURST; case is now handled as
-- C_DMA_BURST_SIZE = 1.
-- Added the option to handle the remainder (the amount left
-- to be moved by DMA when it is less than a full burst) as
-- a succession of single transactions rather than as a
-- short burst. This adds generic C_DMA_SHORT_BURST_REMAINDER
-- to the parameters. So, these options are now available:
--
-- 1. Single transactions only when C_DMA_BURST_SIZE = 1.
-- 2. Burst transactions, with remainders as singles when
-- C_DMA_BURST_SIZE > 1 and
-- C_DMA_SHORT_BURST_REMAINDER= false.
-- 3. Burst transactions, with remainders as short burst when
-- C_DMA_BURST_SIZE > 1 and
-- C_DMA_SHORT_BURST_REMAINDER = true.
-- ~~~~~~
-- FLO 06/26/2003
-- ^^^^^^
-- Implemented XST WA for G.23 that was communicated by XST team.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity burst_size_calc is
generic (
C_LENGTH_WIDTH : positive := 11;
C_MSTNUM_WIDTH : positive := 5;
C_DMA_BURST_SIZE : positive := 16;
C_BYTES_PER_SINGLE_TRANSFER : positive := 4;
C_DMA_SHORT_BURST_REMAINDER : integer := 0
);
port (
Bus2IP_Clk : in std_logic;
LENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
PLENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
Rx_cco : in std_logic;
MstNum : out std_logic_vector(0 to C_MSTNUM_WIDTH-1)
);
-- Operational constraints:
-- - PLENGTH_cco is used only for Rx channels and for Rx channels, it is
-- assumed that LENGTH_cco decrements if and only if PLENGTH_cco decrements
-- by the same ammount. Thus, the relationship LENGTH_cco < PLENGTH_cco
-- remains invariant as these quantities change value.
-- - C_BYTES_PER_SINGLE_TRANSFER must be a power of two.
constant TPB : positive := C_DMA_BURST_SIZE; -- Transfers Per Burst
constant BPST : positive := C_BYTES_PER_SINGLE_TRANSFER;
constant BPST_BITS : natural := log2(BPST);
end burst_size_calc;
library unisim;
--use unisim.all;
use unisim.VCOMPONENTS.all;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v1_00_b;
use proc_common_v1_00_b.or_muxcy;
architecture imp of burst_size_calc is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := ('0', '1');
-- Number of of high-order bits that give a length in
-- units of single transfers (units of the bus width).
-- LW_STU stands for LENGTH_WIDTH in Single Transfer Units.
constant LW_STU : positive := C_LENGTH_WIDTH-BPST_BITS;
constant TPB_U : UNSIGNED(0 to LW_STU-1)
:= (TO_UNSIGNED(TPB, LW_STU));
constant TPB_BITS : natural := log2(TPB+1); -- 0 to TPB values to encode
signal pl_gte_l : std_logic; -- PLENGTH_cco >= LENGTH_cco (forced
-- to true when not Rx_cco, which
-- causes PLENGTH_cco to be ignored
-- in downstream calculations).
signal pl_gte_l_d1 : std_logic;
signal min_pl_l_gte_tpb : std_logic; -- min(PLENGTH_cco, LENGTH_cco) is
-- greater than or equal to TPB
signal min_pl_l_minus_tpb : std_logic_vector(0 to C_LENGTH_WIDTH-1);
-- min(PLENGTH_cco, LENGTH_cco) - TPB
component or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
begin
DISALLOW_BURST_GEN: if C_DMA_BURST_SIZE = 1 generate
begin
MstNum <= std_logic_vector(TO_UNSIGNED(1, MstNum'length));
end generate;
ALLOW_BURST_GEN: if C_DMA_BURST_SIZE > 1 generate ---(
begin
-- indentation waived
PL_GTE_L_BLOCK: block ---(
signal brw_n : std_logic_vector(0 to C_LENGTH_WIDTH);
signal lut : std_logic_vector(0 to C_LENGTH_WIDTH-1);
signal mult_and : std_logic_vector(0 to C_LENGTH_WIDTH-1);
begin
--------------------------------------------------------------------------
-- This block assigns:
--
-- pl_gte_l <= not Rx_cco or bo2sl( PLENGTH_cco(0 to C_LENGTH_WIDTH-1)
-- > LENGTH_cco(0 to C_LENGTH_WIDTH-1)
-- );
--------------------------------------------------------------------------
brw_n(brw_n'right) <= '1';
PL_GTE_L_BIT_GEN: for i in C_LENGTH_WIDTH-1 downto 0 generate
begin
lut(i) <= not (Rx_cco and LENGTH_cco(i))
xor PLENGTH_cco(i);
--
-- When Rx_cco = '1', then the minimum of LENGTH_cco and
-- PLENGTH_cco is used in the calculation of the burst
-- size. Otherwise, only LENGTH_cco is used. A little trick
-- is used to assure that LENGTH_cco is used when Rx_cco = '0'.
-- The trick is that PLENGTH_cco is compared with a
-- forced zero, assuring that pl_gte_l is true and that
-- LENGTH_cco will be used in the next stage.
----------------------------------------------------------------------
-- brw_n(i) <= (not lut(i) and not mult_and(i)) or
-- ( lut(i) and brw_n(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => PLENGTH_cco(i),
CI => brw_n(i+1),
S => lut(i),
O => brw_n(i)
);
end generate;
pl_gte_l <= brw_n(0);
end block; ---)
PL_GTE_L_D1_PROC: process(Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
pl_gte_l_d1 <= pl_gte_l;
end if;
end process;
MIN_PL_L_MINUS_TPB_BLOCK: block ---(
signal brw_n : std_logic_vector(0 to C_LENGTH_WIDTH);
signal lut : std_logic_vector(0 to C_LENGTH_WIDTH-1);
constant TPBB_U : UNSIGNED(0 to C_LENGTH_WIDTH-1)
:= (TO_UNSIGNED(TPB*BPST, C_LENGTH_WIDTH));
signal lut_tmp1 : std_logic_vector(0 to C_LENGTH_WIDTH-1); --XST WA for G.23
signal lut_tmp2 : std_logic_vector(0 to C_LENGTH_WIDTH-1); --XST WA for G.23
begin
brw_n(brw_n'length-1) <= '1';
MIN_PL_L_MINUS_TPB_BIT_GEN: for i in C_LENGTH_WIDTH-1 downto 0 generate
begin
-- lut(i) <= ( ( pl_gte_l_d1 and LENGTH_cco(i))
-- or (not pl_gte_l_d1 and PLENGTH_cco(i))
-- )
-- xor not TPBB_U(i);
-------------------
-- The above, using a cycle-delayed pl_gte_l may not
-- be permissable because MstNum likely is used
-- in state DONECHK when on the cycle right after cco changes.
lut_tmp1(i) <= not TPBB_U(i); --XST WA for G.23
lut_tmp2(i) <= ( ( pl_gte_l and LENGTH_cco(i))
or (not pl_gte_l and PLENGTH_cco(i))
);
lut(i) <= lut_tmp2(i)
xor lut_tmp1(i);
-- lut(i) <= ( ( pl_gte_l and LENGTH_cco(i))
-- or (not pl_gte_l and PLENGTH_cco(i))
-- )
-- xor not TPBB_U(i);
----------------------------------------------------------------------
-- brw_n(i) <= (not lut(i) and not TPBB_U(i)) or (lut(i) and brw_n(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => (not TPBB_U(i)),
CI => brw_n(i+1),
S => lut(i),
O => brw_n(i)
);
----------------------------------------------------------------------
-- min_pl_l_minus_tpb(i) <= lut(i) xor brw_n(i+1);
----------------------------------------------------------------------
I_XORCY: XORCY
port map (
LI => lut(i),
CI => brw_n(i+1),
O => min_pl_l_minus_tpb(i)
);
end generate;
min_pl_l_gte_tpb <= brw_n(0);
end block; ---)
MSTNUM_SINGLES_REM_GEN:
if C_DMA_SHORT_BURST_REMAINDER = 0 generate ---(
begin
MstNum <= std_logic_vector(TO_UNSIGNED(TPB, MstNum'length))
when min_pl_l_gte_tpb = '1' else
std_logic_vector(TO_UNSIGNED(1, MstNum'length));
end generate; ---)
MSTNUM_BURST_REM_GEN:
if C_DMA_SHORT_BURST_REMAINDER = 1 generate ---(
signal cry : std_logic_vector(0 to TPB_BITS);
signal lut : std_logic_vector(0 to TPB_BITS-1);
signal min_pl_l_lt_tpb : std_logic;
signal mult_and_out : std_logic_vector(0 to TPB_BITS-1);
signal has_partial_bpst: std_logic; -- min(PLENGTH_cco, LENGTH_cco)
-- divided by BPST leaves a non-zero
-- remainder.
signal mplmt_a : std_logic_vector(0 to TPB_BITS-1);
signal mstnum_a : std_logic_vector(0 to TPB_BITS-1);
constant tpb_a : std_logic_vector(0 to TPB_BITS-1)
:= std_logic_vector(TO_UNSIGNED(TPB, TPB_BITS));
begin
I_HAS_PARTIAL_BPST : or_muxcy
generic map (
C_NUM_BITS => BPST_BITS
)
port map (
In_bus => min_pl_l_minus_tpb(C_LENGTH_WIDTH-BPST_BITS to
C_LENGTH_WIDTH-1),
Or_out => has_partial_bpst
);
mplmt_a <= min_pl_l_minus_tpb(C_LENGTH_WIDTH-TPB_BITS-BPST_BITS to
C_LENGTH_WIDTH-BPST_BITS-1);
min_pl_l_lt_tpb <= not min_pl_l_gte_tpb;
cry(cry'right) <= has_partial_bpst and min_pl_l_lt_tpb;
MSTNUM_BIT_GEN: for i in TPB_BITS-1 downto 0 generate
begin
----------------------------------------------------------------------
lut(i) <= ( min_pl_l_lt_tpb -- Use "amount left" if it is < TPB.
and ( mplmt_a(i) -- Reconstruct "amount left" by
xor tpb_a(i)) -- adding back TPB.
)
or ( not min_pl_l_lt_tpb
and tpb_a(i) -- Use TPB if "amount left" >= TPB
);
----------------------------------------------------------------------
-- mult_and_out(i) <= min_pl_l_lt_tpb and mplmt_a(i);
----------------------------------------------------------------------
I_MULT_AND: MULT_AND
port map (
LO => mult_and_out(i),
I1 => min_pl_l_lt_tpb,
I0 => mplmt_a(i)
);
----------------------------------------------------------------------
-- cry(i) <= (not lut(i) and mult_and_out(i)) or (lut(i) and cry(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => mult_and_out(i),
CI => cry(i+1),
S => lut(i),
O => cry(i)
);
----------------------------------------------------------------------
-- mstnum_a(i) <= lut(i) xor cry(i+1);
----------------------------------------------------------------------
I_XORCY: XORCY
port map (
LI => lut(i),
CI => cry(i+1),
O => mstnum_a(i)
);
end generate;
MstNum(C_MSTNUM_WIDTH-TPB_BITS to C_MSTNUM_WIDTH-1) <= mstnum_a;
XST_NULL_SLICE_WORKAROUND_MSTNUM_HIGH_BITS_GEN:
if C_MSTNUM_WIDTH > TPB_BITS generate
MstNum(0 to C_MSTNUM_WIDTH-TPB_BITS-1) <= (others => '0');
end generate;
end generate; ---)
-- indentation waived
end generate; ---)
end imp;
| bsd-3-clause | 7ac598a837880357073684fd36c1f8f0 | 0.430297 | 4.04072 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_init_1.vhd | 2 | 16,051 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_1.c
-- arg = * data
-- reg1 = * cond
-- reg2 = * cond_attr
-- The return value should be the condattr->num set by either the
-- software main thread, or the bfl in case of simulation.
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * condattr = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the value of cond
thrd2intrfc_address <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Read the value of cond_attr
thrd2intrfc_address <= arg + 4;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_cond_init( data->cond, data->cond_attr );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- Push data->cond_attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- retVal = data->cond->num;
when STATE_6 =>
-- Load the value of cond->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 835d0c7357ce89e5438ab8f3a2b14d95 | 0.542895 | 3.821667 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd | 2 | 10,541 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| bsd-3-clause | c2bee05a156e5ef603dd0386599e2343 | 0.403377 | 5.014748 | false | false | false | false |
jevinskie/aes-over-pcie | source/experiment/enc.vhd | 1 | 1,263 | -- File name: enc.vhd
-- Created: 2009-02-25
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES encryption block
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity enc is
generic (
k : key := (others => x"00")
);
port (
clk : in std_logic;
nrst : in std_logic;
clr : in std_logic;
i_rdy : in std_logic;
i : in byte;
o_rdy : out std_logic;
o : out state_type
);
end enc;
architecture behavioral of enc is
type master_state_type is (idle, loading, encrypting);
signal master_state, next_master_state : master_state_type;
type enc_state_type is (init, rounds, final);
signal enc_state, next_enc_state : enc_state_type;
type round_state_type is (subbytes, mixcols, mixmul, addkey);
signal round_state, next_round_state : round_state_type;
signal b : state_type;
begin
process(i)
begin
--for x in index loop
-- for y in index loop
-- o(x,y) <= sbox(to_integer(b(x,y)));
-- end loop;
--end loop;
b(0,0) <= sbox(to_integer(b(0,0)));
end process;
o <= b;
end behavioral;
| bsd-3-clause | 6fb5848fe4e5dff4c52daf7da5558e08 | 0.581156 | 3.21374 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_memory_wrapper.vhd | 3 | 6,409 | -------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_slave_bfm_v1_00_a.all;
entity bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0)
);
end bfm_memory_wrapper;
architecture STRUCTURE of bfm_memory_wrapper is
component plbv46_slave_bfm is
generic (
PLB_SLAVE_SIZE : std_logic_vector(0 to 1);
PLB_SLAVE_NUM : std_logic_vector(0 to 3);
PLB_SLAVE_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE_ADDR_HI_1 : std_logic_vector(0 to 31);
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
bfm_memory : plbv46_slave_bfm
generic map (
PLB_SLAVE_SIZE => B"10",
PLB_SLAVE_NUM => B"0000",
PLB_SLAVE_ADDR_LO_0 => X"10000000",
PLB_SLAVE_ADDR_HI_0 => X"1000ffff",
PLB_SLAVE_ADDR_LO_1 => X"20000000",
PLB_SLAVE_ADDR_HI_1 => X"2000ffff",
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_ssize => Sl_ssize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
| bsd-3-clause | 8246c34da7946a3f79a5e3f1cfb65099 | 0.587611 | 3.171202 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_quicksort_v1_00_a/hdl/vhdl/hw_acc_quicksort.vhd | 2 | 4,197 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_quicksort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_quicksort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_quicksort is
component quicksort is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
uut : quicksort
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_dout,
array_dOUT0 => BRAM_A_din,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | e12e885657d0aa756433af1344156eb8 | 0.545866 | 3.165158 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_master.vhd | 1 | 41,808 | --------------------------------------------------------------------------------
-- Title : VME Master
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_master.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 15/12/16
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The WBB2VME core supports several access types to the VMEbus. Dependent on
-- the type of backplane connection, the data width can be chosen between D8/D16
-- (one VME connector) and D32 (two VME connectors). D64 transfers are supported
-- by the DMA, when two VME connectors are used.
-- The VMEbus is separated into several address spaces which can be accessed
-- from the WBB2VME core: A16, A24 and A32 each separated in supervisory and
-- non-privileged data/program. All supported address modifiers are in the
-- following table:
-- VME Master Address Modifiers
-- Hex 543210 Function How to use
-- 0x3F HHHHHH A24 supervisory block transfer (BLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
-- 0x3E HHHHHL A24 supervisory program access direct access via VME A24D16 or VME A24D32 windows, configured in register MSTR: A24_MODE
-- 0x3D HHHHLH A24 supervisory data access direct access via VME A24D16 or VME A24D32 windows, configured in register MSTR: A24_MODE
-- 0x3B HHHLHH A24 non privileged block transfer (BLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
-- 0x3A HHHLHL A24 non privileged program access direct access via VME A24D16 or VME A24D32 windows, configured in register MSTR: A24_MODE
-- 0x39 HHHLLH A24 non privileged data access direct access via VME A24D16 or VME A24D32 windows, configured in register MSTR: A24_MODE
-- 0x2D HLHHLH A16 supervisory access direct access via VME A24D16 or VME A24D32 window, configured in register MSTR: A16_MODE
-- 0x2F HLHHHH A24 CR/CSR access direct access via VME A24D16 or VME A24D32 window, configured in register MSTR: CR_CSR_MODE
-- 0x29 HLHLLH A16 non-privileged access direct access via VME A24D16 or VME A24D32 window, configured in register MSTR: A16_MODE
-- 0x0F LLHHHH A32 supervisory block transfer (BLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
-- 0x0E LLHHHL A32 supervisory program access direct access via VME A32 window, configured in register MSTR: A32_MODE
-- 0x0D LLHHLH A32 supervisory data access direct access via VME A32 window, configured in register MSTR: A32_MODE
-- 0x0C LLHHLL A32 supervisory 64-bit block transfer (MBLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
-- 0x0B LLHLHH A32 non privileged block transfer (BLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
-- 0x0A LLHLHL A32 non privileged program access direct access via VME A32 window, configured in register MSTR: A32_MODE
-- 0x09 LLHLLH A32 non privileged data access direct access via VME A32 window, configured in register MSTR: A32_MODE
-- 0x08 LLHLLL A32 non privileged 64-bit block transfer (MBLT) DMA access, configured in buffer descriptor, bits DMA_VME_AM
--
-- IF one of the VME Master windows is accessed by a read or write, the VME bus
-- access will be requested on level 3. If the bus was granted by activation of
-- the arbitration daisy chain input (signal vme_bg_i_n[3]), the VME master will
-- perform the access.
-- The bus requester schemes Release when done and Release on request can be
-- selected (VMEbus Release Mechanism). The access type Read-Modify-Write can
-- be selected by setting the bit Read-Modify-Write enable before the access. If
-- then the Read access to one VME master window gets performed, the bus will be
-- blocked until the Write access follows. No other VME transmission by any
-- other master can be performed between these two accesses!
-- The access type Address Only can be selected by setting the bit ADO before
-- a byte or word read access follows. During this access, no data will be
-- transmitted, but VMEbus participants can monitor (e.g. by the Location
-- Monitor) the bus and can detect this message. No other access types are
-- allowed if the ADO bit is set.
-- All write accesses to the VME bus are handled as posted write.
---------------------------------------------------------------
-- Hierarchy:
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_master.vhd,v $
-- Revision 1.2 2014/04/17 07:35:22 MMiehling
-- removed unused signals
-- bugfix MAIN_PR001486: longword read acccess to D16 space fails
--
-- Revision 1.1 2012/03/29 10:14:36 MMiehling
-- Initial Revision
--
-- Revision 1.8 2006/05/18 14:29:07 MMiehling
-- correct detection of berrn
--
-- Revision 1.7 2004/11/02 11:30:01 mmiehling
-- improved timing
--
-- Revision 1.6 2003/12/17 15:51:50 MMiehling
-- now berr-bit will be set only when direct access from pci, not from dma
--
-- Revision 1.5 2003/12/01 10:03:58 MMiehling
-- added d64
--
-- Revision 1.4 2003/06/24 13:47:13 MMiehling
-- added rst_aonly; changed soen_int
--
-- Revision 1.3 2003/06/13 10:06:40 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/02 16:11:33 MMiehling
-- Der Master funktioniert bis auf Bursts, A16-Zugriffe und Zugriffe auf ungerade A32 Basisadressen (z.B. 0x10000000)
--
-- Revision 1.1 2003/04/01 13:04:44 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.vme_pkg.all;
ENTITY vme_master IS
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic;
test_c : OUT std_logic;
-- control signals from/to mensb_slave
run_mstr : IN std_logic; -- this pulse triggers start of Master
mstr_ack : OUT std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : OUT std_logic; -- master busy, set when running
vme_req : out std_logic; -- request VME interface access
burst : IN std_logic; -- indicates a vme burst request
ma_en_vme_data_in_reg : OUT std_logic; -- load register signal in data switch unit for rd vme
ma_en_vme_data_in_reg_high : OUT std_logic; -- load high register signal in data switch unit for rd vme
brel : OUT std_logic; -- release signal for Requester
wbs_we_i : IN std_logic; -- read /write
wb_dma_acc : IN std_logic; -- indicates dma_access
-- requester
dwb : OUT std_logic; -- device wants vme bus
dgb : IN std_logic; -- device gets vme bus
-------------------------------------------------------------------------------
-- PINs:
-- control signals from VMEbus:
berrn_in : IN std_logic; -- vme bus error signal
dtackn_in : IN std_logic; -- vme bus data acknoledge signal
-- control signals to VMEbus
asn_out : OUT std_logic;
-------------------------------------------------------------------------------
-- connected with vme_du:
rst_rmw : OUT std_logic; -- if bit is set => berr bit will be set
set_berr : OUT std_logic; -- if bit is set => rmw bit will be cleared
ma_oe_vd : OUT std_logic; -- output enable for vme data
ma_oe_va : OUT std_logic; -- output enable for vme adress
mstr_reg : IN std_logic_vector(5 DOWNTO 0); -- master configuration register(BERR-bit, REQ-bit, RMW-bit)
rst_aonly : OUT std_logic; -- resets aonly bit
-- connected with vme_au
dsn_ena : OUT std_logic; -- signal switches dsan and dsbn on and off
mstr_cycle : IN std_logic; -- signal indicates one or two cycles must be done
second_word : OUT std_logic; -- signal indicates the actual master cycle
vam_oe : OUT std_logic; -- vam output enable
d64 : IN std_logic; -- indicates a d64 burst transmission
-- connected with slave:
asn_in : IN std_logic; -- to detect a transaction
--data bus bus control signals for vmebus drivers
ma_io_ctrl : OUT io_ctrl_type
);
END vme_master;
ARCHITECTURE vme_master_arch OF vme_master IS
TYPE mstr_states IS (mstr_idle, req_bus, got_bus, set_adr, set_as, wait_on_dtackn, set_ds, got_low_d64, got_dtackn, data_stored, rmw_wait);
SIGNAL mstr_state : mstr_states;
SIGNAL dtackn : std_logic;
SIGNAL dtackn_reg : std_logic;
SIGNAL berrn : std_logic;
SIGNAL berrn_reg : std_logic;
SIGNAL cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL cnt_start : std_logic;
SIGNAL cnt_end : std_logic;
SIGNAL asn_regd : std_logic;
SIGNAL second_word_int : std_logic;
SIGNAL vam_oe_int : std_logic;
SIGNAL asn_out_int : std_logic;
SIGNAL soen_int : std_logic;
SIGNAL brel_int : std_logic;
SIGNAL wb_dma_acc_q : std_logic;
SIGNAL rst_rmw_int : std_logic;
BEGIN
brel <= brel_int;
asn_out <= asn_out_int;
vam_oe <= vam_oe_int;
second_word <= second_word_int;
rst_rmw <= '1' WHEN rst_rmw_int = '1' AND wb_dma_acc_q = '0' ELSE '0';
test_c <= '1' WHEN mstr_state = set_ds ELSE '0';
-- synchronize dtackn and berrn:
regdinp : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
dtackn <= '1';
berrn <= '1';
berrn_reg <= '1';
asn_regd <= '1';
set_berr <= '0';
rst_aonly <= '0';
dtackn_reg <= '1';
wb_dma_acc_q <= '0';
ELSIF clk'event AND clk = '1' THEN
IF mstr_state = mstr_idle THEN -- keep information "dma- or normal-access" as long as access is ongoing
wb_dma_acc_q <= wb_dma_acc;
END IF;
dtackn_reg <= dtackn_in;
dtackn <= dtackn_reg;
berrn <= berrn_in;
berrn_reg <= berrn;
asn_regd <= asn_in; --to_x01(asn_in);
IF mstr_state = set_as AND wb_dma_acc_q = '0' THEN
rst_aonly <= '1';
ELSE
rst_aonly <= '0';
END IF;
IF berrn = '0' AND berrn_reg = '1' THEN -- falling edge
set_berr <= '1';
ELSE
set_berr <= '0';
END IF;
END IF;
END PROCESS regdinp;
ma_io_ctrl.d_oe_n <= '0';
-- ma_io_ctrl.am_oe_n <= '0';
ma_io_ctrl.a_oe_n <= '0';
-------------------------------------------------------------------------------
mstr_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_state <= mstr_idle;
mstr_ack <= '0';
second_word_int <= '0';
mstr_busy <= '0';
vme_req <= '0';
dwb <= '0';
asn_out_int <= '1';
dsn_ena <= '0';
brel_int <= '1';
soen_int <= '1';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '0';--
ma_en_vme_data_in_reg_high <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '1'; -- inactive in reset
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.d_dir <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE mstr_state IS
WHEN mstr_idle =>
second_word_int <= '0';
mstr_ack <= '0';
mstr_busy <= '0';
vme_req <= '0';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '0';
IF run_mstr = '1' THEN
mstr_state <= req_bus;
ELSE
mstr_state <= mstr_idle;
END IF;
IF run_mstr = '1' THEN
dwb <= '1';
brel_int <= '0';
ELSE
dwb <= '0';
brel_int <= '1';
END IF;
asn_out_int <= '1';
dsn_ena <= '0';
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
soen_int <= '1';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '0';
ma_en_vme_data_in_reg_high <= '0';
WHEN req_bus =>
second_word_int <= second_word_int;
mstr_ack <= '0';
IF dgb = '1' AND asn_regd = '1' AND dtackn = '1' AND berrn = '1' THEN -- wait until last access is done
mstr_state <= got_bus;
ma_io_ctrl.a_dir <= '1';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '1'; -- switch of for dir change
mstr_busy <= '1';
vme_req <= '1';
ELSE
mstr_state <= req_bus;
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '0';
mstr_busy <= '0';
vme_req <= '0';
END IF;
dwb <= '1';
asn_out_int <= asn_out_int;--'1'
dsn_ena <= '0';
ma_io_ctrl.d_dir <= '0';
brel_int <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
soen_int <= soen_int;--'1';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '0';
ma_en_vme_data_in_reg_high <= '0';
WHEN got_bus => -- here start second cycles
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= second_word_int;
IF dtackn = '1' AND berrn = '1' THEN -- 25.04.06
mstr_state <= set_adr;
ELSE
mstr_state <= got_bus;
END IF;
dwb <= '0';
asn_out_int <= asn_out_int;--'1'
dsn_ena <= '0';
IF d64 = '1' AND second_word_int = '1' AND wbs_we_i = '0' THEN -- d64 read burst => address lines should be used as read data
ma_io_ctrl.a_dir <= '0';
ma_oe_va <= '0';
ELSIF wbs_we_i = '0' THEN -- read 32bit
ma_io_ctrl.d_dir <= '0';
ma_oe_va <= '1'; -- 25.03.2014
ELSE -- write
ma_io_ctrl.d_dir <= '1';
ma_oe_va <= '1';
END IF;
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0'; -- activate after dir change
brel_int <= '0';
ma_oe_vd <= '0';
soen_int <= soen_int;--'1';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '1';
ma_en_vme_data_in_reg_high <= '0';
WHEN set_adr =>
mstr_busy <= '1';
vme_req <= '1';
mstr_ack <= '0';
second_word_int <= second_word_int;
IF wbs_we_i = '0' THEN
ma_oe_vd <= '0';
ELSE
ma_oe_vd <= '1';
END IF;
IF berrn = '0' THEN
mstr_state <= mstr_idle; -- error
ma_io_ctrl.d_dir <= '0';
soen_int <= soen_int;--'1';
ELSIF cnt_end = '1' THEN
mstr_state <= set_as; -- for D32 and D16 burst , no additional states are required
soen_int <= '0';
IF wbs_we_i = '0' THEN
ma_io_ctrl.d_dir <= '0';
ELSE
ma_io_ctrl.d_dir <= '1';
END IF;
ELSE
mstr_state <= set_adr;
IF wbs_we_i = '0' THEN
ma_oe_vd <= '0';
ELSE
ma_oe_vd <= '1';
END IF;
soen_int <= soen_int;--'1';
END IF;
asn_out_int <= asn_out_int;--'1'
dwb <= '0';
dsn_ena <= '0';
IF d64 = '1' AND second_word_int = '1' AND wbs_we_i = '0' THEN -- d64 read burst => address lines should be used as read data
ma_io_ctrl.a_dir <= '0';
ma_oe_va <= '0';
ELSE
ma_io_ctrl.a_dir <= '1';
ma_oe_va <= '1';
END IF;
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
brel_int <= '0';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '1';
ma_en_vme_data_in_reg_high <= '0';
WHEN set_as =>
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= second_word_int;
IF berrn = '0' THEN
mstr_state <= mstr_idle; -- error
ELSIF mstr_reg(5) = '1' AND wb_dma_acc_q = '0' AND cnt_end = '1' THEN -- ado-cycle
mstr_state <= got_dtackn;
ELSIF cnt_end = '1' THEN
mstr_state <= set_ds;
ELSE
mstr_state <= set_as;
END IF;
dwb <= '0';
asn_out_int <= '0';
dsn_ena <= '0';
IF d64 = '1' AND second_word_int = '1' AND wbs_we_i = '0' THEN -- d64 read burst => address lines should be used as read data
ma_io_ctrl.a_dir <= '0';
ma_oe_va <= '0';
ELSE
ma_io_ctrl.d_dir <= '1';
ma_oe_va <= '1';
END IF;
IF wbs_we_i = '0' THEN
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
ELSE
ma_io_ctrl.d_dir <= '1';
ma_oe_vd <= '1';
END IF;
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR asn_regd = '1' THEN
brel_int <= '0';
ELSE
brel_int <= '1';
END IF;
soen_int <= '0';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '1';
ma_en_vme_data_in_reg_high <= '0';
WHEN set_ds =>
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= second_word_int;
IF berrn = '0' THEN
mstr_state <= mstr_idle;
ma_io_ctrl.a_dir <= '0';
asn_out_int <= '1';
dsn_ena <= '0';
vam_oe_int <= '0';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '1'; -- disable for dir switch
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
ELSIF dtackn = '0' THEN
mstr_state <= got_dtackn;
dsn_ena <= '0';
ma_io_ctrl.a_dir <= '1';
asn_out_int <= '0';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
IF (mstr_reg(0) = '1' AND wb_dma_acc_q = '0' AND second_word_int = '0') OR burst = '1' THEN --rmw ?
vam_oe_int <= '1';
ELSE
vam_oe_int <= '1';--'0'
END IF;
if burst = '1' then
ma_oe_va <= '1';
else
ma_oe_va <= '0';
end if;
ma_io_ctrl.d_dir <= wbs_we_i;
ma_oe_vd <= '0';
ELSE
mstr_state <= set_ds;
IF wbs_we_i = '0' AND d64 = '1' AND second_word_int = '1' THEN
ma_io_ctrl.a_dir <= '0';
ma_oe_va <= '0';
ELSE
ma_io_ctrl.a_dir <= '1';
ma_oe_va <= '1';
END IF;
asn_out_int <= '0';
dsn_ena <= '1';
vam_oe_int <= '1';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
IF wbs_we_i = '0' THEN
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
ELSE
ma_io_ctrl.d_dir <= '1';
ma_oe_vd <= '1';
END IF;
END IF;
dwb <= '0';
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR asn_regd = '1' THEN
brel_int <= '0';
ELSE
brel_int <= '1';
END IF;
soen_int <= '0';
IF dtackn = '0' AND wbs_we_i = '0' THEN
ma_en_vme_data_in_reg <= '0';-- '1' stop sampling when got dtack
ELSE
ma_en_vme_data_in_reg <= '1';-- '0'
END IF;
if dtackn = '1' and wbs_we_i = '0' and d64 = '1' and second_word_int = '1' then
ma_en_vme_data_in_reg_high <= '1';
else
-- if dtack went down, stop sampling or if we're not in MBLT, then never sample
ma_en_vme_data_in_reg_high <= '0';
end if;
rst_rmw_int <= '0';
WHEN got_low_d64 =>
IF cnt_end = '1' THEN
mstr_state <= got_dtackn;
ma_en_vme_data_in_reg_high <= '0';-- '1' stop sampling when got dtack
ELSE
mstr_state <= got_low_d64;
ma_en_vme_data_in_reg_high <= '1';-- '0'
END IF;
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= second_word_int;
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.d_dir <= '0';
asn_out_int <= '0';
dsn_ena <= '1';
vam_oe_int <= '1';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
dwb <= '0';
brel_int <= '0';
soen_int <= '0';
rst_rmw_int <= '0';
WHEN got_dtackn =>
mstr_busy <= '1';
vme_req <= '1';
mstr_ack <= '0';
IF berrn = '0' THEN
mstr_state <= mstr_idle; -- error
second_word_int <= '0'; --NOT second_word_int;
ELSE
mstr_state <= data_stored;
second_word_int <= second_word_int;
END IF;
dwb <= '0';
IF mstr_reg(0) = '1' AND wb_dma_acc_q = '0' AND second_word_int = '0' THEN -- rmw first phase?
soen_int <= '0';
ma_io_ctrl.a_dir <= '0';
asn_out_int <= '0';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
vam_oe_int <= '1';
ELSIF burst = '1' THEN
soen_int <= '0';
ma_io_ctrl.a_dir <= '1';
asn_out_int <= '0';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
vam_oe_int <= '1';
ELSE
soen_int <= '1';
ma_io_ctrl.a_dir <= '1';
asn_out_int <= '1';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '1'; -- disable for dir switch
vam_oe_int <= '0';
END IF;
dsn_ena <= '0';
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
if burst = '1' then
ma_oe_va <= '1';
else
ma_oe_va <= '0';
end if;
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR asn_regd = '1' THEN
brel_int <= '0';
ELSE
brel_int <= '1';
END IF;
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
ma_en_vme_data_in_reg_high <= '0';
WHEN wait_on_dtackn =>
if dtackn = '1' then
mstr_state <= set_ds;
else
mstr_state <= wait_on_dtackn;
end if;
IF d64 = '0' AND second_word_int = '1' AND mstr_cycle = '1' THEN
second_word_int <= '0';
ELSE
second_word_int <= second_word_int;
END IF;
asn_out_int <= '0';
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
dwb <= '0';
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR burst = '1' THEN
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
ELSE
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '0';
END IF;
dsn_ena <= '0';
IF d64 = '1' AND second_word_int = '0' AND wbs_we_i = '0' THEN -- d64 read burst => address lines should be used as read data
ma_io_ctrl.a_dir <= '0';
ELSE
ma_io_ctrl.a_dir <= '1';
END IF;
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
if burst = '1' then
ma_oe_va <= '1';
else
ma_oe_va <= '0';
end if;
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR asn_regd = '1' THEN
brel_int <= '0';
ELSE
brel_int <= '1';
END IF;
ma_en_vme_data_in_reg <= '0';
ma_en_vme_data_in_reg_high <= '0';
WHEN data_stored =>
IF berrn = '0' THEN
mstr_state <= mstr_idle;
asn_out_int <= '1';
mstr_ack <= '1';
mstr_busy <= '0';
vme_req <= '0';
second_word_int <= '0';
vam_oe_int <= '0';
rst_rmw_int <= '0';
soen_int <= '1';
ELSIF burst = '1' AND run_mstr = '1' THEN
IF wbs_we_i = '0' AND d64 = '1' and dtackn = '1' THEN
mstr_state <= set_ds;
ELSIF wbs_we_i = '0' AND d64 = '1' and dtackn = '0' THEN
mstr_state <= wait_on_dtackn;
ELSE
mstr_state <= got_bus;
END IF;
IF d64 = '0' AND second_word_int = '1' AND mstr_cycle = '1' THEN
second_word_int <= '0';
ELSE
second_word_int <= second_word_int;
END IF;
asn_out_int <= '0';
mstr_ack <= '1'; -- ack imediately next data
mstr_busy <= '1';
vme_req <= '1';
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSIF burst = '1' AND d64 = '1' AND second_word_int = '0' THEN -- was this first cycle of D64?
mstr_state <= got_bus; -- then transmit data of D64
asn_out_int <= '0';
mstr_ack <= '0'; -- no ack, because first D64 cycle transmits only addresses
mstr_busy <= '0';
-- vme_req <= '0';
vme_req <= '1'; -- keep the bus for the whole BLT transfer
second_word_int <= '1'; -- now all data transfers
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSIF burst = '1' AND d64 = '0' AND second_word_int = '0' AND mstr_cycle = '1' THEN -- was this first cycle of D16?
mstr_state <= got_bus; -- then transmit second word
asn_out_int <= '0';
mstr_ack <= '0'; -- no ack, because first D16 cycle transmits only low word
mstr_busy <= '0';
vme_req <= '1';
second_word_int <= '1';
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSIF burst = '1' AND d64 = '0' AND second_word_int = '1' AND mstr_cycle = '1' THEN -- was this second cycle of D16?
mstr_state <= data_stored; -- wait for run-mstr
asn_out_int <= '0';
mstr_ack <= '1'; -- ack 4 byte
mstr_busy <= '0';
vme_req <= '1';
second_word_int <= '1';
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSIF burst = '1' THEN
mstr_state <= data_stored;
asn_out_int <= '0';
mstr_ack <= '1';
mstr_busy <= '0';
-- if d64 = '1' then
-- vme_req <= '0';
-- else
vme_req <= '1'; -- keep the bus for the whole BLT transfer
-- end if;
second_word_int <= second_word_int;
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSIF mstr_cycle = '1' AND second_word_int = '0' THEN -- run second time for long on D16 transmission
mstr_state <= got_bus;
asn_out_int <= '1';
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= '1';
vam_oe_int <= '0';
rst_rmw_int <= '0';
soen_int <= '1';
ELSIF mstr_reg(0) = '1' AND wb_dma_acc_q = '0' AND second_word_int = '0' THEN -- rmw cycle ?
mstr_state <= rmw_wait;
asn_out_int <= '0';
mstr_ack <= '1'; -- ack read of rmw
mstr_busy <= '0';
vme_req <= '0';
second_word_int <= '1';
vam_oe_int <= '1';
rst_rmw_int <= '0';
soen_int <= '0';
ELSE
mstr_state <= mstr_idle;
asn_out_int <= '1';
mstr_ack <= '1';
mstr_busy <= '0';
vme_req <= '0';
second_word_int <= '0';
vam_oe_int <= '0';
rst_rmw_int <= '1';
soen_int <= '1';
END IF;
dwb <= '0';
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR burst = '1' THEN
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
ELSE
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '0';
END IF;
dsn_ena <= '0';
IF d64 = '1' AND second_word_int = '0' AND wbs_we_i = '0' THEN -- d64 read burst => address lines should be used as read data
ma_io_ctrl.a_dir <= '0';
ELSE
ma_io_ctrl.a_dir <= '1';
END IF;
ma_io_ctrl.d_dir <= '0';
ma_oe_vd <= '0';
if burst = '1' then
ma_oe_va <= '1';
else
ma_oe_va <= '0';
end if;
IF (((mstr_reg(0) = '1' AND wb_dma_acc_q = '0') OR mstr_cycle = '1') AND second_word_int = '0') OR asn_regd = '1' THEN
brel_int <= '0';
ELSE
brel_int <= '1';
END IF;
ma_en_vme_data_in_reg <= '0';
ma_en_vme_data_in_reg_high <= '0';
WHEN rmw_wait =>
mstr_ack <= '0';
mstr_busy <= '1';
vme_req <= '1';
second_word_int <= second_word_int;
IF berrn = '0' THEN
mstr_state <= mstr_idle;
ELSIF run_mstr = '1' THEN
mstr_state <= got_bus;
ELSE
mstr_state <= rmw_wait;
END IF;
dwb <= '0';
asn_out_int <= '0';
dsn_ena <= '0';
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.d_dir <= '0';
ma_io_ctrl.am_dir <= '1';
ma_io_ctrl.am_oe_n <= '0';
brel_int <= '0';
ma_oe_vd <= '0';
ma_oe_va <= '0';
soen_int <= '0';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '1';
ma_en_vme_data_in_reg_high <= '0';
WHEN OTHERS =>
mstr_ack <= '0';
mstr_busy <= '0';
vme_req <= '0';
second_word_int <= '0';
mstr_state <= mstr_idle;
dwb <= '0';
asn_out_int <= '1';
dsn_ena <= '0';
ma_io_ctrl.a_dir <= '0';
ma_io_ctrl.d_dir <= '0';
ma_io_ctrl.am_dir <= '0';
ma_io_ctrl.am_oe_n <= '0';
brel_int <= '1';
ma_oe_vd <= '0';
ma_oe_va <= '0';
soen_int <= '1';
ma_en_vme_data_in_reg <= '0';
rst_rmw_int <= '0';
vam_oe_int <= '0';
ma_en_vme_data_in_reg_high <= '0';
END CASE;
END IF;
END PROCESS mstr_fsm;
mstr_out : PROCESS (mstr_state, dtackn, mstr_cycle, wbs_we_i, d64, second_word_int)
BEGIN
CASE mstr_state IS
WHEN mstr_idle =>
cnt_start <= '0';
WHEN req_bus =>
cnt_start <= '0';
WHEN got_bus =>
cnt_start <= '1';
WHEN set_adr =>
cnt_start <= '1';
WHEN set_as =>
cnt_start <= '0';
WHEN set_ds =>
IF dtackn = '0' AND wbs_we_i = '0' AND d64 = '1' AND second_word_int = '1' THEN
cnt_start <= '1';
ELSE
cnt_start <= '0';
END IF;
WHEN got_low_d64 =>
cnt_start <= '0';
WHEN got_dtackn =>
cnt_start <= '0';
WHEN data_stored =>
cnt_start <= '0';
WHEN rmw_wait =>
cnt_start <= '0';
WHEN OTHERS =>
cnt_start <= '0';
END CASE;
END PROCESS mstr_out;
cnt_p : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF cnt /= "00" THEN
cnt <= cnt - 1;
ELSIF cnt_start = '1' THEN
cnt <= "10";
END IF;
END IF;
END PROCESS cnt_p;
cnt_end <= '1' WHEN cnt = "00" ELSE '0';
END vme_master_arch;
| gpl-3.0 | 30d1004a347ba46d5980e4f767b2a3a0 | 0.378564 | 3.978683 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/reset_control.vhd | 3 | 4,514 | -------------------------------------------------------------------------------
-- $Id: reset_control.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- reset_control.vhd v1.01a
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: reset_control.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Ethernet IPIF Reset support block.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- reset_control.vhd
-- |
-- |
-- |-- ipif_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 21, 2001 -- V1.01a (initial release)
-- LCW Nov 8, 2004 -- updated for NCSim
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ipif_reset;
entity reset_control is
generic (
C_IPIF_MIR_ENABLE : BOOLEAN := True;
C_IPIF_TYPE : INTEGER := 1;
C_IPIF_BLK_ID : INTEGER := 255;
C_IPIF_REVISION : INTEGER := 1;
C_IPIF_MINOR_VERSION : INTEGER := 0;
C_IPIF_MAJOR_VERSION : INTEGER := 0;
C_OPB_DBUS_WIDTH : INTEGER := 32 -- Width of the input and output data buses
);
port (
Bus2IP_Clk_i : in std_logic;
Bus_DBus : in std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
IP_Reset_RdCE : in std_logic;
IP_Reset_WrCE : in std_logic;
Reset : in std_logic;
Reset2Bus_DBus : out std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
Reset2Bus_Error : out std_logic;
Reset2Bus_RdAck : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic;
Reset2Bus_WrAck : out std_logic;
Reset2IP_Reset : out std_logic
);
end reset_control;
architecture implementation of reset_control is
begin
I_RESET_CONTROLLER: entity opb_ipif_v2_00_h.ipif_reset
generic map (C_OPB_DBUS_WIDTH,
C_IPIF_MIR_ENABLE,
C_IPIF_TYPE,
C_IPIF_BLK_ID,
C_IPIF_REVISION,
C_IPIF_MINOR_VERSION,
C_IPIF_MAJOR_VERSION)
port map (
Reset => Reset,
Bus2IP_Clk_i => Bus2IP_Clk_i,
IP_Reset_WrCE => IP_Reset_WrCE,
IP_Reset_RdCE => IP_Reset_RdCE,
Bus_DBus => Bus_DBus(0 to C_OPB_DBUS_WIDTH - 1),
Reset2IP_Reset => Reset2IP_Reset,
Reset2Bus_DBus => Reset2Bus_DBus(0 to C_OPB_DBUS_WIDTH - 1),
Reset2Bus_WrAck => Reset2Bus_WrAck,
Reset2Bus_RdAck => Reset2Bus_RdAck,
Reset2Bus_Error => Reset2Bus_Error,
Reset2Bus_Retry => Reset2Bus_Retry,
Reset2Bus_ToutSup => Reset2Bus_ToutSup);
end implementation;
| bsd-3-clause | bccbd4da6073f5e83896c8e91435d0c7 | 0.420691 | 4.348748 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_addr_cntr.vhd | 2 | 36,642 | -------------------------------------------------------------------------------
-- $Id: xbic_addr_cntr.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_cntr.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_addr_cntr.vhd
--
-- Description:
-- Address Counter for XPS BRAM IF Cntlr.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $5/21/2007$
--
-- History:
-- DET 5/21/2007 Initial Version
--
--
-- DET 6/8/2007 jm.10
-- ~~~~~~
-- - Added additional filter logic to cover bugs found with 128-bit master
-- and 64-bit Native DWidth case.
-- ^^^^^^
--
-- DET 8/25/2008 v1_00_b
-- ~~~~~~
-- - Updated library references to v1_00_b
-- ^^^^^^
--
-- DET 9/9/2008 v1_00_b for EDK 11.1 release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library xps_bram_if_cntlr_v1_00_b;
use xps_bram_if_cntlr_v1_00_b.xbic_be_reset_gen;
library unisim; -- Required for Xilinx primitives
use unisim.all;
-------------------------------------------------------------------------------
entity xbic_addr_cntr is
generic (
C_SMALLEST_MASTER : integer range 32 to 128 := 32;
C_CACHLINE_ADDR_MODE : Integer range 0 to 1 := 0;
C_ADDR_CNTR_WIDTH : Integer := 32;
C_NATIVE_DWIDTH : Integer range 32 to 128 := 64;
C_PLB_AWIDTH : Integer range 32 to 36 := 32
);
port (
-- Clock and Reset
Bus_Rst : In std_logic;
Bus_clk : In std_logic;
-- Inputs from Slave Attachment
Mstr_Size_in : In std_logic_vector(0 to 1);
PLB_Size_in : In std_logic_vector(0 to 3);
PLB_RNW_in : In std_logic;
Bus_Addr_in : in std_logic_vector(0 to C_PLB_AWIDTH-1);
Addr_Load : In std_logic;
Addr_Cnt_en : In std_logic;
Qualifiers_Load : In std_logic;
BE_in : In Std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
--Reset_BE : in std_logic_vector(0 to (C_NATIVE_DWIDTH/32) - 1);
-- BE Outputs
BE_out : Out Std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
-- IPIF & IP address bus source (AMUX output)
Address_Out : out std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1)
);
end entity xbic_addr_cntr;
architecture implementation of xbic_addr_cntr is
-- Constants
Constant CLINE_CNTR_WIDTH : integer := 5;
Constant CLINE_GEN_MUX_WIDTH : integer := 4;
Constant CLINE_8_ADDR_MUX_BIT_OFFSET: integer := 5;
-- Types
-- Signals
signal single : std_logic;
signal flburst : std_logic;
signal cacheln_4 : std_logic;
signal cacheln_8 : std_logic;
signal words : std_logic;
signal dblwrds : std_logic;
signal qwdwrds : std_logic;
signal master_32 : std_logic;
signal master_64 : std_logic;
signal master_128 : std_logic;
signal flbrst_inc_value : std_logic_vector(0 to 4);
signal cline_inc_value : std_logic_vector(0 to 4);
-- Sample and hold signals
signal single_s_h : std_logic;
signal flburst_s_h : std_logic;
signal cacheln_4_s_h : std_logic;
signal cacheln_8_s_h : std_logic;
signal words_s_h : std_logic;
signal dblwrds_s_h : std_logic;
signal qwdwrds_s_h : std_logic;
signal msize_s_h : std_logic_vector(0 to 1);
signal rnw_s_h : std_logic;
signal master_32_s_h : std_logic;
signal master_64_s_h : std_logic;
signal master_128_s_h : std_logic;
signal flbrst_inc_value_s_h : std_logic_vector(0 to 4);
signal cline_inc_value_s_h : std_logic_vector(0 to 4);
Signal sig_cline_slice_cntr : unsigned(0 to CLINE_CNTR_WIDTH-1);
Signal sig_addr_cntr : unsigned(0 to C_ADDR_CNTR_WIDTH-1);
signal sig_addr_inc_value : unsigned(0 to C_ADDR_CNTR_WIDTH-1);
signal sig_cline_inc_value : unsigned(0 to CLINE_CNTR_WIDTH-1);
signal sig_cline_ld_value : unsigned(0 to CLINE_CNTR_WIDTH-1);
signal sig_cline_addr_slice_slv : std_logic_vector(0 to CLINE_CNTR_WIDTH-1);
signal sig_cline_addr_ld_mask_final : std_logic_vector(0 to CLINE_CNTR_WIDTH-1);
signal sig_cline_addr_ld_mask : std_logic_vector(0 to CLINE_CNTR_WIDTH-1);
--signal sig_cline_addr_slice : std_logic_vector(0 to CLINE_CNTR_WIDTH-1);
signal sig_ld_addr_cntr : std_logic;
signal sig_incr_addr_cntr : std_logic;
signal sig_ld_cline_addr_cntr : std_logic;
signal sig_incr_cline_addr_cntr : std_logic;
signal sig_address_out : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal sig_s_h_qualifiers : std_logic;
Signal sig_addr_4_3_s_h : std_logic_vector(0 to 1);
Signal sig_singles_be_mask : std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
signal sig_be_in_s_h : std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
signal sig_masked_be : std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
--signal sig_burst_be_s_h : std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
signal sig_cline_burst_be : std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1);
begin --(architecture implementation)
------------------------------------------------------------------
-- Output BE assignment logic
--
--
------------------------------------------------------------------
-- BE_out <= sig_burst_be_s_h
-- when single_s_h = '1'
-- Else (others => '1')
-- When (cacheln_4_s_h = '1' or
-- cacheln_8_s_h = '1')
-- Else sig_burst_be;
-- Select the appropriate BE source for the transfer case
BE_out <= (others => '1') -- set to all ones
when rnw_s_h = '1' -- for all reads
Else sig_masked_be
When single_s_h = '1' -- single beat write
Else sig_cline_burst_be; -- bursts and cacheline writes
sig_masked_be <= sig_be_in_s_h and sig_singles_be_mask;
master_32 <= not(Mstr_Size_in(0)) and
not(Mstr_Size_in(1));
master_64 <= not(Mstr_Size_in(0)) and
Mstr_Size_in(1);
--GAB master_128 <= Mstr_Size_in(0) and
--GAB Mstr_Size_in(1);
master_128 <= Mstr_Size_in(0) and
not(Mstr_Size_in(1));
------------------------------------------------------------------
-- Output address assignment logic
--
-- The Lower 4 LSBs of the address are muxed between the main address
-- counter and the 4 lsbs of the Cacheline address counter during
-- any cachline operation.
--
-- The 5th lsb bit is muxed between the Main address counter and
-- the cachline mux based on cacheline 8wd execution
------------------------------------------------------------------
Address_Out <= sig_address_out;
-- rip the main address counter bits that are used for all transfers
sig_address_out(0 to C_ADDR_CNTR_WIDTH-(CLINE_GEN_MUX_WIDTH+2)) <=
STD_LOGIC_VECTOR(sig_addr_cntr(0 to C_ADDR_CNTR_WIDTH-
(CLINE_GEN_MUX_WIDTH+2)));
-- Mux the address bit that is needed for only cachline 8
sig_address_out(C_ADDR_CNTR_WIDTH-CLINE_8_ADDR_MUX_BIT_OFFSET)
<= STD_LOGIC(sig_cline_slice_cntr(CLINE_CNTR_WIDTH-CLINE_8_ADDR_MUX_BIT_OFFSET))
When (cacheln_8_s_h = '1')
Else STD_LOGIC(sig_addr_cntr(C_ADDR_CNTR_WIDTH-CLINE_8_ADDR_MUX_BIT_OFFSET));
-- Mux the address bits that are needed for cachline 8 and cacheline 4
sig_address_out(C_ADDR_CNTR_WIDTH-CLINE_GEN_MUX_WIDTH to
C_ADDR_CNTR_WIDTH-1)
<= STD_LOGIC_VECTOR(sig_cline_slice_cntr(CLINE_CNTR_WIDTH-CLINE_GEN_MUX_WIDTH to CLINE_CNTR_WIDTH-1))
When (cacheln_4_s_h = '1' or
cacheln_8_s_h = '1')
Else STD_LOGIC_VECTOR(sig_addr_cntr(C_ADDR_CNTR_WIDTH-CLINE_GEN_MUX_WIDTH to
C_ADDR_CNTR_WIDTH-1));
sig_s_h_qualifiers <= Qualifiers_Load;
------------------------------------------------------------------
-- Use size bits to determine transfer type
--
------------------------------------------------------------------
-- PLB_Size = "0000"
single <= not(PLB_Size_in(0)) and
not(PLB_Size_in(1)) and
not(PLB_Size_in(2)) and
not(PLB_Size_in(3));
-- PLB_Size = "0X00"
flburst <= PLB_Size_in(0);
-- PLB_Size = "1XXX"
cacheln_4 <= not(PLB_Size_in(0)) and
not(PLB_Size_in(2)) and
PLB_Size_in(3);
-- PLB_Size = "0X10"
cacheln_8 <= not(PLB_Size_in(0)) and
PLB_Size_in(2) and
not(PLB_Size_in(3));
-- not supported
-- -- PLB_Size = "0X11"
-- cacheln_16 <= not(PLB_Size_in(0)) and
-- PLB_Size_in(2) and
-- not(PLB_Size_in(3);
------------------------------------------------------------------
-- Case for BRAM Native DWidth of 32 bits
--
------------------------------------------------------------------
GEN_NATIVE_WIDTH32 : if (C_NATIVE_DWIDTH = 32) generate
-- PLB_Size = "1010"
-- words <= PLB_Size_in(0) and
-- not(PLB_Size_in(1)) and
-- PLB_Size_in(2) and
-- not(PLB_Size_in(3));
-- always 32-bit transfer for Burst and cachelines
words <= '1';
-- not supported
dblwrds <= '0';
-- not supported
qwdwrds <= '0';
-- always 4 bytes/dbeat
flbrst_inc_value <= "00100";
-- always 4 bytes/dbeat
cline_inc_value <= "00100";
sig_cline_addr_ld_mask <= "11100";
-- Burst and Cline BE's will always be set
sig_cline_burst_be <= (others => '1');
-- No masking required
sig_singles_be_mask <= (others => '1');
end generate GEN_NATIVE_WIDTH32;
------------------------------------------------------------------
-- Case for BRAM Native DWidth of 64 bits
--
------------------------------------------------------------------
GEN_NATIVE_WIDTH64 : if (C_NATIVE_DWIDTH = 64) generate
-- PLB_Size = "1010"
-- words <= PLB_Size_in(0) and
-- not(PLB_Size_in(1)) and
-- PLB_Size_in(2) and
-- not(PLB_Size_in(3));
words <= '1'
When (PLB_Size_in = "1010" or
(master_32 = '1' and
(cacheln_4 = '1' or
cacheln_8 = '1')))
Else '0';
-- -- PLB_Size = "1011"
-- dblwrds <= PLB_Size_in(0) and
-- not(PLB_Size_in(1)) and
-- PLB_Size_in(2) and
-- PLB_Size_in(3);
dblwrds <= '1'
When ((PLB_Size_in = "1011" or
PLB_Size_in = "1100") or
((master_64 = '1' or
master_128 = '1') and
(cacheln_4 = '1' or
cacheln_8 = '1')))
Else '0';
-- not supported
qwdwrds <= '0';
-- either 4 or 8 bytes/dbeat
flbrst_inc_value <= "01000" -- 8
when dblwrds = '1'
else "00100"; -- 4
-- either 4 or 8 bytes/dbeat
cline_inc_value <= "01000" -- 8
when (master_64 = '1' or -- 64-bit master or
master_128 = '1') -- 128-bit master
else "00100"; -- else 32-bit master
sig_cline_addr_ld_mask <= "11100"
When master_32 = '1' -- 32-bit master limited
Else "11000"; -- 64-bit xfer
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GEN_BURST_CLINE_BE_N64
--
-- Process Description:
-- This process generates the 8 BE bits needed during fixed
-- length burst writes and Cacheline writes. Since the
-- Native DWIDTH is 64 for this IfGen, then only Word transfers
-- require special handling.
--
-------------------------------------------------------------
GEN_BURST_CLINE_BE_N64 : process (words_s_h,
--dblwrds_s_h,
--qwdwrds_s_h,
sig_address_out)
begin
if (words_s_h = '1') then
if (sig_address_out(C_ADDR_CNTR_WIDTH-3) = '1') then
sig_cline_burst_be <= "00001111";
else
sig_cline_burst_be <= "11110000";
end if;
else -- dwrds or quad words
sig_cline_burst_be <= (others => '1');
end if;
end process GEN_BURST_CLINE_BE_N64;
----------------------------------------------------------------------
-- I_BE_MASK_GEN_64:
-- Singles BE Mask Generation Logic
-- This special logic is needed for the case when a Master that is
-- narrower than the BRAM Native Dwidth is doing a single data beat
-- write.
--
-----------------------------------------------------------------------
I_BE_MASK_GEN_64 : entity xps_bram_if_cntlr_v1_00_b.xbic_be_reset_gen
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DWIDTH ,
C_SMALLEST => C_SMALLEST_MASTER
)
port map (
Addr => sig_addr_4_3_s_h ,
MSize => msize_s_h ,
BE_Sngl_Mask => sig_singles_be_mask
);
end generate GEN_NATIVE_WIDTH64;
------------------------------------------------------------------
-- Case for BRAM Native DWidth of 128 bits
--
------------------------------------------------------------------
GEN_NATIVE_WIDTH128 : if (C_NATIVE_DWIDTH = 128) generate
signal sig_addr_bits_128 : std_logic_vector(0 to 1);
begin
-- -- PLB_Size = "1010"
-- words <= PLB_Size_in(0) and
-- not(PLB_Size_in(1)) and
-- PLB_Size_in(2) and
-- not(PLB_Size_in(3));
words <= '1'
When (PLB_Size_in = "1010" or
(master_32 = '1' and
(cacheln_4 = '1' or
cacheln_8 = '1')))
Else '0';
-- -- PLB_Size = "1011"
-- dblwrds <= PLB_Size_in(0) and
-- not(PLB_Size_in(1)) and
-- PLB_Size_in(2) and
-- PLB_Size_in(3);
dblwrds <= '1'
When (PLB_Size_in = "1011" or
(master_64 = '1' and
(cacheln_4 = '1' or
cacheln_8 = '1')))
Else '0';
-- -- PLB_Size = "1100"
-- qwdwrds <= PLB_Size_in(0) and
-- PLB_Size_in(1) and
-- not(PLB_Size_in(2)) and
-- not(PLB_Size_in(3));
qwdwrds <= '1'
When (PLB_Size_in = "1100" or
(master_128 = '1' and
(cacheln_4 = '1' or
cacheln_8 = '1')))
Else '0';
-- either 4, 8, or 16 bytes/dbeat
flbrst_inc_value <= "10000" -- 16
When qwdwrds = '1'
Else "01000" -- 8
when dblwrds = '1'
else "00100"; -- 4
-- either 4, 8, or 16 bytes/dbeat
cline_inc_value <= "10000" -- 16 bytes/dbeat
When master_128 = '1' -- 128-bit master
Else "01000" -- 8 bytes/dbeat
when master_64 = '1' -- 64-bit master
else "00100"; -- 4 bytes/dbeat
sig_cline_addr_ld_mask <= "10000" -- 16 bytes/dbeat
When master_128 = '1' -- 128-bit master
Else "11000" -- 8 bytes/dbeat
when master_64 = '1' -- 64-bit master
else "11100"; -- 32-bit master
-------------------------------------------------------------
-- Combinational Process
--
-- Label: GEN_BURST_CLINE_BE_N128
--
-- Process Description:
-- This process generates the 16 BE bits needed during fixed
-- length burst writes and Cacheline writes. Since the
-- Native DWIDTH is 128 for this IfGen, then Word and Dblwrd
-- transfers require special handling based on address.
--
--
-------------------------------------------------------------
GEN_BURST_CLINE_BE_N128 : process (words_s_h,
dblwrds_s_h,
--qwdwrds_s_h,
sig_address_out,
sig_addr_bits_128)
begin
sig_addr_bits_128 <= sig_address_out(C_ADDR_CNTR_WIDTH-4 to
C_ADDR_CNTR_WIDTH-3);
if (words_s_h = '1') then
case sig_addr_bits_128 is
when "01" =>
sig_cline_burst_be <= "0000111100000000";
when "10" =>
sig_cline_burst_be <= "0000000011110000";
when "11" =>
sig_cline_burst_be <= "0000000000001111";
when others =>
sig_cline_burst_be <= "1111000000000000";
end case;
Elsif (dblwrds_s_h = '1') Then
if (sig_address_out(C_ADDR_CNTR_WIDTH-4) = '1') then
sig_cline_burst_be <= "0000000011111111";
else
sig_cline_burst_be <= "1111111100000000";
end if;
else -- quad words
sig_cline_burst_be <= (others => '1');
end if;
end process GEN_BURST_CLINE_BE_N128;
----------------------------------------------------------------------
-- I_BE_MASK_GEN_128:
-- Singles BE Mask Generation Logic
-- This special logic is needed for the case when a Master that is
-- narrower than the BRAM Native Dwidth is doing a single data beat
-- write.
--
-----------------------------------------------------------------------
I_BE_MASK_GEN_128 : entity xps_bram_if_cntlr_v1_00_b.xbic_be_reset_gen
generic map (
C_NATIVE_DWIDTH => C_NATIVE_DWIDTH ,
C_SMALLEST => C_SMALLEST_MASTER
)
port map (
Addr => sig_addr_4_3_s_h ,
MSize => msize_s_h ,
BE_Sngl_Mask => sig_singles_be_mask
);
end generate GEN_NATIVE_WIDTH128;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SAMP_HOLD_REG
--
-- Process Description:
-- This process samples and holds the needed qualifiers for
-- the duration of the transfer data phase.
--
-------------------------------------------------------------
SAMP_HOLD_REG : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
single_s_h <= '0'; -- : std_logic;
flburst_s_h <= '0'; -- : std_logic;
cacheln_4_s_h <= '0'; -- : std_logic;
cacheln_8_s_h <= '0'; -- : std_logic;
words_s_h <= '0'; -- : std_logic;
dblwrds_s_h <= '0'; -- : std_logic;
qwdwrds_s_h <= '0'; -- : std_logic;
msize_s_h <= (others => '0');
sig_be_in_s_h <= (others => '0');
rnw_s_h <= '0';
master_32_s_h <= '0'; -- : std_logic;
master_64_s_h <= '0'; -- : std_logic;
master_128_s_h <= '0'; -- : std_logic;
flbrst_inc_value_s_h <= (others => '0'); -- : std_logic_vector(0 to 4);
cline_inc_value_s_h <= (others => '0'); -- : std_logic_vector(0 to 4);
--sig_burst_be_s_h <= (others => '0');
sig_addr_4_3_s_h <= (others => '0');
elsif (sig_s_h_qualifiers = '1') then
single_s_h <= single ; -- : std_logic;
flburst_s_h <= flburst ; -- : std_logic;
cacheln_4_s_h <= cacheln_4 ; -- : std_logic;
cacheln_8_s_h <= cacheln_8 ; -- : std_logic;
words_s_h <= words ; -- : std_logic;
dblwrds_s_h <= dblwrds ; -- : std_logic;
qwdwrds_s_h <= qwdwrds ; -- : std_logic;
msize_s_h <= Mstr_Size_in ;
sig_be_in_s_h <= BE_in ;
rnw_s_h <= PLB_RNW_in ;
master_32_s_h <= master_32 ; -- : std_logic;
master_64_s_h <= master_64 ; -- : std_logic;
master_128_s_h <= master_128 ; -- : std_logic;
flbrst_inc_value_s_h <= flbrst_inc_value; -- : std_logic_vector(0 to 4);
cline_inc_value_s_h <= cline_inc_value ; -- : std_logic_vector(0 to 4);
--sig_burst_be_s_h <= BE_in ;
sig_addr_4_3_s_h <= Bus_Addr_in(C_PLB_AWIDTH-4 to C_PLB_AWIDTH-3);
else
null; -- hold current values
end if;
end if;
end process SAMP_HOLD_REG;
-----------------------------------------------------------------
-- Main Address counter logic
--
--
-----------------------------------------------------------------
sig_addr_inc_value(0 to C_ADDR_CNTR_WIDTH-6)
<= (others => '0');
sig_addr_inc_value(C_ADDR_CNTR_WIDTH-5 to C_ADDR_CNTR_WIDTH-1)
<= UNSIGNED(flbrst_inc_value_s_h);
sig_ld_addr_cntr <= Addr_Load;
sig_incr_addr_cntr <= Addr_Cnt_en and
flburst_s_h;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_ADDR_CNTR
--
-- Process Description:
-- This process implements the main address counter.
--
-------------------------------------------------------------
GEN_ADDR_CNTR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr <= UNSIGNED(Bus_Addr_in);
Elsif (sig_incr_addr_cntr = '1') Then
sig_addr_cntr <= sig_addr_cntr +
sig_addr_inc_value;
else
null; -- hold current value
end if;
end if;
end process GEN_ADDR_CNTR;
-----------------------------------------------------------------
-- Cacheline Address counter logic
--
--
-----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_CACHLINE_ADDR_MODE
--
-- If Generate Description:
-- This IfGen implements the legacy starting address mode
-- for Cacheline operations which is Line word first for
-- writes and target word first for reads.
--
--
------------------------------------------------------------
LEGACY_CACHLINE_ADDR_MODE : if (C_CACHLINE_ADDR_MODE = 0) generate
-- Local Constants
-- Local variables
-- local signals
-- local components
begin
-- Rip the applicable bits from the input address
-- for the starting cacheline address
sig_cline_addr_slice_slv <=
Bus_Addr_in(C_ADDR_CNTR_WIDTH-CLINE_CNTR_WIDTH to
C_ADDR_CNTR_WIDTH-1);
-- -- always zero ls 2 bits of the input address for cachelines
-- sig_cline_addr_slice_slv(CLINE_CNTR_WIDTH-2 to
-- CLINE_CNTR_WIDTH-1) <= (others => '0');
sig_cline_addr_ld_mask_final <= sig_cline_addr_ld_mask;
end generate LEGACY_CACHLINE_ADDR_MODE;
------------------------------------------------------------
-- If Generate
--
-- Label: LINEAR_CACHLINE_ADDR_MODE
--
-- If Generate Description:
-- This IfGen implements the linear starting address mode
-- for Cacheline operations which is Line word first for
-- both writes and reads.
--
------------------------------------------------------------
LINEAR_CACHLINE_ADDR_MODE : if (C_CACHLINE_ADDR_MODE = 1) generate
-- constant WORD_ADDR_BIT : natural := CLINE_CNTR_WIDTH - 3;
-- constant DBLWORD_ADDR_BIT : natural := CLINE_CNTR_WIDTH - 4;
-- constant QUAD_WORD_ADDR_BIT : natural := CLINE_CNTR_WIDTH - 5;
--constant OCT_WORD_ADDR_BIT : natural := C_ADDR_CNTR_WIDTH - 6;
begin
-------------------------------------------------------------
-- REALIGN_CACHELINE_ADDR
-- This process implements the Cacheline starting address
-- realignment function.
-------------------------------------------------------------
REALIGN_CACHELINE_ADDR : process (Bus_Addr_in,
-- cacheln_8,
cacheln_4)
begin
-- -- Rip the applicable bits from the input address
-- -- for the starting cacheline address
-- sig_cline_addr_slice_slv(0 to CLINE_CNTR_WIDTH-3) <=
-- Bus_Addr_in(C_ADDR_CNTR_WIDTH-CLINE_CNTR_WIDTH to
-- C_ADDR_CNTR_WIDTH-3);
--
-- -- always zero ls 2 bits of the input address for cachelines
-- sig_cline_addr_slice_slv(CLINE_CNTR_WIDTH-2 to
-- CLINE_CNTR_WIDTH-1) <= (others => '0');
--
--
--
-- -- Clear applicable address bits to align address to the
-- -- requested cacheline size
-- if (cacheln_4 = '1') then -- realign to Cacheline 4
-- sig_cline_addr_slice_slv(WORD_ADDR_BIT) <= '0';
-- sig_cline_addr_slice_slv(DBLWORD_ADDR_BIT) <= '0';
-- elsif (cacheln_8 = '1') then -- realign to Cacheline 8
-- sig_cline_addr_slice_slv(WORD_ADDR_BIT) <= '0';
-- sig_cline_addr_slice_slv(DBLWORD_ADDR_BIT) <= '0';
-- sig_cline_addr_slice_slv(QUAD_WORD_ADDR_BIT) <= '0';
-- -- elsif (cacheln_16 = '1') then -- realign to Cacheline 16
-- -- sig_cline_addr_slice_slv(WORD_ADDR_BIT) <= '0';
-- -- sig_cline_addr_slice_slv(DBLWORD_ADDR_BIT) <= '0';
-- -- sig_cline_addr_slice_slv(QUAD_WORD_ADDR_BIT) <= '0';
-- -- sig_cline_addr_slice_slv(OCT_WORD_ADDR_BIT) <= '0';
-- else -- not a cacheline op
-- null; -- do nothing else
-- end if;
--
-- Rip the applicable bits from the input address
-- for the starting cacheline address
sig_cline_addr_slice_slv <=
Bus_Addr_in(C_ADDR_CNTR_WIDTH-CLINE_CNTR_WIDTH to
C_ADDR_CNTR_WIDTH-1);
-- Clear applicable address bits to align address to the
-- requested cacheline size
if (cacheln_4 = '1') then -- realign to Cacheline 4
sig_cline_addr_ld_mask_final <= "10000";
else -- realign to cacheline 8
sig_cline_addr_ld_mask_final <= "00000";
end if;
end process REALIGN_CACHELINE_ADDR;
end generate LINEAR_CACHLINE_ADDR_MODE;
sig_cline_ld_value <= UNSIGNED(sig_cline_addr_slice_slv and
sig_cline_addr_ld_mask_final);
sig_cline_inc_value <= UNSIGNED(cline_inc_value_s_h);
sig_ld_cline_addr_cntr <= Addr_Load;
sig_incr_cline_addr_cntr <= Addr_Cnt_en and
(cacheln_4_s_h or
cacheln_8_s_h);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_CLINE_ADDR_CNTR
--
-- Process Description:
-- This process implements the main address counter.
--
-------------------------------------------------------------
GEN_CLINE_ADDR_CNTR : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
sig_cline_slice_cntr <= (others => '0');
elsif (sig_ld_cline_addr_cntr = '1') then
sig_cline_slice_cntr <= sig_cline_ld_value;
Elsif (sig_incr_cline_addr_cntr = '1') Then
sig_cline_slice_cntr <= sig_cline_slice_cntr +
sig_cline_inc_value;
else
null; -- hold current value
end if;
end if;
end process GEN_CLINE_ADDR_CNTR;
end implementation;
| bsd-3-clause | 4dae5d5f6744ed17f678f6e381e69bd7 | 0.421756 | 4.237049 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/z091_01_wb_adr_dec.vhd | 1 | 3,666 | --------------------------------------------------------------------------------
-- Title : 16z091-01 specific Wishbone bus
-- Project :
-------------------------------------------------------------------------------
-- File : z091_01_wb_adr_dec.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2012-12-19
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Special address decoder that can be used with configurations
-- to enable multiple instances of the 16z091-01 IP core
-- that can have their unique address decoder
-------------------------------------------------------------------------------
-- Hierarchy:
-- ip_16z091_01_top
-- ip_16z091_01
-- Hard_IP
-- * z091_01_wb_adr_dec
--
-------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity z091_01_wb_adr_dec is
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port(
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end z091_01_wb_adr_dec;
-------------------------------------------------------------------------
-- sim_test_arch implements a sample pcie address decoder to enable
-- the simulation iram models
-------------------------------------------------------------------------
architecture sim_test_arch of z091_01_wb_adr_dec is
signal zero : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
zero <= (others => '0');
process(wbm_adr_o_q, pci_cyc_i, zero)
variable wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
wbm_cyc_o_int := (others => '0');
-- iram 1 - cycle 0 - offset 00000000 - size 1000 --
if pci_cyc_i(0) = '1' then
wbm_cyc_o_int(0) := '1';
else
wbm_cyc_o_int(0) := '0';
end if;
-- iram 2 - cycle 1 - offset 00000000 - size 2000 --
if pci_cyc_i(1) = '1' then
wbm_cyc_o_int(1) := '1';
else
wbm_cyc_o_int(1) := '0';
end if;
-- iram 2 - cycle 2 - offset 00000000 - size 1000 --
if pci_cyc_i(2) = '1' then
wbm_cyc_o_int(2) := '1';
else
wbm_cyc_o_int(2) := '0';
end if;
--if pci_cyc_i /= zero and wbm_cyc_o_int = "000" then
if pci_cyc_i /= "0000000" and wbm_cyc_o_int = zero then
wbm_cyc_o_int(0) := '1';
end if;
wbm_cyc_o <= wbm_cyc_o_int;
end process;
end sim_test_arch;
| gpl-3.0 | 8f8cdd82d25d23d0847ff9def16432d5 | 0.490998 | 3.916667 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE_READ/re_control.vhd | 1 | 3,641 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:01 11/12/2015
-- Design Name:
-- Module Name: re_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity re_control is
Port ( c_clk : in STD_LOGIC;
c_rst : in STD_LOGIC;
cpu_rd : in STD_LOGIC;
cpu_sc : in STD_LOGIC;
cpu_pa : in STD_LOGIC;
ready : out STD_LOGIC;
rd_enable : out STD_LOGIC;
mux_enable : out STD_LOGIC_vector(2 downto 0);
rd_strobe : out STD_LOGIC );
end re_control;
architecture Behavioral of re_control is
type states is (idle, hold, hold1, read0, read1, read2, read3, read4, finish);
signal nState, cState: states;
begin
re_control: process(c_clk, c_rst)
begin
if (c_rst = '1') then
cState <= idle;
elsif (c_clk'event and c_clk = '1') then
cState <= nState;
end if;
end process;
re_control_unit: process(cState, cpu_pa, cpu_sc, cpu_rd) --, parity, c_cpu_sc
begin
case cState is
when idle =>
rd_enable <= '0';
rd_strobe <= '1';
ready<= '0';
mux_enable <= "000";
if ((cpu_sc = '1') and (cpu_pa = '1')) then
nState <= hold;
else
nState <= idle;
end if;
when hold =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '0';
mux_enable <= "000";
if (cpu_rd = '1') then
nState <= hold1;
else nState <= idle;
end if;
when hold1 =>
rd_enable <= '0';
rd_strobe <= '0';
ready <= '1';
mux_enable <= "000";
nState <= read0;
when read0 =>
rd_enable <= '1';
rd_strobe <= '1';
ready <= '1';
mux_enable <= "000";
nState <= read1;
when read1 =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '1';
mux_enable <= "001";
nState <= read2;
when read2 =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '1';
mux_enable <= "010";
nState <= read3;
when read3 =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '1';
mux_enable <= "011";
nState <= read4;
when read4 =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '1';
mux_enable <= "100";
nState <= finish;
when finish =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '0';
mux_enable <= "000";
nState <= idle;
when others =>
rd_enable <= '0';
rd_strobe <= '1';
ready <= '0';
mux_enable <= "000";
nState <= idle;
end case;
end process;
end Behavioral;
| unlicense | 760bb7476f8f02af16f6deb9d28a9a43 | 0.437792 | 3.707739 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_pkg.vhd | 1 | 11,909 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE FiFo512Core32W32R_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT FiFo512Core32W32R_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FiFo512Core32W32R_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FiFo512Core32W32R_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT FiFo512Core32W32R_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FiFo512Core32W32R_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FiFo512Core32W32R_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END FiFo512Core32W32R_pkg;
PACKAGE BODY FiFo512Core32W32R_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END FiFo512Core32W32R_pkg;
| gpl-2.0 | 3f41f95b527cfe35a298964207ceb884 | 0.493912 | 3.955164 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_data_steer.vhd | 2 | 10,250 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_data_steer.vhd
-- Version: v1.10.a
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_data_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
-- BLT 5-13-2002 -- Added capability for peripherals larger
-- than bus, new optimizations
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH_BUS : integer := width of host databus attached to the IPIF
-- C_DWIDTH_IP : integer := width of IP databus attached to the IPIF
-- C_SMALLEST_MASTER : integer := width of smallest master (not access size)
-- attached to the IPIF
-- C_SMALLEST_IP : integer := width of smallest IP device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Data_Steer is
generic (
C_DWIDTH_BUS : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_IP : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_MASTER : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IP : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH_BUS-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH_IP-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_BUS/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH_IP-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH_BUS-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_IP/8-1)
);
end entity IPIF_Data_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Data_Steer is
component Steer_Module_Write is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end component Steer_Module_Write;
component Steer_Module_Read is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end component Steer_Module_Read;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
WRITE_I: Steer_Module_Write
generic map (
C_DWIDTH_IN => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Wr_Data_In, --[in]
BE_In => BE_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Wr_Data_Out, --[out]
BE_Out => BE_Out --[out]
);
READ_I: Steer_Module_Read
generic map (
C_DWIDTH_IN => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT => C_SMALLEST_MASTER, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Rd_Data_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Rd_Data_Out --[out]
);
end architecture IMP;
| bsd-3-clause | 21f1e57f59fe8f03f87dac8452a6d286 | 0.420683 | 4.059406 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/async_fifo_bram.vhd | 2 | 16,800 | -------------------------------------------------------------------------------
-- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- gen_sync_bram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
--
-- Description:
-- Code to infer asynchronous dual port bram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Async_FIFO_BRAM is
generic (
WordSize : integer := 8;
MemSize : integer := 16;
Protect : boolean := false
);
port (
Reset : in std_logic;
-- Clock region WrClk
WrClk : in std_logic;
WE : in std_logic;
DataIn : in std_logic_vector(WordSize-1 downto 0);
Full : out std_logic;
-- Clock region RdClk
RdClk : in std_logic;
RD : in std_logic;
DataOut : out std_logic_vector(WordSize-1 downto 0);
Exists : out std_logic
);
end entity Async_FIFO_BRAM;
architecture IMP of Async_FIFO_BRAM is
attribute ram_style : string;
function Bin2Gray(constant bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
gray(bin'high) := bin(bin'high);
for I in bin'high - 1 downto bin'low loop
gray(I) := bin(I + 1) xor bin(I);
end loop;
return gray;
end function Bin2Gray;
function Log2(x : integer) return integer is
variable i : integer := 0;
begin
-- coverage off
if x = 0 then return 0;
-- coverage on
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function Log2;
type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
signal ram_mem : ram_type;
attribute ram_style of ram_mem : signal is "block";
signal read_enable : std_logic;
signal write_enable : std_logic;
signal read_allow : std_logic;
signal write_allow : std_logic;
signal empty_allow : std_logic;
signal full_allow : std_logic;
signal full_i : std_logic;
signal empty : std_logic;
signal emptyg : std_logic;
signal fullg : std_logic;
signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
begin
-- Assign local signals from ports
read_enable <= RD;
write_enable <= WE;
-- Memory array
WritePort : process (WrClk)
begin
if (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
end if;
end if;
end process WritePort;
ReadPort : process (RdClk)
begin
if (RdClk'event and RdClk = '1') then
DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
end if;
end process ReadPort;
----------------------------------------------------------------
-- Allow flags determine whether FIFO control logic can --
-- operate. If read_enable is driven high, and the FIFO is --
-- not Empty, then Reads are allowed. Similarly, if the --
-- write_enable signal is high, and the FIFO is not Full, --
-- then Writes are allowed. --
----------------------------------------------------------------
read_allow <= (read_enable and not empty);
write_allow <= (write_enable and not full_i);
---------------------------------------------------------------
-- Empty flag is set on Reset (initial), or when gray --
-- code counters are equal, or when there is one word in --
-- the FIFO, and a Read operation is about to be performed. --
---------------------------------------------------------------
empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
EmptyFlag : process (RdClk, Reset)
begin
if (Reset = '1') then
empty <= '1';
elsif (RdClk'event and RdClk = '1') then
if (empty_allow = '1') then
empty <= emptyg;
end if;
end if;
end process EmptyFlag;
Exists <= not empty;
---------------------------------------------------------------
-- Full flag is set on Reset (initial, but it is cleared --
-- on the first valid write_clock edge after Reset is --
-- de-asserted), or when Gray-code counters are one away --
-- from being equal (the Write Gray-code address is equal --
-- to the Last Read Gray-code address), or when the Next --
-- Write Gray-code address is equal to the Last Read Gray- --
-- code address, and a Write operation is about to be --
-- performed. --
---------------------------------------------------------------
full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
FullFlag : process (WrClk, Reset)
begin
if (Reset = '1') then
full_i <= '1';
elsif (WrClk'event and WrClk = '1') then
if (full_allow = '1') then
full_i <= fullg;
end if;
end if;
end process FullFlag;
Full <= full_i;
----------------------------------------------------------------
-- Generation of Read address pointers. The primary one is --
-- binary (read_addr), and the Gray-code derivatives are --
-- generated via pipelining the binary-to-Gray-code result. --
-- The initial values are important, so they're in sequence. --
-- --
-- Grey-code addresses are used so that the registered --
-- Full and Empty flags are always clean, and never in an --
-- unknown state due to the asynchonous relationship of the --
-- Read and Write clocks. In the worst case scenario, Full --
-- and Empty would simply stay active one cycle longer, but --
-- it would not generate an error or give false values. --
----------------------------------------------------------------
read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
ReadAddrCnt : process (RdClk, Reset)
begin
if (Reset = '1') then
read_addr <= (others => '0');
elsif (RdClk'event and RdClk = '1') then
read_addr <= read_addr_next;
end if;
end process ReadAddrCnt;
ReadNextGray : process (RdClk, Reset)
begin
if (Reset = '1') then
read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
read_nextgray(read_nextgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_nextgray <= Bin2Gray(read_addr);
end if;
end if;
end process ReadNextGray;
ReadAddrGray : process (RdClk, Reset)
begin
if (Reset = '1') then
read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
read_addrgray(0) <= '1';
read_addrgray(read_addrgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_addrgray <= read_nextgray;
end if;
end if;
end process ReadAddrGray;
ReadLastGrey : process (RdClk, Reset)
begin
if (Reset = '1') then
read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
read_lastgray(0) <= '1';
read_lastgray(1) <= '1';
read_lastgray(read_lastgray'high) <= '1';
elsif (RdClk'event and RdClk = '1') then
if (read_allow = '1') then
read_lastgray <= read_addrgray;
end if;
end if;
end process ReadLastGrey;
----------------------------------------------------------------
-- Generation of Write address pointers. Identical copy of --
-- read pointer generation above, except for names. --
----------------------------------------------------------------
WriteAddrCnt : process (WrClk, Reset)
begin
if (Reset = '1') then
write_addr <= (others => '0');
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_addr <= std_logic_vector(unsigned(write_addr) + 1);
end if;
end if;
end process WriteAddrCnt;
WriteNextGray : process (WrClk, Reset)
begin
if (Reset = '1') then
write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
write_nextgray(write_nextgray'high) <= '1';
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_nextgray <= Bin2Gray(write_addr);
end if;
end if;
end process WriteNextGray;
WriteAddrGray : process (WrClk, Reset)
begin
if (Reset = '1') then
write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
write_addrgray(0) <= '1';
write_addrgray(write_addrgray'high) <= '1';
elsif (WrClk'event and WrClk = '1') then
if (write_allow = '1') then
write_addrgray <= write_nextgray;
end if;
end if;
end process WriteAddrGray;
----------------------------------------------------------------
-- The two conditions decoded with special carry logic are --
-- Empty and Full (gated versions). These are used to --
-- determine the next state of the Full/Empty flags. Carry --
-- logic is used for optimal speed. (The previous --
-- implementation of AlmostEmpty and AlmostFull have been --
-- wrapped into the corresponding carry chains for faster --
-- performance). --
-- --
-- When write_addrgray is equal to read_addrgray, the FIFO --
-- is Empty, and emptyg (combinatorial) is asserted. Or, --
-- when write_addrgray is equal to read_nextgray (1 word in --
-- the FIFO) then the FIFO potentially could be going Empty, --
-- so emptyg is asserted, and the Empty flip-flop enable is --
-- gated with empty_allow, which is conditioned with a valid --
-- read. --
-- --
-- Similarly, when read_lastgray is equal to write_addrgray, --
-- the FIFO is full (511 addresses). Or, when read_lastgray --
-- is equal to write_nextgray, then the FIFO potentially --
-- could be going Full, so fullg is asserted, and the Full --
-- flip-flop enable is gated with full_allow, which is --
-- conditioned with a valid write. --
-- --
-- Note: To have utilized the full address space (512) --
-- would have required extra logic to determine Full/Empty --
-- on equal addresses, and this would have slowed down the --
-- overall performance, which was the top priority. --
----------------------------------------------------------------
ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
begin
for I in 0 to Log2(MemSize)-1 loop
ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
(not (write_addrgray(I) xor read_nextgray(I)) and not empty);
end loop;
end process ECompare;
emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
begin
emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
end generate Gen_emuxcy;
emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
begin
for I in 0 to Log2(MemSize)-1 loop
fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
(not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
end loop;
end process FCompare;
fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
begin
fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
end generate Gen_fmuxcy;
fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
end architecture IMP;
| bsd-3-clause | 6baa7f5c7a9fbeff679f8b9dd3724b97 | 0.558155 | 4.042348 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_arbiter.vhd | 1 | 3,877 | --------------------------------------------------------------------------------
-- Title : Arbiter for DMA controller
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_arbiter.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module arbitrates the accesses from vme_dma_slv and vme_dma_mstr.
-- The request and acknoledge signals are like the whisbone
-- stb and ack signals. The arbitration result indicates the
-- signal arbit_slv. If set, the vme_dma_slv has access and vica
-- verse.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_arbiter
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_dma_arbiter.vhd,v $
-- Revision 1.1 2012/03/29 10:14:47 MMiehling
-- Initial Revision
--
-- Revision 1.3 2006/05/18 14:02:18 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:21 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/07/27 17:23:17 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:47 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma_arbiter IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- vme_dma_slv
slv_req : IN std_logic;
slv_ack : OUT std_logic;
-- vme_dma_mstr
mstr_req : IN std_logic;
mstr_ack : OUT std_logic;
-- result
arbit_slv : OUT std_logic -- if set, vme_dma_slv has access and vica verse
);
END vme_dma_arbiter;
ARCHITECTURE vme_dma_arbiter_arch OF vme_dma_arbiter IS
BEGIN
arbit_slv <= '0';
slv_ack <= '0';
arb : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
-- arbit_slv <= '0';
-- slv_ack <= '0';
mstr_ack <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
mstr_ack <= mstr_req;
-- IF mstr_req = '1' THEN -- vme_dma_mstr access is requested
-- mstr_ack <= '1';
-- slv_ack <= '0';
-- arbit_slv <= '0';
-- ELSIF slv_req = '1' THEN -- vme_dma_slv access is requested
-- mstr_ack <= '0';
-- slv_ack <= '1';
-- arbit_slv <= '1';
-- ELSE -- no requests
-- mstr_ack <= '0';
-- slv_ack <= '0';
-- arbit_slv <= '0';
-- END IF;
END IF;
END PROCESS arb;
END vme_dma_arbiter_arch;
| gpl-3.0 | d3bea89999ae2b7712c9e6b4009ab1bf | 0.475883 | 4.124468 | false | false | false | false |
iocoder/graduation | hardware/vga/vga.vhd | 1 | 12,584 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga is
Port ( CLK : in STD_LOGIC; -- 50MHz clock input
-- System Bus
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
RDY : out STD_LOGIC := '0';
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
-- VGA Port
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end vga;
architecture Structural of vga is
component clkgen is
Port (CLK : in STD_LOGIC;
CLK_56MHz : out STD_LOGIC;
CLK_50MHz : out STD_LOGIC;
CLK_28MHz : out STD_LOGIC;
CLK_25MHz : out STD_LOGIC;
CLK_12MHz : out STD_LOGIC);
end component;
component graphics is
Port ( CLK50 : in STD_LOGIC;
CLK12 : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
VBLANK : in STD_LOGIC;
VRAM0Read : out STD_LOGIC;
VRAM1Read : out STD_LOGIC;
VRAM2Read : out STD_LOGIC;
VRAM3Read : out STD_LOGIC;
VRAM4Read : out STD_LOGIC;
VRAM0Write : out STD_LOGIC;
VRAM1Write : out STD_LOGIC;
VRAM2Write : out STD_LOGIC;
VRAM3Write : out STD_LOGIC;
VRAM4Write : out STD_LOGIC;
VRAMAddr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAMDataOut : out STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : out STD_LOGIC;
SprWR : out STD_LOGIC;
SprAddr : out STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : out STD_LOGIC;
PalWR : out STD_LOGIC;
PalAddr : out STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
ROW_BASE : out STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : out STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : out STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
PPU_HSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_VSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
MODE : out STD_LOGIC);
end component;
component vgaram is
Port (CLK : in STD_LOGIC;
-- sequencer port:
SeqReadEnable : in STD_LOGIC;
SeqAddr : in STD_LOGIC_VECTOR (10 downto 0);
SeqDataOut : out STD_LOGIC_VECTOR ( 8 downto 0) := "000000000";
-- GU port:
GUReadEnable : in STD_LOGIC;
GUWriteEnable : in STD_LOGIC;
GUAddr : in STD_LOGIC_VECTOR (10 downto 0);
GUDataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
GUDataOut : out STD_LOGIC_VECTOR ( 8 downto 0));
end component;
component sequencer is
Port (CLK56 : in STD_LOGIC;
CLK28 : in STD_LOGIC;
SE : in STD_LOGIC;
MODE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC;
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC;
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC;
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC;
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0));
end component;
component dac is
Port (DE : in STD_LOGIC;
MODE : in STD_LOGIC;
COLOR : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component crt is
Port (CLK : in STD_LOGIC;
MODE : in STD_LOGIC;
VBLANK : out STD_LOGIC;
HS : out STD_LOGIC := '0';
VS : out STD_LOGIC := '0';
SE : out STD_LOGIC := '0';
DE : out STD_LOGIC := '0';
X : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
Y : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
B9 : out STD_LOGIC := '0');
end component;
signal CLK_56MHz : STD_LOGIC;
signal CLK_50MHz : STD_LOGIC;
signal CLK_28MHz : STD_LOGIC;
signal CLK_25MHz : STD_LOGIC;
signal CLK_12MHz : STD_LOGIC;
signal VRAM0Read : STD_LOGIC;
signal VRAM1Read : STD_LOGIC;
signal VRAM2Read : STD_LOGIC;
signal VRAM3Read : STD_LOGIC;
signal VRAM4Read : STD_LOGIC;
signal VRAM0Write : STD_LOGIC;
signal VRAM1Write : STD_LOGIC;
signal VRAM2Write : STD_LOGIC;
signal VRAM3Write : STD_LOGIC;
signal VRAM4Write : STD_LOGIC;
signal VRAMAddrFromGU : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM0DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM1DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM2DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM3DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM4DataToGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAMDataFromGU : STD_LOGIC_VECTOR ( 8 downto 0);
signal ROW_BASE : STD_LOGIC_VECTOR ( 7 downto 0);
signal CURSOR_ROW : STD_LOGIC_VECTOR ( 7 downto 0);
signal CURSOR_COL : STD_LOGIC_VECTOR ( 7 downto 0);
signal MODE : STD_LOGIC;
signal PPU_CTRL : STD_LOGIC_VECTOR (15 downto 0);
signal PPU_HSCR : STD_LOGIC_VECTOR ( 7 downto 0);
signal PPU_VSCR : STD_LOGIC_VECTOR ( 7 downto 0);
signal VBLANK : STD_LOGIC;
signal SE : STD_LOGIC;
signal DE : STD_LOGIC;
signal X : STD_LOGIC_VECTOR (15 downto 0);
signal Y : STD_LOGIC_VECTOR (15 downto 0);
signal B9 : STD_LOGIC;
signal COLOR : STD_LOGIC_VECTOR ( 5 downto 0);
signal VRAM0ReadEnable : STD_LOGIC;
signal VRAM0ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM0ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM1ReadEnable : STD_LOGIC;
signal VRAM1ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM1ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM2ReadEnable : STD_LOGIC;
signal VRAM2ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM2ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM3ReadEnable : STD_LOGIC;
signal VRAM3ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM3ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal VRAM4ReadEnable : STD_LOGIC;
signal VRAM4ReadAddr : STD_LOGIC_VECTOR (10 downto 0);
signal VRAM4ReadData : STD_LOGIC_VECTOR ( 8 downto 0);
signal SprRD : STD_LOGIC;
signal SprWR : STD_LOGIC;
signal SprAddr : STD_LOGIC_VECTOR ( 7 downto 0);
signal SprDataIn : STD_LOGIC_VECTOR ( 7 downto 0);
signal SprDataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal PalRD : STD_LOGIC;
signal PalWR : STD_LOGIC;
signal PalAddr : STD_LOGIC_VECTOR ( 4 downto 0);
signal PalDataIn : STD_LOGIC_VECTOR ( 7 downto 0);
signal PalDataOut : STD_LOGIC_VECTOR ( 7 downto 0);
begin
u0: clkgen port map (CLK, CLK_56MHz, CLK_50MHz, CLK_28MHz,
CLK_25MHz, CLK_12MHz);
u1: graphics port map (CLK, CLK_12MHz, CS, RW, A, Din, Dout,
INT, IAK, VBLANK,
VRAM0Read, VRAM1Read, VRAM2Read,
VRAM3Read, VRAM4Read,
VRAM0Write, VRAM1Write, VRAM2Write,
VRAM3Write, VRAM4Write,
VRAMAddrFromGU,
VRAM0DataToGU, VRAM1DataToGU, VRAM2DataToGU,
VRAM3DataToGU, VRAM4DataToGU, VRAMDataFromGU,
SprRD, SprWR, SprAddr, SprDataOut, SprDataIn,
PalRD, PalWR, PalAddr, PalDataOut, PalDataIn,
ROW_BASE, CURSOR_ROW, CURSOR_COL,
PPU_CTRL, PPU_HSCR, PPU_VSCR, MODE);
u2: vgaram port map (CLK_56MHz,
VRAM0ReadEnable, VRAM0ReadAddr, VRAM0ReadData,
VRAM0Read, VRAM0Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM0DataToGU);
u3: vgaram port map (CLK_56MHz,
VRAM1ReadEnable, VRAM1ReadAddr, VRAM1ReadData,
VRAM1Read, VRAM1Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM1DataToGU);
u4: vgaram port map (CLK_56MHz,
VRAM2ReadEnable, VRAM2ReadAddr, VRAM2ReadData,
VRAM2Read, VRAM2Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM2DataToGU);
u5: vgaram port map (CLK_56MHz,
VRAM3ReadEnable, VRAM3ReadAddr, VRAM3ReadData,
VRAM3Read, VRAM3Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM3DataToGU);
u6: vgaram port map (CLK_56MHz,
VRAM4ReadEnable, VRAM4ReadAddr, VRAM4ReadData,
VRAM4Read, VRAM4Write,
VRAMAddrFromGU, VRAMDataFromGU, VRAM4DataToGU);
u7: sequencer port map (CLK_56MHz, CLK_28MHz, SE,
MODE, ROW_BASE, CURSOR_ROW, CURSOR_COL,
PPU_CTRL, PPU_HSCR, PPU_VSCR,
X, Y, B9,
VRAM0ReadEnable, VRAM0ReadAddr, VRAM0ReadData,
VRAM1ReadEnable, VRAM1ReadAddr, VRAM1ReadData,
VRAM2ReadEnable, VRAM2ReadAddr, VRAM2ReadData,
VRAM3ReadEnable, VRAM3ReadAddr, VRAM3ReadData,
VRAM4ReadEnable, VRAM4ReadAddr, VRAM4ReadData,
SprRD, SprWR, SprAddr, SprDataIn, SprDataOut,
PalRD, PalWR, PalAddr, PalDataIn, PalDataOut,
COLOR);
u8: dac port map (DE, MODE, COLOR, R, G, B);
u9: crt port map (CLK_28MHz, MODE, VBLANK, HS, VS, SE, DE, X, Y, B9);
end Structural;
| gpl-3.0 | 193184c2d62f15641c2f9e2d9e4309ac | 0.547123 | 3.724179 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/complete_pic_test.vhd | 2 | 6,970 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:58:07 09/10/2009
-- Design Name:
-- Module Name: /home/abaez/ise_projects/complete_pic/src//complete_pic_test.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: complete_pic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY complete_pic_test IS
generic (
C_NUM_INTERRUPTS : integer := 8;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
)
END complete_pic_test;
ARCHITECTURE behavior OF complete_pic_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT complete_pic
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : IN std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1);
CMD_IN : IN std_logic_vector(0 to C_CMD_WIDTH-1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
interrupts_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal go : std_logic := '0';
signal TID_IN : std_logic_vector(0 to 7) := (others => '0');
signal IID_IN : std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1) := (others => '0');
signal CMD_IN : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal interrupts_in : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
signal RET_OUT : std_logic_vector(0 to 7);
signal TID_OUT : std_logic_vector(0 to 7);
-- Clock period definitions
constant clock_sig_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: complete_pic PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => go,
ack => ack,
TID_IN => TID_IN,
IID_IN => IID_IN,
CMD_IN => CMD_IN,
RET_OUT => RET_OUT,
TID_OUT => TID_OUT,
interrupts_in => interrupts_in,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Stimulus process
stim_proc: process
procedure assoc(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '0';
wait until ack = '0';
end procedure assoc;
procedure read_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '0';
wait until ack = '0';
end procedure read_entry;
procedure clear_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '0';
wait until ack = '0';
end procedure clear_entry;
procedure generate_interrupt(intr : in std_logic_vector(0 to C_NUM_INTERRUPTS-1)) is
begin
wait until clock_sig = '0';
interrupts_in <= intr;
wait until clock_sig = '1';
wait for 5*clock_sig_period;
end procedure generate_interrupt;
begin
-- hold reset state for 100ms.
wait for 50 ns;
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for 5*clock_sig_period;
-- insert stimulus here
go <= '0';
-- start. Write into memory #2 and #3 values 15 and 8.
assoc("00001111","010");
assoc("00001000","011");
-- Change the command to interrupt read an empty register
generate_interrupt("0100");
read_entry("00001010","010");
-- write another TID to memory #0
assoc("10110000","000");
-- specify another write to already chosen memory #0 - failure condition
assoc("00100000","000");
-- Set go to LOW and try to write.
wait for 4*clock_sig_period;
go <= '0';
TID_IN <= "11001100";
IID_IN <= "10";
-- Generate an interrupt for registers #0,#1 and #3
generate_interrupt("1101");
-- read memory address 3
read_entry("00110011","011");
-- Generate last interrupt
wait for 5*clock_sig_period;
generate_interrupt("1111");
wait;
end process;
END;
| bsd-3-clause | e70c06681b691c9323507f82be0d8f6c | 0.594835 | 3.300189 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_destroy_2.vhd | 2 | 15,751 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-- attr_destroy_2.c
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
-- hthread_attr_destroy( attr );
when STATE_3 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- retVal = hthread_attr_init( attr );
when STATE_5 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 52d89db60ccf7ed889a109f12e39adc3 | 0.548854 | 3.782661 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_scheduler_smp_v1_00_a/hdl/vhdl/plb_scheduler_smp.vhd | 2 | 36,069 | ------------------------------------------------------------------------------
-- plb_scheduler_smp.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler_smp.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_scheduler_smp_v1_00_a;
use plb_scheduler_smp_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_scheduler_smp is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_NUM_CPUS : integer := 2;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
-- current_thread for CPU 0 = TM2SCH_current_cpu_tid(0 to 7)
-- current_thread for CPU 1 = TM2SCH_current_cpu_tid(8 to 15)
-- current_thread for CPU N = TM2SCH_current_cpu_tid(8*(N-1) to 8*N-1)
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 8*C_NUM_CPUS - 1);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
-- preempt for CPU 0 = Preemption_Interrupt(0)
-- preempt for CPU 1 = Preemption_Interrupt(1)
-- preempt for CPU N = Preemption_Interrupt(N-1)
Preemption_Interrupt : out std_logic_vector(0 to C_NUM_CPUS - 1);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_scheduler_smp;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_scheduler_smp is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_scheduler_smp_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_NUM_CPUS => C_NUM_CPUS,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
Soft_Stop => Soft_Stop ,
SWTM_DOB => SWTM_DOB ,
SWTM_ADDRB => SWTM_ADDRB ,
SWTM_DIB => SWTM_DIB ,
SWTM_ENB => SWTM_ENB ,
SWTM_WEB => SWTM_WEB ,
TM2SCH_current_cpu_tid => TM2SCH_current_cpu_tid ,
TM2SCH_opcode => TM2SCH_opcode ,
TM2SCH_data => TM2SCH_data ,
TM2SCH_request => TM2SCH_request ,
SCH2TM_busy => SCH2TM_busy ,
SCH2TM_data => SCH2TM_data ,
SCH2TM_next_cpu_tid => SCH2TM_next_cpu_tid ,
SCH2TM_next_tid_valid => SCH2TM_next_tid_valid ,
Preemption_Interrupt => Preemption_Interrupt ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
end IMP;
| bsd-3-clause | 24d208eaee764a5dd3036c2023802e4e | 0.46192 | 4.180944 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg.vhd | 3 | 8,321 | -------------------------------------------------------------------------------
-- $Id: dma_sg.vhd,v 1.5 2003/11/04 20:11:33 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg entity (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg.vhd
--
-- Description: Entity declaration for dma_sg.
-- This entity defines a DMA capability that is intended
-- for embodiement inside the IPIF (IP Interface).
--
-- Four types of DMA channels are available:
-- (1) Simple DMA
-- (2) Scatter gather DMA
-- (3) Scatter gather packet transmit
-- (4) Scatter gather packet receive
--
-- An arbitrary number of channels, each of any of the types,
-- may be included in an instantiation through appropriate
-- generic settings.
--
-- Packet transmit and receive channels may be outfitted with
-- optional interrupt-coalescing support.
--
-- The maximum length of DMA transfers is user selectable and
-- using the smallest feasible value may reduce FPGA resource
-- usage.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
-- -- Channels fixed at two for this version
-- -- to allow XST E.33 compatibility.
--
-- FLO 06/07/02 -- Added generic C_WFIFO_VACANCY_WIDTH.
--
-- FLO 01/30/03
-- ^^^^^^
-- Fixed Bus2IP_Data and DMA2Bus_Data at 32 bits, 0 to 31.
-- Fixed Bus2IP_BE 4 bits, 0 to 3.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE: positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 1;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to C_DMA_CHAN_TYPE'length-1)
);
constant TPB : positive := C_DMA_BURST_SIZE;
end dma_sg;
| bsd-3-clause | 9902e41fdb11de88b55f26727c5f868c | 0.465689 | 4.015927 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_three_v1_00_a/hdl/vhdl/old/user_logic_hwtul.vhd | 2 | 19,798 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal condAddr, condAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
mutexAddr <= mutexAddr_next;
condAddr <= condAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
mutexAddr_next <= mutexAddr;
condAddr_next<= condAddr;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of condvar
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg4_next <= intrfc2thrd_value;
next_state <= STATE_21;
new_request <= '0';
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_7 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_9;
else
next_state <= STATE_16;
end if;
new_request <= '0';
-- hthread_cond_signal( condvar );
when STATE_9 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call COND_SIGNAL
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- hthread_cond_wait( condvar, mutex );
when STATE_11 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_cond_wait
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_14 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- END OF WHILE LOOP
-- hthread_cond_broadcast( condvar );
when STATE_16 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call COND_BROADCAST
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_18 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
when STATE_20 =>
next_state <= FUNCTION_EXIT;
new_request <= '0';
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | c0bbcf15459a7f4598aba2621d674d5f | 0.559349 | 3.716538 | false | false | false | false |
michaelmiehling/A25_VME | Source/wb_bus.vhd | 1 | 17,012 | --------------------------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
--------------------------------------------------------------------------------
-- File : wb_bus.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : Quartus II
--------------------------------------------------------------------------------
-- Description :
-- Master # 0 1 2
-- Slave : 0 1 0 0
-- Slave : 1 1 0 0
-- Slave : 2 1 0 1
-- Slave : 3 1 1 1
-- Slave : 4 0 1 1
-- Master 0 = 4 connection(s)
-- Master 1 = 2 connection(s)
-- Master 2 = 3 connection(s)
-- Slave 0 = 1 connection(s)
-- Slave 1 = 1 connection(s)
-- Slave 2 = 2 connection(s)
-- Slave 3 = 3 connection(s)
-- Slave 4 = 2 connection(s)
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wb_pkg.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision: 1.6
--
--------------------------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.wb_pkg.ALL;
ENTITY wb_bus IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- Master Bus
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
-- Slave Bus
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
wbso_1 : IN wbi_type;
wbsi_1 : OUT wbo_type;
wbsi_1_cyc : OUT std_logic;
wbso_2 : IN wbi_type;
wbsi_2 : OUT wbo_type;
wbsi_2_cyc : OUT std_logic;
wbso_3 : IN wbi_type;
wbsi_3 : OUT wbo_type;
wbsi_3_cyc : OUT std_logic;
wbso_4 : IN wbi_type;
wbsi_4 : OUT wbo_type;
wbsi_4_cyc : OUT std_logic
);
END wb_bus;
ARCHITECTURE wb_bus_arch OF wb_bus IS
-- COMPONENT DECLARATIONS
COMPONENT switch_fab_1
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT switch_fab_2
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT switch_fab_3
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END COMPONENT;
-- synthesis translate_off
COMPONENT wbmon
GENERIC (
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic
);
END COMPONENT;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL wbs_0_ack : std_logic;
SIGNAL wbs_0_err : std_logic;
SIGNAL wbs_1_ack : std_logic;
SIGNAL wbs_1_err : std_logic;
SIGNAL wbs_2_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_2_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_3_ack : std_logic_vector(2 DOWNTO 0);
SIGNAL wbs_3_err : std_logic_vector(2 DOWNTO 0);
SIGNAL wbs_4_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_4_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbsi_1_int : wbo_type;
SIGNAL wbsi_1_cyc_int : std_logic;
SIGNAL wbsi_2_int : wbo_type;
SIGNAL wbsi_2_cyc_int : std_logic;
SIGNAL wbsi_3_int : wbo_type;
SIGNAL wbsi_3_cyc_int : std_logic;
SIGNAL wbsi_4_int : wbo_type;
SIGNAL wbsi_4_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmo_1_cyc_s : std_logic;
SIGNAL wbmi_2_int : wbi_type;
SIGNAL wbmo_2_cyc_s : std_logic;
BEGIN
wbsi_0 <= wbsi_0_int;
wbsi_0_cyc <= wbsi_0_cyc_int;
wbsi_1 <= wbsi_1_int;
wbsi_1_cyc <= wbsi_1_cyc_int;
wbsi_2 <= wbsi_2_int;
wbsi_2_cyc <= wbsi_2_cyc_int;
wbsi_3 <= wbsi_3_int;
wbsi_3_cyc <= wbsi_3_cyc_int;
wbsi_4 <= wbsi_4_int;
wbsi_4_cyc <= wbsi_4_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
wbmi_2 <= wbmi_2_int;
-- data multiplexer for master #0
data_mux (
cyc => wbmo_0_cyc,
data_in_0 => wbso_0.dat,
data_in_1 => wbso_1.dat,
data_in_2 => wbso_2.dat,
data_in_3 => wbso_3.dat,
data_out => wbmi_0_int.dat
);
wbmi_0_int.ack <= wbs_0_ack OR wbs_1_ack OR wbs_2_ack(0) OR wbs_3_ack(0);
wbmi_0_int.err <= wbs_0_err OR wbs_1_err OR wbs_2_err(0) OR wbs_3_err(0);
-- data multiplexer for master #1
data_mux (
cyc => wbmo_1_cyc,
data_in_0 => wbso_3.dat,
data_in_1 => wbso_4.dat,
data_out => wbmi_1_int.dat
);
wbmi_1_int.ack <= wbs_3_ack(1) OR wbs_4_ack(0);
wbmi_1_int.err <= wbs_3_err(1) OR wbs_4_err(0);
-- data multiplexer for master #2
data_mux (
cyc => wbmo_2_cyc,
data_in_0 => wbso_2.dat,
data_in_1 => wbso_3.dat,
data_in_2 => wbso_4.dat,
data_out => wbmi_2_int.dat
);
wbmi_2_int.ack <= wbs_2_ack(1) OR wbs_3_ack(2) OR wbs_4_ack(1);
wbmi_2_int.err <= wbs_2_err(1) OR wbs_3_err(2) OR wbs_4_err(1);
-- sf for slave #0:
sf_0: switch_fab_1
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(0),
ack_0 => wbs_0_ack,
err_0 => wbs_0_err,
-- slave bus:
wbo_slave => wbso_0,
wbi_slave => wbsi_0_int,
wbi_slave_cyc => wbsi_0_cyc_int
);
-- sf for slave #1:
sf_1: switch_fab_1
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(1),
ack_0 => wbs_1_ack,
err_0 => wbs_1_err,
-- slave bus:
wbo_slave => wbso_1,
wbi_slave => wbsi_1_int,
wbi_slave_cyc => wbsi_1_cyc_int
);
-- sf for slave #2:
sf_2: switch_fab_2
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(2),
ack_0 => wbs_2_ack(0),
err_0 => wbs_2_err(0),
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(0),
ack_1 => wbs_2_ack(1),
err_1 => wbs_2_err(1),
-- slave bus:
wbo_slave => wbso_2,
wbi_slave => wbsi_2_int,
wbi_slave_cyc => wbsi_2_cyc_int
);
-- sf for slave #3:
sf_3: switch_fab_3
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc(3),
ack_0 => wbs_3_ack(0),
err_0 => wbs_3_err(0),
wbo_1 => wbmo_1,
cyc_1 => wbmo_1_cyc(0),
ack_1 => wbs_3_ack(1),
err_1 => wbs_3_err(1),
wbo_2 => wbmo_2,
cyc_2 => wbmo_2_cyc(1),
ack_2 => wbs_3_ack(2),
err_2 => wbs_3_err(2),
-- slave bus:
wbo_slave => wbso_3,
wbi_slave => wbsi_3_int,
wbi_slave_cyc => wbsi_3_cyc_int
);
-- sf for slave #4:
sf_4: switch_fab_2
GENERIC MAP (
registered => FALSE
)
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_1,
cyc_0 => wbmo_1_cyc(1),
ack_0 => wbs_4_ack(0),
err_0 => wbs_4_err(0),
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(2),
ack_1 => wbs_4_ack(1),
err_1 => wbs_4_err(1),
-- slave bus:
wbo_slave => wbso_4,
wbi_slave => wbsi_4_int,
wbi_slave_cyc => wbsi_4_cyc_int
);
-- synthesis translate_off
wbmo_0_cyc_s <= '1' WHEN wbmo_0_cyc = 0 ELSE '1';
wbm_0: wbmon
GENERIC MAP (
wbname => "wbm_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_0.adr,
sldat_i => wbmo_0.dat,
sldat_o => wbmi_0_int.dat,
cti => wbmo_0.cti,
sel => wbmo_0.sel,
cyc => wbmo_0_cyc_s,
stb => wbmo_0.stb,
ack => wbmi_0_int.ack,
err => wbmi_0_int.err,
we => wbmo_0.we
);
wbmo_1_cyc_s <= '1' WHEN wbmo_1_cyc = 0 ELSE '1';
wbm_1: wbmon
GENERIC MAP (
wbname => "wbm_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_1.adr,
sldat_i => wbmo_1.dat,
sldat_o => wbmi_1_int.dat,
cti => wbmo_1.cti,
sel => wbmo_1.sel,
cyc => wbmo_1_cyc_s,
stb => wbmo_1.stb,
ack => wbmi_1_int.ack,
err => wbmi_1_int.err,
we => wbmo_1.we
);
wbmo_2_cyc_s <= '1' WHEN wbmo_2_cyc = 0 ELSE '1';
wbm_2: wbmon
GENERIC MAP (
wbname => "wbm_2",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_2.adr,
sldat_i => wbmo_2.dat,
sldat_o => wbmi_2_int.dat,
cti => wbmo_2.cti,
sel => wbmo_2.sel,
cyc => wbmo_2_cyc_s,
stb => wbmo_2.stb,
ack => wbmi_2_int.ack,
err => wbmi_2_int.err,
we => wbmo_2.we
);
wbs_0: wbmon
GENERIC MAP (
wbname => "wbs_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_0_int.adr,
sldat_i => wbsi_0_int.dat,
sldat_o => wbso_0.dat,
cti => wbsi_0_int.cti,
sel => wbsi_0_int.sel,
cyc => wbsi_0_cyc_int,
stb => wbsi_0_int.stb,
ack => wbso_0.ack,
err => wbso_0.err,
we => wbsi_0_int.we
);
wbs_1: wbmon
GENERIC MAP (
wbname => "wbs_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_1_int.adr,
sldat_i => wbsi_1_int.dat,
sldat_o => wbso_1.dat,
cti => wbsi_1_int.cti,
sel => wbsi_1_int.sel,
cyc => wbsi_1_cyc_int,
stb => wbsi_1_int.stb,
ack => wbso_1.ack,
err => wbso_1.err,
we => wbsi_1_int.we
);
wbs_2: wbmon
GENERIC MAP (
wbname => "wbs_2",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_2_int.adr,
sldat_i => wbsi_2_int.dat,
sldat_o => wbso_2.dat,
cti => wbsi_2_int.cti,
sel => wbsi_2_int.sel,
cyc => wbsi_2_cyc_int,
stb => wbsi_2_int.stb,
ack => wbso_2.ack,
err => wbso_2.err,
we => wbsi_2_int.we
);
wbs_3: wbmon
GENERIC MAP (
wbname => "wbs_3",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_3_int.adr,
sldat_i => wbsi_3_int.dat,
sldat_o => wbso_3.dat,
cti => wbsi_3_int.cti,
sel => wbsi_3_int.sel,
cyc => wbsi_3_cyc_int,
stb => wbsi_3_int.stb,
ack => wbso_3.ack,
err => wbso_3.err,
we => wbsi_3_int.we
);
wbs_4: wbmon
GENERIC MAP (
wbname => "wbs_4",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_4_int.adr,
sldat_i => wbsi_4_int.dat,
sldat_o => wbso_4.dat,
cti => wbsi_4_int.cti,
sel => wbsi_4_int.sel,
cyc => wbsi_4_cyc_int,
stb => wbsi_4_int.stb,
ack => wbso_4.ack,
err => wbso_4.err,
we => wbsi_4_int.we
);
-- synthesis translate_on
END wb_bus_arch;
| gpl-3.0 | ba49dfef4b5dd1869b7c19e6643c433e | 0.417881 | 3.445119 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_sys_arbiter.vhd | 1 | 11,000 | --------------------------------------------------------------------------------
-- Title : sys_arbiter for mensb or vme accesses
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_sys_arbiter.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module arbitrates the wbb or vmebus accesses.
-- The modules vme_master or vme_slave can generate a request
-- signal. If there is no current transmission, the vme_sys_arbiter
-- activates the corresponding acknoledge signal. This signal
-- is active until the request is deasserted. If other requests
-- are asserted during this time, they have to wait until the
-- ongoing one is finished.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_sys_arbiter
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_sys_arbiter.vhd,v $
-- Revision 1.3 2014/04/17 07:35:20 MMiehling
-- removed unused signals
--
-- Revision 1.2 2012/08/27 12:57:07 MMiehling
-- added second_word for d64 slave access
--
-- Revision 1.1 2012/03/29 10:14:31 MMiehling
-- Initial Revision
--
-- Revision 1.3 2003/12/01 10:03:40 MMiehling
-- added d64
--
-- Revision 1.2 2003/07/14 08:38:00 MMiehling
-- lword was missing
--
-- Revision 1.1 2003/04/01 13:04:35 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.ALL;
ENTITY vme_sys_arbiter IS
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
io_ctrl : OUT io_ctrl_type;
ma_io_ctrl : IN io_ctrl_type;
sl_io_ctrl : IN io_ctrl_type;
mensb_req : IN std_logic; -- request signal for mensb slave access, from vme_wbs
slave_req : IN std_logic; -- request signal for slave access
mstr_busy : IN std_logic; -- master busy
mstr_vme_req : IN std_logic; -- master request VME interface
mensb_active : OUT std_logic; -- acknoledge/active signal for mensb slave access
slave_active : OUT std_logic; -- acknoledge/active signal for slave access
lwordn_slv : IN std_logic; -- stored for vme slave access
lwordn_mstr : IN std_logic; -- master access lwordn
lwordn : OUT std_logic; -- lwordn for vme_du multiplexer
write_flag : OUT std_logic; -- write flag for register access dependent on arbitration
ma_byte_routing : IN std_logic;
sl_byte_routing : IN std_logic;
byte_routing : OUT std_logic;
sl_sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select: 00=wbm_dat_i 01=wbs_dat_i 10=reg_data
sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0);
ma_oe_vd : IN std_logic; -- master output enable signal for VAD
sl_oe_vd : IN std_logic; -- slave output enable signal for VAD
oe_vd : OUT std_logic; -- output enable signal for VAD
ma_oe_va : IN std_logic; -- master output enable signal for VAD
sl_oe_va : IN std_logic; -- slave output enable signal for VAD
oe_va : OUT std_logic; -- output enable signal for VAD
ma_en_vme_data_out_reg : IN std_logic;
sl_en_vme_data_out_reg : IN std_logic;
reg_en_vme_data_out_reg : IN std_logic;
en_vme_data_out_reg : OUT std_logic;
ma_en_vme_data_out_reg_high : IN std_logic;
sl_en_vme_data_out_reg_high : IN std_logic;
en_vme_data_out_reg_high : OUT std_logic;
swap : OUT std_logic; -- swapping of data bytes on/off
ma_swap : IN std_logic;
sl_d64 : IN std_logic;
ma_d64 : IN std_logic;
d64 : OUT std_logic; -- indicates d64 master access
ma_second_word : IN std_logic; -- differs between address and data phase in d64
sl_second_word : IN std_logic; -- differs between address and data phase in d64
second_word : OUT std_logic; -- differs between address and data phase in d64
ma_en_vme_data_in_reg : IN std_logic; -- master enable of vme data in registers
sl_en_vme_data_in_reg : IN std_logic; -- slave enable of vme data in registers
en_vme_data_in_reg : OUT std_logic; -- enable of vme data in registers
ma_en_vme_data_in_reg_high : IN std_logic; -- master enable of vme data high in registers
sl_en_vme_data_in_reg_high : IN std_logic; -- slave enable of vme data high in registers
en_vme_data_in_reg_high : OUT std_logic; -- enable of vme data high in registers
vme_adr_locmon : OUT std_logic_vector(31 DOWNTO 2); -- adress for location monitor (either vme_adr_in or vme_adr_out)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress sampled with en_vme_adr_in
vme_adr_out : IN std_logic_vector(31 DOWNTO 2); -- vme adress for master access
loc_write_flag : IN std_logic; -- write flag for register access from mensb side
sl_write_flag : IN std_logic -- write flag for register access from vme side
);
END vme_sys_arbiter;
ARCHITECTURE vme_sys_arbiter_arch OF vme_sys_arbiter IS
TYPE arbit_states IS (arbit_mensb, arbit_vme);
SIGNAL arbit_state : arbit_states;
SIGNAL mensb_active_int : std_logic;
SIGNAL en_vme_data_in_reg_int : std_logic;
BEGIN
io_ctrl <= ma_io_ctrl WHEN mstr_vme_req = '1' ELSE sl_io_ctrl;
second_word <= ma_second_word WHEN mstr_vme_req = '1' ELSE sl_second_word;
en_vme_data_out_reg <= ma_en_vme_data_out_reg WHEN mstr_vme_req = '1' ELSE sl_en_vme_data_out_reg OR reg_en_vme_data_out_reg;
en_vme_data_in_reg <= ma_en_vme_data_in_reg WHEN mstr_vme_req = '1' ELSE sl_en_vme_data_in_reg;
en_vme_data_in_reg_high <= ma_en_vme_data_in_reg_high WHEN mstr_vme_req = '1' ELSE sl_en_vme_data_in_reg_high;
sel_vme_data_out <= "01" WHEN mstr_vme_req = '1' ELSE sl_sel_vme_data_out;
vme_adr_locmon <= vme_adr_out WHEN mstr_vme_req = '1' ELSE vme_adr_in_reg;
d64 <= ma_d64 WHEN mstr_vme_req = '1' ELSE sl_d64;
en_vme_data_out_reg_high <= ma_en_vme_data_out_reg_high WHEN mstr_vme_req = '1' ELSE sl_en_vme_data_out_reg_high;
byte_routing <= ma_byte_routing WHEN mstr_vme_req = '1' ELSE sl_byte_routing;
-- en_vme_data_in_reg <= en_vme_data_in_reg_int;
mensb_active <= mensb_active_int;
write_flag <= loc_write_flag WHEN mensb_active_int = '1' ELSE sl_write_flag;
reg : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
oe_vd <= '0';
oe_va <= '0';
lwordn <= '0';
swap <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
IF mstr_vme_req = '1' THEN
oe_va <= ma_oe_va;
ELSE
oe_va <= sl_oe_va;
END IF;
if mstr_busy = '1' then
swap <= ma_swap;
oe_vd <= ma_oe_vd;
lwordn <= lwordn_mstr;
else
swap <= '1';
oe_vd <= sl_oe_vd;
lwordn <= lwordn_slv;
end if;
END IF;
END PROCESS reg;
arbit_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
arbit_state <= arbit_mensb;
mensb_active_int <= '1';
slave_active <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE arbit_state IS
WHEN arbit_mensb =>
IF slave_req = '1' AND mensb_req = '0' THEN
arbit_state <= arbit_vme;
mensb_active_int <= '0';
slave_active <= '1';
ELSE
arbit_state <= arbit_mensb;
mensb_active_int <= '1';
slave_active <= '0';
END IF;
WHEN arbit_vme =>
IF slave_req = '0' THEN
arbit_state <= arbit_mensb;
mensb_active_int <= '1';
slave_active <= '0';
ELSE
arbit_state <= arbit_vme;
mensb_active_int <= '0';
slave_active <= '1';
END IF;
WHEN OTHERS =>
arbit_state <= arbit_mensb;
END CASE;
END IF;
END PROCESS arbit_fsm;
END vme_sys_arbiter_arch;
| gpl-3.0 | c0375cf222f2b9e684843b407f5f1c4a | 0.481455 | 4.115226 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter.vhd | 3 | 5,355 | -------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
| bsd-3-clause | 3e5d22c47d83d261475c010aa364e715 | 0.363959 | 4.616379 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/equal_2.vhd | 2 | 15,082 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- equal_2.c
-- FIRST_THREAD 5
-- SECOND_THREAD 7
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- if ( hthread_self( FIRST_THREAD, SECOND_THREAD ) == 0 ) retVal = SUCCESS;
-- else retVal = FAILURE;
when FUNCTION_START =>
-- Push FIRST_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push SECOND_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000007";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_equal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EQUAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
case intrfc2thrd_value is
when x"00000000" =>
retVal_next <= Z32;
when others =>
retVal_next <= x"00000001";
end case;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | d7939c14381952ab7d6742ab43bac652 | 0.536666 | 3.868171 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/zcpsm.vhd | 1 | 9,226 | --=============================================================================
-- Project: ZCPSM
-- Copyright: GPLv2
-- Author: Zhao Ming
-- Revision: V1.0
-- Last revised:
-- Workfile: zcpsm.vhd
-- Archive:
-------------------------------------------------------------------------------
-- Description:
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity zcpsm is
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end zcpsm;
architecture fast of zcpsm is
----------------------------------------------------------------
-- To inprove preformace, decode instruction two step
-- Heap address is connect direct to instruction
-- components:
-- Heap: controling s00~s1F's read two(asychronous), write one
-- every time(synchronous)
-- Stack: program stack, push and pop the addresses of instructions
-- Clk_Gen: output proper clk signal to control other blocks
----------------------------------------------------------------
component zHeap
port (
reset : in std_logic;
addra: in std_logic_vector(4 downto 0);
dia: in std_logic_vector(7 downto 0);
wea: in std_logic;
clk: in std_logic;
clk_en: in std_logic;
addrb: in std_logic_vector(4 downto 0);
doa: out std_logic_vector(7 downto 0);
dob: out std_logic_vector(7 downto 0)
);
end component;
component pcstack
generic(
depth:integer:=16;
awidth:integer:=4;
width:integer:=8
);
port (
reset : in std_logic;
clk: in std_logic;
en: in std_logic;
pop_push: in std_logic;
din: in std_logic_vector(width-1 downto 0);
dout: out std_logic_vector(width-1 downto 0)
);
end component;
component addsub
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
C_IN: IN std_logic;
C_EN: IN std_logic;
C_OUT: OUT std_logic;
sub: IN std_logic;
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END component;
component logical
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
OP: IN std_logic_vector( 1 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END component;
component shiftL
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
Ci: In std_logic;
OP: IN std_logic_vector( 2 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0);
Co: out std_logic
);
END component;
component shiftR
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
Ci: In std_logic;
OP: IN std_logic_vector( 2 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0);
Co: out std_logic
);
END component;
--clock signals
--heap signals
signal heap_dia: std_logic_vector(7 downto 0);
signal heap_wea: std_logic;
signal heap_addra: std_logic_vector(4 downto 0);
signal heap_addrb: std_logic_vector(4 downto 0);
signal heap_dob: std_logic_vector(7 downto 0);
signal heap_doa: std_logic_vector(7 downto 0);
--ALU signals
signal alu_A: std_logic_vector(7 downto 0);
signal alu_B: std_logic_vector(7 downto 0);
signal alu_op: std_logic_vector(2 downto 0);
signal shift_op: std_logic_vector(3 downto 0);
signal alu_out: std_logic_vector(7 downto 0);
signal alu_cflag_out: std_logic;
signal shift_sel : std_logic;
--addsub signals
signal sum_out:std_logic_vector(7 downto 0);
signal sum_cflag_out:std_logic;
--shift l signals
signal shiftl_out:std_logic_vector(7 downto 0);
signal shiftl_cflag_out:std_logic;
--shift r signals
signal shiftr_out:std_logic_vector(7 downto 0);
signal shiftr_cflag_out:std_logic;
--logic signals
signal logical_out:std_logic_vector(7 downto 0);
--ZC_Reg signals
signal cflag: std_logic;
signal zflag: std_logic;
--PC signals
signal pc: std_logic_vector(11 downto 0);
signal nextPc: std_logic_vector(11 downto 0);
signal jumpEn,jumpFlag,jumpSet : std_logic;
--Stack signals
signal stack_en: std_logic;
signal stack_po_pu: std_logic;
signal stack_din: std_logic_vector(11 downto 0);
signal stack_dout: std_logic_vector(11 downto 0);
--Port_ctrl signals
signal io_read_strobe_int: std_logic;
signal io_write_strobe_int: std_logic;
signal ins : std_logic_vector( 17 downto 0 );
begin
AHeap: zHeap
port map(
reset => reset,
addra => heap_addra,
dia => heap_dia,
wea => heap_wea,
clk => clk,
clk_en => '0', -- why '0' means enable
addrb => heap_addrb,
doa => heap_doa,
dob => heap_dob
);
port_id <= ins( 7 downto 0 ) when ins(12)='0' else heap_dob;
ALU_OP <= ins( 14 downto 12 ) when ins(15)='0' else ins( 2 downto 0 );
SHIFT_OP <= ins( 3 downto 0 );
ALU_A <= heap_doa;
ALU_B <= ins( 7 downto 0 ) when ins(15)='0' else heap_dob;
ALUProc:process( ALU_OP, SHIFT_OP,SHIFT_SEL,logical_out,sum_out,sum_cflag_out,shiftl_out,shiftl_cflag_out,shiftr_out,shiftr_cflag_out )
variable alu_res: std_logic_vector( 8 downto 0 );
begin
if SHIFT_SEL='0' then
if ALU_OP(2)='0' then
alu_out<=logical_out;
alu_cflag_out<='0';
else
alu_out<=sum_out;
alu_cflag_out<=sum_cflag_out;
end if;
else
if shift_op(3)='0' then
alu_out<=shiftl_out;
alu_cflag_out<=shiftl_cflag_out;
else
alu_out<=shiftr_out;
alu_cflag_out<=shiftr_cflag_out;
end if;
end if;
end process;
-- Heap address and data define
heap_addra <= ins(17) & ins( 11 downto 8 );
heap_addrb <= ins(16) & ins( 7 downto 4 );
heap_dia <= in_port when io_read_strobe_int='1' else
alu_out;
-- Lock heap wea
heap_wea<='0' when ins(15 downto 13 )="100" or ins(15 downto 13 )="111" else '1';
-- Lock Shift sel
SHIFT_SEL<='1' when ins(15 downto 12 )="1101" else '0';
-- Lock in out strobe
io_read_strobe_int<='1' when ins( 15 downto 13 )="101" else '0';
io_write_strobe_int<='1' when ins( 15 downto 13 )="111" else '0';
nextPc<=pc+1;
PcProc:process(reset,clk)
begin
if reset = '1' then
pc<=(others=>'0');
jumpSet<='0';
ins<="001100000000000000";
elsif rising_edge(clk) then
if ins( 15 downto 13 ) ="100" then
if (jumpFlag='1' and ins( 12 ) = '1') -- condition jump
or ( ins(12 downto 10) ="000" ) -- uncondition jump
or ( ins(12 downto 10) ="011" ) -- call
then
pc<=ins(17 downto 16) & ins(9 downto 0);
jumpSet<='0';
ins <= "001100000000000000";
elsif ins( 12 downto 10 ) = "010" then --Return
pc<=stack_dout;
jumpSet<='0';
ins <= "001100000000000000";
else
pc<=nextpc;
jumpSet<='1';
if jumpSet='0' then
ins <= "001100000000000000";
else
ins <= instruction;
end if;
end if;
else
pc<=nextpc;
jumpSet<='1';
if jumpSet='0' then
ins <= "001100000000000000";
else
ins <= instruction;
end if;
end if;
end if;
end process;
secondHalfProc:process(reset,clk)
begin
if reset = '1' then
CFLAG <= '0';
ZFLAG <= '0';
elsif rising_edge(clk) then
if heap_wea='1' then
if ALU_OP/="0000" then
CFLAG<=alu_cflag_out;
if alu_out="00000000" then
ZFLAG<='1';
else
ZFLAG<='0';
end if;
end if;
end if;
end if;
end process;
address<=pc;
write_strobe<=io_write_strobe_int;
out_port<=alu_A;
read_strobe<=io_read_strobe_int;
stack_din<=pc-1;
Astack: pcstack
generic map(
depth => 16,
awidth => 4,
width => 12
)
port map(
reset => reset,
clk => clk,
en => stack_en,
pop_push => stack_po_pu,
din => stack_din,
dout => stack_dout
);
jumpFlag <= (cflag xor ins(10)) when ins(11)='1' else (zflag xor ins(10));
stack_en <= '1' when ins( 15 downto 13 ) ="100" and (ins( 12 downto 11 ) = "01" ) else '0';
stack_po_pu <= '1' when ins( 10 ) = '1' else '0';
addsub_a:addsub
generic map (
width => 8
)
port map(
A=>alu_A,
B=>alu_B,
C_IN=>cflag,
C_EN=>ALU_OP(0),
C_OUT=>sum_cflag_out,
sub=>ALU_OP(1),
S=>sum_out
);
logical_a:logical
generic map (
width => 8
)
port map(
A=>alu_A,
B=>alu_B,
OP=>alu_op( 1 downto 0 ),
S=>logical_out
);
shiftl_a:shiftL
generic map (
width => 8
)
port map(
A=> alu_A,
Ci=>CFLAG,
OP=>shift_op( 2 downto 0 ),
S=> shiftl_out,
Co=>shiftl_cflag_out
);
shiftr_a:shiftR
generic map (
width => 8
)
port map(
A=> alu_A,
Ci=>CFLAG,
OP=>shift_op( 2 downto 0 ),
S=> shiftr_out,
Co=>shiftr_cflag_out
);
end fast;
| gpl-2.0 | fb7d422110a4109000ef775d5209d4a5 | 0.57674 | 2.782268 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_init_4.vhd | 2 | 14,977 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: attr_init_4.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | a81482e6e1d7352ff9ea05252f3e5863 | 0.537825 | 3.857069 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/user_logic_orig.vhd | 9 | 26,750 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal mst_reg_write_req : std_logic;
signal mst_reg_read_req : std_logic;
signal mst_reg_write_sel : std_logic_vector(0 to 3);
signal mst_reg_read_sel : std_logic_vector(0 to 3);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_ip2bus_be : std_logic_vector(0 to 15);
signal mst_go : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the PLBv46 master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the PLBv46
-- master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Busy (User Logic Master is Busy)
-- bit 2 - Error (User Logic Master request got error response)
-- bit 3 - Tmout (User Logic Master request is timeout)
-- bit 2-7 - Spare (Spare Status Bits)
-- Addrress Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - Target Address (This 32-bit value is used to populate the
-- IP2Bus_Mst_Addr(0:31) address bus during a Read or Write
-- user logic master operation)
-- Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-15 - Master BE (This 16-bit value is used to populate the
-- IP2Bus_Mst_BE byte enable bus during a Read or Write user
-- logic master operation for single data beat transfer)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-3 - Reserved
-- bit 4-15 - Transfer Length (This 12-bit value is used to populate the
-- IP2Bus_Mst_Length(0:11) transfer length bus which specifies
-- the number of bytes (1 to 4096) to transfer during user logic
-- master Read or Write fixed length burst operations)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (Write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the target address to the address register
-- 3. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 4. write 0x0004 to the length register
-- 5. write 0x0a to the go register, this will start the master write operation
--
------------------------------------------
mst_reg_write_req <= Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
mst_reg_read_req <= Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
mst_reg_write_sel <= Bus2IP_WrCE(1 to 4);
mst_reg_read_sel <= Bus2IP_RdCE(1 to 4);
mst_write_ack <= mst_reg_write_req;
mst_read_ack <= mst_reg_read_req;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2bus_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_be <= mst_reg(8) & mst_reg(9);
mst_xfer_length <= mst_reg(12)(4 to 7) & mst_reg(13);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, mst_reg_write_req, mst_reg_write_sel ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= mst_reg_write_req and
mst_reg_write_sel(byte_index/BE_WIDTH) and
Bus2IP_BE(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH);
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_cmd_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'/'error'/'timeout'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8);
mst_reg(1)(2) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+2);
mst_reg(1)(3) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+3);
else
-- 'Done'/'error'/'timeout' from master control state machine
mst_reg(1)(0) <= mst_cmd_sm_set_done or mst_reg(1)(0);
mst_reg(1)(2) <= mst_cmd_sm_set_error or mst_reg(1)(2);
mst_reg(1)(3) <= mst_cmd_sm_set_timeout or mst_reg(1)(3);
end if;
-- byte 2 and 3 are reserved
-- address register (byte 4 to 7)
-- be register (byte 8 to 9)
-- length register (byte 12 to 13)
-- byte 10, 11 and 14 are reserved
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8 to
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_cmd_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_cmd_sm_busy = '0' and mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_sel, mst_reg ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
case mst_reg_read_sel is
when "1000" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "0100" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH+byte_index);
end loop;
when "0010" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*2+byte_index);
end loop;
when "0001" =>
for byte_index in 0 to BE_WIDTH-1 loop
if ( byte_index = BE_WIDTH-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*3+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= mst_cntl_rd_req;
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr;
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be(16-C_MST_DWIDTH/8 to 15);
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- local srl fifo for data storage
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n);
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n);
DATA_CAPTURE_FIFO_I : entity proc_common_v2_00_a.srl_fifo_f
generic map
(
C_DWIDTH => C_MST_DWIDTH,
C_DEPTH => 16
)
port map
(
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
FIFO_Write => mst_fifo_valid_write_xfer,
Data_In => Bus2IP_MstRd_d,
FIFO_Read => mst_fifo_valid_read_xfer,
Data_Out => IP2Bus_MstWr_d,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
mst_ip2bus_data when mst_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | 8df908a949255ae0f2e9c65ecaede75a | 0.514654 | 3.662878 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/counter_bit.vhd | 3 | 8,843 | -------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:00 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
| bsd-3-clause | 0877c927aa7381480313db52e4ab8fca | 0.409816 | 4.931958 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/bus2ip_amux.vhd | 3 | 8,587 | -------------------------------------------------------------------------------
-- $Id: bus2ip_amux.vhd,v 1.1 2003/03/15 01:05:24 ostlerf Exp $
-------------------------------------------------------------------------------
-- bus2ip_amux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: bus2ip_amux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address Bus Output
-- multiplexer.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- bus2ip_amux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET May-9-01
-- ~~~~~~
-- First version
-- ^^^^^^
--
-- DET May-22-01
-- ~~~~~~
-- Changed architecture to reflect addr counter
-- and non-registered address outputs.
-- ^^^^^^
--
-- FO Oct-15-01
-- ~~~~~~
-- Added byte-enable channel.
-- Subsumed ipif_interrupt.vhd into this file; there is no
-- longer a wrapper.
-- ^^^^^^
--
-- FO Dec-11-01
-- ~~~~~~
-- The automatic sequential address now increments by the word size
-- in bytes instead of by one byte.
-- ^^^^^^
--
-- FO Jan-02-02
-- ~~~~~~
-- Misc cleanup and signal rename actions.
-- ^^^^^^
--
-- FO Nov-01-02
-- ~~~~~~
-- Added an XST workaround (keep attribute on signal reg_addr_plus1).
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need the unsigned functions
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity bus2ip_amux is
Generic (
C_IPIF_ABUS_WIDTH : Integer;
C_IPIF_DBUS_WIDTH : integer
);
port (
-- Clock and Reset
Bus2IP_Reset_i : in std_logic;
Bus2IP_Clk_i : in std_logic;
-- Select control from the Master Attachment
Mstr_sel_ma : in std_logic;
-- Slave Attachment I/O
Addr_Cntr_ClkEN : in std_logic;
Addr_Sel : in std_logic_vector(0 to 1);
Bus2IP_Addr_sa : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Address Bus inputs from the IP Master
IP2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Address Bus inputs from the DMA/SG engine
DMA2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- IPIF & IP address bus source (AMUX output)
Bus2IP_Addr_i : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Byte-enable channels
Bus2IP_BE_sa : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
IP2IP_BE : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
DMA2IP_BE : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
Bus2IP_BE_i : out std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1)
);
end bus2ip_amux;
architecture implementation of bus2ip_amux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
Signal selected_addr : std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
Signal reg_addr_plus1 : unsigned(0 to C_IPIF_ABUS_WIDTH-1);
Signal addr_plus1 : unsigned(0 to C_IPIF_ABUS_WIDTH-1);
Signal selected_be : std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8-1);
-------------------------
-- XST Begin Work Around, needed at least until F.28, where a fix is planned.
-------------------------
attribute KEEP : string;
attribute KEEP of reg_addr_plus1: signal is "TRUE";
-----------------------
-- XST End Work Around
-----------------------
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
Bus2IP_Addr_i <= selected_addr;
Bus2IP_BE_i <= selected_be;
-------------------------------------------------------------------------
-- This process switches the desired input address to the MUX output.
-------------------------------------------------------------------------
SELECT_THE_ADDRESSES : process (Addr_Sel, Mstr_sel_ma, Bus2IP_Addr_sa, DMA2IP_Addr,
IP2IP_Addr, reg_addr_plus1,
DMA2IP_BE, IP2IP_BE, Bus2IP_BE_sa)
Begin
Case Addr_Sel Is
When "00" => -- External Bus address Selected
selected_addr <= Bus2IP_Addr_sa;
selected_be <= Bus2IP_BE_sa;
When "01" => -- Local Master Address Selected
If (Mstr_sel_ma = '1') Then
selected_addr <= DMA2IP_Addr;
selected_be <= DMA2IP_BE;
else
selected_addr <= IP2IP_Addr;
selected_be <= IP2IP_BE;
End if;
When "10" => -- Address Register Output Plus 1 Selected
selected_addr <= std_logic_vector(reg_addr_plus1);
If (Mstr_sel_ma = '1') Then
selected_be <= DMA2IP_BE;
else
selected_be <= IP2IP_BE;
End if;
When others => -- Default to External Bus Selected
selected_addr <= Bus2IP_Addr_sa;
selected_be <= Bus2IP_BE_sa;
End case;
End process; --SELECT_THE_ADDRESSES
-------------------------------------------------------------------------
-- Combinationally increment the registered address output for
-- feedback into the select mux
-------------------------------------------------------------------------
INCREMENT_THE_ADDR : process (selected_addr)
Begin
addr_plus1 <= unsigned(selected_addr) + C_IPIF_DBUS_WIDTH/8;
End process; -- INCREMENT_THE_ADDR
-------------------------------------------------------------------------
-- Combinationally increment the registered address by the word size for
-- feedback into the select mux
-------------------------------------------------------------------------
REG_THE_ADDR_PLUS_1 : process (Bus2IP_Reset_i, Bus2IP_Clk_i)
Begin
If (Bus2IP_Reset_i = '1') Then
reg_addr_plus1 <= (others => '0');
Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Addr_Cntr_ClkEN = '1') Then
reg_addr_plus1 <= addr_plus1; -- register address+1 input
Else
null; -- Hold last address+1 registered
End if;
else
null;
End if;
End process; -- REG_THE_ADDR_PLUS_1
end implementation;
| bsd-3-clause | f3f84fe892c6af15da2b69474362753b | 0.421451 | 4.419454 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/rx_ctrl.vhd | 1 | 18,272 | --------------------------------------------------------------------------------
-- Title : RX control state machine
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-24
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- RX path state machine for Avalon ST and FIFO control
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- * rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.src_utils_pkg.all;
entity rx_ctrl is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- Hard IP
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- RX FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
sop_q_i : in std_logic;
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end entity rx_ctrl;
architecture rx_ctrl_arch of rx_ctrl is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component rx_len_cntr
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- rx_get_data
load_cntr_val_i : in std_logic_vector(9 downto 0);
-- rx_ctrl
load_cntr_i : in std_logic;
enable_cntr_i : in std_logic;
len2fifo_o : out std_logic_vector(9 downto 0)
);
end component;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
type fsm_state is (WAITING, IDLE, WRRD, CPL, ECRC_ERROR, LOAD_CNTR, FALSE_PACKET);
signal state : fsm_state;
signal int_fifo_c_en : std_logic;
signal int_fifo_wr_en : std_logic;
signal int_len2fifo_wr : std_logic_vector(9 downto 0);
signal int_len2fifo_c : std_logic_vector(9 downto 0);
signal int_enable_c_cntr : std_logic;
signal int_enable_wr_cntr : std_logic;
signal int_load_c_cntr : std_logic;
signal int_load_wr_cntr : std_logic;
signal int_c_wr : std_logic;
signal int_sop : std_logic;
signal int_false_packet : std_logic;
signal int_rxstvalid0_q : std_logic;
signal int_rxstsop0_q : std_logic;
signal int_rxsteop0_q : std_logic;
signal int_rxsteop0_qq : std_logic;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
rx_fifo_c_enable_o <= int_fifo_c_en;
rx_fifo_wr_enable_o <= int_fifo_wr_en;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
reg_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_c_wr <= '0';
int_sop <= '0';
int_false_packet <= '0';
int_rxstvalid0_q <= '0';
int_rxstsop0_q <= '0';
int_rxsteop0_q <= '0';
int_rxsteop0_qq <= '0';
elsif clk_i'event and clk_i = '1' then
int_rxstvalid0_q <= rx_st_valid0;
int_rxstsop0_q <= rx_st_sop0;
int_rxsteop0_q <= rx_st_eop0;
int_rxsteop0_qq <= int_rxsteop0_q;
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
int_sop <= '1';
elsif rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_sop <= '0';
else
int_sop <= int_sop;
end if;
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
if tlp_type_i = TYPE_IS_MEMORY or tlp_type_i = TYPE_IS_IO then
int_c_wr <= '1';
elsif tlp_type_i = TYPE_IS_CPL and tlp_fmt_i = FMT_IS_WRITE then
int_c_wr <= '0';
else
int_c_wr <= '0';
end if;
else
int_c_wr <= int_c_wr;
end if;
-----------------------------------------------------------
-- if the transfer is invalid set int_false_packet to '1'
-- invalid = all packet types except I/O wr/rd,
-- memory wr/rd or completion (not locked)
-----------------------------------------------------------
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
if (tlp_fmt_i = FMT_IS_READ and tlp_type_i = TYPE_IS_MEMORY) or
(tlp_fmt_i = FMT_IS_READ and tlp_type_i = TYPE_IS_IO) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_MEMORY) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_IO) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_CPL) then
int_false_packet <= '0';
else
int_false_packet <= '1';
end if;
elsif rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_false_packet <= '0';
end if;
end if;
end process reg_proc;
------------------------------
-- state machine transitions
------------------------------
fsm_trans : process(rst_i, clk_i)
begin
if rst_i = '1' then
state <= IDLE;
elsif clk_i'event and clk_i = '1' then
case state is
when IDLE =>
------------------------------------------------------
-- go to LOAD_CNTR if a transfer after ECRC error is
-- not finished yet or a new, valid transfer starts
-- if the transfer is invalid go to FALSE_PACKET
-- invalid => int_false_packet = '1'
------------------------------------------------------
if int_rxstvalid0_q = '0' and int_sop = '1' then
state <= LOAD_CNTR;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
if int_false_packet = '1' then
state <= FALSE_PACKET;
else
state <= LOAD_CNTR;
end if;
else
state <= IDLE;
end if;
when LOAD_CNTR =>
--------------------------------------------
-- load counter values for length counters
--------------------------------------------
if int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_c_wr = '0' then
state <= CPL;
else
state <= WRRD;
end if;
when CPL =>
---------------------------------------------------------
-- transfer completion data to the completion FIFO
-- go to ECRC_ERROR if the transfer is terminated early
-- go to WAITING if rx_st_valid0 is deasserted
-- go to IDLE if all data is transferred
---------------------------------------------------------
if int_rxsteop0_qq = '1' and int_len2fifo_c > ONE_10B then
state <= ECRC_ERROR;
elsif int_len2fifo_c > ONE_10B and int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
state <= LOAD_CNTR;
elsif (int_len2fifo_c = ONE_10B and int_rxstvalid0_q = '0') or
(int_len2fifo_c = ZERO_10B and int_rxstvalid0_q = '0' and int_rxsteop0_qq = '1') then
state <= IDLE;
else
state <= CPL;
end if;
when WRRD =>
---------------------------------------------------------
-- transfer write or read data to the wr FIFO
-- go to ECRC_ERROR if the transfer is terminated early
-- go to WAITING if rx_st_valid0 is deasserted
-- go to IDLE if all data is transferred
---------------------------------------------------------
if int_rxsteop0_qq = '1' and int_len2fifo_wr > ONE_10B then
state <= ECRC_ERROR;
elsif int_len2fifo_wr > ONE_10B and int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
state <= LOAD_CNTR;
elsif (int_len2fifo_wr = ONE_10B and int_rxstvalid0_q = '0') or
(int_len2fifo_wr = ZERO_10B and int_rxstvalid0_q = '0' and int_rxsteop0_qq = '1') then
state <= IDLE;
else
state <= WRRD;
end if;
when WAITING =>
-------------------------------------------------
-- wait until hard IP is ready to transfer data
-------------------------------------------------
if int_rxstvalid0_q = '1' then
if int_c_wr = '1' then
state <= WRRD;
else
state <= CPL;
end if;
else
state <= WAITING;
end if;
when ECRC_ERROR =>
----------------------------------------------------
-- if an ECRC error occurs the transfer may be
-- terminated early
-- in that case store dummy data to the FIFO until
-- the original transfer length is achieved
-- then go to IDLE
----------------------------------------------------
if int_c_wr = '0' and int_len2fifo_c = ONE_10B then
state <= IDLE;
elsif int_c_wr = '1' and int_len2fifo_wr = ONE_10B then
state <= IDLE;
else
state <= ECRC_ERROR;
end if;
when FALSE_PACKET =>
---------------------------------------------------------------
-- some packet types, e.g. messages, are forwarded by the
-- hard IP although the 16z091-01 core does not process them
-- in this case acknowledge the transfer but don't store
-- anything to the FIFO
---------------------------------------------------------------
if int_rxstvalid0_q = '1' and int_rxsteop0_q = '1' then
state <= IDLE;
else
state <= FALSE_PACKET;
end if;
when others =>
state <= IDLE;
assert false report "undecoded state in process fsm_trans in rx_ctrl.vhd" severity error;
end case;
end if;
end process fsm_trans;
--------------------------
-- state machine outputs
--------------------------
fsm_out : process(state, int_c_wr, int_len2fifo_c, int_len2fifo_wr)
begin
case state is
when IDLE =>
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when LOAD_CNTR =>
fifo_action_done_o <= '0';
if int_c_wr = '0' then
int_load_c_cntr <= '1';
int_load_wr_cntr <= '0';
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
else
int_load_c_cntr <= '0';
int_load_wr_cntr <= '1';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
end if;
when CPL =>
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_len2fifo_c = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when WRRD =>
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_len2fifo_wr = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when WAITING =>
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when ECRC_ERROR =>
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_c_wr = '0' then
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
else
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
end if;
if int_len2fifo_c = ONE_10B or int_len2fifo_wr = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when FALSE_PACKET =>
------------------------------------------
-- a false packet should be acknowledged
-- but not stored to the FIFO
------------------------------------------
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when others =>
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
fifo_action_done_o <= '0';
assert false report "undecoded state in process fsm_trans in rx_ctrl.vhd" severity error;
end case;
end process fsm_out;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
c_len_cntr_comp : rx_len_cntr
port map(
clk_i => clk_i,
rst_i => rst_i,
-- rx_get_data
load_cntr_val_i => len_cntr_val_i,
-- rx_ctrl
load_cntr_i => int_load_c_cntr,
enable_cntr_i => int_enable_c_cntr,
len2fifo_o => int_len2fifo_c
);
wr_len_cntr_comp : rx_len_cntr
port map(
clk_i => clk_i,
rst_i => rst_i,
-- rx_get_data
load_cntr_val_i => len_cntr_val_i,
-- rx_ctrl
load_cntr_i => int_load_wr_cntr,
enable_cntr_i => int_enable_wr_cntr,
len2fifo_o => int_len2fifo_wr
);
-------------------------------------------------------------------------------
end architecture rx_ctrl_arch;
| gpl-3.0 | 351add9bf11c5907d42e3c75f13a8bab | 0.393389 | 4.167883 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/steer_module_write.vhd | 2 | 26,663 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_write.vhd,v 1.2 2003/03/17 18:31:19 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Write - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: steer_module_write.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- steer_module_write.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 4-26-2002 -- First version
-- ^^^^^^
-- First version of steering logic module.
-- ~~~~~~
--
-- DET 8/26/2002 Initial
-- ^^^^^^
-- - Corrected a problem with the BE outputs when Decode_size = "100" and
-- the decode_size is supposed to be used.
-- ~~~~~~
--
-- BLT 11-18-2002 -- Update to version v1.00b
-- ^^^^^^
-- Updated to use ipif_common_v1_00_b, which fixed a simulation problem
-- in the ipif_steer logic
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.STEER_TYPES.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_LARGEST : integer := width of largest device (not access size)
-- attached to the IPIF
-- C_MIRROR_SIZE : integer := smallest unit of data that is mirrored
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-- Note: I have no way of knowing what the master size is for master writes
-- so smaller masters on the
-------------------------------------------------------------------------------
entity Steer_Module_Write is
generic (
C_DWIDTH_IN : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer := 32
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end entity Steer_Module_Write;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of Steer_Module_Write is
-------------------------------------------------------------------------------
-- Function max -- returns maximum of x and y
-------------------------------------------------------------------------------
function max(x : integer; y : integer) return integer is
begin
if x > y then return x;
else return y;
end if;
end function max;
-------------------------------------------------------------------------------
-- Function min -- returns minimum of x and y
-------------------------------------------------------------------------------
function min(x : integer; y : integer) return integer is
begin
if x < y then return x;
else return y;
end if;
end function min;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- returns x**y for integers x and y, y>=0
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
function Addr_Start_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Start;
end function Addr_Start_Func;
function Addr_Stop_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Stop;
end function Addr_Stop_Func;
constant Addr_Size : integer_array_type(0 to 63) :=
(1=>1,3=>1,5=>1,7=>1,9=>1,11=>1,13=>1,15=>1,
17=>1,19=>1,21=>1,23=>1,25=>1,27=>1,29=>1,31=>1,
33=>1,35=>1,37=>1,39=>1,41=>1,43=>1,45=>1,47=>1,
49=>1,51=>1,53=>1,55=>1,57=>1,59=>1,61=>1,63=>1,
2=>2,6=>2,10=>2,14=>2,18=>2,22=>2,26=>2,30=>2,
34=>2,38=>2,42=>2,46=>2,50=>2,54=>2,58=>2,62=>2,
4=>4,12=>4,20=>4,28=>4,36=>4,44=>4,52=>4,60=>4,
8=>8,24=>8,40=>8,56=>8,16=>16,48=>16,32=>32,0=>64);
constant IP_Addr_Start : integer := Addr_Start_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
constant IP_Addr_Stop : integer := Addr_Stop_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- BE_STEER_PROC: process( Decode_size ) is
-- begin
-- BE_Steer <= '0';
-- case Decode_size is
-- when "000" => BE_Steer <= '0';
-- when "001" => if C_DWIDTH_IN > 8 then BE_Steer <= '1'; end if;
-- when "010" => if C_DWIDTH_IN > 16 then BE_Steer <= '1'; end if;
-- when "011" => if C_DWIDTH_IN > 32 then BE_Steer <= '1'; end if;
-- when "100" => if C_DWIDTH_IN > 64 then BE_Steer <= '1'; end if;
-- when "101" => if C_DWIDTH_IN > 128 then BE_Steer <= '1'; end if;
-- when "110" => if C_DWIDTH_IN > 256 then BE_Steer <= '1'; end if;
-- when "111" => if C_DWIDTH_IN > 512 then BE_Steer <= '1'; end if;
-- when others => BE_Steer <= '0';
-- end case;
-- end process BE_STEER_PROC;
MUX_PROCESS: process( Data_In,Decode_size,Addr,BE_In ) is
variable factor : integer;
variable addr_loop : integer;
variable addr_integer : integer;
variable num_addr_bits : integer;
variable size : integer;
variable address : integer;
variable data_address : integer;
variable replicate_factor : integer;
variable be_addr_base : integer;
variable be_addr_right : integer;
variable be_addr_left : integer;
variable be_num_addr_bits : integer;
variable be_uses_addr : boolean;
variable be_uses_decode_size : boolean;
variable be_start_addr : integer;
variable be_stop_addr : integer;
begin
num_addr_bits := IP_Addr_Stop-IP_Addr_Start+1;
-- Set up default condition
if C_DWIDTH_IN <= C_DWIDTH_OUT then
BE_Out(0 to C_DWIDTH_OUT/8-1) <= (others => '0');
for i in 0 to C_DWIDTH_OUT/C_DWIDTH_IN-1 loop
Data_Out(i*C_DWIDTH_IN to (i+1)*C_DWIDTH_IN-1) <= Data_In;
end loop;
else
Data_Out <= Data_In(0 to C_DWIDTH_OUT-1);
BE_Out <= BE_In(0 to C_DWIDTH_OUT/8-1);
end if;
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/C_SMALLEST_OUT);
be_addr_left := log2(C_DWIDTH_OUT/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if C_DWIDTH_OUT > C_SMALLEST_OUT then
be_uses_decode_size := TRUE;
else
be_uses_decode_size := FALSE;
end if;
if be_uses_decode_size then
for k in log2(C_SMALLEST_OUT/8)+1 to log2(C_DWIDTH_OUT/8)+1 loop -- 1,2,3,4,5,6,7 6 for now
factor := pwr(2,k)/2; -- 1,2,4,8,16,32,64 number of byte lanes
if Decode_size = Conv_std_logic_vector(k,3) then
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/factor/8);
be_addr_left := log2((factor*8)/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if be_uses_addr then -- BE IS a function of address -- TESTED
for j in 0 to pwr(2,be_num_addr_bits)-1 loop
if Addr(be_start_addr to be_stop_addr) = Conv_std_logic_vector(j,be_num_addr_bits) then
address := j*pwr(2,C_AWIDTH-be_stop_addr-1); -- generate real address from j loop variable
data_address := address;
if C_DWIDTH_IN < factor*8 then
for chunk in 0 to C_DWIDTH_IN/8-1 loop
BE_Out(address+chunk) <= BE_In(chunk);
end loop;
else
for chunk in 0 to factor-1 loop
BE_Out(chunk) <= BE_In(address+chunk);
end loop;
end if;
end if;
end loop;
else -- ADDED DET 8-26-02
BE_Out <= BE_In; -- ADDED DET 8-26-02
end if;
end if;
end loop;
else -- BE_Out is not a function of Decode_Size
be_addr_base := C_AWIDTH - log2(C_DWIDTH_IN/8);
be_addr_right := log2(C_DWIDTH_IN/C_DWIDTH_OUT);
be_addr_left := log2(C_DWIDTH_OUT/C_DWIDTH_IN);
be_num_addr_bits := be_addr_left + be_addr_right;
if be_addr_right+be_addr_left = 0 then
be_uses_addr := FALSE;
else
be_uses_addr := TRUE;
be_start_addr := be_addr_base - be_addr_left;
be_stop_addr := be_addr_base + be_addr_right - 1;
end if;
if be_uses_addr then -- BE IS a function of address -- TESTED
for j in 0 to pwr(2,be_num_addr_bits)-1 loop
if Addr(be_start_addr to be_stop_addr) = Conv_std_logic_vector(j,be_num_addr_bits) then
address := j*pwr(2,C_AWIDTH-be_stop_addr-1); -- generate real address from j loop variable
data_address := address;
if C_DWIDTH_IN < C_DWIDTH_OUT then
for chunk in 0 to C_DWIDTH_IN/8-1 loop
BE_Out(address+chunk) <= BE_In(chunk);
end loop;
else
for chunk in 0 to C_DWIDTH_OUT/8-1 loop
BE_Out(chunk) <= BE_In(address+chunk);
end loop;
end if;
end if;
end loop;
else
BE_Out <= BE_In;
end if;
end if;
-- end of be logic
-- Data_Out is not a function of Decode_Size
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
if address = 0 then -- special case for address zero
size := C_DWIDTH_IN; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if C_DWIDTH_OUT >= C_DWIDTH_IN then -- peripheral is bigger than host bus
replicate_factor := C_DWIDTH_OUT/C_DWIDTH_IN;
else replicate_factor := 1;
end if;
for r in 0 to replicate_factor-1 loop
for p in 0 to (address*8)/size+1 loop -- loop only until address is covered
for m in 0 to size-1 loop -- set data to data on Data_In at "address"
if p*size+m+r*C_DWIDTH_IN < C_DWIDTH_OUT then -- stop at width of C_DWIDTH_OUT
Data_Out(p*size+m+r*C_DWIDTH_IN) <= Data_In(address*8+m);
end if;
end loop;
end loop;
end loop;
end if;
end loop;
else -- Data_Out is not a function of address
for m in 0 to C_DWIDTH_OUT-1 loop -- 0 to 3
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end process MUX_PROCESS;
end architecture IMP;
| bsd-3-clause | b1ce7e7ae39b875fc8a6cb2b455c33e3 | 0.449724 | 3.615812 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 34,238 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library fsl_v20_v2_11_a;
use fsl_v20_v2_11_a.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
C_IID_WIDTH : integer := 3;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
--interrupts_in : in std_logic_vector(0 to 2**C_IID_WIDTH-1);
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS-1);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_READ : std_logic_vector(0 to 4-1) := x"0";
constant OPCODE_WRITE : std_logic_vector(0 to 4-1) := x"1";
constant OPCODE_CLEAR : std_logic_vector(0 to 4-1) := x"2";
constant OPCODE_MANUAL_RESET : std_logic_vector(0 to 4-1) := x"3";
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal OPWrite_Request : std_logic;
signal OPRead_Request : std_logic;
signal OPClear_Request : std_logic;
signal OPManualReset_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
opwrite_begin,
opwrite_wait_4_busy,
opwrite_finish,
opread_begin,
opread_wait_4_busy,
opread_finish,
manual_reset_begin,
manual_reset_wait,
manual_reset_finish,
opclear_begin,
opclear_wait_4_busy,
opclear_finish
);
signal current_state, next_state : master_state_type := idle;
--Core Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal iid : std_logic_vector(0 to C_IID_WIDTH-1) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal core_reset, reset_sig : std_logic := '0';
-- Core Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
signal ret_out: std_logic_vector(0 to 7);
signal tid_out : std_logic_vector(0 to 7);
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
COMPONENT complete_pic
generic(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : in std_logic_vector(0 to IID_WIDTH - 1);
CMD_IN : in std_logic_vector(0 to CMD_WIDTH - 1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
-- interrupts_in : in std_logic_vector(0 to 2**IID_WIDTH - 1);
-- TODO: Fix files to handle variable number and not exactly 8!
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
-- ***************************
-- ChipScope Cores
-- ***************************
-- ChipScope signals
-- signal CONTROL0 : std_logic_vector(35 downto 0);
-- signal TRIG0 : std_logic_vector(15 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(3 downto 0);
--
-- component chipscope_icon_v1_03_a
-- PORT (
-- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
--
-- end component;
--
-- component chipscope_ila_ul_v1_02_a
-- PORT (
-- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-- CLK : IN STD_LOGIC;
-- TRIG0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
--
-- end component;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getIID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
--return "00" & addr(24 to 29);
return addr( 24 to (24+C_IID_WIDTH-1) );
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
core_reset <= reset_sig; -- or Bus2IP_Reset;
-- Instantiate the Core
internalCore: complete_pic
-- internalCore : entity plb_fsmlang_special_pic_v1_00_a.complete_pic
-- internalCore : entity complete_pic
GENERIC MAP (
IID_WIDTH => C_IID_WIDTH,
REG_SIZE => C_REG_SIZE,
CMD_WIDTH => C_CMD_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => cmd,
ack => ack,
TID_IN => tid,
IID_IN => iid,
CMD_IN => opcode,
RET_OUT => ret_out,
TID_OUT => tid_out,
interrupts_in => interrupts_in,
clock_sig => Bus2IP_Clk,
reset_sig => core_reset
);
-- ChipScope Instantiations
-- pic_icon : chipscope_icon_v1_03_a
-- port map (
-- CONTROL0 => CONTROL0);
--
-- pic_ila_ul : chipscope_ila_ul_v1_02_a
-- port map (
-- CONTROL => CONTROL0,
-- CLK => Bus2IP_Clk,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2);
--
-- TRIG0 <= FSL_S_Exists & FSL_S_Read & mst_go & mst_cmd_sm_rd_req & Bus2IP_Mst_CmdAck & Bus2IP_Mst_Cmplt & Bus2IP_Mst_Cmd_Timeout & Bus2IP_Mst_Error & FSL_Data;
-- TRIG1 <= mst_cmd_sm_ip2bus_addr;
-- TRIG2 <= interrupts_in;
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
FSL_S_Read <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
OPWrite_Request <= '0';
OPRead_Request <= '0';
OPClear_Request <= '0';
OPManualReset_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(12 to 15) is
when OPCODE_WRITE => OPWrite_Request <= '1';
when OPCODE_READ => OPRead_Request <= '1';
when OPCODE_CLEAR => OPClear_Request <= '1';
when OPCODE_MANUAL_RESET => OPManualReset_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, OPWrite_Request, OPRead_Request, OPManualReset_Request,
OPClear_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 4);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (OPWrite_Request & OPRead_Request & OPClear_Request & OPManualReset_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "10000" => next_state <= opwrite_begin; -- OPWrite
when "01000" => next_state <= opread_begin; -- OPRead
when "00100" => next_state <= opclear_begin; -- OPReadAll
when "00010" => next_state <= manual_reset_begin; -- Manual Reset
when "00001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- MANUAL_RESET: begin
----------------------------
when manual_reset_begin =>
reset_sig <= '1'; -- begin reset on cvCore
next_state <= manual_reset_wait;
when manual_reset_wait =>
if (ack = '1') then
next_state <= manual_reset_finish;
else
next_state <= manual_reset_wait;
end if;
when manual_reset_finish =>
-- Finish transaction
bus_data_out <= x"ABCDABCD";
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- MANUAL_RESET: end
----------------------------
----------------------------
-- WRITE: begin
----------------------------
when opwrite_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_WRITE;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opwrite_wait_4_busy;
else
-- Persist with request and remain
next_state <= opwrite_begin;
end if;
when opwrite_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opwrite_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_WRITE;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opwrite_wait_4_busy;
end if;
when opwrite_finish =>
-- Finish transaction
bus_data_out <= conv_std_logic_vector(conv_integer(ret_out),32);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- READ: begin
----------------------------
when opread_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_READ;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opread_wait_4_busy;
else
-- Persist with request and remain
next_state <= opread_begin;
end if;
when opread_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opread_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_READ;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opread_wait_4_busy;
end if;
when opread_finish =>
-- Finish transaction
bus_data_out <= conv_std_logic_vector(conv_integer(ret_out(7) & tid_out),32);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- CLEAR: begin
----------------------------
when opclear_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_CLEAR;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opclear_wait_4_busy;
else
-- Persist with request and remain
next_state <= opclear_begin;
end if;
when opclear_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opclear_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_CLEAR;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opclear_wait_4_busy;
end if;
when opclear_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 58d9649eda9bd9d4c8da31677a0c54ba | 0.518313 | 3.48372 | false | false | false | false |
iocoder/graduation | hardware/cpu/clkdiv.vhd | 1 | 2,575 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.cpu_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clkdiv is
Port (
CLK : in STD_LOGIC;
-- CPU interface
CLK50MHz : out STD_LOGIC := '0';
CLK25MHz : out STD_LOGIC := '0';
CLK2MHz : out STD_LOGIC := '0';
CLK1MHz : out STD_LOGIC := '0';
CACHE_EN : out STD_LOGIC := '0'
);
end entity;
architecture Behavioral of clkdiv is
signal oCLK1MHz : STD_LOGIC := '0';
signal oCLK2MHz : STD_LOGIC := '0';
signal oCLK12_5MHz : STD_LOGIC := '0';
signal oCLK6_25MHz : STD_LOGIC := '0';
signal oCLK3_150MHz : STD_LOGIC := '0';
signal oCLK1_5MHz : STD_LOGIC := '0';
signal oCLK25MHz : STD_LOGIC := '0';
signal oCLK50MHz : STD_LOGIC := '0';
signal bCLK25MHz : STD_LOGIC := '0';
signal bCLK50MHz : STD_LOGIC := '0';
attribute clock_signal : string;
attribute clock_signal of oCLK50MHz : signal is "yes";
attribute clock_signal of oCLK25MHz : signal is "yes";
signal counter1MHz : integer := 24;
signal counter2MHz : integer := 11;
signal delay : integer := 3;
begin
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
if (delay /= 0) then
delay <= delay - 1;
end if;
end if;
end process;
oCLK50MHz <= CLK when delay = 0 else '0';
CACHE_EN <= '1' when delay = 0 else '0';
process (oCLK50MHz)
begin
if ( oCLK50MHz = '1' and oCLK50MHz'event ) then
oCLK25MHz <= NOT oCLK25MHz;
end if;
if ( oCLK25MHz = '1' and oCLK25MHz'event ) then
oCLK12_5MHz <= NOT oCLK12_5MHz;
end if;
if ( oCLK12_5MHz = '1' and oCLK12_5MHz'event ) then
oCLK6_25MHz <= NOT oCLK6_25MHz;
end if;
if ( oCLK6_25MHz = '1' and oCLK6_25MHz'event ) then
oCLK3_150MHz <= NOT oCLK3_150MHz;
end if;
if ( oCLK3_150MHz = '1' and oCLK3_150MHz'event ) then
oCLK1_5MHz <= NOT oCLK1_5MHz;
end if;
if ( oCLK50MHz = '1' and oCLK50MHz'event ) then
if (counter2MHz = 11) then
oCLK2MHz <= NOT oCLK2MHz;
counter2MHz <= 0;
else
counter2MHz <= counter2MHz + 1;
end if;
end if;
if ( oCLK2MHz = '1' and oCLK2MHz'event ) then
oCLK1MHz <= NOT oCLK1MHz;
end if;
end process;
bufg0 : bufg port map(i=>oCLK50MHz, o=>bCLK50MHz);
bufg1 : bufg port map(i=>oCLK25MHz, o=>bCLK25MHz);
CLK50MHz <= bCLK50MHz;
CLK25MHz <= bCLK25MHz;
CLK2MHz <= oCLK2MHz;
CLK1MHz <= oCLK1MHz;
end Behavioral;
| gpl-3.0 | ac28451db55f3f6441a1dd2646023d41 | 0.597282 | 2.95977 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/mux_onehot.vhd | 3 | 14,095 | -------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- mux_onehot.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
-- Version: v1.02e
-- Description: Parameterizable multiplexer with one hot select lines
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
| bsd-3-clause | e1fffda8be84499f6675572b2694d646 | 0.429869 | 4.311716 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethtx_output.vhd | 1 | 15,834 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(7 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end ethtx_output;
architecture arch_ethtx_output of ethtx_output is
component crcrom
port(
addr : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async use entity WORK.fifo_async(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
-- constant INFO_LENGTH : natural := 7;
constant INFO_LENGTH : natural := 8;
signal full : std_logic;
signal ce : std_logic;
signal txd_int : std_logic_vector(3 downto 0);
signal txen_int : std_logic;
signal txd_buf : std_logic_vector(3 downto 0);
signal txen_buf : std_logic;
signal d_int : std_logic_vector(4 downto 0);
signal d_ext : std_logic_vector(4 downto 0);
signal busy : std_logic;
signal nibble_cnt : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d1 : std_logic;
signal data_ena_d2 : std_logic;
signal data_ena_d3 : std_logic;
signal data_ena_d4 : std_logic;
signal data_ena_d5 : std_logic;
signal head_ena : std_logic;
signal buff_ena : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal byte_data : std_logic_vector(7 downto 0);
signal nibble_data : std_logic_vector(3 downto 0);
signal nibble_data_buf : std_logic_vector(3 downto 0);
signal nibble_data_dly : std_logic_vector(3 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(3 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(3 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(3 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
-- p_IFG_count : process(clk, reset)
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
end if;
end process;
-- busy <= info_start or info_ena or data_start or data_ena or data_ena_d3;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d4 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_nibble_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
nibble_cnt <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif nibble_cnt = (data_length & '0') - 1 then
data_ena <= '0';
end if;
if data_start = '1' then
nibble_cnt <= (others => '0');
else
nibble_cnt <= nibble_cnt + 1;
end if;
end if;
end if;
end process;
head_ena <= '1' when data_ena = '1' and nibble_cnt < head_length & '0' else '0';
buff_ena <= '1' when data_ena = '1' and nibble_cnt >= head_length & '0' else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or (head_ena and (not nibble_cnt(0)))) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when nibble_cnt = head_length & '0' else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
-- 4 bytes dma addr --
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
--when 6 =>
--dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt = INFO_LENGTH and ce = '1' and data_length /= head_length else '0';
dma_length <= SXT(data_length, 16) - SXT(head_length, 16);
------------------------------------------------------------------------------
buff_rden <= buff_ena and (not nibble_cnt(0)) and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
end if;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
byte_data <= head_rdata when head_ena = '1' else
buff_rdata when buff_ena = '1' else
(others => '0');
p_nibble_data_buf : process(clk, reset)
begin
if reset = '1' then
nibble_data_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
nibble_data_buf <= byte_data(7 downto 4);
end if;
end if;
end process;
--local time --
p_localtime : process(reset, clk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(clk) then
if nibble_cnt = 15 then
localtime_reg <= localtime;
end if;
end if;
end process;
nibble_data <= localtime_reg(31 downto 28) when nibble_cnt = 29 and source_select = '0' else
localtime_reg(27 downto 24) when nibble_cnt = 28 and source_select = '0' else
localtime_reg(23 downto 20) when nibble_cnt = 31 and source_select = '0' else
localtime_reg(19 downto 16) when nibble_cnt = 30 and source_select = '0' else
localtime_reg(15 downto 12) when nibble_cnt = 33 and source_select = '0' else
localtime_reg(11 downto 8) when nibble_cnt = 32 and source_select = '0' else
localtime_reg(7 downto 4) when nibble_cnt = 35 and source_select = '0' else
localtime_reg(3 downto 0) when nibble_cnt = 34 and source_select = '0' else
byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
-- nibble_data <= byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
------------------------------------------------------------------------------
u_crc_rom : CRCRom
port map(
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 28);
crc_din <= (others => '0') when data_ena = '0' else
not (nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3)) when nibble_cnt < 8 else
nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3);
p_calc_crc : process(clk, reset)
begin
if reset = '1' then
crc_reg <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
crc_reg <= (others => '0');
elsif data_ena_d1 = '1' then
crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
else
crc_reg <= (crc_reg(27 downto 0) & crc_din);
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 16 -- 8
)
port map(
clk => clk,
ce => ce,
D => nibble_data,
Q => nibble_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => crc_reg(31 downto 28),
Q => crc_reg_dly(3 downto 0),
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena;
data_ena_d1 <= v1(0);
data_ena_d2 <= v2(0);
data_ena_d3 <= v3(0);
txd_int <= "0101" when data_ena = '1' and nibble_cnt < 15 else
"1101" when data_ena = '1' and nibble_cnt = 15 else
--
nibble_data_dly when data_ena_d2 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3));
txen_int <= data_ena or data_ena_d3;
------------------------------------------------------------------------------
-- u_dout_sync : fifo_async
-- generic map(
-- depth => 4,
-- awidth => 2,
-- dwidth => 5,
-- ram_type => "DIS_RAM"
-- )
-- port map(
-- reset => reset,
-- clr => '0',
-- clka => clk,
-- wea => ce,
-- dia => d_int,
-- clkb => txclk,
-- rdb => '1',
-- dob => d_ext,
-- empty => open,
-- full => full,
-- dn => open
-- );
u_dout_sync : fifo_async
generic map(
depth => 16,
awidth => 4,
dwidth => 5,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => '0',
clka => clk,
wea => ce,
dia => d_int,
clkb => txclk,
rdb => s_N_Empty_TxClk,
dob => d_ext,
empty => open,
full => full,
dn => m4_TxFIFO_DN
);
NEmpty : process( reset, clk )
begin
if ( reset = '1' ) then
s_N_Empty <= '0';
elsif ( rising_edge( clk ) ) then
if ( m4_TxFIFO_DN > "0111" ) then
s_N_Empty <= '1';
-- else
-- s_N_Empty <= '0';
end if;
end if;
end process;
NEmpty_TxClk : process( reset, txclk )
begin
if ( reset = '1' ) then
s_N_Empty_TxClk <= '0';
s_N_Empty_TxClk_D1 <= '0';
elsif ( rising_edge( txclk ) ) then
s_N_Empty_TxClk <= s_N_Empty;
s_N_Empty_TxClk_D1 <= s_N_Empty_TxClk;
end if;
end process;
d_int <= txen_int & txd_int;
txen_buf <= d_ext(4) and s_N_Empty_TxClk_D1;
txd_buf <= d_ext(3 downto 0) and ( s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 );
ce <= not full;
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
--------------------------------------------------------------
--- IFG - Inter Frame Gap generation
----------------------------------------------------------------
p_ifg_count : process(clk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
elsif rising_edge(clk) then
data_ena_d4 <= data_ena_d3;
data_ena_d5 <= data_ena_d4;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(clk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(clk) then
if data_ena_d3 = '0' and data_ena_d4 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
| gpl-2.0 | 457075cccde21f78710eca67b69f744d | 0.540104 | 2.772059 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE_READ/reg_read.vhd | 1 | 1,348 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:00 11/12/2015
-- Design Name:
-- Module Name: reg_read - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_read is
port( re_clk: in std_logic;
re_rst: in std_logic;
re_ld: in std_logic;
re_reg_in: in std_logic_vector(15 downto 0);
re_reg_out: out std_logic_vector(15 downto 0)
);
end reg_read;
architecture Behavioral of reg_read is
begin
process(re_clk, re_rst, re_ld)
begin
if (re_rst='1') then
re_reg_out <= (others=>'0');
elsif (re_clk'event and re_clk='1') then
if (re_ld='1') then
re_reg_out <= re_reg_in;
end if;
end if;
end process;
end Behavioral;
| unlicense | 577a121aa28ee8a2c0bd030e32ffca83 | 0.566024 | 3.45641 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/test_cmds.vhd | 11 | 25,702 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity test_cmds is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8;
BASE : std_logic_vector := x"75000000"
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
addr : out std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
datain : in std_logic_vector(0 to C_DWIDTH-1);
kind : out std_logic_vector(0 to 1);
owner : out std_logic_vector(0 to C_TWIDTH-1);
count : out std_logic_vector(0 to C_CWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end test_cmds;
architecture behavioral of test_cmds is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
SETID,
SETMID,
DOLOCK,
DOUNLOCK,
DOTRYLOCK,
DOSETKIND,
DOGETKIND,
DOGETCOUNT,
DOGETOWNER,
DONE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
-- Signals for stuff
signal tid : std_logic_vector(0 to C_TWIDTH-1);
signal mid : std_logic_vector(0 to C_MWIDTH-1);
signal tidn : std_logic_vector(0 to C_TWIDTH-1);
signal midn : std_logic_vector(0 to C_MWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
tid <= (others => '0');
mid <= (others => '0');
else
lock_cs <= lock_ns;
tid <= tidn;
mid <= midn;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
tidn <= tid;
midn <= mid;
case lock_cs is
when IDLE =>
if( start = '1' ) then
if( mikind = "00" ) then
lock_ns <= DOLOCK;
elsif( mikind = "01" ) then
lock_ns <= SETID;
else
lock_ns <= SETMID;
end if;
end if;
when SETID =>
tidn <= miowner;
lock_ns <= IDLE;
when SETMID =>
midn <= mutex;
lock_ns <= IDLE;
-- LOCK Command:
-- To perform a lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_lockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use when locking the mutex
-- and the 7th parameter is the mutex identifier to lock.
--
-- Thus a to generate the address to use when performing a lock operation:
-- synch_lockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_locksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the lock operation:
-- synch_locksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_LOCKSTA_CONTINUE then the lock was
-- successfully locked and the thread can continue to run. If the
-- returned status is SYNCH_LOCKSTA_BLOCK then the thread did not get
-- the lock and should not continue to run.
when DOLOCK =>
addr <= synch_lockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_locksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_LOCKSTA_CONTINUE ) then
null; -- Continue the operation of the core
else
null; -- Halt the operation of the core
end if;
lock_ns <= DOUNLOCK;
-- UNLOCK Command:
-- To perform an unlock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_unlockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use the 7th parameter is the
-- mutex identifier.
--
-- Thus a to generate the address to use when performing an unlock operation:
-- synch_unlockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_unlocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the unlock operation:
-- synch_unlocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_UNLOCKSTA_SUCCESS then the unlock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_UNLOCKSTA_ERROR then the thread did not unlock
-- the lock because some error occurred.
when DOUNLOCK =>
addr <= synch_unlockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if (synch_unlocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_UNLOCKSTA_SUCCESS ) then
null; -- Unlock operation was successful
else
null; -- Unlock operation failed because of some reason
end if;
lock_ns <= DOTRYLOCK;
-- TRYLOCK Command:
-- To perform a try lock operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_trylockcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing a try lock:
-- synch_trylockcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_trylocksta which will return information on whether the mutex
-- was successfully locked or not. This function has 6 parameters. The
-- first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the status of the trylock operation:
-- synch_trylocksta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- If the returned status is SYNCH_TRYLOCKSTA_SUCCESS then the lock was
-- successful and the thread can continue to run. If the returned
-- status is SYNCH_TRYLOCKSTA_ERROR then the thread did not get the lock
-- because the lock was already owned by another thread.
when DOTRYLOCK =>
addr<=synch_trylockcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
if( synch_trylocksta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain) =
SYNCH_TRYLOCKSTA_SUCCESS ) then
null; -- Lock was acquired
else
null; -- Lock was already owned by another thread
end if;
lock_ns <= DOSETKIND;
-- SET KIND Command:
-- To perform a kind set operation with the synchronization manager you
-- perform a write to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to set the kind of an mutex:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- Since this is a write operation no status information is returned.
when DOSETKIND =>
-- As write operation
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
lock_ns <= DOGETKIND;
-- GET KIND Command:
-- To perform a get kind operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_kindcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_kindcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_kindsta which will gets the kind. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to get the kind of a mutex:
-- synch_kindsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned from this function is one of SYNCH_FAST, SYNCH_RECURS,
-- or SYNCH_ERROR depending on the type of mutex that was returned.
when DOGETKIND =>
-- As read operations
addr <= synch_kindcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
kind <= synch_kindsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETCOUNT;
-- GET COUNT Command:
-- To perform a get count operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_countcmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_countcmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_countsta which will gets the count. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the recursive lock count of a mutex::
-- synch_countsta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the recursive lock count.
when DOGETCOUNT =>
addr <= synch_countcmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
count <= synch_countsta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DOGETOWNER;
-- GET OWNER Command:
-- To perform a get owner operation with the synchronization manager you
-- perform a read to the address generated by the function
-- synch_ownercmd. This command has 7 parameters. The first 5 parameters
-- are used to pass information on the bit widths of certain parameters
-- (this is used to support generics in the VHDL which can be used to
-- configure the number of threads/mutexes at synthesis time). The 6th
-- paramaeter if the thread identifier to use and the 7th parameter is
-- the mutex identifier.
--
-- Thus a to generate the address to use when performing the operation:
-- synch_ownercmd( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- THREAD ID, -- Thread identifier to use
-- MUTEX ID ); -- Mutex identifier to use
--
-- The results of the read operation can then be sent to the function
-- synch_ownersta which will gets the owner. This function has 6 parameters.
-- The first five parameters are the same generic parameters used in the
-- lock command. The 6th parameter is the value returned from the read
-- operation.
--
-- Thus to check the owner of a mutex::
-- synch_ownersta( BASE, -- The base addr of the synch. man.
-- DATA WIDTH, -- Number of bits for the data bus
-- MUTEX BITS, -- Number of bits for the mutex id
-- THREAD BITS, -- Number of bits for the thread id
-- COUNT BITS, -- Number of bits for the lock count
-- READ VALUE); -- Result returned by synch. man.
--
-- The value returned by this function is the owner of the mutex.
when DOGETOWNER =>
addr <= synch_ownercmd(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,tid,mid);
owner <= synch_ownersta(BASE,C_DWIDTH,C_MWIDTH,C_TWIDTH,C_CWIDTH,datain);
lock_ns <= DONE;
when DONE =>
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
| bsd-3-clause | 354e861a1142866ce9d352c06415f53e | 0.525056 | 4.892823 | false | false | false | false |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/many_devices.vhd | 1 | 2,960 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for many devices
-- Project :
---------------------------------------------------------------
-- File : manny_devices.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 08/10/17
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
-- exampel for fpga_pkg_2 usage
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: many_devices.vhd,v $
-- Revision 1.3 2008/11/21 15:16:58 FWombacher
-- changed name of the fpga_pkg to allow use together with local version
--
-- Revision 1.2 2008/10/24 16:40:00 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:18 FWombacher
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY many_devices IS
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END many_devices;
ARCHITECTURE many_devices_arch OF many_devices IS
COMPONENT cyclone_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT cyclone2_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT a3p_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT arria_gx_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
gen_cyc : IF (FPGA_FAMILY = CYCLONE) GENERATE
the_cyclone_implementation : cyclone_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_cyc2 : IF (FPGA_FAMILY = CYCLONE2) GENERATE
the_cyclone2_implementation : cyclone2_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_a3p : IF (FPGA_FAMILY = A3P) GENERATE
the_a3p_implementation : a3p_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_ariagx : IF (FPGA_FAMILY = ARRIA_GX) GENERATE
the_arria_gx_implementation : arria_gx_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
END many_devices_arch;
| gpl-3.0 | 296b58f2fcaa75b6eeb3e35d7771ca15 | 0.508784 | 4.365782 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_signal_1.vhd | 2 | 22,003 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_signal_1.c
-- NUM_THREADS = 3
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * waken_num
-- reg6 = * function
-- reg7 = * attr
-- reg8 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of waken_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 20;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_7 =>
reg7_next <= intrfc2thrd_value;
-- set i=0
reg1_next <= Z32;
next_state <= STATE_8;
when STATE_8 =>
case reg1 is
when x"00000000" => next_state <= STATE_9;
when x"00000001" => next_state <= STATE_9;
when x"00000002" => next_state <= STATE_9;
when others => next_state <= STATE_14;
end case;
-- hthread_create( &data->thread[i], data->attr, data->function, (void *) data );
when STATE_9 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000018" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_14 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
case intrfc2thrd_value is
when x"00000003" => next_state <= STATE_17;
when others => next_state <= STATE_16;
end case;
when STATE_16 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_17 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- hthread_cond_signal( data->cond );
when STATE_19 =>
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_cond_signal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_21 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- while( *(data->waken_num) == 0 ) hthread_yield();
when STATE_23 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
case intrfc2thrd_value is
when x"00000000" => next_state <= STATE_25;
when others => next_state <= STATE_26;
end case;
when STATE_25 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- retVal = *( data->waken_num )
when STATE_26 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_27;
when STATE_27 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 242f0d11797f5e5c2437beff058df29f | 0.552107 | 3.633856 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd | 2 | 14,291 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.clog2;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v1_01_a.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| bsd-3-clause | 1671dd68c5292397e657ee2178e1aecc | 0.482891 | 4.065718 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/opb_SynchManager.vhd | 2 | 37,085 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify maximum data bus width among all user logic address ranges.
constant USER_MAX_AR_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify index for first user logic address range chip select.
constant USER_AR_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_01);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_ArData : std_logic_vector(0 to USER_MAX_AR_DWIDTH-1);
signal uBus2IP_ArBE : std_logic_vector(0 to USER_MAX_AR_DWIDTH/8-1);
signal uBus2IP_ArCS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
signal uIP2Bus_ArData : std_logic_vector(0 to USER_MAX_AR_DWIDTH-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_MAX_AR_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_ArData => uBus2IP_ArData,
Bus2IP_ArBE => uBus2IP_ArBE,
Bus2IP_ArCS => uBus2IP_ArCS,
IP2Bus_ArData => uIP2Bus_ArData,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_MAX_AR_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_ArBE <= iBus2IP_BE(0 to USER_MAX_AR_DWIDTH/8-1);
uBus2IP_ArData <= iBus2IP_Data(0 to USER_MAX_AR_DWIDTH-1);
uBus2IP_ArCS <= iBus2IP_CS(USER_AR_CS_INDEX to USER_AR_CS_INDEX+USER_NUM_ADDR_RNG-1);
iIP2Bus_Data(0 to USER_MAX_AR_DWIDTH-1) <= uIP2Bus_ArData;
------------------------------------------
-- implement data mux
------------------------------------------
--data_mux_proc : process( iBus2IP_CS(USER_MASTER_CS_INDEX), uIP2Bus_Data, uIP2Bus_ArData ) is
--begin
-- iIP2Bus_Data <= (others => '0');
-- if ( iBus2IP_CS(USER_MASTER_CS_INDEX) = '1' ) then
-- iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
-- else
-- iIP2Bus_Data(0 to USER_MAX_AR_DWIDTH-1) <= uIP2Bus_ArData;
-- end if;
--end process data_mux_proc;
end imp;
| bsd-3-clause | 7d541866ddbe58e1bd5dda015075eff0 | 0.52137 | 4.038441 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/plb_hthread_reset_core.vhd | 9 | 24,727 | ------------------------------------------------------------------------------
-- plb_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_hthread_reset_core_v1_00_a;
use plb_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_hthread_reset_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause | afe7b06bb6197387d94770a9726fa8d5 | 0.457395 | 4.370272 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_arbiter.vhd | 1 | 15,148 | --------------------------------------------------------------------------------
-- Title : VME Arbiter
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_arbiter.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 10/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
-- This Unit contains the Arbiter and the Bus Arbitration Timer.
-- These Functions are
-- only enabled if the Bridge resides on a module in Slot 1 of a VMEbus system.
-- If this is the case, then after reset, the input pin 'bg3n_in' sets the
-- SYSCON bit in the SYSCTL-Register. If this bit is set wrong (external
-- Slot01-detection failed), it can be set/reset through the PowerPC-bus.
--
-- The WBB2VME core supports bus arbitration for all levels. If the location is
-- detected in slot 1, the arbitration logic is enabled and handles all requests
-- on signals vme_br[3..0] in a round-robin manner.
-- If more than one master requests the bus on the same level, the daisy-chain
-- architecture arbitrates the accesses. This results in: if a master is located
-- near to slot 1, it has the higher priority than the one which is located far
-- away from slot 1.
-- If more than one master request the bus on different levels, the arbitration
-- scheme is round-robin, which results in an equal bus occupation of the
-- masters.
-- The bus occupation is also depending on the requesters behavior and need to be
-- considered for system arbitration concepts. There are two options:
-- release-on-request and release-when-done.
--------------------------------------------------------------------------------
-- Hierarchy:
-- wbb2vme
-- vme_ctrl
-- vme_arbiter
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_arbiter.vhd,v $
-- Revision 1.3 2012/11/12 08:13:15 MMiehling
-- changed comments
--
-- Revision 1.2 2012/08/27 12:57:27 MMiehling
-- changed comments
--
-- Revision 1.1 2012/03/29 10:14:53 MMiehling
-- Initial Revision
--
-- Revision 1.6 2006/05/18 14:28:59 MMiehling
-- changed fsm to moore-type
-- arbitration failures when pci2vme is in slot1 => bugfix in deglitcher
--
-- Revision 1.5 2004/11/02 11:29:48 mmiehling
-- removed cnt from severity list
--
-- Revision 1.4 2003/12/01 10:03:46 MMiehling
-- changed arbitres
--
-- Revision 1.3 2003/06/13 10:06:29 MMiehling
-- deglitched bbsyn
--
-- Revision 1.2 2003/04/22 11:02:54 MMiehling
-- improved fsm
--
-- Revision 1.1 2003/04/01 13:04:39 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY vme_arbiter IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
bgintn : OUT std_logic_vector(3 DOWNTO 0); -- bus grant for all levels
-- vme_du
set_ato : OUT std_logic; -- if bit is set => ato bit will be set
sysc_bit : IN std_logic; -- '1' if board is in slot 1 => enables this vme arbiter
bgouten : IN std_logic; -- enables SGL and bg3out signal
-- PINs:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic
);
--
END vme_arbiter;
ARCHITECTURE vme_arbiter_arc OF vme_arbiter IS
-- TYPE arbit_states IS (idle, grant); -- SGL states
TYPE arbit_states IS (grant_0, grant_0_idle, grant_1, grant_1_idle, grant_2, grant_2_idle, grant_3, grant_3_idle); -- Round-Robin states
SIGNAL arbit_state : arbit_states;
SIGNAL br_i_n_q : std_logic_vector(3 DOWNTO 0);
SIGNAL bbsyn_degl : std_logic;
SIGNAL bg_i_n_q : std_logic_vector(3 DOWNTO 0);
SIGNAL atoresn : std_logic;
SIGNAL arbitres : std_logic;
SIGNAL ibgoutn : std_logic_vector(3 DOWNTO 0);
SIGNAL bbsyn_q : std_logic;
SIGNAL bbsyn_qq : std_logic;
SIGNAL bbsyn_qqq : std_logic;
SIGNAL cnt : std_logic_vector(10 DOWNTO 0);
BEGIN
-------------------------------------------------------------------------------
-- Synchronizing asynchronous VMEbus inputs:
-------------------------------------------------------------------------------
syncinp : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
br_i_n_q <= (OTHERS => '1');
bg_i_n_q <= (OTHERS => '1');
bbsyn_degl <= '1';
bbsyn_q <= '1';
bbsyn_qq <= '1';
bbsyn_qqq <= '1';
ELSIF clk'event AND clk = '1' THEN
br_i_n_q <= br_i_n;
bg_i_n_q <= bg_i_n;
bbsyn_q <= bbsyn_in;
bbsyn_qq <= bbsyn_q;
bbsyn_qqq <= bbsyn_qq;
-- deglitching of bus busy signal
IF bbsyn_q = '0' AND bbsyn_qq = '0' AND bbsyn_qqq = '0' THEN
bbsyn_degl <= '0';
ELSIF bbsyn_q = '1' AND bbsyn_qq = '1' AND bbsyn_qqq = '1' THEN
bbsyn_degl <= '1';
ELSE
bbsyn_degl <= bbsyn_degl;
END IF;
END IF;
END PROCESS syncinp;
-------------------------------------------------------------------------------
-- Arbiter drives bus grant daisy chain if in slot 1
-------------------------------------------------------------------------------
-- depending on activation of internal Arbiter, the bus grant signal comes
-- either from VMEbus or internal Arbiter. Selection with System Controller bit
-- the slot1 detection takes longer than this, therefore the enable signal bgouten
-- controls the startup until slot1-detection is done
bgintn <= ibgoutn WHEN sysc_bit = '1' AND bgouten = '1' ELSE -- if in slot1 => insert single level arbiter
bg_i_n_q WHEN sysc_bit = '0' AND bgouten = '1' ELSE -- if not slot1 => feed through bus grant
"1111"; -- during powerup => drive with '1' for slot1 detection logic
---------------------------------------------------------------------------------
---- The Single Level Arbiter (SGL). sysc_bit must be set for it to work.
---------------------------------------------------------------------------------
--arbit_fsm : PROCESS (clk, rst)
-- BEGIN
-- IF rst = '1' THEN
-- arbit_state <= idle;
-- ibgoutn <= "1111";
-- ELSIF clk'EVENT AND clk = '1' THEN
-- CASE arbit_state IS
-- WHEN idle =>
-- IF br_i_n_q(3) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
-- arbit_state <= grant;
-- ibgoutn <= "0111"; -- grant on level 3
-- ELSE
-- arbit_state <= idle;
-- ibgoutn <= "1111";
-- END IF;
--
-- WHEN grant =>
-- IF bbsyn_degl = '0' THEN
-- arbit_state <= idle;
-- ibgoutn <= "1111";
-- ELSE
-- arbit_state <= grant;
-- ibgoutn <= "0111"; -- grant on level 3
-- END IF;
--
-- WHEN OTHERS =>
-- arbit_state <= idle;
-- ibgoutn <= "1111";
-- END CASE;
-- END IF;
-- END PROCESS arbit_fsm;
-------------------------------------------------------------------------------
-- Round-Robin Arbiter: sysc_bit must be set for it to work.
-------------------------------------------------------------------------------
arbit_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSIF clk'EVENT AND clk = '1' THEN
CASE arbit_state IS
WHEN grant_0 =>
IF bbsyn_degl = '0' THEN -- master has occupied bus => remove grant
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSIF br_i_n_q(0) /= '0' OR arbitres = '1' THEN -- request was removed before access started or arbitration timeout occured
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSE
arbit_state <= grant_0;
ibgoutn <= "1110"; -- grant on level 0
END IF;
WHEN grant_0_idle =>
IF br_i_n_q(1) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_1;
ibgoutn <= "1101"; -- grant on level 1
ELSIF br_i_n_q(2) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_2;
ibgoutn <= "1011"; -- grant on level 2
ELSIF br_i_n_q(3) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_3;
ibgoutn <= "0111"; -- grant on level 3
ELSIF br_i_n_q(0) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_0;
ibgoutn <= "1110"; -- grant on level 0
ELSE
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
END IF;
WHEN grant_1 =>
IF bbsyn_degl = '0' THEN
arbit_state <= grant_1_idle;
ibgoutn <= "1111";
ELSIF br_i_n_q(1) /= '0' OR arbitres = '1' THEN -- request was removed before access started or arbitration timeout occured
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSE
arbit_state <= grant_1;
ibgoutn <= "1101"; -- grant on level 1
END IF;
WHEN grant_1_idle =>
IF br_i_n_q(2) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_2;
ibgoutn <= "1011"; -- grant on level 2
ELSIF br_i_n_q(3) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_3;
ibgoutn <= "0111"; -- grant on level 3
ELSIF br_i_n_q(0) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_0;
ibgoutn <= "1110"; -- grant on level 0
ELSIF br_i_n_q(1) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_1;
ibgoutn <= "1101"; -- grant on level 1
ELSE
arbit_state <= grant_1_idle;
ibgoutn <= "1111";
END IF;
WHEN grant_2 =>
IF bbsyn_degl = '0' THEN
arbit_state <= grant_2_idle;
ibgoutn <= "1111";
ELSIF br_i_n_q(2) /= '0' OR arbitres = '1' THEN -- request was removed before access started or arbitration timeout occured
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSE
arbit_state <= grant_2;
ibgoutn <= "1011"; -- grant on level 2
END IF;
WHEN grant_2_idle =>
IF br_i_n_q(3) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_3;
ibgoutn <= "0111"; -- grant on level 3
ELSIF br_i_n_q(0) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_0;
ibgoutn <= "1110"; -- grant on level 0
ELSIF br_i_n_q(1) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_1;
ibgoutn <= "1101"; -- grant on level 1
ELSIF br_i_n_q(2) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_2;
ibgoutn <= "1011"; -- grant on level 2
ELSE
arbit_state <= grant_2_idle;
ibgoutn <= "1111";
END IF;
WHEN grant_3 =>
IF bbsyn_degl = '0' THEN
arbit_state <= grant_3_idle;
ibgoutn <= "1111";
ELSIF br_i_n_q(3) /= '0' OR arbitres = '1' THEN -- request was removed before access started or arbitration timeout occured
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
ELSE
arbit_state <= grant_3;
ibgoutn <= "0111"; -- grant on level 3
END IF;
WHEN grant_3_idle =>
IF br_i_n_q(0) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_0;
ibgoutn <= "1110"; -- grant on level 0
ELSIF br_i_n_q(1) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_1;
ibgoutn <= "1101"; -- grant on level 1
ELSIF br_i_n_q(2) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_2;
ibgoutn <= "1011"; -- grant on level 2
ELSIF br_i_n_q(3) = '0' AND bbsyn_degl = '1' AND sysc_bit = '1' THEN
arbit_state <= grant_3;
ibgoutn <= "0111"; -- grant on level 3
ELSE
arbit_state <= grant_3_idle;
ibgoutn <= "1111";
END IF;
WHEN OTHERS =>
arbit_state <= grant_0_idle;
ibgoutn <= "1111";
END CASE;
END IF;
END PROCESS arbit_fsm;
-------------------------------------------------------------------------------
-- The Counters (Timers)
-------------------------------------------------------------------------------
-- Arbiter TimeOut. Works only when sysc_bit is set.
atoresn <= '0' WHEN (rst = '1' OR bbsyn_degl = '0' OR sysc_bit = '0') ELSE '1';
arbit_to : PROCESS (clk, rst, cnt)
BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF atoresn = '0' THEN
cnt <= (OTHERS => '0');
ELSIF ibgoutn /= "1111" THEN -- each time bus is granted, counting
cnt <= cnt + '1';
END IF;
END IF;
arbitres <= cnt(10);
END PROCESS arbit_to;
set_ato <= arbitres;
END vme_arbiter_arc;
| gpl-3.0 | 1c3ed2dd880175f7a2289b0219666257 | 0.484024 | 3.956124 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_arbiter_core.vhd | 3 | 24,936 | -------------------------------------------------------------------------------
-- $Id: opb_arbiter_core.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_arbiter_core.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_arbiter_core.vhd
-- Version: v1.02e
-- Description: This is the top-level design file for the OPB Arbiter core.
-- It supports 1-16 masters and both fixed and dynamic priority
-- algorithms via user-configurable parameters. The user can
-- also include support for bus parking and the OPB slave
-- interface by setting parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 07/05/05
-- ^^^^^^
-- Fixed XST issue in ipif_regonly_slave.vhd. This fixes CR211277.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
-- OPB_ARB_PKG contains the necessary constants and functions for the
-- OPB Arbiter
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
-- C_OPBADDR_WIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
--
-- output ARB_DBus -- Arbiter's data bus to OPB
-- output ARB_ErrAck -- Arbiter's error acknowledge - unused
-- output ARB_Retry -- Arbiter's retry signal - unused
-- output ARB_XferAck -- Arbiter's xfer acknowledge
-- input OPB_Clk -- Clock
-- input M_request -- Masters' request signals
-- input OPB_Abus -- OPB Address bus
-- input OPB_BE -- OPB Byte Enables
-- input OPB_buslock -- Bus lock
-- input OPB_Dbus -- OPB Data bus
-- output OPB_MGrant -- Masters' grant signals
-- input OPB_retry -- Retry
-- input OPB_RNW -- Read not Write
-- input OPB_select -- Master has control of bus
-- input OPB_seqAddr -- Sequential Address
-- output OPB_timeout -- Timeout
-- input OPB_toutSup -- Timeout suppress
-- input OPB_xferAck -- OPB xfer acknowledge
-- input OPB_Rst -- Reset
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_arbiter_core is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_NUM_MASTERS : integer := 4;
C_OPBDATA_WIDTH : integer := 32;
C_OPBADDR_WIDTH : integer := 32;
C_DYNAM_PRIORITY : boolean := False;
C_REG_GRANTS : boolean := True;
C_PARK : boolean := False;
C_PROC_INTRFCE : boolean := False;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
ARB_DBus : out std_logic_vector(0 to C_OPBDATA_WIDTH-1);
ARB_ErrAck : out std_logic;
ARB_Retry : out std_logic;
ARB_ToutSup : out std_logic;
ARB_XferAck : out std_logic;
OPB_Clk : in std_logic;
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_Abus : in std_logic_vector(0 to C_OPBADDR_WIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPBDATA_WIDTH/8-1);
OPB_buslock : in std_logic;
OPB_Dbus : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : in std_logic;
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : in std_logic;
OPB_xferAck : in std_logic;
OPB_Rst : in std_logic
);
end opb_arbiter_core;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of opb_arbiter_core is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant NUM_MID_BITS : integer := max2(1,log2(C_NUM_MASTERS));
constant PMID_START_LOC : integer := C_OPBDATA_WIDTH - NUM_MID_BITS;
constant DEV_ADDR_DECODE_WIDTH : integer :=
Addr_Bits(C_BASEADDR,C_HIGHADDR,C_OPBADDR_WIDTH);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- internal connections
signal arb2bus_data : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal arb2bus_rdack : std_logic;
signal arb2bus_wrack : std_logic;
signal arb_cycle : std_logic;
signal any_mgrant : std_logic;
signal bus2ip_data : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal bus2ip_reg_rdce : std_logic_vector(0 to C_NUM_MASTERS);
signal bus2ip_reg_wrce : std_logic_vector(0 to C_NUM_MASTERS);
signal bus_park : std_logic;
signal ctrl_reg : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal grant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal mgrant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal mgrant_n : std_logic_vector(0 to C_NUM_MASTERS-1);
signal opb_mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1);
signal opb_timeout_i : std_logic;
signal priority_IDs : std_logic_vector(0 to C_NUM_MASTERS * NUM_MID_BITS-1);
signal priority_register: std_logic_vector(0 to C_NUM_MASTERS * C_OPBDATA_WIDTH-1);
signal clk : std_logic;
signal rst : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- none
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign internal grant signals to output port
-------------------------------------------------------------------------------
OPB_MGrant <= opb_mgrant_i;
OPB_timeout <= opb_timeout_i;
-------------------------------------------------------------------------------
-- Instantiate logic as determined by parameter values. Note that the
-- OPB Arbiter will always contain a watchdog timer, regardless of the number
-- of masters on the bus or the other features specified.
-------------------------------------------------------------------------------
WATCHDOG_TIMER_I: entity opb_v20_v1_10_d.watchdog_timer
port map (
OPB_select => OPB_select,
OPB_xferAck => OPB_xferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_timeout => opb_timeout_i,
Clk => clk,
Rst => rst);
-------------------------------------------------------------------------------
-- Number of Masters
-- If the number of masters is 1, then simply assign the OPB_MGrant output of
-- the OPB Arbiter to '1'.
-------------------------------------------------------------------------------
SINGLE_MASTER_GEN: if C_NUM_MASTERS = 1 generate
opb_mgrant_i <= (others => '1');
ARB_DBus <= (others => '0');
ARB_ErrAck <= '0';
ARB_Retry <= '0';
ARB_ToutSup <= '0';
ARB_XferAck <= '0';
clk <= OPB_Clk;
rst <= OPB_Rst;
end generate SINGLE_MASTER_GEN;
-------------------------------------------------------------------------------
-- Number of Masters
-- If the number of masters is > 1, then the arbiter needs the logic components
-- define below.
-------------------------------------------------------------------------------
MULTI_MASTER_GEN: if C_NUM_MASTERS > 1 generate
---------------------------------------------------------------------------
-- CONTROL_REGISTER_LOGIC contains the control register
---------------------------------------------------------------------------
CTRLREG_I: entity opb_v20_v1_10_d.control_register_logic
generic map (C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE)
port map (
Ctrlreg_wrce => bus2ip_reg_wrce(0),
Bus2Ip_Data => bus2ip_data(0 to C_OPBDATA_WIDTH - 1),
Ctrl_reg => ctrl_reg(0 to C_OPBDATA_WIDTH - 1),
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- PRIORITY_REGISTER_LOGIC contains the priority register and update logic
---------------------------------------------------------------------------
PRIORITY_REGS_I: entity opb_v20_v1_10_d.priority_register_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY)
port map (
MGrant => mgrant(0 to C_NUM_MASTERS-1),
MGrant_n => mgrant_n(0 to C_NUM_MASTERS-1),
Bus2IP_Data => bus2ip_data(0 to C_OPBDATA_WIDTH-1),
Bus2IP_Reg_WrCE => bus2ip_reg_wrce(1 to C_NUM_MASTERS),
Dpen => ctrl_reg(DPEN_LOC),
Prv => ctrl_reg(PRV_LOC),
Priority_register => priority_register,
Priority_IDs => Priority_IDs,
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- Only instantiate the OPB Bus slave components if the design has been
-- parameterized to support a processor interface
-- Otherwise, set ports and interface signals to GND
---------------------------------------------------------------------------
OPBSLAVE_GEN: if C_PROC_INTRFCE generate
IPIF_I: entity opb_v20_v1_10_d.ipif_regonly_slave
generic map (C_OPB_ABUS_WIDTH => C_OPBADDR_WIDTH,
C_OPB_DBUS_WIDTH => C_OPBDATA_WIDTH,
C_BASEADDR => C_BASEADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_DEV_ADDR_DECODE_WIDTH => DEV_ADDR_DECODE_WIDTH)
port map (
Bus2IP_Data => bus2ip_data,
Bus2IP_Reg_RdCE => bus2ip_reg_rdce,
Bus2IP_Reg_WrCE => bus2ip_reg_wrce,
Bus2IP_Clk => clk,
Bus2IP_Reset => rst,
IP2Bus_Data => arb2bus_data,
IP2Bus_RdAck => arb2bus_rdack,
IP2Bus_WrAck => arb2bus_wrack,
OPB_ABus => OPB_Abus,
OPB_BE => OPB_BE,
OPB_Clk => OPB_Clk,
OPB_DBus => OPB_Dbus,
OPB_RNW => OPB_RNW,
OPB_Select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
Rst => OPB_Rst,
Sln_DBus => ARB_DBus,
Sln_ErrAck => ARB_ErrAck,
Sln_Retry => ARB_Retry,
Sln_ToutSup => ARB_ToutSup,
Sln_XferAck => ARB_XferAck);
ARB2BUS_DATAMUX_I: entity opb_v20_v1_10_d.arb2bus_data_mux
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_OPBDATA_WIDTH=> C_OPBDATA_WIDTH)
port map (
Bus2IP_Reg_RdCE => bus2ip_reg_rdce(0 to C_NUM_MASTERS),
Bus2IP_Reg_WrCE => bus2ip_reg_wrce(0 to C_NUM_MASTERS),
Ctrl_reg => ctrl_reg,
Priority_regs => priority_register,
Arb2bus_wrack => arb2bus_wrack,
Arb2bus_rdack => arb2bus_rdack,
Arb2bus_data => arb2bus_data);
end generate OPBSLAVE_GEN;
NO_OPBSLAVE_GEN: if not(C_PROC_INTRFCE) generate
bus2ip_data <= (others => '0');
bus2ip_reg_rdce <= (others => '0');
bus2ip_reg_wrce <= (others => '0');
ARB_DBus <= (others => '0');
ARB_ErrAck <= '0';
ARB_Retry <= '0';
ARB_ToutSup <= '0';
ARB_XferAck <= '0';
clk <= OPB_Clk;
rst <= OPB_Rst;
end generate NO_OPBSLAVE_GEN;
------------------------------------------------------------------------
-- ARBITRATION_LOGIC determines the priority level of each recieved
-- Master's request and determines the intermediate grant signal for
-- each Master.
------------------------------------------------------------------------
ARB_LOGIC_I: entity opb_v20_v1_10_d.arbitration_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_REG_GRANTS => C_REG_GRANTS)
port map (
OPB_select => OPB_select,
OPB_xferAck => OPB_xferAck,
M_request => M_request(0 to C_NUM_MASTERS-1),
Bus_park => bus_park,
Any_mgrant => any_mgrant,
OPB_buslock => OPB_buslock,
Priority_ids => Priority_IDs(0 to
C_NUM_MASTERS * NUM_MID_BITS-1),
Arb_cycle => arb_cycle,
Grant => grant(0 to C_NUM_MASTERS-1),
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- PARK_LOCK_LOGIC determines which Master has locked the bus (if any) and
-- which Master the bus should park on (if enabled). It then determines the
-- final grant signal for each Master based on the intermediate grants from
-- the arbitration logic and the park/lock status of the bus. If parking is
-- not supported, this block eliminates the park logic.
---------------------------------------------------------------------------
PARK_LOCK_I: entity opb_v20_v1_10_d.park_lock_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_PARK => C_PARK,
C_REG_GRANTS => C_REG_GRANTS)
port map (
Arb_cycle => arb_cycle,
OPB_buslock => OPB_buslock,
Park_master_notlast => ctrl_reg(PMN_LOC),
Park_master_id => ctrl_reg(PMID_START_LOC to C_OPBDATA_WIDTH-1),
Park_enable => ctrl_reg(PEN_LOC),
Grant => grant(0 to C_NUM_MASTERS-1),
M_request => M_request(0 to C_NUM_MASTERS-1),
Bus_park => bus_park,
Any_mgrant => any_mgrant,
OPB_Mgrant => opb_mgrant_i(0 to C_NUM_MASTERS-1),
Mgrant => mgrant(0 to C_NUM_MASTERS-1),
MGrant_n => mgrant_n(0 to C_NUM_MASTERS-1),
Clk => clk,
Rst => rst);
end generate MULTI_MASTER_GEN;
end implementation;
| bsd-3-clause | 13c30c0bbd2b8442d7d514c5b30c7c31 | 0.419434 | 4.764234 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/acc_vadd_hls/solution1/syn/vhdl/acc_vadd_hls.vhd | 4 | 21,156 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acc_vadd_hls is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
cmd_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
cmd_TVALID : IN STD_LOGIC;
cmd_TREADY : OUT STD_LOGIC;
resp_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
resp_TVALID : OUT STD_LOGIC;
resp_TREADY : IN STD_LOGIC;
a_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_EN_A : OUT STD_LOGIC;
a_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
a_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
a_Clk_A : OUT STD_LOGIC;
a_Rst_A : OUT STD_LOGIC;
b_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_EN_A : OUT STD_LOGIC;
b_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
b_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
b_Clk_A : OUT STD_LOGIC;
b_Rst_A : OUT STD_LOGIC;
result_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_EN_A : OUT STD_LOGIC;
result_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
result_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
result_Clk_A : OUT STD_LOGIC;
result_Rst_A : OUT STD_LOGIC );
end;
architecture behav of acc_vadd_hls is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"acc_vadd_hls,hls_ip_2014_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg900-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal grp_fu_149_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal tmp_fu_158_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal op_reg_228 : STD_LOGIC_VECTOR (31 downto 0);
signal end_reg_234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_247 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_251 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_173_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_1_reg_128_temp: signed (32-1 downto 0);
signal tmp_s_reg_258 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_fu_168_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_179_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_273 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_190_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_138_temp: signed (32-1 downto 0);
signal tmp_5_reg_280 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_185_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_196_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_295 : STD_LOGIC_VECTOR (0 downto 0);
signal i_3_fu_209_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_ioackin_resp_TREADY : STD_LOGIC;
signal i_2_fu_222_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_128 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_138 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ioackin_resp_TREADY : STD_LOGIC := '0';
signal b_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal a_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_fu_202_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal result_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
signal ap_sig_bdd_86 : BOOLEAN;
signal ap_sig_bdd_100 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_resp_TREADY assign process. --
ap_reg_ioackin_resp_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
else
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_273)) and not((not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_295)) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_295))))))) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
elsif ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_1 = resp_TREADY)) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_295)) and (ap_const_logic_1 = resp_TREADY)))) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- i_1_reg_128 assign process. --
i_1_reg_128_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_158_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_163_p2)))) then
i_1_reg_128 <= cmd_TDATA;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))))) then
i_1_reg_128 <= i_3_fu_209_p2;
end if;
end if;
end process;
-- i_reg_138 assign process. --
i_reg_138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and not((tmp_fu_158_p2 = ap_const_lv1_0)))) then
i_reg_138 <= cmd_TDATA;
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_295)))))) then
i_reg_138 <= i_2_fu_222_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st2_fsm_1 = ap_CS_fsm))) then
end_reg_234 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
op_reg_228 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_158_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_163_p2))) or ((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and not((tmp_fu_158_p2 = ap_const_lv1_0))))) then
reg_154 <= grp_fu_149_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_247) and not((ap_const_lv1_0 = tmp_2_reg_251)) and not((ap_const_lv1_0 = tmp_8_fu_168_p2)))) then
tmp_10_reg_273 <= tmp_10_fu_179_p2;
tmp_s_reg_258 <= tmp_s_fu_173_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_158_p2 = ap_const_lv1_0))) then
tmp_2_reg_251 <= tmp_2_fu_163_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_247)) and not((ap_const_lv1_0 = tmp_3_fu_185_p2)))) then
tmp_5_reg_280 <= tmp_5_fu_190_p1;
tmp_7_reg_295 <= tmp_7_fu_196_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)))) then
tmp_reg_247 <= tmp_fu_158_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (cmd_TVALID, ap_CS_fsm, tmp_reg_247, tmp_2_reg_251, tmp_8_fu_168_p2, tmp_10_reg_273, tmp_3_fu_185_p2, tmp_7_reg_295, ap_sig_ioackin_resp_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if ((((ap_const_lv1_0 = tmp_reg_247) and (ap_const_lv1_0 = tmp_2_reg_251)) or (not((ap_const_lv1_0 = tmp_reg_247)) and (ap_const_lv1_0 = tmp_3_fu_185_p2)) or ((ap_const_lv1_0 = tmp_reg_247) and (ap_const_lv1_0 = tmp_8_fu_168_p2)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif ((not((ap_const_lv1_0 = tmp_reg_247)) and not((ap_const_lv1_0 = tmp_3_fu_185_p2)))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if (not((not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_295))))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
a_Addr_A <= std_logic_vector(shift_left(unsigned(a_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- a_Addr_A_orig assign process. --
a_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_fu_173_p1, tmp_5_fu_190_p1, ap_sig_bdd_86, ap_sig_bdd_100)
begin
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
if (ap_sig_bdd_100) then
a_Addr_A_orig <= tmp_5_fu_190_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_86) then
a_Addr_A_orig <= tmp_s_fu_173_p1(32 - 1 downto 0);
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
a_Clk_A <= ap_clk;
a_Din_A <= ap_const_lv32_0;
-- a_EN_A assign process. --
a_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_247, tmp_2_reg_251, tmp_8_fu_168_p2, tmp_3_fu_185_p2)
begin
if ((((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_247) and not((ap_const_lv1_0 = tmp_2_reg_251)) and not((ap_const_lv1_0 = tmp_8_fu_168_p2))) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_247)) and not((ap_const_lv1_0 = tmp_3_fu_185_p2))))) then
a_EN_A <= ap_const_logic_1;
else
a_EN_A <= ap_const_logic_0;
end if;
end process;
a_Rst_A <= ap_rst_n;
a_WEN_A <= ap_const_lv4_0;
-- ap_sig_bdd_100 assign process. --
ap_sig_bdd_100_assign_proc : process(tmp_reg_247, tmp_3_fu_185_p2)
begin
ap_sig_bdd_100 <= (not((ap_const_lv1_0 = tmp_reg_247)) and not((ap_const_lv1_0 = tmp_3_fu_185_p2)));
end process;
-- ap_sig_bdd_86 assign process. --
ap_sig_bdd_86_assign_proc : process(tmp_reg_247, tmp_2_reg_251, tmp_8_fu_168_p2)
begin
ap_sig_bdd_86 <= ((ap_const_lv1_0 = tmp_reg_247) and not((ap_const_lv1_0 = tmp_2_reg_251)) and not((ap_const_lv1_0 = tmp_8_fu_168_p2)));
end process;
-- ap_sig_ioackin_resp_TREADY assign process. --
ap_sig_ioackin_resp_TREADY_assign_proc : process(resp_TREADY, ap_reg_ioackin_resp_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)) then
ap_sig_ioackin_resp_TREADY <= resp_TREADY;
else
ap_sig_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end process;
b_Addr_A <= std_logic_vector(shift_left(unsigned(b_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- b_Addr_A_orig assign process. --
b_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_fu_173_p1, tmp_5_fu_190_p1, ap_sig_bdd_86, ap_sig_bdd_100)
begin
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
if (ap_sig_bdd_100) then
b_Addr_A_orig <= tmp_5_fu_190_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_86) then
b_Addr_A_orig <= tmp_s_fu_173_p1(32 - 1 downto 0);
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
b_Clk_A <= ap_clk;
b_Din_A <= ap_const_lv32_0;
-- b_EN_A assign process. --
b_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_247, tmp_2_reg_251, tmp_8_fu_168_p2, tmp_3_fu_185_p2)
begin
if ((((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_247) and not((ap_const_lv1_0 = tmp_2_reg_251)) and not((ap_const_lv1_0 = tmp_8_fu_168_p2))) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_247)) and not((ap_const_lv1_0 = tmp_3_fu_185_p2))))) then
b_EN_A <= ap_const_logic_1;
else
b_EN_A <= ap_const_logic_0;
end if;
end process;
b_Rst_A <= ap_rst_n;
b_WEN_A <= ap_const_lv4_0;
-- cmd_TREADY assign process. --
cmd_TREADY_assign_proc : process(cmd_TVALID, ap_CS_fsm)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0))) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st2_fsm_1 = ap_CS_fsm)))) then
cmd_TREADY <= ap_const_logic_1;
else
cmd_TREADY <= ap_const_logic_0;
end if;
end process;
grp_fu_149_p2 <= std_logic_vector(unsigned(end_reg_234) + unsigned(ap_const_lv32_FFFFFFFF));
i_2_fu_222_p2 <= std_logic_vector(unsigned(i_reg_138) + unsigned(ap_const_lv32_1));
i_3_fu_209_p2 <= std_logic_vector(unsigned(i_1_reg_128) + unsigned(ap_const_lv32_1));
resp_TDATA <= ap_const_lv32_1;
-- resp_TVALID assign process. --
resp_TVALID_assign_proc : process(ap_CS_fsm, tmp_10_reg_273, tmp_7_reg_295, ap_reg_ioackin_resp_TREADY)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_295)) and (ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)))) then
resp_TVALID <= ap_const_logic_1;
else
resp_TVALID <= ap_const_logic_0;
end if;
end process;
result_Addr_A <= std_logic_vector(shift_left(unsigned(result_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- result_Addr_A_orig assign process. --
result_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_reg_258, tmp_5_reg_280)
begin
if ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_5_reg_280(32 - 1 downto 0);
elsif ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_s_reg_258(32 - 1 downto 0);
else
result_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
result_Clk_A <= ap_clk;
-- result_Din_A assign process. --
result_Din_A_assign_proc : process(ap_CS_fsm, tmp_9_fu_202_p2, tmp_6_fu_215_p2)
begin
if ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Din_A <= tmp_6_fu_215_p2;
elsif ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
result_Din_A <= tmp_9_fu_202_p2;
else
result_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- result_EN_A assign process. --
result_EN_A_assign_proc : process(ap_CS_fsm, tmp_10_reg_273, tmp_7_reg_295, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_295))))))) then
result_EN_A <= ap_const_logic_1;
else
result_EN_A <= ap_const_logic_0;
end if;
end process;
result_Rst_A <= ap_rst_n;
-- result_WEN_A assign process. --
result_WEN_A_assign_proc : process(ap_CS_fsm, tmp_10_reg_273, tmp_7_reg_295, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_273)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_295))))))) then
result_WEN_A <= ap_const_lv4_F;
else
result_WEN_A <= ap_const_lv4_0;
end if;
end process;
tmp_10_fu_179_p2 <= "1" when (i_1_reg_128 = reg_154) else "0";
tmp_2_fu_163_p2 <= "1" when (op_reg_228 = ap_const_lv32_2) else "0";
tmp_3_fu_185_p2 <= "1" when (signed(i_reg_138) < signed(end_reg_234)) else "0";
i_reg_138_temp <= signed(i_reg_138);
tmp_5_fu_190_p1 <= std_logic_vector(resize(i_reg_138_temp,64));
tmp_6_fu_215_p2 <= std_logic_vector(unsigned(b_Dout_A) + unsigned(a_Dout_A));
tmp_7_fu_196_p2 <= "1" when (i_reg_138 = reg_154) else "0";
tmp_8_fu_168_p2 <= "1" when (signed(i_1_reg_128) < signed(end_reg_234)) else "0";
tmp_9_fu_202_p2 <= std_logic_vector(unsigned(a_Dout_A) + unsigned(b_Dout_A));
tmp_fu_158_p2 <= "1" when (op_reg_228 = ap_const_lv32_1) else "0";
i_1_reg_128_temp <= signed(i_1_reg_128);
tmp_s_fu_173_p1 <= std_logic_vector(resize(i_1_reg_128_temp,64));
end behav;
| bsd-3-clause | b837f820f0bde93be647a147afa61938 | 0.563764 | 2.774557 | false | false | false | false |
jevinskie/aes-over-pcie | source/state_filter_in.vhd | 1 | 1,868 | -- File name: state_filter_in.vhd
-- Created: 2009-03-30
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael state filter for subblock inputs
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_filter_in is
port (
s : in state_type;
subblock : in subblock_type;
round_key : in key_type;
i : in g_index;
d_out : out slice;
filtered_key : out byte
);
end entity state_filter_in;
architecture behavioral of state_filter_in is
begin
process(i, subblock, s, round_key)
variable r, c : index;
variable i_clamped : index;
begin
-- by default output dont cares
for j in index loop
d_out(j) <= (others => '0');
end loop;
i_clamped := to_integer(to_unsigned(i, 2));
r := i_clamped;
c := i / 4;
d_out(0) <= s(r, c);
filtered_key <= round_key(r, c);
case subblock is
when sub_bytes =>
-- output the indexed byte
d_out(0) <= s(r, c);
when shift_rows =>
-- output the indexed row
for j in index loop
d_out(j) <= s(i_clamped, j);
end loop;
when mix_columns =>
-- output the indexed column
for j in index loop
d_out(j) <= s(j, i_clamped);
end loop;
when add_round_key =>
-- output the indexed byte
d_out(0) <= s(r, c);
filtered_key <= round_key(r, c);
when store_ct =>
d_out(0) <= s(r, c);
when others =>
-- dont care - already done at the top
end case;
end process;
end architecture behavioral;
| bsd-3-clause | cbb7c8bcfdf1fa625c090dc5dd57cba5 | 0.505353 | 3.648438 | false | false | false | false |
jevinskie/aes-over-pcie | source/aes_textio.vhd | 1 | 4,536 | -- File name: aes_textio.vhd
-- Created: 2009-04-06
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES textio package
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
library work;
use work.numeric_std_textio.all;
use work.aes.all;
package aes_textio is
procedure read(l : inout line; value : out state_type);
procedure read(l : inout line; value : out state_type; good : out boolean);
procedure hread(l : inout line; value : out state_type);
procedure hread(l : inout line; value : out state_type; good : out boolean);
procedure read(l : inout line; value : out slice);
procedure read(l : inout line; value : out slice; good : out boolean);
procedure hread(l : inout line; value : out slice);
procedure hread(l : inout line; value : out slice; good : out boolean);
procedure hwrite(l : inout line; value : in byte; justified : in side := right; field : in width := 0);
procedure hwrite(l : inout line; value : in state_type; justified : in side := right; field : in width := 0);
end package aes_textio;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library work;
use work.numeric_std_textio.all;
package body aes_textio is
-- state_type stuff
procedure read(l : inout line; value : out key_type) is
variable good : boolean;
begin
read(l, value, good);
assert good
report "aes_textio: read(line, key_type) failed"
severity error;
end procedure read;
procedure read(l : inout line; value : out key_type; good : out boolean) is
variable good_overall : boolean;
variable good_temp : boolean;
begin
good_overall := true;
for i in g_index loop
read(l, value(i mod 4, i / 4), good_temp);
good_overall := good_overall and good_temp;
end loop;
good := good_overall;
end procedure read;
procedure hread(l : inout line; value : out key_type) is
variable good : boolean;
begin
hread(l, value, good);
assert good
report "aes_textio: hread(line, key_type) failed"
severity error;
end procedure hread;
procedure hread(l : inout line; value : out key_type; good : out boolean) is
variable good_overall : boolean;
variable good_temp : boolean;
begin
good_overall := true;
for i in g_index loop
hread(l, value(i mod 4, i / 4), good_temp);
good_overall := good_overall and good_temp;
end loop;
good := good_overall;
end procedure hread;
-- slice stuff
procedure read(l : inout line; value : out slice) is
variable good : boolean;
begin
read(l, value, good);
assert good
report "aes_textio: read(line, slice) failed"
severity error;
end procedure read;
procedure read(l : inout line; value : out slice; good : out boolean) is
variable good_overall : boolean;
variable good_temp : boolean;
begin
good_overall := true;
for i in index loop
read(l, value(i), good_temp);
good_overall := good_overall and good_temp;
end loop;
good := good_overall;
end procedure read;
procedure hread(l : inout line; value : out slice) is
variable good : boolean;
begin
hread(l, value, good);
assert good
report "aes_textio: hread(line, slice) failed"
severity error;
end procedure hread;
procedure hread(l : inout line; value : out slice; good : out boolean) is
variable good_overall : boolean;
variable good_temp : boolean;
begin
good_overall := true;
for i in index loop
hread(l, value(i), good_temp);
good_overall := good_overall and good_temp;
end loop;
good := good_overall;
end procedure hread;
-- hwrite stuff
procedure hwrite(l : inout line; value : in byte; justified : in side := right; field : in width := 0) is
begin
hwrite(l, std_logic_vector(value), justified, field);
end procedure hwrite;
procedure hwrite(l : inout line; value : in state_type; justified : in side := right; field : in width := 0) is
begin
for i in g_index loop
hwrite(l, value(i mod 4, i / 4), justified, field);
end loop;
end procedure hwrite;
end package body aes_textio;
| bsd-3-clause | 6ede27cf6ffedd1b6e8920c2809889dc | 0.621914 | 3.814971 | false | false | false | false |
michaelmiehling/A25_VME | 16z024-01_src/Source/iram_dp_wb.vhd | 1 | 8,167 | ---------------------------------------------------------------
-- Title : Dual Ported IRAM with Wishbone Interface
-- Project : -
---------------------------------------------------------------
-- File : iram_dp_wb.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/11/05
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: iram_dp_wb.vhd,v $
-- Revision 1.3 2007/11/21 13:46:06 FLenhardt
-- Added ERR output to Wishbone interfaces
--
-- Revision 1.2 2006/01/04 15:57:18 mmiehling
-- added generic usedw_width
--
-- Revision 1.1 2005/12/15 15:38:42 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_dp_wb IS
GENERIC
(
USEDW_WIDTH : positive := 6; -- width of address vector (6 = one M4K)
SAME_CLK : boolean:= TRUE -- true: sl0_clk = sl1_clk; false: sl0_clk /= sl1_clk
);
PORT
(
rst : IN std_logic; -- global async high active reset
-- Wishbone Bus #0
sl0_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl0_stb : IN std_logic; -- request
sl0_cyc : IN std_logic; -- chip select
sl0_ack : OUT std_logic; -- acknowledge
sl0_err : OUT std_logic; -- error
sl0_we : IN std_logic; -- write=1 read=0
sl0_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl0_adr : IN std_logic_vector(31 DOWNTO 0);
sl0_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl0_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
-- Wishbone Bus #0
sl1_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl1_stb : IN std_logic; -- request
sl1_cyc : IN std_logic; -- chip select
sl1_ack : OUT std_logic; -- acknowledge
sl1_err : OUT std_logic; -- error
sl1_we : IN std_logic; -- write=1 read=0
sl1_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl1_adr : IN std_logic_vector(31 DOWNTO 0);
sl1_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl1_dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_dp_wb;
ARCHITECTURE iram_dp_wb_arch OF iram_dp_wb IS
SIGNAL sl0_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl0_ack_o_int : std_logic;
SIGNAL sl0_clk_int : std_logic;
SIGNAL sl0_write : std_logic;
SIGNAL sl1_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl1_ack_o_int : std_logic;
SIGNAL sl1_clk_int : std_logic;
SIGNAL sl1_write : std_logic;
BEGIN
-------------------------------------------------------------------------------------------
-- WB #0 Interface
sl0_ack <= sl0_ack_o_int;
sl0_err <= '0';
sl0_write <= '1' WHEN sl0_ack_o_int = '1' AND sl0_we = '1' ELSE '0';
sl0: PROCESS(rst, sl0_clk_int)
BEGIN
IF(rst = '1') THEN
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
ELSIF(sl0_clk_int'EVENT AND sl0_clk_int = '1') THEN
IF((sl0_stb = '1' AND sl0_cyc = '1') AND sl0_ack_o_int = '0') THEN
IF(sl0_we = '1') THEN
sl0_loc_be <= sl0_sel;
ELSE
sl0_loc_be <= (OTHERS => '0');
END IF;
sl0_ack_o_int <= '1';
ELSE
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl0;
-------------------------------------------------------------------------------------------
-- WB #1 Interface
sl1_ack <= sl1_ack_o_int;
sl1_err <= '0';
sl1_write <= '1' WHEN sl1_ack_o_int = '1' AND sl1_we = '1' ELSE '0';
sl1: PROCESS(rst, sl1_clk_int)
BEGIN
IF(rst = '1') THEN
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
ELSIF(sl1_clk_int'EVENT AND sl1_clk_int = '1') THEN
IF((sl1_stb = '1' AND sl1_cyc = '1') AND sl1_ack_o_int = '0') THEN
IF(sl1_we = '1') THEN
sl1_loc_be <= sl1_sel;
ELSE
sl1_loc_be <= (OTHERS => '0');
END IF;
sl1_ack_o_int <= '1';
ELSE
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl1;
-------------------------------------------------------------------------------------------
gen_2clk: IF NOT SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl1_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK1",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK1",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
power_up_uninitialized => "FALSE",
init_file => "iram.hex"
)
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
clock1 => sl1_clk,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_2clk;
gen_1clk: IF SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl0_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
ram_block_type => "M4K",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK0",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK0",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "iram.hex")
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_1clk;
END iram_dp_wb_arch;
| gpl-3.0 | 100123735cbd5a3d16bfbea59b12b050 | 0.499082 | 2.99048 | false | false | false | false |
QuickJack/logi-hard | hdl/control/ping_sensor.vhd | 2 | 6,694 | ------------------------------------------------------------------------------------
--state machine:
--1) idle: wait for the period to start the ping sensing
--2) trigger: send the 10us trigger pulse
--3) wait echo: wait for the echo high edge, if timeout_cnt reaches 50ms, restart
--4) echo count: echo rising edge received begin count, end count when echo falling edge, if timeout_cnt reaches 50ms, restart
--5) wait next: wait for timeout to reach 50ms.
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
entity ping_sensor is
generic (CLK_FREQ_NS : positive := 20);
port( clk : in std_logic;
reset: in std_logic;
--ping signals
ping_io: inout std_logic; --tristate option usage
echo_length : out std_logic_vector(15 downto 0);
ping_enable: in std_logic;
echo_done_out: out std_logic;
state_debug: out std_logic_vector(2 downto 0);
timeout: out std_logic;
busy : out std_logic
);
end ping_sensor ;
architecture Behavioral of ping_sensor is
type state_type is (idle, trigger_on, trigger_off, echo_wait, echo_cnt, echo_wait_low, wait_next); --,wait_sample_period);
signal state_reg, state_next: state_type;
--@50Mhz
constant VAL_1us :integer:= 1_000/CLK_FREQ_NS;
constant VAL_WAIT_NEXT_PING: integer := 5000; -- found that at least 170 us need on the parallax sensor.
constant VAL_10us :integer:= 10 ; --10us
constant TIMEOUT_VAL: integer := 50_000; --50ms
signal echo_reading_r: unsigned(31 downto 0);
--general purpose 1us counter used in state machine
signal cnt_us_r: unsigned(31 downto 0);
signal cnt_us_rst, cnt_us_rst_r: std_logic;
signal trigger_out_n, echo_done : std_logic ;
signal timeout_q : std_logic ;
--usec counter signals
signal end_usec, load_usec_counter : std_logic ;
signal usec_counter : std_logic_vector(31 downto 0);
--IF USING TRISTATE VALUES
signal echo_in, trigger_out: std_logic;
signal trigger_out_temp: std_logic;
signal echo_in_r: std_logic;
signal echo_in_debounced: std_logic_vector(7 downto 0);
begin
--tristate option
with state_reg select
ping_io <= '1' when trigger_on,
'Z' when echo_wait,
'Z' when echo_cnt,
'Z' when echo_wait_low,
'0' when others ;
with state_reg select
echo_in <= ping_io when echo_wait,
ping_io when echo_cnt,
'0' when others ;
-- input latch
process(clk, reset)
begin
if reset = '1' then
echo_in_r <= '0';
echo_in_debounced <= (others => '0');
elsif clk'event and clk = '1' then
echo_in_debounced(echo_in_debounced'high downto 1) <= echo_in_debounced((echo_in_debounced'high-1) downto 0);
echo_in_debounced(0) <= echo_in ;
if echo_in_debounced = 0 then
echo_in_r <= '0' ;
elsif echo_in_debounced = X"FF" then
echo_in_r <= '1';
end if ;
end if;
end process ;
--state register
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
elsif clk'event and clk = '1' then
state_reg <= state_next;
end if;
end process ;
process(state_reg, ping_enable, echo_in_r,cnt_us_r, end_usec, timeout_q)
begin
state_next <= state_reg;
case state_reg is
when idle =>
if (ping_enable = '1') then --start trigger sequence
state_next <= trigger_on;
end if;
when trigger_on =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= trigger_off;
end if;
when trigger_off =>
if (cnt_us_r >= VAL_10US and end_usec = '1') then
state_next <= echo_wait;
end if;
when echo_wait => --wait for echo to go high
if (echo_in_r = '1' and end_usec = '1') then --echo went high
state_next <= echo_cnt;
elsif timeout_q = '1' then
state_next <= wait_next;
end if;
when echo_cnt => --cnt length of echo pulse
if (echo_in_r = '0' and end_usec = '1') then --ECHO received - DONE!
state_next <= wait_next;
elsif timeout_q = '1' then --check to see if the timeout
state_next <= echo_wait_low;
end if;
when echo_wait_low => --this will wait to ensure echo has gone low, sr04 will timeout @200ms with echo high
if(echo_in_r = '0' and end_usec = '1') then
state_next <= wait_next;
end if;
when wait_next => -- wait end of timeout to start next measurement
if (cnt_us_r >= VAL_WAIT_NEXT_PING and end_usec = '1') then --putting lower values here throws wrencn in the works
state_next <= idle;
end if;
end case;
end process;
with state_reg select
state_debug <= "000" when idle,
"001" when trigger_on,
"010" when trigger_off,
"011" when echo_wait,
"100" when echo_cnt,
"101" when echo_wait_low,
"110" when others ;
cnt_us_rst <= '1' when state_reg = idle else
'1' when state_next /= state_reg else
'0';
echo_done <= '1' when state_reg = echo_cnt and echo_in_r = '0' else
'0' ;
timeout_q <= '1' when state_reg = echo_wait and cnt_us_r >= TIMEOUT_VAL else
'1' when state_reg = echo_cnt and cnt_us_r >= TIMEOUT_VAL else
'0' ;
timeout <= timeout_q ;
busy <= '0' when state_reg = idle and ping_enable = '0' else
'1' ;
-- usec counter
process(clk, reset)
begin
if reset = '1' then
cnt_us_r <= (others => '0');
elsif clk'event and clk = '1' then
if cnt_us_rst = '1' then
cnt_us_r <= (others => '0');
elsif end_usec = '1' then
cnt_us_r <= cnt_us_r + 1 ;
end if ;
end if ;
end process ;
-- main clock divider to generate usec period
process(clk, reset)
begin
if reset = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
elsif clk'event and clk = '1' then
if load_usec_counter = '1' then
usec_counter <= std_logic_vector(to_unsigned(VAL_1us-1, 32));
else
usec_counter <= usec_counter - 1 ;
end if ;
end if ;
end process ;
end_usec <= '1' when usec_counter = 0 else
'0' ;
load_usec_counter <= '1' when state_reg = idle else
end_usec;
--result latch
process(clk, reset)
begin
if reset = '1' then
echo_reading_r <= (others => '0');
elsif clk'event and clk = '1' then
if echo_done = '1' then
echo_reading_r <= cnt_us_r;
end if ;
end if ;
end process ;
--register latch the reset signal, getting glic
process(clk, reset)
begin
if reset = '1' then
cnt_us_rst_r <= '0';
elsif clk'event and clk = '1' then
cnt_us_rst_r <= cnt_us_rst ;
end if ;
end process ;
echo_length <= std_logic_vector(echo_reading_r(15 downto 0)) ;
echo_done_out <= echo_done;
end Behavioral;
| lgpl-3.0 | 10fd7bc61405cbcb78bf4f7bd90b0e07 | 0.606663 | 2.948899 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_requester.vhd | 1 | 12,131 | --------------------------------------------------------------------------------
-- Title : VMEbus Requester
-- Project : 16z002-
--------------------------------------------------------------------------------
-- File : vme_requester.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 30/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus
--------------------------------------------------------------------------------
-- Description :
--
-- The requester is used to get the busownership before a vme master access can
-- be performed. The vme_master indicates the request for bus access by
-- assertion of dwb. The requester has the job to gain the busownership by
-- assertion of bus request (brn). There are four bus request levels which can
-- be used. If the bus request gets answered by the bus grant on the same level
-- (bg[x]), the bus can be used. The usage gets indicated by asserting bus busy
-- signal until the master access gets started (AS is asserted). If the master
-- access is ongoing, the bus busy gets released and the bus ownership can
-- change to another bus participant.
--------------------------------------------------------------------------------
-- Hierarchy:
-- none
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_requester.vhd,v $
-- Revision 1.1 2012/03/29 10:14:33 MMiehling
-- Initial Revision
--
-- Revision 1.6 2006/05/18 14:29:09 MMiehling
-- corrected deglitching of bbsyn
-- corrected behaviour in state pass: not possible to use granted bus
--
-- Revision 1.5 2005/02/04 13:44:19 mmiehling
-- added fair requester bit
--
-- Revision 1.4 2003/06/13 10:06:42 MMiehling
-- deglitched bbsyn; improved bus release mechanism (dwb)
--
-- Revision 1.3 2003/04/22 11:03:04 MMiehling
-- now fsm from Ecki
--
-- Revision 1.2 2003/04/02 16:11:35 MMiehling
-- Der Requester sollte funktionieren, ist aber noch nicht ausführlich getestet worden
--
-- Revision 1.1 2003/04/01 13:04:45 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY vme_requester IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS:
-- Requesters Pins:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic;
bbsyn : OUT std_logic; -- bus busy signal
-------------------------------------------------------------------------------
-- connected with PowerPC Access
dwb : IN std_logic;
dgb : OUT std_logic;
FairReqEn : IN std_logic;
brl : IN std_logic_vector(1 DOWNTO 0); -- bus request level
-- from Arbiter:
bgintn : IN std_logic_vector(3 DOWNTO 0); -- from internal Arbiter if in Slot 1,
-- else outside from VMEbus
-- connected with master unit:
req_bit : IN std_logic; -- '0'= release on request; '1'= release when done
brel : IN std_logic -- indicates whether the bus arbitration can be released
);
END vme_requester;
ARCHITECTURE vme_requester_arc OF vme_requester IS
-- CONSTANT FairReqEn : std_logic := '1'; --for customer CARTS this bit = '0'
TYPE rstates IS (ridle, rpass, rreq, rgrant1, rgrant, rgntrel);
SIGNAL rstate : rstates;
SIGNAL bbsyn_degl : std_logic;
SIGNAL br_i_n_q : std_logic_vector(3 DOWNTO 0);
SIGNAL bbsyn_q : std_logic;
SIGNAL bbsyn_qq : std_logic;
SIGNAL bbsyn_qqq : std_logic;
SIGNAL brl_q : std_logic_vector(1 DOWNTO 0);
BEGIN
-- Synchronize asynchronous VMEbus inputs:
sync : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
br_i_n_q <= (OTHERS => '1');
bbsyn_degl <= '1';
bbsyn_q <= '1';
bbsyn_qq <= '1';
bbsyn_qqq <= '1';
brl_q <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
br_i_n_q <= br_i_n;
bbsyn_q <= bbsyn_in;
bbsyn_qq <= bbsyn_q;
bbsyn_qqq <= bbsyn_qq;
-- deglitch registers
IF bbsyn_q = '0' AND bbsyn_qq = '0' AND bbsyn_qqq = '0' THEN
bbsyn_degl <= '0';
ELSIF bbsyn_q = '1' AND bbsyn_qq = '1' AND bbsyn_qqq = '1' THEN
bbsyn_degl <= '1';
ELSE
bbsyn_degl <= bbsyn_degl;
END IF;
IF dwb = '1' THEN
brl_q <= brl; -- store in order to prevent changes during request cycle
END IF;
END IF;
END PROCESS sync;
-------------------------------------------------------------------------------
-- The vme_requester (FAIR)
-------------------------------------------------------------------------------
-- (1) This Requester does NOT release BBSY# when:
-- (a) The REQ-bit is '0' (default), which means ROR, and no one is
-- requesting the bus.
-- (b) A doubleword from/to PCI is transfered. Requester does not remove
-- BBSY# before the second run of vmeacc-FSM, even if 'brel' from
-- Internal Master Unit is asserted, or an external Master requests
-- the bus.
--
-- (2) Early busrelease is implemented (If master asserts AS# it issues 'brel',
-- then the requester removes BBSY# to allow bus-arbitration during the cycle).
-- Exceptions see (1).
-------------------------------------------------------------------------------
req : PROCESS(clk, rst)
BEGIN
IF (rst = '1') THEN
rstate <= ridle;
br_o_n <= (OTHERS => '1');
bg_o_n <= (OTHERS => '1');
bbsyn <= '1';
dgb <= '0';
ELSIF (clk'event AND clk = '1') THEN
CASE rstate IS
-- wait for internal bus request; pass grants of other requests on daisy-chain
WHEN ridle =>
br_o_n <= (OTHERS => '1');
bbsyn <= '1';
dgb <= '0';
IF bgintn /= "1111" THEN -- is there any grant active which is not for me
rstate <= rpass;
bg_o_n <= bgintn; -- pass all grants because no request from here
ELSIF dwb = '1' AND FairReqEn = '0' THEN -- NO FAIR: request bus independent on other request on same level
rstate <= rreq;
bg_o_n <= (OTHERS => '1'); -- pass no grant
ELSIF dwb = '1' AND br_i_n_q(to_integer(unsigned(brl_q))) = '1' AND FairReqEn = '1' THEN --FAIR: request bus if no other request is pending
rstate <= rreq;
bg_o_n <= (OTHERS => '1'); -- pass no grant
ELSE
rstate <= ridle;
bg_o_n <= (OTHERS => '1'); -- pass no grant
END IF;
WHEN rpass =>
br_o_n <= (OTHERS => '1');
bbsyn <= '1';
dgb <= '0';
IF bgintn /= "1111" THEN -- is there any grant active which is not for me
rstate <= rpass;
bg_o_n <= bgintn; -- pass all grants because no request from here
ELSE
rstate <= ridle;
bg_o_n <= (OTHERS => '1'); -- deactivate bus grant signals
END IF;
-- assert request and wait until grant gets received on daisy-chain
WHEN rreq =>
br_o_n(to_integer(unsigned(brl_q))) <= '0'; -- assert request
bbsyn <= '1';
dgb <= '0';
IF bgintn(to_integer(unsigned(brl_q))) = '0' AND bbsyn_degl = '1' THEN -- is there a grant and last access finished?
rstate <= rgrant1;
bg_o_n <= (OTHERS => '1'); -- if reqest was granted, do not pass grant to others
ELSE
rstate <= rreq;
bg_o_n <= bgintn; -- pass all grants because no request from here
END IF;
-- keep bus request and activate bus busy signal; wait until stable bus busy
WHEN rgrant1 =>
br_o_n(to_integer(unsigned(brl_q))) <= '0'; -- assert request
bg_o_n <= (OTHERS => '1');
bbsyn <= '0'; -- assert bus busy
dgb <= '0';
IF bbsyn_degl = '0' THEN -- readback: is bus busy asserted on the bus?
rstate <= rgrant;
ELSE
rstate <= rgrant1;
END IF;
-- remove request, keep bus busy and trigger master to do access
WHEN rgrant =>
br_o_n <= (OTHERS => '1'); -- remove request now
bg_o_n <= (OTHERS => '1');
bbsyn <= '0'; -- assert bus busy
IF (brel = '1' AND req_bit = '1') OR -- release when done; supports Early bus release feature
(brel = '1' AND br_i_n_q /= "1111" AND req_bit = '0' AND dwb = '0') THEN -- release on request; supports Early bus release feature
rstate <= rgntrel;
dgb <= '0'; -- indicate to master that bus is occupied
ELSE
rstate <= rgrant;
dgb <= '1'; -- indicate to master that bus is ready for access
END IF;
-- master indicates 'access finished'; wait for removal of bus grant on daisy-chain before bus busy removal
-- BBSY# MUST NOT be removed until bus grant from Arbiter is removed
WHEN rgntrel => -- wait until arbiter removes grant
br_o_n <= (OTHERS => '1');
bg_o_n <= (OTHERS => '1');
dgb <= '0';
IF bgintn(to_integer(unsigned(brl_q))) = '1' THEN
rstate <= ridle;
bbsyn <= '1'; -- release bus busy
ELSE
rstate <= rgntrel;
bbsyn <= '0'; -- must be kept asserted til bg(x) is released!
END IF;
WHEN OTHERS =>
br_o_n <= (OTHERS => '1');
bg_o_n <= (OTHERS => '1');
bbsyn <= '1';
dgb <= '0';
rstate <= ridle;
ASSERT false REPORT "OOOPS Undecoded State .." SEVERITY warning;
END CASE;
END IF;
END PROCESS req;
END vme_requester_arc;
| gpl-3.0 | 6cb7799bf100cdd5f1afd469794423da | 0.472838 | 4.382587 | false | false | false | false |
QuickJack/logi-hard | hdl/control/mcp3002_interface.vhd | 2 | 7,395 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:47:08 08/26/2013
-- Design Name:
-- Module Name: mcp3002_interface - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.utils_pack.all ;
entity mcp3002_interface is
generic(CLK_DIV : positive := 1024;
SAMPLING_DIV : positive := 2048);
port(
clk, resetn : std_logic ;
sample : out std_logic_vector(9 downto 0);
dv : out std_logic ;
chan : in std_logic ;
-- spi signals
DOUT : out std_logic ;
DIN : in std_logic ;
SCLK : out std_logic ;
SSN : out std_logic
);
end mcp3002_interface;
architecture Behavioral of mcp3002_interface is
type tranfer_state is (WAIT_SAMPLE, ASSERT_CS, XFER_DATA, DEASSERT_CS);
signal current_transfer_state, next_transfer_state : tranfer_state;
signal data_out_shift_reg, data_in_shift_reg : std_logic_vector(15 downto 0) ;
signal load_shift_register : std_logic ;
signal tempo_val : std_logic_vector(15 downto 0);
signal count_tempo : std_logic_vector(15 downto 0 );
signal load_tempo, en_tempo, end_tempo : std_logic ;
signal data_clk, data_clk_old, data_clk_re, data_clk_fe : std_logic ;
signal en_bit_count, reset_bit_count : std_logic ;
signal bit_count : std_logic_vector(4 downto 0);
signal bit_count_eq_16 : std_logic ;
signal cmd_word : std_logic_vector(15 downto 0);
signal ssn_d : std_logic ;
begin
-- tempo
process(clk, resetn)
begin
if resetn = '0' then
count_tempo <= (others => '1');
elsif clk'event and clk = '1' then
if load_tempo = '1' then
count_tempo <= tempo_val ;
elsif en_tempo = '1' then
if count_tempo /= 0 then
count_tempo <= count_tempo - 1 ;
end if ;
end if ;
end if ;
end process ;
end_tempo <= '1' when count_tempo = 0 else
'0' ;
-- bit counter
process(clk, resetn)
begin
if resetn = '0' then
bit_count <= (others => '0');
elsif clk'event and clk = '1' then
if reset_bit_count = '1' then
bit_count <= (others => '0');
elsif en_bit_count = '1' then
bit_count <= bit_count + 1 ;
end if ;
end if ;
end process ;
bit_count_eq_16 <= '1' when bit_count = 16 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
current_transfer_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
current_transfer_state <= next_transfer_state;
end if ;
end process ;
process(bit_count, end_tempo)
begin
next_transfer_state <= current_transfer_state ;
case current_transfer_state is
when wait_sample =>
if end_tempo = '1' then
next_transfer_state <= assert_cs ;
end if ;
when assert_cs =>
if end_tempo = '1' then
next_transfer_state <= xfer_data ;
end if ;
when xfer_data =>
if bit_count = 16 then
next_transfer_state <= deassert_cs ;
end if ;
when deassert_cs =>
if end_tempo = '1' then
next_transfer_state <= wait_sample ;
end if ;
when others =>
next_transfer_state <= wait_sample ;
end case;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_clk <= '0' ;
elsif clk'event and clk = '1' then
if current_transfer_state = xfer_data then
if end_tempo = '1' then
data_clk <= not data_clk ;
end if ;
else
data_clk <= '0' ;
end if ;
end if ;
end process ;
-- data clock rising edge and falling edge detect
process(clk, resetn)
begin
if resetn = '0' then
data_clk_old <= '0' ;
elsif clk'event and clk = '1' then
data_clk_old <= data_clk ;
end if ;
end process ;
data_clk_re <= data_clk and (not data_clk_old);
data_clk_fe <= (not data_clk) and data_clk_old;
cmd_word <= "10" & chan & "0" & X"000" ;
--shift register for data out
process(clk, resetn)
begin
if resetn = '0' then
data_out_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if load_shift_register = '1' then
data_out_shift_reg <= cmd_word ;
elsif data_clk_fe = '1' then
data_out_shift_reg(15 downto 1) <= data_out_shift_reg(14 downto 0) ;
data_out_shift_reg(0) <= '0' ;
end if ;
end if ;
end process ;
--shift register for data in
process(clk, resetn)
begin
if resetn = '0' then
data_in_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if data_clk_re = '1' then
data_in_shift_reg(15 downto 1) <= data_in_shift_reg(14 downto 0) ;
data_in_shift_reg(0) <= DIN ;
end if ;
end if ;
end process ;
with current_transfer_state select
load_shift_register <= end_tempo when assert_cs,
'0' when others ;
en_tempo <= '1' ;
with current_transfer_state select
tempo_val <= std_logic_vector(to_unsigned(CLK_DIV, 16)) when wait_sample,
std_logic_vector(to_unsigned(CLK_DIV, 16)) when assert_cs,
std_logic_vector(to_unsigned(CLK_DIV, 16)) when xfer_data,
std_logic_vector(to_unsigned(SAMPLING_DIV, 16)) when deassert_cs,
(others => '0') when others ;
with current_transfer_state select
load_tempo <= end_tempo when wait_sample,
end_tempo when assert_cs,
end_tempo when xfer_data,
end_tempo when deassert_cs,
'0' when others ;
with current_transfer_state select
en_bit_count <= data_clk_fe when xfer_data,
'0' when others ;
with current_transfer_state select
reset_bit_count <= bit_count_eq_16 when xfer_data,
'1' when others ;
-- outputs
with current_transfer_state select
ssn_d <= '0' when assert_cs,
'0' when xfer_data,
'1' when others ;
sample <= data_in_shift_reg(9 downto 0);
dv <= '1' when current_transfer_state=xfer_data and bit_count_eq_16= '1' else
'0' ;
-- todo may delete following stuf, output are not combinatorial ...
process(clk, resetn)
begin
if resetn = '0' then
DOUT <= '0' ;
SCLK <= '0' ;
SSN <= '1' ;
elsif clk'event and clk = '1' then
DOUT <= data_out_shift_reg(15) ;
SCLK <= data_clk ;
SSN <= ssn_d ;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 | 75998a6d9fca4c3ffda0484e823fe5ca | 0.627586 | 3.148148 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu2_f.vhd | 2 | 17,083 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu2_f.vhd,v 1.1.4.50 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu2_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu2_f.vhd
--
-- See the end of the Description for information on
-- the small differences to srl_fifo_rbu_f, from.
-- which srl_fifo_rbu2_f is derived.
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- - srl_fifo_rbu2_f has two differences from srl_fifo_rbu_f.
-- - srl_fifo_rbu_f could not be parameterized to a C_DEPTH
-- of one because a targeted synthesis tool could not
-- handle some null cases. A couple of minor workarounds
-- were put into place to get past this restriction.
-- - srl_fifo_rbu2_f brings out signals Addr_p1 and
-- FIFO_empty_p1, which are the values that will be
-- captured as Addr and FIFO_Empty on the next clock.
-- These can be helpful in balancing timing paths
-- in some cases where custom fifo flags such as Almost
-- Empty are used by deep downstream logic.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu2_f.vhd
-- dynshreg2_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 04/24/09 First Version. Derived from srl_fifo_rbu_f.
-- ~~~~~~
-- FLO YYY-MM-DD
-- ^^^^^^
-- History comment.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity srl_fifo_rbu2_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic;
FIFO_Empty_p1 : out std_logic;
Addr_p1 : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_rbu2_f;
architecture imp of srl_fifo_rbu2_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
FIFO_Empty_p1 <= addr_i_p1(ADDR_BITS);
Addr_p1(0 to ADDR_BITS-1) <= addr_i_p1(ADDR_BITS-1 downto 0);
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v3_00_a.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v3_00_a.dynshreg2_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or('0' & Num_To_Reread)='1') and
-- The concatenated '0' in the bitwise_or argument is
-- a workaround for XST for the C_DEPTH=1 case.
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
| bsd-3-clause | 56379178c2fe8628260c935385d62f88 | 0.451736 | 4.928736 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/init.vhd | 1 | 8,159 | --------------------------------------------------------------------------------
-- Title : init module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : init.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 13.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module collects information from the config space provided by the hard
-- IP core and presents it to the 16z091-01 design
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- * init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity init is
port(
core_clk : in std_logic; -- synchronous to core_clk from hard IP core
clk : in std_logic;
rst : in std_logic;
-- IP core
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
-- interrupt module
cfg_msicsr : out std_logic_vector(15 downto 0);
-- Tx Module
bus_dev_func : out std_logic_vector(15 downto 0);
max_read : out std_logic_vector(2 downto 0);
max_payload : out std_logic_vector(2 downto 0)
);
end entity init;
-- ****************************************************************************
architecture init_arch of init is
-- internal signals -----------------------------------------------------------
signal data : std_logic_vector(15 downto 0);
signal data_q : std_logic_vector(15 downto 0);
signal data_qq : std_logic_vector(15 downto 0);
signal ctl_max : std_logic;
signal ctl_bus : std_logic;
signal ctl_msi : std_logic;
signal ctl_max_q : std_logic;
signal ctl_max_qq : std_logic;
signal ctl_max_qqq : std_logic;
signal ctl_bus_q : std_logic;
signal ctl_bus_qq : std_logic;
signal ctl_bus_qqq : std_logic;
signal ctl_msi_q : std_logic;
signal ctl_msi_qq : std_logic;
signal ctl_msi_qqq : std_logic;
signal bus_dev_func_int : std_logic_vector(15 downto 0);
signal max_read_int : std_logic_vector(2 downto 0);
signal max_payload_int : std_logic_vector(2 downto 0);
signal cfg_msicsr_int : std_logic_vector(15 downto 0);
signal sample : std_logic;
signal get_sample : std_logic;
signal tl_cfg_ctl_wr_q : std_logic;
-------------------------------------------------------------------------------
begin
cfg_get_info : process(rst, core_clk)
begin
if(rst = '1') then
data <= (others => '0');
ctl_max <= '0';
ctl_bus <= '0';
sample <= '0';
tl_cfg_ctl_wr_q <= '0';
elsif(core_clk'event and core_clk = '1') then
tl_cfg_ctl_wr_q <= tl_cfg_ctl_wr;
if(((tl_cfg_ctl_wr = '1' and tl_cfg_ctl_wr_q = '0') or (tl_cfg_ctl_wr = '0' and tl_cfg_ctl_wr_q = '1'))
and (tl_cfg_add = x"0" or tl_cfg_add = x"D" or tl_cfg_add = x"F") ) then
sample <= '1';
elsif(sample = '1') then
sample <= '0';
end if;
-- store values due to appropriate tl_cfg cycle represented by tl_cfg_add
-- if(tl_cfg_add = x"0") then
if(tl_cfg_add = x"0" and sample = '1') then
ctl_max <= '1';
data <= tl_cfg_ctl(31 downto 16);
elsif(tl_cfg_add /= x"0") then
ctl_max <= '0';
end if;
-- if(tl_cfg_add = x"D") then
if(tl_cfg_add = x"D" and sample = '1') then
ctl_msi <= '1';
data <= tl_cfg_ctl(15 downto 0);
elsif(tl_cfg_add /= x"D") then
ctl_msi <= '0';
end if;
-- if(tl_cfg_add = x"F") then
if(tl_cfg_add = x"F" and sample = '1') then
ctl_bus <= '1';
data <= tl_cfg_ctl(15 downto 0);
elsif(tl_cfg_add /= x"F") then
ctl_bus <= '0';
end if;
end if;
end process cfg_get_info;
-------------------------------------------------------------------------------
cfg_put_info : process(rst, clk)
begin
if(rst = '1') then
bus_dev_func <= (others => '0');
max_read <= (others => '0');
max_payload <= (others => '0');
cfg_msicsr <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
ctl_max_q <= '0';
ctl_max_qq <= '0';
ctl_max_qqq <= '0';
ctl_bus_q <= '0';
ctl_bus_qq <= '0';
ctl_bus_qqq <= '0';
ctl_msi_q <= '0';
ctl_msi_qq <= '0';
ctl_msi_qqq <= '0';
get_sample <= '0';
elsif(clk'event and clk = '1') then
data_q <= data;
data_qq <= data_q;
ctl_max_q <= ctl_max;
ctl_max_qq <= ctl_max_q;
ctl_max_qqq <= ctl_max_qq;
ctl_bus_q <= ctl_bus;
ctl_bus_qq <= ctl_bus_q;
ctl_bus_qqq <= ctl_bus_qq;
ctl_msi_q <= ctl_msi;
ctl_msi_qq <= ctl_msi_q;
ctl_msi_qqq <= ctl_msi_qq;
if((ctl_max_qq = '1' and ctl_max_qqq = '0') or (ctl_bus_qq = '1' and ctl_bus_qqq = '0') or (ctl_msi_qq = '1' and ctl_msi_qqq = '0')
) then
get_sample <= '1';
elsif(get_sample = '1') then
get_sample <= '0';
end if;
-- propagate stored values to the other clock domain modules
if(ctl_max_qq = '1' and get_sample = '1') then
max_payload <= data_qq(7 downto 5);
max_read <= data_qq(14 downto 12);
end if;
-- hard IP stores bus and device number but for PCIe packets, the function number must be included
-- thus shift function number = 000 into signal
if(ctl_bus_qq = '1' and get_sample = '1') then
bus_dev_func <= data_qq(12 downto 0) & "000";
end if;
if(ctl_msi_qq = '1' and get_sample = '1') then
cfg_msicsr <= data_qq(15 downto 0);
end if;
end if;
end process cfg_put_info;
-------------------------------------------------------------------------------
end architecture init_arch;
| gpl-3.0 | b66e4730fd19c4f7af671538d0b3316b | 0.449565 | 3.758176 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/addsub.vhd | 1 | 1,026 | library ieee;
use ieee.std_logic_1164.all;
ENTITY addsub IS
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
C_IN: IN std_logic;
C_EN: IN std_logic;
C_OUT: OUT std_logic;
sub: IN std_logic;
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END addsub;
ARCHITECTURE behavior OF addsub IS
component ADDC is
generic (
width : integer
);
port(
opa: in std_logic_vector(width-1 downto 0);
opb: in std_logic_vector(width-1 downto 0);
ci: in std_logic;
sum: out std_logic_vector(width-1 downto 0);
co: out std_logic
);
end component;
signal B_int : std_logic_vector( width-1 downto 0 ):=(others=>'0');
signal ci,co : std_logic:='0';
begin
B_int<=B when sub='0' else (not B);
ci<=(C_In and C_EN) xor sub;
C_out<=co xor sub;
ADDC_a : ADDC
generic map (
width => width )
port map (
opa => A,
opb => B_int,
Ci => ci,
co => co,
sum => S
);
end behavior;
| gpl-2.0 | d95cfa7473ca1166f6052253bb545796 | 0.598441 | 2.584383 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_wb_if_arbiter.vhd | 1 | 9,810 | ---------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
---------------------------------------------------------------
-- File : z126_01_wb_if_arbiter.vhd
-- Author : ....
-- Email : ....
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created :
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : Quartus II
---------------------------------------------------------------
-- Description :
-- Master # 0 1
-- Slave : 0 1 1
-- Master 0 = 1 connection(s)
-- Master 1 = 1 connection(s)
-- Slave 0 = 2 connection(s)
--
-- This module is derived from the 16z100-
-- It contaions an additional arbitration of control
-- signals for the z126_01_wb2pasmi.vhd module in the 16z126-01
-- design.
---------------------------------------------------------------
-- Hierarchy:
--
-- z126_01_wb_pkg.vhd
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_if_arbiter.vhd,v $
-- Revision 1.1 2014/03/03 17:49:57 AGeissler
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.z126_01_pkg.ALL;
USE work.z126_01_wb_pkg.ALL;
ENTITY z126_01_wb_if_arbiter IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- master 0 interface
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic;
-- wb2pasmi master 0 control signals
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
-- master 1 interface
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic;
-- wb2pasmi master 1 control signals
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
-- slave 0 interface
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
-- wb2pasmi slave 0 control signals
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END z126_01_wb_if_arbiter;
ARCHITECTURE z126_01_wb_if_arbiter_arch OF z126_01_wb_if_arbiter IS
-- COMPONENT DECLARATIONS
COMPONENT z126_01_switch_fab_2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic;
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END COMPONENT;
-- synthesis translate_off
COMPONENT z126_01_wbmon IS
GENERIC (
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
bte : IN std_logic_vector(1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic
);
END COMPONENT;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL wbs_0_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_0_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmo_1_cyc_s : std_logic;
BEGIN
wbsi_0 <= wbsi_0_int;
wbsi_0_cyc <= wbsi_0_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
-- no data multiplexer for master #0 is needed, because of connection to one slave only
wbmi_0_int.dat <= wbso_0.dat;
wbmi_0_int.ack <= wbs_0_ack(0);
wbmi_0_int.err <= wbs_0_err(0);
-- no data multiplexer for master #1 is needed, because of connection to one slave only
wbmi_1_int.dat <= wbso_0.dat;
wbmi_1_int.ack <= wbs_0_ack(1);
wbmi_1_int.err <= wbs_0_err(1);
-- sf for slave #0:
sf_0: z126_01_switch_fab_2
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc,
ack_0 => wbs_0_ack(0),
err_0 => wbs_0_err(0),
wbo_1 => wbmo_1,
cyc_1 => wbmo_1_cyc,
ack_1 => wbs_0_ack(1),
err_1 => wbs_0_err(1),
-- slave bus:
wbo_slave => wbso_0,
wbi_slave => wbsi_0_int,
wbi_slave_cyc => wbsi_0_cyc_int,
-- wb2pasmi control signals
ctrlmo_0 => ctrlmo_0,
ctrlmi_0 => ctrlmi_0,
ctrlmo_1 => ctrlmo_1,
ctrlmi_1 => ctrlmi_1,
ctrlso_0 => ctrlso_0,
ctrlsi_0 => ctrlsi_0
);
-- synthesis translate_off
wbmo_0_cyc_s <= '1' WHEN wbmo_0_cyc = '0' ELSE '1';
wbm_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_0.adr,
sldat_i => wbmo_0.dat,
sldat_o => wbmi_0_int.dat,
cti => wbmo_0.cti,
bte => wbmo_0.bte,
sel => wbmo_0.sel,
cyc => wbmo_0_cyc_s,
stb => wbmo_0.stb,
ack => wbmi_0_int.ack,
err => wbmi_0_int.err,
we => wbmo_0.we
);
wbmo_1_cyc_s <= '1' WHEN wbmo_1_cyc = '0' ELSE '1';
wbm_1: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_1.adr,
sldat_i => wbmo_1.dat,
sldat_o => wbmi_1_int.dat,
cti => wbmo_1.cti,
bte => wbmo_1.bte,
sel => wbmo_1.sel,
cyc => wbmo_1_cyc_s,
stb => wbmo_1.stb,
ack => wbmi_1_int.ack,
err => wbmi_1_int.err,
we => wbmo_1.we
);
wbs_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbs_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_0_int.adr,
sldat_i => wbsi_0_int.dat,
sldat_o => wbso_0.dat,
cti => wbsi_0_int.cti,
bte => wbsi_0_int.bte,
sel => wbsi_0_int.sel,
cyc => wbsi_0_cyc_int,
stb => wbsi_0_int.stb,
ack => wbso_0.ack,
err => wbso_0.err,
we => wbsi_0_int.we
);
-- synthesis translate_on
END z126_01_wb_if_arbiter_arch;
| gpl-3.0 | ffde2f6a0cfba242315a686bf997c4ac | 0.436595 | 3.797909 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hwti_common_v1_00_a/hdl/vhdl/hwtireg.vhd | 2 | 1,552 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity hwtireg is
generic
(
REG_WIDTH : integer := 32;
USE_HIGH : boolean := false;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64
);
port
(
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
data : in std_logic_vector(0 to C_DWIDTH-1);
rdack : out std_logic;
wrack : out std_logic;
value : out std_logic_vector(0 to REG_WIDTH-1);
output : out std_logic_vector(0 to C_DWIDTH-1)
);
end entity;
architecture behavioral of hwtireg is
signal reg : std_logic_vector(0 to REG_WIDTH-1);
begin
value <= reg;
wrack <= wr;
rdack <= rd;
output(C_DWIDTH-REG_WIDTH to C_DWIDTH-1) <= reg when rd = '1' else (others => '0');
zero : if( REG_WIDTH < C_DWIDTH ) generate
begin
output(0 to C_DWIDTH-REG_WIDTH-1) <= (others => '0');
end generate;
regproc : process(clk,rst,rd,wr,data,reg) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
reg <= (others => '0');
elsif( wr = '1' ) then
reg <= data(C_DWIDTH-REG_WIDTH to C_DWIDTH-1);
end if;
end if;
end process regproc;
end architecture;
| bsd-3-clause | 222930f11c980f25765b5861086f677c | 0.529639 | 3.274262 | false | false | false | false |
1995parham/Learning | vhdl/crc/crc.vhd | 1 | 934 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-02-2016
-- Module Name: crc.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity crc is
generic (g : std_logic_vector);
port (d, clk : in std_logic;
r : buffer std_logic_vector(g'high - 1 downto g'low) := (others => '0'));
end entity;
architecture arch_crc of crc is
begin
process (clk)
begin
if clk = '1' and clk'event then
if g(g'low) = '1' then
r(g'low) <= r(g'high - 1) xor d;
elsif g(g'low) = '0' then
r(g'low) <= d;
end if;
for I in g'low + 1 to g'high - 1 loop
if g(I) = '1' then
r(I) <= r(g'high - 1) xor r(I - 1);
elsif g(I) = '0' then
r(I) <= r(I - 1);
end if;
end loop;
end if;
end process;
end architecture arch_crc;
| gpl-2.0 | 2f0d3df477af8f253d6d340ed2416afe | 0.474304 | 2.91875 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_init_1.vhd | 2 | 15,229 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- condattr_init_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * condattr = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_condattr_init( cond_attr );
when STATE_2 =>
-- Push data->cond_attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = condattr->num;
when STATE_4 =>
-- Load the value of condattr->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 9a5e2c0783a428b33b901ff0240e16fe | 0.538709 | 3.849596 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/logi_wishbone_peripherals_pack.vhd | 1 | 15,008 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.logi_utils_pack.all ;
package logi_wishbone_peripherals_pack is
type slv16_array is array(natural range <>) of std_logic_vector(15 downto 0);
type slv32_array is array(natural range <>) of std_logic_vector(31 downto 0);
component wishbone_register is
generic(
wb_size : natural := 16; -- Data port size for wishbone
nb_regs : natural := 1 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reg_out : out slv16_array(0 to nb_regs-1);
reg_in : in slv16_array(0 to nb_regs-1)
);
end component;
component wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
B_THRESHOLD : positive := 4;
A_THRESHOLD : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
read_fifo_empty, read_fifo_full, read_fifo_threshold : out std_logic ;
write_fifo_empty, write_fifo_full, write_fifo_threshold : out std_logic ;
read_fifo_reset, write_fifo_reset : out std_logic
);
end component;
component wishbone_max7219 is
generic(NB_DEVICE : positive := 2;
CLK_DIV : positive := 1024;
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- max7219 signals
DOUT : out std_logic ;
SCLK : out std_logic ;
LOAD : out std_logic
);
end component;
component wishbone_servo is
generic(NB_SERVOS : positive := 2;
wb_size : natural := 16 ; -- Data port size for wishbone
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
failsafe : in std_logic ;
servos : out std_logic_vector(NB_SERVOS-1 downto 0)
);
end component;
component wishbone_pwm is
generic( nb_chan : positive := 3;
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
pwm_out : out std_logic_vector(nb_chan-1 downto 0)
);
end component;
component wishbone_interrupt_manager is
generic(NB_INTERRUPT_LINES : positive := 3;
NB_INTERRUPTS : positive := 1;
ADDR_WIDTH : positive := 16;
DATA_WIDTH : positive := 16);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( DATA_WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( DATA_WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
interrupt_lines : out std_logic_vector(0 to NB_INTERRUPT_LINES-1);
interrupts_req : in std_logic_vector(0 to NB_INTERRUPTS-1)
);
end component;
component wishbone_mem is
generic( mem_size : positive := 3;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 -- addr port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end component;
component wishbone_gpio is
generic(
wb_size : natural := 16
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
gpio: inout std_logic_vector(15 downto 0)
);
end component;
component wishbone_watchdog is
generic(
wb_size : natural := 16; -- Data port size for wishbone
watchdog_timeout_ms : positive := 160;
clock_period_ns : positive := 10
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reset_out : out std_logic
);
end component;
component wishbone_7seg4x is
generic(
wb_size : natural := 16; -- Data port size for wishbone
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end component;
component wishbone_shared_mem is
generic( mem_size : positive := 256;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 ; -- Data port size for wishbone
logic_addr_size : natural := 10 ;
logic_data_size : natural := 16
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Logic signals
write_in : in std_logic ;
addr_in : in std_logic_vector(logic_addr_size-1 downto 0);
data_in : in std_logic_vector(logic_data_size-1 downto 0);
data_out : out std_logic_vector(logic_data_size-1 downto 0)
);
end component;
component wishbone_gps is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
rx_in : in std_logic
);
end component;
component wishbone_ping is
generic( nb_ping : positive := 2;
clock_period_ns : integer := 10
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( 15 downto 0);
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
ping_io : inout std_logic_vector(nb_ping-1 downto 0 )
);
end component;
component wishbone_led_matrix_ctrl is
generic(wb_size : positive := 16;
clk_div : positive := 10;
nb_panels : positive := 1 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle : positive := 1910
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end component;
component wishbone_pmic is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
sample_rate : positive := 48_000;
sclk_period_ns : positive := 80
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
ss, sck : out std_logic ;
miso : in std_logic
);
end component;
component wishbone_i2c_master is
generic(
wb_size : natural := 16 -- data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
scl, sda : inout std_logic
);
end component;
component wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end component;
end logi_wishbone_peripherals_pack;
package body logi_wishbone_peripherals_pack is
end logi_wishbone_peripherals_pack;
| lgpl-3.0 | 1076f790427239d354ccc70e65fe9731 | 0.615672 | 3.317418 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hvm_control_interface_v1_00_a/hdl/vhdl/hvm_control_interface.vhd | 2 | 20,039 | ------------------------------------------------------------------------------
-- hvm_control_interface.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hvm_control_interface.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Wed Apr 16 16:10:38 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library hvm_control_interface_v1_00_a;
use hvm_control_interface_v1_00_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity hvm_control_interface is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
go : out std_logic;
my_rst : out std_logic;
mode : out std_logic_vector(0 to 1);
done : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity hvm_control_interface;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of hvm_control_interface is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 4;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal DISABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '1'); -- disable posted write behavior for acknowledged write behavior
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => DISABLE_POSTED_WRITE,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity hvm_control_interface_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
go => go,
my_rst => my_rst,
mode => mode,
done => done,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-3-clause | 2aa9886777c47106804a4ab4e50535da | 0.438146 | 4.59821 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hls_cores/vector_add/vectoradd_prj/solution1/syn/vhdl/vectoradd.vhd | 3 | 21,301 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vectoradd is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
cmd_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
cmd_TVALID : IN STD_LOGIC;
cmd_TREADY : OUT STD_LOGIC;
resp_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
resp_TVALID : OUT STD_LOGIC;
resp_TREADY : IN STD_LOGIC;
a_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_EN_A : OUT STD_LOGIC;
a_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
a_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
a_Clk_A : OUT STD_LOGIC;
a_Rst_A : OUT STD_LOGIC;
b_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_EN_A : OUT STD_LOGIC;
b_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
b_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
b_Clk_A : OUT STD_LOGIC;
b_Rst_A : OUT STD_LOGIC;
result_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_EN_A : OUT STD_LOGIC;
result_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
result_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
result_Clk_A : OUT STD_LOGIC;
result_Rst_A : OUT STD_LOGIC );
end;
architecture behav of vectoradd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"vectoradd,hls_ip_2014_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx485tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.410000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal grp_fu_155_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_160 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal tmp_fu_164_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal op_reg_234 : STD_LOGIC_VECTOR (31 downto 0);
signal end_reg_240 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_253 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_257 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_179_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_1_reg_134_temp: signed (32-1 downto 0);
signal tmp_s_reg_264 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_fu_174_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_185_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_279 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_196_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_144_temp: signed (32-1 downto 0);
signal tmp_5_reg_286 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_202_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_301 : STD_LOGIC_VECTOR (0 downto 0);
signal i_3_fu_215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_ioackin_resp_TREADY : STD_LOGIC;
signal i_2_fu_228_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_134 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_144 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ioackin_resp_TREADY : STD_LOGIC := '0';
signal a_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal b_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_fu_208_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_221_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal result_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
signal ap_sig_bdd_87 : BOOLEAN;
signal ap_sig_bdd_101 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_resp_TREADY assign process. --
ap_reg_ioackin_resp_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
else
if ((((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_279)) and not((not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_301)) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_301))))))) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
elsif ((((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_1 = resp_TREADY)) or ((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_301)) and (ap_const_logic_1 = resp_TREADY)))) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- i_1_reg_134 assign process. --
i_1_reg_134_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_164_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_169_p2)))) then
i_1_reg_134 <= cmd_TDATA;
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))))) then
i_1_reg_134 <= i_3_fu_215_p2;
end if;
end if;
end process;
-- i_reg_144 assign process. --
i_reg_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and not((tmp_fu_164_p2 = ap_const_lv1_0)))) then
i_reg_144 <= cmd_TDATA;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_301)))))) then
i_reg_144 <= i_2_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm))) then
end_reg_240 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st2_fsm_1 = ap_CS_fsm))) then
op_reg_234 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_164_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_169_p2))) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and not((tmp_fu_164_p2 = ap_const_lv1_0))))) then
reg_160 <= grp_fu_155_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st5_fsm_4 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_253) and not((ap_const_lv1_0 = tmp_2_reg_257)) and not((ap_const_lv1_0 = tmp_8_fu_174_p2)))) then
tmp_10_reg_279 <= tmp_10_fu_185_p2;
tmp_s_reg_264 <= tmp_s_fu_179_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)) and (tmp_fu_164_p2 = ap_const_lv1_0))) then
tmp_2_reg_257 <= tmp_2_fu_169_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_253)) and not((ap_const_lv1_0 = tmp_3_fu_191_p2)))) then
tmp_5_reg_286 <= tmp_5_fu_196_p1;
tmp_7_reg_301 <= tmp_7_fu_202_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)))) then
tmp_reg_253 <= tmp_fu_164_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (cmd_TVALID, ap_CS_fsm, tmp_reg_253, tmp_2_reg_257, tmp_8_fu_174_p2, tmp_10_reg_279, tmp_3_fu_191_p2, tmp_7_reg_301, ap_sig_ioackin_resp_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st2_fsm_1 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if ((((ap_const_lv1_0 = tmp_reg_253) and (ap_const_lv1_0 = tmp_2_reg_257)) or (not((ap_const_lv1_0 = tmp_reg_253)) and (ap_const_lv1_0 = tmp_3_fu_191_p2)) or ((ap_const_lv1_0 = tmp_reg_253) and (ap_const_lv1_0 = tmp_8_fu_174_p2)))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((ap_const_lv1_0 = tmp_reg_253)) and not((ap_const_lv1_0 = tmp_3_fu_191_p2)))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
if (not((not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if (not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_301))))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
a_Addr_A <= std_logic_vector(shift_left(unsigned(a_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- a_Addr_A_orig assign process. --
a_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_fu_179_p1, tmp_5_fu_196_p1, ap_sig_bdd_87, ap_sig_bdd_101)
begin
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
if (ap_sig_bdd_101) then
a_Addr_A_orig <= tmp_5_fu_196_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_87) then
a_Addr_A_orig <= tmp_s_fu_179_p1(32 - 1 downto 0);
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
a_Clk_A <= ap_clk;
a_Din_A <= ap_const_lv32_0;
-- a_EN_A assign process. --
a_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_253, tmp_2_reg_257, tmp_8_fu_174_p2, tmp_3_fu_191_p2)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_253) and not((ap_const_lv1_0 = tmp_2_reg_257)) and not((ap_const_lv1_0 = tmp_8_fu_174_p2))) or ((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_253)) and not((ap_const_lv1_0 = tmp_3_fu_191_p2))))) then
a_EN_A <= ap_const_logic_1;
else
a_EN_A <= ap_const_logic_0;
end if;
end process;
a_Rst_A <= ap_rst_n;
a_WEN_A <= ap_const_lv4_0;
-- ap_sig_bdd_101 assign process. --
ap_sig_bdd_101_assign_proc : process(tmp_reg_253, tmp_3_fu_191_p2)
begin
ap_sig_bdd_101 <= (not((ap_const_lv1_0 = tmp_reg_253)) and not((ap_const_lv1_0 = tmp_3_fu_191_p2)));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(tmp_reg_253, tmp_2_reg_257, tmp_8_fu_174_p2)
begin
ap_sig_bdd_87 <= ((ap_const_lv1_0 = tmp_reg_253) and not((ap_const_lv1_0 = tmp_2_reg_257)) and not((ap_const_lv1_0 = tmp_8_fu_174_p2)));
end process;
-- ap_sig_ioackin_resp_TREADY assign process. --
ap_sig_ioackin_resp_TREADY_assign_proc : process(resp_TREADY, ap_reg_ioackin_resp_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)) then
ap_sig_ioackin_resp_TREADY <= resp_TREADY;
else
ap_sig_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end process;
b_Addr_A <= std_logic_vector(shift_left(unsigned(b_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- b_Addr_A_orig assign process. --
b_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_fu_179_p1, tmp_5_fu_196_p1, ap_sig_bdd_87, ap_sig_bdd_101)
begin
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
if (ap_sig_bdd_101) then
b_Addr_A_orig <= tmp_5_fu_196_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_87) then
b_Addr_A_orig <= tmp_s_fu_179_p1(32 - 1 downto 0);
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
b_Clk_A <= ap_clk;
b_Din_A <= ap_const_lv32_0;
-- b_EN_A assign process. --
b_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_253, tmp_2_reg_257, tmp_8_fu_174_p2, tmp_3_fu_191_p2)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_reg_253) and not((ap_const_lv1_0 = tmp_2_reg_257)) and not((ap_const_lv1_0 = tmp_8_fu_174_p2))) or ((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_reg_253)) and not((ap_const_lv1_0 = tmp_3_fu_191_p2))))) then
b_EN_A <= ap_const_logic_1;
else
b_EN_A <= ap_const_logic_0;
end if;
end process;
b_Rst_A <= ap_rst_n;
b_WEN_A <= ap_const_lv4_0;
-- cmd_TREADY assign process. --
cmd_TREADY_assign_proc : process(cmd_TVALID, ap_CS_fsm)
begin
if ((((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0))) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st2_fsm_1 = ap_CS_fsm)) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm)))) then
cmd_TREADY <= ap_const_logic_1;
else
cmd_TREADY <= ap_const_logic_0;
end if;
end process;
grp_fu_155_p2 <= std_logic_vector(unsigned(end_reg_240) + unsigned(ap_const_lv32_FFFFFFFF));
i_2_fu_228_p2 <= std_logic_vector(unsigned(i_reg_144) + unsigned(ap_const_lv32_1));
i_3_fu_215_p2 <= std_logic_vector(unsigned(i_1_reg_134) + unsigned(ap_const_lv32_1));
resp_TDATA <= ap_const_lv32_1;
-- resp_TVALID assign process. --
resp_TVALID_assign_proc : process(ap_CS_fsm, tmp_10_reg_279, tmp_7_reg_301, ap_reg_ioackin_resp_TREADY)
begin
if ((((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)) or ((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_7_reg_301)) and (ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)))) then
resp_TVALID <= ap_const_logic_1;
else
resp_TVALID <= ap_const_logic_0;
end if;
end process;
result_Addr_A <= std_logic_vector(shift_left(unsigned(result_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- result_Addr_A_orig assign process. --
result_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_s_reg_264, tmp_5_reg_286)
begin
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_5_reg_286(32 - 1 downto 0);
elsif ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_s_reg_264(32 - 1 downto 0);
else
result_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
result_Clk_A <= ap_clk;
-- result_Din_A assign process. --
result_Din_A_assign_proc : process(ap_CS_fsm, tmp_9_fu_208_p2, tmp_6_fu_221_p2)
begin
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_Din_A <= tmp_6_fu_221_p2;
elsif ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Din_A <= tmp_9_fu_208_p2;
else
result_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- result_EN_A assign process. --
result_EN_A_assign_proc : process(ap_CS_fsm, tmp_10_reg_279, tmp_7_reg_301, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st7_fsm_6 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_301))))))) then
result_EN_A <= ap_const_logic_1;
else
result_EN_A <= ap_const_logic_0;
end if;
end process;
result_Rst_A <= ap_rst_n;
-- result_WEN_A assign process. --
result_WEN_A_assign_proc : process(ap_CS_fsm, tmp_10_reg_279, tmp_7_reg_301, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((not((ap_const_lv1_0 = tmp_10_reg_279)) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) or ((ap_ST_st7_fsm_6 = ap_CS_fsm) and not(((ap_const_logic_0 = ap_sig_ioackin_resp_TREADY) and not((ap_const_lv1_0 = tmp_7_reg_301))))))) then
result_WEN_A <= ap_const_lv4_F;
else
result_WEN_A <= ap_const_lv4_0;
end if;
end process;
tmp_10_fu_185_p2 <= "1" when (i_1_reg_134 = reg_160) else "0";
tmp_2_fu_169_p2 <= "1" when (op_reg_234 = ap_const_lv32_2) else "0";
tmp_3_fu_191_p2 <= "1" when (signed(i_reg_144) < signed(end_reg_240)) else "0";
i_reg_144_temp <= signed(i_reg_144);
tmp_5_fu_196_p1 <= std_logic_vector(resize(i_reg_144_temp,64));
tmp_6_fu_221_p2 <= std_logic_vector(unsigned(b_Dout_A) + unsigned(a_Dout_A));
tmp_7_fu_202_p2 <= "1" when (i_reg_144 = reg_160) else "0";
tmp_8_fu_174_p2 <= "1" when (signed(i_1_reg_134) < signed(end_reg_240)) else "0";
tmp_9_fu_208_p2 <= std_logic_vector(unsigned(a_Dout_A) - unsigned(b_Dout_A));
tmp_fu_164_p2 <= "1" when (op_reg_234 = ap_const_lv32_1) else "0";
i_1_reg_134_temp <= signed(i_1_reg_134);
tmp_s_fu_179_p1 <= std_logic_vector(resize(i_1_reg_134_temp,64));
end behav;
| bsd-3-clause | a0e103256280ba9818bd56c25f7675eb | 0.563401 | 2.776822 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_au.vhd | 1 | 59,604 | --------------------------------------------------------------------------------
-- Title : VME Address Unit
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_au.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 14/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of all adress counters, switches and
-- muxes which are controlled by vme_master and vme_slave.
-- The usage gets arbitrated by vme_sys_arbiter.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_au
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision 1.8 2017/06/13 07:00:00 mmiehling
-- changed vme_acc_type setting for CR/CSR and D32 to be compliant to DMA configuration bits
--
-- Revision 1.7 2015/09/16 09:20:09 mwawrik
-- Added generics A16_REG_MAPPING and USE_LONGADD
--
-- Revision 1.6 2015/04/07 14:30:16 AGeissler
-- R1: MAIN_PR002233
-- M1: Added a valid signal for sl_acc to inform the VME slave component, that
-- it can use sl_acc to define the type of the access
--
-- Revision 1.5 2014/04/17 07:35:31 MMiehling
-- added generic LONGADD_SIZE
-- changed vme slave access to A16 to sram access
-- added address modifiers for vme slave access: 0x3e, 0x3a, 0x0e, 0x0a
--
-- Revision 1.4 2014/02/07 17:00:06 MMiehling
-- bugfix: IACK addressing
--
-- Revision 1.2 2012/08/27 12:57:24 MMiehling
-- added comments
-- changed iackn handling
--
-- Revision 1.1 2012/03/29 10:14:51 MMiehling
-- Initial Revision
--
-- Revision 1.16 2010/03/12 13:38:18 mmiehling
-- changed
-- iackoutn <= iackoutn_int WHEN asn_in = '0' ELSE '1'; -- rising edge of asn_in must inactivate iackoutn immediately!
-- to
-- iackoutn <= iackoutn_int;
--
-- Revision 1.15 2006/11/17 08:55:58 mmiehling
-- added synchronisation register for iack_in and iachin_daisy
--
-- Revision 1.14 2006/06/02 15:48:53 MMiehling
-- logic for iackoutn => when asn=1 then iackoutn<=1
-- corrected condition for entering state otherirq
--
-- Revision 1.13 2006/05/26 14:34:48 MMiehling
-- added fsm for my_iack detection and iack-daisy-chain => irqs will not be lost
--
-- Revision 1.12 2006/05/18 14:29:01 MMiehling
-- iack daisy chain input was not correct detected (when dsa/b goes low is correct)
-- unused address signals of vme-master access are set to '0'
--
-- Revision 1.11 2004/11/02 11:29:50 mmiehling
-- improved timing and area
--
-- Revision 1.10 2004/07/27 17:15:35 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.9 2004/06/17 13:02:23 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.8 2003/12/17 15:51:41 MMiehling
-- byte swapping was wrong in "not swapped" mode
--
-- Revision 1.6 2003/07/14 08:38:04 MMiehling
-- lwordn was wrong
--
-- Revision 1.5 2003/06/24 13:47:04 MMiehling
-- changed int_adr
--
-- Revision 1.4 2003/06/13 10:06:31 MMiehling
-- improved
--
-- Revision 1.3 2003/04/22 11:02:56 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/02 16:11:31 MMiehling
-- Kommentar entfernt
--
-- Revision 1.1 2003/04/01 13:04:40 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY vme_au IS
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
test : OUT std_logic;
-- mensb slave
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0); -- mensb slave adress lines
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0); -- mensb slave byte enable lines
wbs_we_i : IN std_logic; -- mensb slave read/write
vme_acc_type : IN std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME slave access
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- mensb master
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0); -- mensb master adress lines
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0); -- mensb master byte enable lines
wbm_we_o : OUT std_logic; -- mensb master read/write
sram_acc : OUT std_logic; -- sram access is requested by vmebus
pci_acc : OUT std_logic; -- pci access is requested by vmebus
reg_acc : OUT std_logic; -- reg access is requested by vmebus
sl_acc_wb : OUT std_logic_vector(4 DOWNTO 0); -- sampled with ld_loc_adr_cnt
-- vme
vme_adr_in : IN std_logic_vector(31 DOWNTO 0); -- vme address input lines
vme_adr_out : OUT std_logic_vector(31 DOWNTO 0); -- vme address output lines
---------------------------------------------------------------------------------------------------
-- pins to vmebus
asn_in : IN std_logic; -- vme adress strobe input
vam : INOUT std_logic_vector(5 DOWNTO 0); -- vme address modifier
dsan_out : OUT std_logic; -- data strobe byte(0) out
dsbn_out : OUT std_logic; -- data strobe byte(1) out
dsan_in : IN std_logic; -- data strobe byte(0) in
dsbn_in : IN std_logic; -- data strobe byte(1) in
writen : INOUT std_logic; -- write enable tco = tbd. tsu <= tbd. PIN tbd.
iackn : INOUT std_logic; -- handler's output ! PIN tbd.
iackin : IN std_logic; -- vme daisy chain interrupt acknoledge input
iackoutn : OUT std_logic; -- vme daisy chain interrupt acknoledge output
---------------------------------------------------------------------------------------------------
mensb_active : IN std_logic; -- acknoledge/active signal for mensb slave access
-- vme master
mstr_cycle : OUT std_logic; -- number of master cycles should be done (0=1x, 1=2x)
second_word : IN std_logic; -- indicates the second transmission if in D16 mode and 32bit should be transmitted
dsn_ena : IN std_logic; -- signal switches dsan_out and dsbn_out on and off
vam_oe : IN std_logic; -- vam output enable
ma_d64 : OUT std_logic; -- indicates a d64 burst transmission
sl_d64 : OUT std_logic; -- indicates a d64 burst transmission
-- vme slave
sl_acc : OUT std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
sl_acc_valid : OUT std_logic; -- sl_acc has been calculated and is valid
asn_in_sl_reg : IN std_logic; -- registered asn signal
ld_loc_adr_m_cnt : IN std_logic; -- load address counter
inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_writen_reg : OUT std_logic;
iackn_in_reg : OUT std_logic; -- iack signal (registered with en_vme_adr_in)
my_iack : OUT std_logic;
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
sl_en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
-- sys_arbiter
sl_byte_routing : OUT std_logic; -- to mensb byte routing
ma_byte_routing : OUT std_logic; -- signal for byte swapping
sl_sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0); -- mux select: 00=loc_data_in_m 01=loc_data_in_s 10=reg_data
lwordn_slv : OUT std_logic; -- stored for vme slave access
lwordn_mstr : OUT std_logic; -- master access lwordn
-- locmon
vam_reg : OUT std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : OUT std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
-- vme_du
mstr_reg : IN std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE)
longadd : IN std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
slv16_reg : IN std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : IN std_logic_vector(3 DOWNTO 0); -- interrupt request register
sysc_reg : IN std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
pci_offset_q : IN std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
int_be : OUT std_logic_vector(3 DOWNTO 0); -- internal byte enables
int_adr : OUT std_logic_vector(18 DOWNTO 0) -- internal adress
);
END vme_au;
ARCHITECTURE vme_au_arch OF vme_au IS
CONSTANT AM_NON_DAT : std_logic_vector(1 DOWNTO 0):="00"; -- address modifier code for non-privileged data access
CONSTANT AM_NON_PRO : std_logic_vector(1 DOWNTO 0):="01"; -- address modifier code for non-privileged program access
CONSTANT AM_SUP_DAT : std_logic_vector(1 DOWNTO 0):="10"; -- address modifier code for supervisory data access
CONSTANT AM_SUP_PRO : std_logic_vector(1 DOWNTO 0):="11"; -- address modifier code for supervisory program access
TYPE irq_states IS (idle, myirq, otherirq);
SIGNAL irq_state : irq_states;
SIGNAL vam_in : std_logic_vector(5 DOWNTO 0);
SIGNAL vam_out : std_logic_vector(5 DOWNTO 0);
SIGNAL vme_a1 : std_logic;
SIGNAL my_iack_int : std_logic;
SIGNAL dsan_out_int : std_logic;
SIGNAL dsbn_out_int : std_logic;
SIGNAL wbm_adr_o_cnt : std_logic_vector(31 DOWNTO 1);
SIGNAL wbm_adr_load : std_logic_vector(31 DOWNTO 1);
SIGNAL ld_loc_adr_m_cnt_q : std_logic;
SIGNAL vam_in_reg : std_logic_vector(5 DOWNTO 0);
SIGNAL dsan_in_reg : std_logic;
SIGNAL dsbn_in_reg : std_logic;
SIGNAL sl_acc_d_type : std_logic_vector(3 DOWNTO 0); -- slave access data type
SIGNAL wbm_sel_o_int : std_logic_vector(3 DOWNTO 0);
SIGNAL sl_byte_routing_int : std_logic;
SIGNAL sl_hit : std_logic_vector(2 DOWNTO 0); -- sl32, sl24, sl16, sl24, sl32
SIGNAL pci_hit : std_logic_vector(1 DOWNTO 0);
SIGNAL sl_acc_valid_int : std_logic;
SIGNAL sl_acc_valid_int_q : std_logic;
SIGNAL sl_acc_valid_int_qq : std_logic;
SIGNAL sl_acc_a_type : std_logic_vector(4 DOWNTO 0); -- slave access address type (sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64)
SIGNAL sl_acc_int : std_logic_vector(4 DOWNTO 0);
SIGNAL sl_writen_reg_int : std_logic;
SIGNAL sl_writen_int : std_logic;
SIGNAL reg_acc_int : std_logic;
SIGNAL iackn_out : std_logic;
SIGNAL iackn_in : std_logic;
SIGNAL iackin_daisy : std_logic;
SIGNAL iackn_int_in : std_logic;
SIGNAL vme_adr_in_reg_int : std_logic_vector(31 DOWNTO 0);
SIGNAL wbm_sel_o_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL mstr_cycle_int : std_logic;
SIGNAL lwordn_mstr_int : std_logic;
SIGNAL sl_acc_reg : std_logic_vector(5 DOWNTO 0);
SIGNAL pci_acc_int : std_logic;
SIGNAL lwordn_slv_int : std_logic;
SIGNAL asn_q : std_logic;
SIGNAL iackn_in_q : std_logic;
signal writen_int : std_logic;
SIGNAL vme_a16_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL vme_a24_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL vme_a32_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL vme_a24_pci_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL vme_a32_pci_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL vme_adr_mask : std_logic_vector(31 DOWNTO 12);
SIGNAL iackoutn_int : std_logic;
BEGIN
sl_acc <= sl_acc_reg(4 DOWNTO 0);
sl_d64 <= sl_acc_reg(0);
pci_acc <= pci_acc_int;
lwordn_slv <= lwordn_slv_int;
lwordn_mstr <= lwordn_mstr_int;
sl_writen_reg <= sl_writen_reg_int;
mstr_cycle <= mstr_cycle_int;
reg_acc <= reg_acc_int;
wbm_sel_o <= wbm_sel_o_reg;
my_iack <= my_iack_int;
vme_adr_in_reg <= vme_adr_in_reg_int(31 DOWNTO 2);
-- sl_sel_vme_data_out <= "10" WHEN reg_acc_int = '1' OR my_iack_int = '1' ELSE "00";
sl_sel_vme_data_out <= "10" WHEN reg_acc_int = '1' ELSE "00";
-- if swapping is disabled, dsan and dsbn is exchanged
-- vme_acc_type(5) = swap-bit
dsan_out <= dsan_out_int WHEN dsn_ena = '1' AND vme_acc_type(5) = '1' ELSE
dsbn_out_int WHEN dsn_ena = '1' AND vme_acc_type(5) = '0' ELSE '1';
dsbn_out <= dsbn_out_int WHEN dsn_ena = '1' AND vme_acc_type(5) = '1' ELSE
dsan_out_int WHEN dsn_ena = '1' AND vme_acc_type(5) = '0' ELSE '1';
vme_adr_out(1 DOWNTO 0) <= vme_a1 & lwordn_mstr_int;
wbm_adr_o <= wbm_adr_o_cnt(31 DOWNTO 2) & "00";
sl_acc_d_type <= dsbn_in_reg & dsan_in_reg & wbm_adr_o_cnt(1) & lwordn_slv_int; -- dsan, dsbn, a1, lwordn_slv
sl_acc_valid <= sl_acc_valid_int_qq;
-- sl_hit: vme slave base adress is hit in A16, A24, A32 mode
-- sl_acc_a_type: AM hit sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64
sl_acc_int <= (sl_hit AND sl_acc_a_type(4 DOWNTO 2)) & sl_acc_a_type(1 DOWNTO 0);
vam_reg <= vam_in_reg;
-------------------------------------------------------------------------------
-- IACK-Daisy Chain Driver
-------------------------------------------------------------------------------
-- It is needed to reset the iackn_int_in signal asynchron (if sysc = 1), in
-- order to meet timing: v_asin = 0->1 => iackout = 0->1 after max 30ns
-- (spec: page 183 time 35)
iackn_int_in <= iackn_in_q WHEN sysc_reg(0) = '1' ELSE iackin_daisy; -- if in slot 1, don't wait on asn
iackoutn <= iackoutn_int;
test <= '0' WHEN irq_state = idle ELSE '1';
irq_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
irq_state <= idle;
my_iack_int <= '0';
iackoutn_int <= '1';
asn_q <= '1';
iackin_daisy <= '1';
iackn_in_q <= '1';
writen_int <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
iackn_in_q <= iackn_in;
asn_q <= asn_in;
iackin_daisy <= iackin;
writen_int <= NOT wbs_we_i;
CASE irq_state IS
WHEN idle =>
IF iackn_in_q = '0' AND asn_q = '0' AND iackn_int_in = '0' AND (dsan_in_reg = '0' OR dsbn_in_reg = '0') AND
intr_reg(3) = '1' AND intr_reg(2 DOWNTO 0) = vme_adr_in_reg_int(3 DOWNTO 1) THEN
irq_state <= myirq;
my_iack_int <= '1'; -- my iack => answer iack
iackoutn_int <= '1'; -- my iack => do not give to next board
ELSIF iackn_in_q = '0' AND asn_q = '0' AND iackn_int_in = '0' AND (dsan_in_reg = '0' OR dsbn_in_reg = '0') THEN
irq_state <= otherirq;
my_iack_int <= '0'; -- not my iack => do not answer iack
iackoutn_int <= '0'; -- not my iack => give to next board
ELSE
irq_state <= idle;
my_iack_int <= '0';
iackoutn_int <= '1';
END IF;
WHEN myirq =>
IF clr_intreq = '1' THEN
irq_state <= idle;
my_iack_int <= '0';
iackoutn_int <= '1';
ELSE
irq_state <= myirq;
my_iack_int <= '1'; -- my iack => answer iack
iackoutn_int <= '1'; -- my iack => do not give to next board
END IF;
WHEN otherirq =>
IF asn_q = '1' THEN
irq_state <= idle;
my_iack_int <= '0';
iackoutn_int <= '1';
ELSE
irq_state <= otherirq;
my_iack_int <= '0'; -- not my iack => do not answer iack
iackoutn_int <= '0'; -- not my iack => give to next board
END IF;
WHEN OTHERS =>
irq_state <= idle;
my_iack_int <= '0';
iackoutn_int <= '1';
END CASE;
END IF;
END PROCESS irq_fsm;
am : PROCESS(vam, vam_oe, vam_out)
BEGIN
IF vam_oe = '1' THEN
vam <= vam_out;
vam_in <= to_x01(vam);
ELSE
vam <= (OTHERS => 'Z');
vam_in <= to_x01(vam);
END IF;
END PROCESS am;
wri : PROCESS(vam_oe, wbs_we_i, writen, writen_int)
BEGIN
IF vam_oe = '1' THEN
writen <= writen_int;
sl_writen_int <= to_x01(writen);
ELSE
writen <= 'Z';
sl_writen_int <= to_x01(writen);
END IF;
END PROCESS wri;
iack : PROCESS (vam_oe, iackn, iackn_out)
BEGIN
IF vam_oe = '1' THEN
iackn <= iackn_out;
iackn_in <= to_x01(iackn);
ELSE
iackn <= 'Z';
iackn_in <= to_x01(iackn);
END IF;
END PROCESS iack;
acc_type : PROCESS(sl_acc_d_type, my_iack_int)
BEGIN
IF my_iack_int = '1' THEN
wbm_sel_o_int <= "1111";
sl_byte_routing_int <= '1';
ELSE
CASE sl_acc_d_type IS -- dsan, dsbn, a1, lwordn_slv
WHEN "0000" => wbm_sel_o_int <= "1111";
sl_byte_routing_int <= '0';
WHEN "0011" => wbm_sel_o_int <= "1100";
sl_byte_routing_int <= '0';
WHEN "0001" => wbm_sel_o_int <= "0011";
sl_byte_routing_int <= '1';
WHEN "1011" => wbm_sel_o_int <= "1000";
sl_byte_routing_int <= '0';
WHEN "0111" => wbm_sel_o_int <= "0100";
sl_byte_routing_int <= '0';
WHEN "1001" => wbm_sel_o_int <= "0010";
sl_byte_routing_int <= '1';
WHEN "0101" => wbm_sel_o_int <= "0001";
sl_byte_routing_int <= '1';
WHEN OTHERS => wbm_sel_o_int <= "0000";
sl_byte_routing_int <= '0';
END CASE;
END IF;
END PROCESS acc_type;
mstr_adr : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
wbm_adr_o_cnt <= (OTHERS => '0');
wbm_adr_load <= (OTHERS => '0');
wbm_we_o <= '1';
wbm_sel_o_reg <= "0000";
vam_in_reg <= (OTHERS => '0');
dsan_in_reg <= '1';
dsbn_in_reg <= '1';
sram_acc <= '0';
pci_acc_int <= '0';
reg_acc_int <= '0';
vme_adr_in_reg_int <= (OTHERS => '0');
vme_adr_out(31 DOWNTO 2) <= (OTHERS => '0');
int_adr <= (OTHERS => '0');
int_be <= (OTHERS => '0');
ld_loc_adr_m_cnt_q <= '0';
lwordn_slv_int <= '0';
sl_acc_wb <= (OTHERS => '0');
sl_acc_valid_int <= '0';
sl_acc_valid_int_q <= '0';
sl_acc_valid_int_qq <= '0';
sl_writen_reg_int <= '0';
sl_byte_routing <= '0';
sl_hit <= (OTHERS => '0');
sl_acc_reg <= (OTHERS => '0');
iackn_in_reg <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
ld_loc_adr_m_cnt_q <= ld_loc_adr_m_cnt;
--sl_acc_valid
------------------------------------------
-- wait for valid address
IF asn_in_sl_reg = '1' THEN
sl_acc_valid_int <= '0';
ELSIF en_vme_adr_in = '1' THEN
sl_acc_valid_int <= '1';
END IF;
-- wait until address is check to generate sl_hit signals
IF asn_in_sl_reg = '1' THEN
sl_acc_valid_int_q <= '0';
ELSE
sl_acc_valid_int_q <= sl_acc_valid_int;
END IF;
-- wait until hit is stored in sl_acc_reg register
IF asn_in_sl_reg = '1' THEN
sl_acc_valid_int_qq <= '0';
ELSE
sl_acc_valid_int_qq <= sl_acc_valid_int_q;
END IF;
-----------------------------------------
IF mensb_active = '1' THEN
int_adr <= wbs_adr_i(18 DOWNTO 0);
int_be <= wbs_sel_i;
ELSE
int_adr <= wbm_adr_o_cnt(18 DOWNTO 2) & "00";
int_be <= wbm_sel_o_reg;
END IF;
-- select VME address based on address mode, LONGADD register and generics
IF ma_en_vme_data_out_reg = '1' THEN
if vme_acc_type(1 DOWNTO 0) = "00" then -- A24
vme_adr_out(31 DOWNTO 2) <= "00000000" & wbs_adr_i(23 DOWNTO 2);
elsif vme_acc_type(1 downto 0) = "01" then -- A32
IF wbs_tga_i(7) = '0' THEN -- single access from PCI / no dma?
IF USE_LONGADD = TRUE THEN -- flexible size of longadd parameter => not compatible to A21!
vme_adr_out(31 DOWNTO 2) <= longadd(7 DOWNTO (8-LONGADD_SIZE)) & wbs_adr_i((31-LONGADD_SIZE) DOWNTO 2);
ELSE -- compatibility mode: uses 3 bits of longadd (compatible to A21/A15)
vme_adr_out(31 DOWNTO 2) <= longadd(2 DOWNTO 0) & wbs_adr_i(28 DOWNTO 2);
END IF;
ELSE -- dma access uses complete address (no LONGADD usage)
vme_adr_out(31 DOWNTO 2) <= wbs_adr_i(31 DOWNTO 2);
END IF;
else -- A16
vme_adr_out(31 DOWNTO 2) <= "0000000000000000" & wbs_adr_i(15 DOWNTO 2);
END if;
END IF;
IF en_vme_adr_in = '1' THEN -- samples adress and am at falling edge asn
vme_adr_in_reg_int <= vme_adr_in;
vam_in_reg <= vam_in;
sl_writen_reg_int <= sl_writen_int;
iackn_in_reg <= iackn_in;
END IF;
sl_acc_reg(4 DOWNTO 0) <= sl_acc_int;
IF (pci_hit(0) = '1' AND sl_hit(0) = '1') OR (pci_hit(1) = '1' AND sl_hit(1) = '1') THEN
sl_acc_reg(5) <= '1';
ELSE
sl_acc_reg(5) <= '0';
END IF;
IF sl_en_vme_data_in_reg = '1' THEN
wbm_sel_o_reg <= wbm_sel_o_int;
END IF;
sl_byte_routing <= sl_byte_routing_int;
dsan_in_reg <= dsan_in;
dsbn_in_reg <= dsbn_in;
IF slv16_reg(4) = '1' AND slv16_reg(3 DOWNTO 0) = vme_adr_in_reg_int(15 DOWNTO 12) THEN
sl_hit(2) <= '1'; -- sl16 base address hit
ELSE
sl_hit(2) <= '0';
END IF;
IF slv24_reg(4) = '1' AND
( (slv24_reg(3 DOWNTO 0) & (slv24_reg(15 DOWNTO 12) AND slv24_reg(11 DOWNTO 8))) =
(vme_adr_in_reg_int(23 DOWNTO 20) & (slv24_reg(15 DOWNTO 12) AND vme_adr_in_reg_int(19 DOWNTO 16))) ) THEN
sl_hit(1) <= '1';
pci_hit(1) <= '0'; -- sl24 base address hit
ELSIF slv24_pci_q(4) = '1' AND
( (slv24_pci_q(3 DOWNTO 0) & (slv24_pci_q(15 DOWNTO 12) AND slv24_pci_q(11 DOWNTO 8))) =
(vme_adr_in_reg_int(23 DOWNTO 20) & (slv24_pci_q(15 DOWNTO 12) AND vme_adr_in_reg_int(19 DOWNTO 16))) ) THEN
sl_hit(1) <= '1';
pci_hit(1) <= '1'; -- sl24 base address hit
ELSE
sl_hit(1) <= '0';
pci_hit(1) <= '0'; -- sl24 base address hit
END IF;
IF slv32_reg(4) = '1' AND
( (slv32_reg(3 DOWNTO 0) & (slv32_reg(15 DOWNTO 8) AND slv32_reg(23 DOWNTO 16))) =
(vme_adr_in_reg_int(31 DOWNTO 28) & (vme_adr_in_reg_int(27 DOWNTO 20) AND slv32_reg(23 DOWNTO 16))) ) THEN
sl_hit(0) <= '1';
pci_hit(0) <= '0'; -- sl32 base address hit
ELSIF slv32_pci_q(4) = '1' AND
( (slv32_pci_q(3 DOWNTO 0) & (slv32_pci_q(15 DOWNTO 8) AND slv32_pci_q(23 DOWNTO 16))) =
(vme_adr_in_reg_int(31 DOWNTO 28) & (vme_adr_in_reg_int(27 DOWNTO 20) AND slv32_pci_q(23 DOWNTO 16))) ) THEN
sl_hit(0) <= '1';
pci_hit(0) <= '1'; -- sl32 base address hit
ELSE
sl_hit(0) <= '0';
pci_hit(0) <= '0'; -- sl32 base address hit
END IF;
IF ld_loc_adr_m_cnt = '1' THEN
lwordn_slv_int <= vme_adr_in_reg_int(0);
sl_acc_wb <= sl_acc_reg(4 DOWNTO 0);
wbm_we_o <= NOT sl_writen_reg_int;
IF sl_acc_reg(4) = '1' THEN -- A16 space is requested by vme bus
IF A16_REG_MAPPING THEN
-- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions of A21)
IF vme_adr_in_reg_int(11) = '1' THEN -- sram access is requested (0x800)
sram_acc <= '1';
reg_acc_int <= '0';
ELSE
reg_acc_int <= '1'; -- register access is requested (0x000)
sram_acc <= '0';
END IF;
-- if false, access to vme slave A16 space goes to sram
ELSE
sram_acc <= '1';
reg_acc_int <= '0';
END IF;
pci_acc_int <= '0';
ELSIF (sl_acc_reg(3) = '1' OR sl_acc_reg(2) = '1') AND sl_acc_reg(5) = '0' THEN -- A24 or A32 space is requested by vme bus
sram_acc <= '1'; -- sram access is requested
reg_acc_int <= '0';
pci_acc_int <= '0';
ELSIF (sl_acc_reg(3) = '1' OR sl_acc_reg(2) = '1') AND sl_acc_reg(5) = '1' THEN -- A24 or A32 space is requested by vme bus
sram_acc <= '0';
reg_acc_int <= '0';
pci_acc_int <= '1'; -- pci access is requested
ELSE
sram_acc <= '0';
reg_acc_int <= '0';
pci_acc_int <= '0';
END IF;
wbm_adr_load(31 DOWNTO 1) <= vme_adr_mask & vme_adr_in_reg_int(11 DOWNTO 1) ;
END IF;
IF ld_loc_adr_m_cnt_q = '1' AND pci_acc_int = '1' THEN
wbm_adr_o_cnt <= (wbm_adr_load(31 DOWNTO 12) + pci_offset_q(31 DOWNTO 12)) & wbm_adr_load(11 DOWNTO 1);
ELSIF ld_loc_adr_m_cnt_q = '1' AND pci_acc_int = '0' THEN
wbm_adr_o_cnt <= wbm_adr_load;
ELSIF (inc_loc_adr_m_cnt = '1' OR sl_inc_loc_adr_m_cnt = '1') AND lwordn_slv_int = '0' THEN
wbm_adr_o_cnt(31 DOWNTO 2) <= wbm_adr_o_cnt(31 DOWNTO 2) + 1;
wbm_adr_o_cnt(1) <= '0';
ELSIF (inc_loc_adr_m_cnt = '1' OR sl_inc_loc_adr_m_cnt = '1') AND lwordn_slv_int = '1' THEN
wbm_adr_o_cnt(31 DOWNTO 1) <= wbm_adr_o_cnt(31 DOWNTO 1) + 1;
END IF;
END IF;
END PROCESS mstr_adr;
vme_a16_mask <= "00000000000000000000";
vme_a24_mask <= "000000000000" & (vme_adr_in_reg_int(19 DOWNTO 16) AND NOT slv24_reg(11 DOWNTO 8)) & vme_adr_in_reg_int(15 DOWNTO 12);
vme_a24_pci_mask <= "000000000000" & (vme_adr_in_reg_int(19 DOWNTO 16) AND NOT slv24_pci_q(11 DOWNTO 8)) & vme_adr_in_reg_int(15 DOWNTO 12);
vme_a32_mask <= "0000" & (vme_adr_in_reg_int(27 DOWNTO 20) AND NOT slv32_reg(23 DOWNTO 16)) & vme_adr_in_reg_int(19 DOWNTO 12);
vme_a32_pci_mask <= "0000" & (vme_adr_in_reg_int(27 DOWNTO 20) AND NOT slv32_pci_q(23 DOWNTO 16)) & vme_adr_in_reg_int(19 DOWNTO 12);
vme_adr_mask <= vme_a24_pci_mask WHEN sl_acc_a_type(4 DOWNTO 3) = "01" AND sl_acc_reg(5) = '1' ELSE
vme_a24_mask WHEN sl_acc_a_type(4 DOWNTO 3) = "01" AND sl_acc_reg(5) = '0' ELSE
vme_a16_mask WHEN sl_acc_a_type(4 DOWNTO 3) = "10" ELSE
vme_a32_pci_mask WHEN sl_acc_a_type(4 DOWNTO 3) = "00" AND sl_acc_reg(5) = '1' ELSE
vme_a32_mask;
lg_dec : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
sl_acc_a_type <= "00000";
ELSIF clk'EVENT AND clk = '1' THEN
CASE vam_in_reg(5 DOWNTO 0) IS
-- sl_acc_a_type = sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64
WHEN "111111" => sl_acc_a_type <= "01010"; -- 3f A24 supervisory block transfer
WHEN "111110" => sl_acc_a_type <= "01000"; -- 3e A24 supervisory program access
WHEN "111101" => sl_acc_a_type <= "01000"; -- 3d A24 supervisory data access
WHEN "111100" => sl_acc_a_type <= "01001"; -- 3c A24 supervisory 64-bit block transfer
WHEN "111011" => sl_acc_a_type <= "01010"; -- 3b A24 non privileged block transfer
WHEN "111010" => sl_acc_a_type <= "01000"; -- 3a A24 non privileged program transfer
WHEN "111001" => sl_acc_a_type <= "01000"; -- 39 A24 non privileged data access
WHEN "111000" => sl_acc_a_type <= "01001"; -- 38 A24 non privileged 64-bit block transfer
WHEN "101101" => sl_acc_a_type <= "10000"; -- 2d A16 supervisory access
WHEN "101001" => sl_acc_a_type <= "10000"; -- 29 A16 non privileged access
WHEN "001111" => sl_acc_a_type <= "00110"; -- 0f A32 supervisory block transfer
WHEN "001110" => sl_acc_a_type <= "00100"; -- 0e A32 supervisory program access
WHEN "001101" => sl_acc_a_type <= "00100"; -- 0d A32 supervisory data access
WHEN "001100" => sl_acc_a_type <= "00101"; -- 0c A32 supervisory 64-bit block transfer
WHEN "001011" => sl_acc_a_type <= "00110"; -- 0b A32 non privileged block transfer
WHEN "001010" => sl_acc_a_type <= "00100"; -- 0a A32 non privileged program access
WHEN "001001" => sl_acc_a_type <= "00100"; -- 09 A32 non privileged data access
WHEN "001000" => sl_acc_a_type <= "00101"; -- 08 A32 non privileged 64-bit block transfer
WHEN OTHERS => sl_acc_a_type <= "00000";
END CASE;
END IF;
END PROCESS lg_dec;
-- vme_acc_type:
-- M D R S B D A
-- 8 7 6 5 4 32 10
-- A16/D16 m d u 0 0 00 10
-- A16/D32 m d u 0 0 01 10
-- A24/D16 m d u 0 0 00 00
-- A24/D32 m d u 0 0 01 00
-- CR/CSR x d u 0 0 10 00
-- A32/D32 m d u 0 0 01 01
-- IACK m d u 0 0 00 11
-- A32/D32/BLT m d u 0 1 01 01
-- A32/D64/BLT m d u 0 1 11 01
-- A24/D16/BLT m d u 0 1 00 00
-- A24/D32/BLT m d u 0 1 01 00
-- A24/D64/BLT m d u 0 1 11 00 new
-- " swapped m d u 1 x xx xx
--
-- m = 0: non-privileged
-- m = 1: supervisory
--
-- d = 0: host access
-- d = 1: DMA access
--
-- u: unused
vam_proc : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
vam_out <= (OTHERS => '0');
lwordn_mstr_int <= '0';
ma_byte_routing <= '0';
mstr_cycle_int <= '0';
dsan_out_int <= '1';
dsbn_out_int <= '1';
vme_a1 <= '0';
iackn_out <= '1';
ma_d64 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE vme_acc_type(4 DOWNTO 0) IS
WHEN "00011" => vam_out <= "010000";-- x10 IACK-Cycle
iackn_out <= '0';
mstr_cycle_int <= '0'; -- only one cycle is permitted
ma_d64 <= '0';
IF wbs_sel_i = "1111" THEN
vme_a1 <= '0'; -- longword will be transmitted
dsan_out_int <= '0';
dsbn_out_int <= '0';
ma_byte_routing <= '0';
lwordn_mstr_int <= '0';
ELSIF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
lwordn_mstr_int <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
lwordn_mstr_int <= '1';
END IF;
-- A16 D16
WHEN "00010" =>
IF vme_acc_type(7) = '1' THEN -- DMA access
IF vme_acc_type(8) = '1' THEN
vam_out <= "101101"; -- x2D A16 D16 supervisory access
ELSE
vam_out <= "101001"; -- x29 A16 D16 non-privileged access
END IF;
ELSE -- host access
CASE mstr_reg(9 DOWNTO 8) IS
WHEN AM_NON_DAT => vam_out <= "101001"; -- x29 A16 D16 non-privileged access
WHEN OTHERS => vam_out <= "101101"; -- x2D A16 D16 supervisory access
END CASE;
END IF;
iackn_out <= '1';
ma_d64 <= '0';
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmitt 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
-- A24 D16
WHEN "00000" =>
IF vme_acc_type(7) = '1' THEN -- DMA access
IF vme_acc_type(8) = '1' THEN
vam_out <= "111101"; -- x3D A24 D16 supervisory data access
ELSE
vam_out <= "111001"; -- x39 A24 D16 non-privileged data access
END IF;
ELSE
CASE mstr_reg(11 DOWNTO 10) IS
WHEN AM_NON_DAT => vam_out <= "111001"; -- x39 A24 D16 non-privileged data access
WHEN AM_NON_PRO => vam_out <= "111010"; -- x3A A24 D16 non-privileged program access
WHEN AM_SUP_DAT => vam_out <= "111101"; -- x3D A24 D16 supervisory data access
WHEN OTHERS => vam_out <= "111110"; -- x3E A24 D16 supervisory program access
END CASE;
END IF;
iackn_out <= '1';
ma_d64 <= '0';
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmit 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
-- CR/CSR
WHEN "01000" =>
vam_out <= "101111"; -- x2f CR/CSR access
iackn_out <= '1';
ma_d64 <= '0';
mstr_cycle_int <= '0';
IF wbs_sel_i = "1111" THEN -- D32 access
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ELSE -- D16 access
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
END IF;
-- A24 D32
WHEN "00100" =>
IF vme_acc_type(7) = '1' THEN -- DMA access
IF vme_acc_type(8) = '1' THEN
vam_out <= "111101"; -- x3D A24 D32 supervisory data access
ELSE
vam_out <= "111001"; -- x39 A24 D32 non-privileged data access
END IF;
ELSE
CASE mstr_reg(11 DOWNTO 10) IS
WHEN AM_NON_DAT => vam_out <= "111001"; -- x39 A24 D32 non-privileged data access
WHEN AM_NON_PRO => vam_out <= "111010"; -- x3A A24 D32 non-privileged program access
WHEN AM_SUP_DAT => vam_out <= "111101"; -- x3D A24 D32 supervisory data access
WHEN OTHERS => vam_out <= "111110"; -- x3E A24 D32 supervisory program access
END CASE;
END IF;
iackn_out <= '1';
ma_d64 <= '0';
IF wbs_sel_i = "1111" THEN
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
mstr_cycle_int <= '0';
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ELSE -- same as D16 access
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmit 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
END IF;
-- A16 D32
WHEN "00110" =>
IF vme_acc_type(7) = '1' THEN -- DMA access
IF vme_acc_type(8) = '1' THEN
vam_out <= "101101"; -- x2D A16 D32 supervisory access
ELSE
vam_out <= "101001"; -- x29 A16 D32 non-privileged access
END IF;
ELSE
CASE mstr_reg(9 DOWNTO 8) IS -- A16_MODE
WHEN AM_NON_DAT => vam_out <= "101001"; -- x29 A16 D32 non-privileged access
WHEN OTHERS => vam_out <= "101101"; -- x2D A16 D32 supervisory access
END CASE;
END IF;
iackn_out <= '1';
ma_d64 <= '0';
IF wbs_sel_i = "1111" THEN
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
mstr_cycle_int <= '0';
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ELSE -- same as D16 access
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmitt 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
END IF;
-- A32 D32
WHEN "00101" =>
IF vme_acc_type(7) = '1' THEN -- DMA access
IF vme_acc_type(8) = '1' THEN
vam_out <= "001101"; -- x0D A32 D32 supervisory data access
ELSE
vam_out <= "001001"; -- x09 A32 D32 non-privileged data access
END IF;
ELSE
CASE mstr_reg(13 DOWNTO 12) IS -- A32_MODE
WHEN AM_NON_DAT => vam_out <= "001001"; -- x09 A32 D32 non-privileged data access
WHEN AM_NON_PRO => vam_out <= "001010"; -- x0A A32 D32 non-privileged program access
WHEN AM_SUP_DAT => vam_out <= "001101"; -- x0D A32 D32 supervisory data access
WHEN OTHERS => vam_out <= "001110"; -- x0E A32 D32 supervisory program access
END CASE;
END IF;
iackn_out <= '1';
ma_d64 <= '0';
IF wbs_sel_i = "1111" THEN
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
mstr_cycle_int <= '0';
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ELSE -- same as D16 access
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmit 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
END IF;
-- A24 D16 BLT
WHEN "10000" =>
IF vme_acc_type(8) = '0' THEN
vam_out <= "111011";-- x3b A24 D16 blt non-privileged
ELSE
vam_out <= "111111";-- x3f A24 D16 blt supervisory
END IF;
iackn_out <= '1';
ma_d64 <= '0';
lwordn_mstr_int <= '1';
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') AND (wbs_sel_i(2) = '1' OR wbs_sel_i(3) = '1') THEN
mstr_cycle_int <= '1'; -- there must be two master cycles in order to transmit 32bit in D16 mode
ELSE
mstr_cycle_int <= '0';
END IF;
IF second_word = '0' OR (second_word = '1' AND mstr_cycle_int = '0') THEN -- first word of two
IF (wbs_sel_i(0) = '1' OR wbs_sel_i(1) = '1') THEN
vme_a1 <= '0'; -- only low word will be transmitted
dsan_out_int <= NOT wbs_sel_i(1);
dsbn_out_int <= NOT wbs_sel_i(0);
ma_byte_routing <= '1';
ELSE
vme_a1 <= '1'; -- only high word will be transmitted
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
END IF;
ELSE -- second word of two
dsan_out_int <= NOT wbs_sel_i(3);
dsbn_out_int <= NOT wbs_sel_i(2);
ma_byte_routing <= '0';
vme_a1 <= '1';
END IF;
-- A32 D32 BLT
WHEN "10101" =>
IF vme_acc_type(8) = '0' THEN
vam_out <= "001011";-- x0b A32 D32 blt non-privileged
ELSE
vam_out <= "001111";-- x0f A32 D32 blt supervisory
END IF;
iackn_out <= '1';
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
mstr_cycle_int <= '0';
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ma_d64 <= '0';
-- A24 D32 BLT
WHEN "10100" =>
IF vme_acc_type(8) = '0' THEN
vam_out <= "111011";-- x3b A24 D32 blt non-privileged
ELSE
vam_out <= "111111";-- x3f A24 D32 blt supervisory
END IF;
iackn_out <= '1';
IF vme_acc_type(5) = '1' THEN
ma_byte_routing <= '0';
ELSE
ma_byte_routing <= '1';
END IF;
mstr_cycle_int <= '0';
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
lwordn_mstr_int <= '0';
ma_d64 <= '0';
-- A24 D64 MBLT
WHEN "11100" =>
IF vme_acc_type(8) = '0' THEN
vam_out <= "111000";-- x38 A24 D64 mblt non-privileged
ELSE
vam_out <= "111100";-- x3c A24 D64 mblt supervisory
END IF;
lwordn_mstr_int <= '0';
ma_byte_routing <= '1';
mstr_cycle_int <= '1'; -- D64
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
iackn_out <= '1';
ma_d64 <= '1';
-- A32 D64 MBLT
WHEN "11101" =>
IF vme_acc_type(8) = '0' THEN
vam_out <= "001000";-- x08 A32 D64 mblt non-privileged
ELSE
vam_out <= "001100";-- x0c A32 D64 mblt supervisory
END IF;
lwordn_mstr_int <= '0';
ma_byte_routing <= '1';
mstr_cycle_int <= '1'; -- D64
dsan_out_int <= '0';
dsbn_out_int <= '0';
vme_a1 <= '0';
iackn_out <= '1';
ma_d64 <= '1';
WHEN OTHERS => -- A32 D64 MBLT
IF vme_acc_type(8) = '0' THEN
vam_out <= "001000";-- x08 A32 D64 mblt non-privileged
ELSE
vam_out <= "001100";-- x0c A32 D64 mblt supervisory
END IF;
ma_d64 <= '0';
iackn_out <= '1';
lwordn_mstr_int <= '0';
ma_byte_routing <= '0';
mstr_cycle_int <= '0';
dsan_out_int <= '1';
dsbn_out_int <= '1';
vme_a1 <= '0';
END CASE;
END IF;
END PROCESS vam_proc;
END vme_au_arch;
| gpl-3.0 | 26258e7c5707390d1d3bcd9e2c50c98c | 0.42222 | 3.844675 | false | false | false | false |
michaelmiehling/A25_VME | 16z024-01_src/Source/iram_av.vhd | 1 | 5,297 | ---------------------------------------------------------------
-- Title : Internal RAM with Avalon I/F
-- Project : 16z024-01
---------------------------------------------------------------
-- File : iram_av.vhd
-- Author : Ferdinand Lenhardt
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 30/05/05
---------------------------------------------------------------
-- Simulator : ModelSim-Altera 5.8e
-- Synthesis : Quartus II 4.2 SP1
---------------------------------------------------------------
-- Description :
--
-- This is a wrapper for "Internal RAM with Wishbone I/F".
-- For ACEX this module can be used only as a ROM.
---------------------------------------------------------------
-- Hierarchy:
--
-- iram_av
-- iram_wb
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: iram_av.vhd,v $
-- Revision 1.7 2009/01/27 14:30:15 FLenhardt
-- Added support for fpga_pkg_2
--
-- Revision 1.6 2007/11/21 13:46:03 FLenhardt
-- Added a commentary to generic USEDW_WIDTH
--
-- Revision 1.5 2006/02/27 16:49:41 TWickleder
-- Changed the handling of the generic read_only to use it in both interfaces
--
-- Revision 1.4 2005/10/19 14:24:18 flenhardt
-- Workaround for SOPC Builder bug regarding a generic of type BOOLEAN
--
-- Revision 1.3 2005/10/19 13:17:04 flenhardt
-- Added generic READ_ONLY
--
-- Revision 1.2 2005/06/28 09:13:47 flenhardt
-- Workaround for SOPC Builder bug regarding generics
--
-- Revision 1.1 2005/05/30 09:43:03 flenhardt
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.ALL;
ENTITY iram_av IS
GENERIC
(
fpga_family: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
usedw_width: positive := 6; -- 2**(usedw_width + 2) bytes
location: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
reset : IN std_logic; -- global async high active reset
-- Avalon signals
av_chipselect : IN std_logic; -- chip select
av_byteenable : IN std_logic_vector(3 DOWNTO 0); -- byte enable
av_write : IN std_logic; -- write enable
av_writedata : IN std_logic_vector(31 DOWNTO 0); -- write data
av_read : IN std_logic; -- read enable
av_readdata : OUT std_logic_vector(31 DOWNTO 0); -- read data
av_address : IN std_logic_vector((usedw_width + 1) DOWNTO 2);
av_waitrequest : OUT std_logic -- delay access
);
END iram_av;
ARCHITECTURE iram_av_arch OF iram_av IS
COMPONENT iram_wb
GENERIC
(
FPGA_FAMILY: family_type;
read_only: natural;
USEDW_WIDTH: positive;
LOCATION: string
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((usedw_width + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END COMPONENT;
SIGNAL wb_stb_i : std_logic;
SIGNAL wb_we_i : std_logic;
SIGNAL wb_ack_o : std_logic;
BEGIN
ram: iram_wb
GENERIC MAP
(
FPGA_FAMILY => FPGA_FAMILY,
read_only => read_only,
usedw_width => usedw_width,
location => location
)
PORT MAP
(
clk => clk,
rst => reset,
stb_i => wb_stb_i,
cyc_i => av_chipselect,
ack_o => wb_ack_o,
we_i => wb_we_i,
sel_i => av_byteenable,
adr_i => av_address,
dat_i => av_writedata,
dat_o => av_readdata
);
wb_stb_i <= av_write OR av_read;
wb_we_i <= av_write;
-- wait request only when stb_i and cyc_i active and no ackowledge yet.
av_waitrequest <= NOT(wb_ack_o) WHEN (av_chipselect='1' AND wb_stb_i='1') ELSE
'1';
END iram_av_arch;
| gpl-3.0 | f7175ba1574c4ba7b2fa23e92e598319 | 0.546913 | 3.735543 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_condVarInitText.vhd | 2 | 14,274 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
FUNCTION_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal condvarAttrPtr, condvarAttrPtr_next : std_logic_vector(0 to 31);
signal condvarPtr, condvarPtr_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
condvarAttrPtr <= condvarAttrPtr_next;
condvarPtr <= condvarPtr_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_15 =>
current_state <= STATE_15;
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
condvarAttrPtr_next <= condvarAttrPtr;
condvarPtr_next <= condvarPtr;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
next_state <= STATE_1;
-- call malloc( 0x4 ) to allocate space for a condvarattr.
when STATE_1 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- store the returned pointer address
when STATE_3 =>
condvarAttrPtr_next <= toUser_value;
next_state <= STATE_4;
-- call hthread_condvarattr_init( *condvarattr );
when STATE_4 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condvarAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_5;
when STATE_5 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- call hthread_condvarattr_setnum( *condvarattr, 4 )
when STATE_6 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= state_7;
when STATE_7 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condvarAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_8;
when STATE_8 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_SETNUM;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
-- call malloc( 0x4 ) to allocate space for a condvar
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
thrd2intrfc_function <= FUNCTION_MALLOC;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
-- store value of condvarPtr
when STATE_11 =>
condvarPtr_next <= toUser_value;
next_state <= STATE_12;
-- call hthread_condvar_init( *condvar, *condvarattr )
when STATE_12 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condvarAttrPtr;
next_state <= WAIT_STATE;
return_state_next <= state_13;
when STATE_13 =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= condvarPtr;
next_state <= WAIT_STATE;
return_state_next <= state_14;
when STATE_14 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 6520d50f1059b0cf9d2de16c6daa4622 | 0.557797 | 4.009551 | false | false | false | false |
QuickJack/logi-hard | hdl/utils/generic_delay.vhd | 2 | 2,650 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 09:30:41 10/03/2012
-- Design Name:
-- Module Name: generic_delay - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work ;
use work.utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity generic_delay is
generic( WIDTH : positive := 1; DELAY : positive := 1);
port(
clk, resetn : std_logic ;
input : in std_logic_vector((WIDTH - 1) downto 0);
output : out std_logic_vector((WIDTH - 1) downto 0)
);
end generic_delay;
architecture Behavioral of generic_delay is
type delay_array is array (0 to(DELAY -1)) of std_logic_vector((WIDTH - 1) downto 0) ;
signal delay_line : delay_array ;
begin
gen_delay : for i in 0 to DELAY generate
gen_unitary : if i = 0 and DELAY = 1 generate
latch_unitary : generic_latch
generic map(NBIT => WIDTH)
port map ( clk => clk,
resetn => resetn ,
sraz => '0' ,
en => '1' ,
d => input ,
q => output);
end generate ;
gen_input : if i = 0 and DELAY > 1 generate
latch_0 : generic_latch
generic map(NBIT => WIDTH)
port map ( clk => clk,
resetn => resetn ,
sraz => '0' ,
en => '1' ,
d => input ,
q => delay_line(0));
end generate ;
gen_delay :if i > 0 and DELAY > 1 and i < DELAY generate
latch_i : generic_latch
generic map(NBIT => WIDTH)
port map ( clk => clk,
resetn => resetn ,
sraz => '0' ,
en => '1' ,
d => delay_line(i-1) ,
q => delay_line(i));
end generate ;
gen_output :if i = DELAY and DELAY > 1 generate
latch_delay : generic_latch
generic map(NBIT => WIDTH)
port map ( clk => clk,
resetn => resetn ,
sraz => '0' ,
en => '1' ,
d => delay_line(i-1) ,
q => output);
end generate ;
end generate ;
end Behavioral;
| lgpl-3.0 | a9ef2251ea863e8191486af2c3b9861d | 0.533208 | 3.748232 | false | false | false | false |
michaelmiehling/A25_VME | Source/A25_top.vhd | 1 | 51,037 | --------------------------------------------------------------------------------
-- Title : Toplevel File of A25 FPGA
-- Project : 1614_CERN_A25
--------------------------------------------------------------------------------
-- File : A25_top.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2016-06-03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- A25_top
-- wbb2vme_top
-- sram
-- ip_16z091_01_top
-- iram_wb
-- pll_pcie
-- z126_01_top
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
USE work.wb_pkg.ALL;
USE work.fpga_pkg_2.ALL;
USE work.z126_01_pkg.ALL;
USE work.vme_pkg.ALL;
ENTITY A25_top IS
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0)
);
END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT ip_16z091_01_top
GENERIC(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10
);
PORT(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic;
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
link_train_active : out std_logic
);
END COMPONENT;
COMPONENT wb_bus
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- Master Bus
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
-- Slave Bus
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
wbso_1 : IN wbi_type;
wbsi_1 : OUT wbo_type;
wbsi_1_cyc : OUT std_logic;
wbso_2 : IN wbi_type;
wbsi_2 : OUT wbo_type;
wbsi_2_cyc : OUT std_logic;
wbso_3 : IN wbi_type;
wbsi_3 : OUT wbo_type;
wbsi_3_cyc : OUT std_logic;
wbso_4 : IN wbi_type;
wbsi_4 : OUT wbo_type;
wbsi_4_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT pll_pcie
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT iram_wb
GENERIC
(
FPGA_FAMILY: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
USEDW_WIDTH: positive := 6; -- 2**(USEDW_WIDTH + 2) bytes
LOCATION: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
err_o : OUT std_logic; -- error
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((USEDW_WIDTH + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END COMPONENT;
COMPONENT sram
PORT (
clk66 : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- local bus
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic; -- high active write enable
sel_i : IN std_logic_vector(3 DOWNTO 0); -- high active byte enables
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(31 DOWNTO 0);
dat_i : IN std_logic_vector(31 DOWNTO 0);
adr_i : IN std_logic_vector(19 DOWNTO 0);
-- pins to sram
bwn : OUT std_logic; -- global byte write enable:
bwan : OUT std_logic; -- byte a write enable:
bwbn : OUT std_logic; -- byte b write enable:
adscn : OUT std_logic; -- Synchronous Address Status Controller: .
roen : OUT std_logic; -- data port output enable: .
ra : OUT std_logic_vector(18 DOWNTO 0); -- address lines:
rd_in : IN std_logic_vector(15 DOWNTO 0); -- data lines:
rd_out : OUT std_logic_vector(15 DOWNTO 0); -- data lines:
rd_oe : OUT std_logic
);
END COMPONENT;
COMPONENT z126_01_top
GENERIC (
SIMULATION : boolean := FALSE; -- true => use the altasmi parallel of an older quartus version (11.1 SP2) the new one can not be simulated
-- (only the M25P32 is supported for simulation!!)
-- false => use the newest altasmi parallel (13.0)
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
FLASH_TYPE : flash_type := M25P32; -- see SUPPORTED_DEVICES for supported serial flash device types
USE_DIRECT_INTERFACE : boolean := TRUE; -- true => the direct interfaces is included and arbitrated with the indirect interface
-- false => only the indirect interface is available (reducing resource consumption)
USE_REMOTE_UPDATE : boolean := TRUE; -- true => the remote update controller is included and more than one FPGA image can be selected
-- false => only the FPGA Fallback Image can be used for FPGA configuration (reducing resource consumption)
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT (
clk_40mhz : IN std_logic; -- serial flash clock (maximum 40 MHz)
rst_clk_40mhz : IN std_logic; -- this reset should be a power up reset to
-- reduce the reconfiguration (load FPGA Image) time when LOAD_FPGA_IMAGE = TRUE.
-- this reset must be deasserted synchronous to the clk_40mhz
clk_dir : IN std_logic; -- wishbone clock for direct interface
rst_dir : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_dir
clk_indi : IN std_logic; -- wishbone clock for indirect interface
rst_indi : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_indi
board_status : OUT std_logic_vector(1 DOWNTO 0);
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb_dir : IN std_logic; -- request
wbs_ack_dir : OUT std_logic; -- acknoledge
wbs_we_dir : IN std_logic; -- write=1 read=0
wbs_sel_dir : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_dir : IN std_logic; -- chip select
wbs_dat_o_dir : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_dir : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_dir : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_dir : OUT std_logic; -- error
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi : IN std_logic; -- request
wbs_ack_indi : OUT std_logic; -- acknoledge
wbs_we_indi : IN std_logic; -- write=1 read=0
wbs_sel_indi : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_indi : IN std_logic; -- chip select
wbs_dat_o_indi : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_indi : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_indi : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_indi : OUT std_logic -- error
);
END COMPONENT;
COMPONENT wbb2vme_top
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
dma_irq : OUT std_logic; -- interrupt request dma to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_ctrl_stb_o : OUT std_logic;
wbm_ctrl_ack_i : IN std_logic;
wbm_ctrl_err_i : IN std_logic;
wbm_ctrl_we_o : OUT std_logic;
wbm_ctrl_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_ctrl_cyc_sram : OUT std_logic;
wbm_ctrl_cyc_pci : OUT std_logic;
wbm_ctrl_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbm_dma_stb_o : OUT std_logic;
wbm_dma_ack_i : IN std_logic;
wbm_dma_we_o : OUT std_logic;
wbm_dma_cti : OUT std_logic_vector(2 DOWNTO 0);
wbm_dma_tga_o : OUT std_logic_vector(8 DOWNTO 0);
wbm_dma_err_i : IN std_logic;
wbm_dma_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_dma_cyc_sram : OUT std_logic;
wbm_dma_cyc_vme : OUT std_logic;
wbm_dma_cyc_pci : OUT std_logic;
wbm_dma_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vmebus
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
bclr_i_n : IN std_logic; -- bus clear input
bclr_o_n : OUT std_logic; -- bus clear output
retry_i_n : IN std_logic; -- bus retry input
retry_o_n : OUT std_logic; -- bus retry output
retry_oe_n : OUT std_logic; -- bus retry output enable
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END COMPONENT;
function f_sel_pcie_lanes(simulation : boolean)
return std_logic_vector is
begin
if (simulation) then
return "001"; -- x1 for simulation
else
return "100"; -- x4 for synthesis
end if;
end function;
function f_sel_cham_hex(simulation : boolean)
return string is
begin
if (simulation) then
return "../../A25_VME/Source/chameleon.hex";
else
return "../Source/chameleon.hex";
end if;
end function;
function f_sel_sim_bool(simulation : boolean)
return std_logic is
begin
if (simulation) then
return '1';
else
return '0';
end if;
end function;
CONSTANT CONST_500HZ : integer := 66667; -- half 500Hz clock period counter value at 66MHz
SIGNAL sys_clk : std_logic; -- system clock 66 MHz
SIGNAL sys_rst : std_logic; -- system async reset
SIGNAL rst_33 : std_logic; -- reset synchronized to clk_33
SIGNAL clk_33 : std_logic; -- 33 MHz clock for 16z066
SIGNAL clk_50 : std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
SIGNAL clk_125 : std_logic; -- 125 MHz clock for fixed_clk
SIGNAL clk_500 : std_logic; -- 500 Hz clock
SIGNAL cnt_500hz : unsigned(16 downto 0);
-- MASTER SIGNALS
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
SIGNAL wbmo_2 : wbo_type;
SIGNAL wbmi_2 : wbi_type;
SIGNAL wbmo_2_cyc : std_logic_vector(2 DOWNTO 0);
-- SLAVE SIGNALS
SIGNAL wbso_0 : wbi_type;
SIGNAL wbsi_0 : wbo_type;
SIGNAL wbsi_0_cyc : std_logic;
SIGNAL wbso_1 : wbi_type;
SIGNAL wbsi_1 : wbo_type;
SIGNAL wbsi_1_cyc : std_logic;
SIGNAL wbso_2 : wbi_type;
SIGNAL wbsi_2 : wbo_type;
SIGNAL wbsi_2_cyc : std_logic;
SIGNAL wbso_3 : wbi_type;
SIGNAL wbsi_3 : wbo_type;
SIGNAL wbsi_3_cyc : std_logic;
SIGNAL wbso_4 : wbi_type;
SIGNAL wbsi_4 : wbo_type;
SIGNAL wbsi_4_cyc : std_logic;
SIGNAL pll_locked : std_logic;
SIGNAL sr_d_oe : std_logic;
SIGNAL sr_d_out : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_d_in : std_logic_vector(15 DOWNTO 0);
SIGNAL vme_irq : std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
SIGNAL berr_irq : std_logic; -- signal berrn interrupt request
SIGNAL locmon_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
SIGNAL mailbox_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
SIGNAL mailbox_irq_i : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL slot01n : std_logic;
SIGNAL pll_locked_inv : std_logic;
SIGNAL startup_rst : std_logic:='1';
SIGNAL porst : std_logic;
SIGNAL porst_n_q : std_logic:='0';
SIGNAL porst_n : std_logic:='0';
SIGNAL vme_berr : std_logic;
SIGNAL vme_mstr_busy : std_logic;
SIGNAL led_cnt : std_logic_vector(17 DOWNTO 0); -- 2^18 = 3.9 ms
SIGNAL v2p_rst : std_logic;
-- high active signals on A25
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
BEGIN
vme_irq_o <= NOT vme_irq_o_n ;
vme_as_oe <= NOT vme_as_oe_n ;
vme_retry_oe <= NOT vme_retry_oe_n ;
vme_sysres_o <= NOT vme_sysres_o_n ;
vme_ds_oe <= NOT vme_ds_oe_n ;
vme_scon <= NOT vme_scon_n ;
vme_sysfail_o <= NOT vme_sysfail_o_n;
vme_bbsy_o <= NOT vme_bbsy_o_n ;
vme_br_o <= NOT vme_br_o_n ;
vme_berr_o <= NOT vme_berr_o_n;
vme_dtack_o <= NOT vme_dtack_o_n;
led_red_n <= NOT vme_berr;
-- led_green_n <= slot01;
vme_sysclk <= clk_16mhz;
vme_scon_n <= slot01n;
v2p_rstn <= '0' WHEN v2p_rst = '1' ELSE 'Z';
-- counter for extending vme master active pulses to at least 3 ms
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
led_cnt <= (OTHERS => '0');
led_green_n <= '1';
ELSIF sys_clk'event AND sys_clk = '1' THEN
IF vme_mstr_busy = '1' THEN -- if master is active, start counter to extend pulse for 3 ms
led_cnt <= (OTHERS => '1');
led_green_n <= '0'; -- switch on LED
ELSIF led_cnt = 0 THEN -- is 3 ms over?
led_cnt <= (OTHERS => '0');
led_green_n <= '1'; -- switch off LED
ELSE
led_cnt <= led_cnt - '1'; -- count for 3 ms
led_green_n <= '0';
END IF;
END IF;
END PROCESS;
pll_locked_inv <= NOT pll_locked;
startup_rst <= pll_locked_inv;
wbso_3.err <= '0';
wbso_4.err <= '0';
wbmo_0.bte <= "00";
wbmo_1.bte <= "00";
wbmo_2.bte <= "00";
wbmo_1.cti <= "000";
fpga_test(1) <= 'Z';
fpga_test(2) <= 'Z';
fpga_test(3) <= 'Z';
fpga_test(4) <= 'Z';
fpga_test(5) <= 'Z';
-- generate power on reset in order to start application fpga load as early as possible
PROCESS (clk_16mhz)
BEGIN
IF clk_16mhz'EVENT AND clk_16mhz = '1' THEN
porst_n_q <= '1';
porst_n <= porst_n_q;
END IF;
END PROCESS;
porst <= NOT porst_n;
-- synchronize reset to 33 MHz clock
PROCESS(clk_33, pll_locked)
BEGIN
IF pll_locked = '0' THEN
rst_33 <= '1';
ELSIF clk_33'EVENT AND clk_33 = '1' THEN
rst_33 <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, hreset_n, pll_locked)
BEGIN
IF hreset_n = '0' OR pll_locked = '0' THEN
sys_rst <= '1';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
sys_rst <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
cnt_500hz <= (others => '0');
clk_500 <= '0';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
IF cnt_500hz = to_unsigned(0, cnt_500hz'length) THEN
cnt_500hz <= to_unsigned(CONST_500HZ, cnt_500hz'length);
clk_500 <= NOT clk_500;
ELSE
cnt_500hz <= cnt_500hz - 1;
END IF;
END IF;
END PROCESS;
pll: pll_pcie
PORT MAP (
areset => porst,
inclk0 => clk_16mhz, -- 16 MHz
c0 => clk_125, -- 125 MHz
c1 => clk_50, -- 50 MHz
c2 => sys_clk, -- 66 MHz
c3 => sr_clk, -- 66 MHz phase shifted to sys_clk
c4 => clk_33, -- 33 MHz
locked => pll_locked
);
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
"0100" WHEN wbmo_0_cyc_int(2) = '1' ELSE -- | 16z002-01 VME | 2 | 10000 | 200 | 0 |
"0100" WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
"1000" WHEN wbmo_0_cyc_int(5) = '1' ELSE -- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
"0100" WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(8) = '1' ELSE -- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
"0100" WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CR/CSR | 9 | 0 | 01000000 | 4 |
"0000"; -- +--------------------------+-----+----------+----------+-----+
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
wbmo_0.tga(6 DOWNTO 0) <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
CONST_VME_A24D16 WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
CONST_VME_A16D16 WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
CONST_VME_A16D32 WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
CONST_VME_IACK WHEN wbmo_0_cyc_int(2) = '1'
AND wbmo_0.adr(8) = '1' ELSE -- |16z002-01 VME IACK | 2 | 10100 | 10 | 0 |
CONST_VME_REGS WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 100 | 0 |
CONST_VME_A32D32 WHEN wbmo_0_cyc_int(8) = '1' ELSE -- |16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
CONST_VME_A24D32 WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: ip_16z091_01_top
GENERIC MAP (
SIMULATION => f_sel_sim_bool(SIMULATION),
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => f_sel_pcie_lanes(SIMULATION),
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
NR_OF_BARS_USED => 5,
VENDOR_ID => 16#1A88#,
DEVICE_ID => 16#4D45#,
REVISION_ID => 16#1#,
CLASS_CODE => 16#068000#,
SUBSYSTEM_VENDOR_ID => 16#D5#,
SUBSYSTEM_DEVICE_ID => 16#5A91#,
BAR_MASK_0 => x"FFFC0000", -- 256k
BAR_MASK_1 => x"FFF00000", -- 1M
BAR_MASK_2 => x"FE000000", -- 32M
BAR_MASK_3 => x"E0000000", -- 512M
BAR_MASK_4 => x"FF000000", -- 16M
BAR_MASK_5 => x"FFFFF000",
PCIE_REQUEST_LENGTH => "0001000000", -- 64DW = 256Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
TX_DATA_LPM_WIDTHU => 7
)
PORT MAP (
-- Hard IP ports:
clk_50 => clk_50,
clk_125 => clk_125,
ref_clk => refclk,
clk_500 => clk_500,
ext_rst_n => hreset_n,
rx_0 => pcie_rx(0),
rx_1 => pcie_rx(1),
rx_2 => pcie_rx(2),
rx_3 => pcie_rx(3),
tx_0 => pcie_tx(0),
tx_1 => pcie_tx(1),
tx_2 => pcie_tx(2),
tx_3 => pcie_tx(3),
wb_clk => sys_clk,
wb_rst => sys_rst,
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_o => wbmo_0_cyc_int,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
wbm_dat_o => wbmo_0.dat,
wbm_cti => wbmo_0.cti,
wbm_tga => open,
wbs_cyc => wbsi_4_cyc,
wbs_stb => wbsi_4.stb,
wbs_we => wbsi_4.we ,
wbs_sel => wbsi_4.sel,
wbs_adr => wbsi_4.adr,
wbs_dat_i => wbsi_4.dat,
wbs_cti => wbsi_4.cti,
wbs_tga => wbsi_4.tga(0),
wbs_ack => wbso_4.ack,
wbs_err => open,
wbs_dat_o => wbso_4.dat,
irq_req_i(0) => vme_irq(0) ,
irq_req_i(1) => vme_irq(1) ,
irq_req_i(2) => vme_irq(2) ,
irq_req_i(3) => vme_irq(3) ,
irq_req_i(4) => vme_irq(4) ,
irq_req_i(5) => vme_irq(5) ,
irq_req_i(6) => vme_irq(6) ,
irq_req_i(7) => vme_irq(7) ,
irq_req_i(8) => berr_irq ,
irq_req_i(9) => dma_irq ,
irq_req_i(10) => locmon_irq(0) ,
irq_req_i(11) => locmon_irq(1) ,
irq_req_i(12) => mailbox_irq_i ,
error_timeout => open,
error_cor_ext_rcv => open,
error_cor_ext_rpl => open,
error_rpl => open,
error_r2c0 => open,
error_msi_num => open,
link_train_active => open
);
mailbox_irq_i <= mailbox_irq(0) OR mailbox_irq(1);
cham: iram_wb
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY,
read_only => 1,
USEDW_WIDTH => 9, -- 0x200 = 512
LOCATION => f_sel_cham_hex(SIMULATION)
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
stb_i => wbsi_0.stb,
cyc_i => wbsi_0_cyc,
ack_o => wbso_0.ack,
err_o => wbso_0.err,
we_i => wbsi_0.we,
sel_i => wbsi_0.sel,
adr_i => wbsi_0.adr(10 DOWNTO 2),
dat_i => wbsi_0.dat,
dat_o => wbso_0.dat
);
srami: sram
PORT MAP (
clk66 => sys_clk,
rst => sys_rst,
stb_i => wbsi_3.stb,
ack_o => wbso_3.ack,
we_i => wbsi_3.we,
sel_i => wbsi_3.sel,
cyc_i => wbsi_3_cyc,
dat_o => wbso_3.dat,
dat_i => wbsi_3.dat,
adr_i => wbsi_3.adr(19 DOWNTO 0),
bwn => sr_bw_n,
bwan => sr_bwa_n,
bwbn => sr_bwb_n,
adscn => sr_adsc_n,
roen => sr_oe_n,
ra => sr_a,
rd_in => sr_d_in,
rd_out => sr_d_out,
rd_oe => sr_d_oe
);
sr_cs1_n <= '0'; --sys_rst; -- selected if FPGA reset is released
srdat: PROCESS(sr_d_oe, sr_d_out, sr_d)
BEGIN
IF sr_d_oe = '1' THEN
sr_d <= sr_d_out;
sr_d_in <= sr_d;
ELSE
sr_d <= (OTHERS => 'Z');
sr_d_in <= sr_d;
END IF;
END PROCESS;
sflash: z126_01_top
GENERIC MAP (
SIMULATION => SIMULATION,
FPGA_FAMILY => CYCLONE4,
FLASH_TYPE => M25P32,
USE_DIRECT_INTERFACE => FALSE,
USE_REMOTE_UPDATE => TRUE,
LOAD_FPGA_IMAGE => TRUE,
LOAD_FPGA_IMAGE_ADR => X"200100"
)
PORT MAP (
clk_40mhz => clk_33,
rst_clk_40mhz => rst_33,
clk_dir => sys_clk,
rst_dir => sys_rst,
clk_indi => sys_clk,
rst_indi => sys_rst,
board_status => open,
wbs_stb_dir => '0',
wbs_ack_dir => OPEN,
wbs_we_dir => '0',
wbs_sel_dir => (OTHERS => '0'),
wbs_cyc_dir => '0',
wbs_dat_o_dir => OPEN,
wbs_dat_i_dir => (OTHERS => '0'),
wbs_adr_dir => (OTHERS => '0'),
wbs_err_dir => OPEN,
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi => wbsi_1.stb,
wbs_ack_indi => wbso_1.ack,
wbs_we_indi => wbsi_1.we,
wbs_sel_indi => wbsi_1.sel,
wbs_cyc_indi => wbsi_1_cyc,
wbs_dat_o_indi => wbso_1.dat,
wbs_dat_i_indi => wbsi_1.dat,
wbs_adr_indi => wbsi_1.adr,
wbs_err_indi => wbso_1.err
);
vme: wbb2vme_top
GENERIC MAP(
A16_REG_MAPPING => true,
LONGADD_SIZE => 3,
USE_LONGADD => TRUE
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
startup_rst => startup_rst,
postwr => open,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
dma_irq => dma_irq ,
prevent_sysrst => '0',
test_vec => open,
-- vmectrl slave
wbs_stb_i => wbsi_2.stb,
wbs_ack_o => wbso_2.ack,
wbs_err_o => wbso_2.err,
wbs_we_i => wbsi_2.we,
wbs_sel_i => wbsi_2.sel,
wbs_cyc_i => wbsi_2_cyc,
wbs_adr_i => wbsi_2.adr,
wbs_dat_o => wbso_2.dat,
wbs_dat_i => wbsi_2.dat,
wbs_tga_i => wbsi_2.tga,
-- vmectrl master
wbm_ctrl_stb_o => wbmo_1.stb,
wbm_ctrl_ack_i => wbmi_1.ack,
wbm_ctrl_err_i => wbmi_1.err,
wbm_ctrl_we_o => wbmo_1.we,
wbm_ctrl_sel_o => wbmo_1.sel,
wbm_ctrl_cyc_sram => wbmo_1_cyc(0),
wbm_ctrl_cyc_pci => wbmo_1_cyc(1),
wbm_ctrl_adr_o => wbmo_1.adr,
wbm_ctrl_dat_o => wbmo_1.dat,
wbm_ctrl_dat_i => wbmi_1.dat,
wbm_dma_stb_o => wbmo_2.stb,
wbm_dma_ack_i => wbmi_2.ack,
wbm_dma_we_o => wbmo_2.we,
wbm_dma_cti => wbmo_2.cti,
wbm_dma_tga_o => wbmo_2.tga,
wbm_dma_err_i => wbmi_2.err,
wbm_dma_sel_o => wbmo_2.sel,
wbm_dma_cyc_vme => wbmo_2_cyc(0),
wbm_dma_cyc_sram => wbmo_2_cyc(1),
wbm_dma_cyc_pci => wbmo_2_cyc(2),
wbm_dma_adr_o => wbmo_2.adr,
wbm_dma_dat_o => wbmo_2.dat,
wbm_dma_dat_i => wbmi_2.dat,
va => vme_a,
vd => vme_d,
vam => vme_am,
writen => vme_write_n,
iackn => vme_iack_n,
irq_i_n => vme_irq_i_n,
irq_o_n => vme_irq_o_n,
as_o_n => vme_as_o_n,
as_oe_n => vme_as_oe_n,
as_i_n => vme_as_i_n,
sysresn => vme_sysres_o_n,
sysresin => vme_sysres_i_n,
ds_o_n => vme_ds_o_n,
ds_i_n => vme_ds_i_n,
ds_oe_n => vme_ds_oe_n,
berrn => vme_berr_o_n,
berrin => vme_berr_i_n,
dtackn => vme_dtack_o_n,
dtackin => vme_dtack_i_n,
slot01n => slot01n,
sysfail_i_n => vme_sysfail_i_n,
sysfail_o_n => vme_sysfail_o_n,
bbsyn => vme_bbsy_o_n,
bbsyin => vme_bbsy_i_n,
bclr_i_n => vme_bclr_i_n,
bclr_o_n => vme_bclr_o_n,
retry_i_n => vme_retry_i_n ,
retry_o_n => vme_retry_o_n ,
retry_oe_n => vme_retry_oe_n ,
br_i_n => vme_br_i_n,
br_o_n => vme_br_o_n,
iackin => vme_iack_i_n,
iackoutn => vme_iack_o_n,
acfailn => vme_acfail_i_n,
bg_i_n => vme_bg_i_n,
bg_o_n => vme_bg_o_n,
ga => vme_ga,
gap => vme_gap,
vme_berr => vme_berr,
vme_mstr_busy => vme_mstr_busy,
d_dir => vme_d_dir ,
d_oe_n => vme_d_oe_n ,
am_dir => vme_am_dir ,
am_oe_n => vme_am_oe_n,
a_dir => vme_a_dir ,
a_oe_n => vme_a_oe_n ,
v2p_rst => v2p_rst
);
wbb : wb_bus
GENERIC MAP (
sets => sets,
timeout => timeout
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
wbmo_0 => wbmo_0,
wbmi_0 => wbmi_0,
wbmo_0_cyc => wbmo_0_cyc,
wbmo_1 => wbmo_1,
wbmi_1 => wbmi_1,
wbmo_1_cyc => wbmo_1_cyc,
wbmo_2 => wbmo_2,
wbmi_2 => wbmi_2,
wbmo_2_cyc => wbmo_2_cyc,
wbso_0 => wbso_0,
wbsi_0 => wbsi_0,
wbsi_0_cyc => wbsi_0_cyc,
wbso_1 => wbso_1,
wbsi_1 => wbsi_1,
wbsi_1_cyc => wbsi_1_cyc,
wbso_2 => wbso_2,
wbsi_2 => wbsi_2,
wbsi_2_cyc => wbsi_2_cyc,
wbso_3 => wbso_3,
wbsi_3 => wbsi_3,
wbsi_3_cyc => wbsi_3_cyc,
wbso_4 => wbso_4,
wbsi_4 => wbsi_4,
wbsi_4_cyc => wbsi_4_cyc
);
-------------------------------------------------------------------------------------------------------------
END A25_top_arch;
-- CONFIGURATION wbm_cfg OF pcies_wbm_ctrl IS
-- FOR pcies_wbm_ctrl_arch
-- FOR wb_adr_dec_inst : pcies_wb_adr_dec
-- USE ENTITY work.pcies_wb_adr_dec(wb_adr_dec_arch);
-- END FOR;
-- END FOR;
-- END CONFIGURATION wbm_cfg;
--
-- CONFIGURATION pcies_wbm_cfg OF pcies_wbm IS
-- FOR pcies_wbm_arch
-- FOR wbm : pcies_wbm_ctrl
-- USE CONFIGURATION work.wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies_wbm_cfg;
--
-- CONFIGURATION pcies2wbb_cfg OF pcies2wbb_top IS
-- FOR pcies2wbb_top_arch
-- FOR pcies_wbm_i : pcies_wbm
-- USE CONFIGURATION work.pcies_wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies2wbb_cfg;
--
-- CONFIGURATION top_cfg of A25_top IS
-- FOR A25_top_arch
-- FOR pcie : pcies2wbb_top
-- USE CONFIGURATION work.pcies2wbb_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION top_cfg;
-- Configurations for 16z091-01 address decoder
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a25_arch);
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION top_cfg OF A25_top IS
FOR A25_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg;
END FOR;
END FOR;
END CONFIGURATION top_cfg;
| gpl-3.0 | 4e514c5f0b83ff1e570c7c60a2cd4996 | 0.460881 | 3.56329 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/base.vhd | 2 | 14,109 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | e4f1c7b99e6d86b567d1995db2c3ab71 | 0.538167 | 3.866539 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/arbitration_logic.vhd | 3 | 34,676 | -------------------------------------------------------------------------------
-- $Id: arbitration_logic.vhd,v 1.1.2.1 2009/10/06 21:14:59 gburch Exp $
------------------------------------------------------------------------------
-- arbitration_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: arbitration_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the priority encoding for the Masters.
-- Based on the current priority of the Masters and their
-- requests, it determines an intermediate grant signal for
-- the Masters. This intermediate grant signal is then input
-- to the Park Lock Logic block to determine the final grant
-- signal based on bus parking and locking.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/30/01
-- ^^^^^^
-- Created version 1.02b to fix problem with registered grants in fixed priority.
-- Created a state machine to generate arb_cycle when grants are registered and
-- in fixed priority. This is not needed in dynamic priority because the internal
-- grant pipeline registers are only enabled during valid arb cycles - also not
-- needed in combinational grants because there isn't a clock delay before master
-- sees the grant and responds with select.
-- ~~~~~~
--
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- When in dynamic priority and combinational outputs, the internal grant
-- registers are like the final registers, so the state machine to control
-- the enable is based on the external grants. When in dynamic priority and
-- registered outputs, the internal state machine is enabled by using the
-- internal grants and the grant registers are enabled by arb_cycle. Arb_cycle
-- is generated from a state machine that uses the external grants. When in
-- fixed priority and registered grants, the same applies. When in fixed priority
-- and combinational grants, arb_cycle is generated by simply examining OPB_Select
-- and OPB_xferAck.
-- ~~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- ~~~~~~
-- chandan 05/25/06
-- ^^^^^^
-- Modified the process MASTERLOOP to remove the latch it was creating.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
--
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
-- The unisim library is required to instantiate Xilinx primitives.
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_NUM_MID_BITS -- number of bits required to encode master ids
-- C_OPBDATA_WIDTH -- number of bits in OPB data bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinatorial grant outputs
--
-- Definition of Ports:
--
-- input OPB_select -- indicates a Master is controlling the bus
-- input OPB_xferAck -- transfer acknowledge
-- input M_request -- bus of master request signals
-- input OPB_buslock -- indicates the OPB is locked
-- input Bus_park -- indicates that the bus is parked
-- input Any_mgrant -- indicates that a Master has been granted the bus
-- input Priority_ids -- the priority IDs of the masters
--
-- output Arb_cycle -- arbitration cycle
-- output Grant -- intermediate Master grant signals
--
-- -- System signals
-- input Clk
-- input Rst
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity arbitration_logic is
generic( C_NUM_MASTERS : integer := 16;
C_NUM_MID_BITS : integer := 4;
C_OPBDATA_WIDTH : integer := 32;
C_DYNAM_PRIORITY: boolean := false;
C_REG_GRANTS : boolean := false
);
port (
OPB_select : in std_logic;
OPB_xferAck : in std_logic;
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_buslock : in std_logic;
Bus_park : in std_logic;
Any_mgrant : in std_logic;
Priority_ids : in std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
Arb_cycle : out std_logic;
Grant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end arbitration_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of arbitration_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- number of priority levels is equal to the number of masters
constant NUM_LVLS : integer := C_NUM_MASTERS;
-- pad number of masters to nearest power of 2 for mux_encode_sel
constant NUM_MSTRS_PAD : integer := pad_power2(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- Need active low request signals to properly drive select lines of muxes
-- this bus will use NUM_MSTRS_PAD so that bus is sized to nearest power of 2
-- for mux_encode_sel. Bus defaults to '0', only the bits up to C_NUM_MASTERS
-- will get assigned a real value.
signal m_request_n : std_logic_vector(0 to NUM_MSTRS_PAD-1) := (others => '0');
-- declare a 2-dimensional array for each master's priority level and mux chain
type MASTER_LVL_TYPE is array(0 to C_NUM_MASTERS-1) of std_logic_vector(0 to NUM_LVLS-1);
signal M_req_lvl : MASTER_LVL_TYPE; -- holds master's priority levels
signal M_muxout : MASTER_LVL_TYPE; -- output of each MUXCY
-- declare a signal to hold decode requests
-- active low bus where if the bit location =0, a request was received at that priority
-- level
signal request_lvl_n : std_logic_vector(0 to NUM_LVLS-1);
-- internal intermediate grant signals
signal grant_i : std_logic_vector(0 to C_NUM_MASTERS-1);
-- OR of all intermediate grant signals
signal any_grant : std_logic;
-- enables grant registers
signal en_grant_reg : std_logic := '0';
-- Enable Grant State Machine signals for dynamic priority, registered outputs
type ENGRNTREG_STATE_TYPE is (IDLE, WAIT1, WAIT2, CHK_SELECT);
signal engrntreg_cs : ENGRNTREG_STATE_TYPE := IDLE;
signal engrntreg_ns : ENGRNTREG_STATE_TYPE := IDLE;
-- Enable Grant State Machine signals for dynamic priority, combinational outputs
type ENGRNTCMB_STATE_TYPE is (IDLE, CHK_SELECT);
signal engrntcmb_cs : ENGRNTCMB_STATE_TYPE := IDLE;
signal engrntcmb_ns : ENGRNTCMB_STATE_TYPE := IDLE;
-- Arb Cycle State Machine signals
type ARBCYCLE_STATE_TYPE is (IDLE, CHK_SELECT);
signal arbcycle_cs : ARBCYCLE_STATE_TYPE := IDLE;
signal arbcycle_ns : ARBCYCLE_STATE_TYPE := IDLE;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUXCY - carry chain multiplexors
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OR_BITS is used to OR all of the intermediate Grant signals so that the
-- enable can be generated to the grant registers (only used when C_DYNAM_PRIORITY
-- =1)
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If Dynamic priority with registered outputs, determine
-- if any grant has been asserted. This is to used to enable the
-- internal grant registers at the proper time.
ANY_GRNT_GEN: if (C_DYNAM_PRIORITY and C_REG_GRANTS) generate
OR_IGRNTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => grant_i,
Sig => '0',
Or_out => any_grant
);
end generate ANY_GRNT_GEN;
-------------------------------------------------------------------------------
-- Set output grants to internal grants
-- If parameterized for dynamic priority, register these signals
-- have to generate the correct clock enables for these internal registers
-- If parameterized for fixed priority, simply assign them
-------------------------------------------------------------------------------
FIXED_GRANT_GENERATE: if not(C_DYNAM_PRIORITY) generate
Grant <= grant_i;
end generate FIXED_GRANT_GENERATE;
DYNAM_GRANT_GENERATE: if C_DYNAM_PRIORITY generate
-- when dyanmic priority and combinational outputs, generate enables to
-- internal grant registers based on the external bus grants (any_mgrant).
DYNAM_CMB_GRANT_GEN: if not(C_REG_GRANTS) generate
---------------------------------------------------------------------------
--ENGRNTCMB_CMB_PROCESS
--ENGRNTCMB_REG_PROCESS
--
-- This state machine generates the enable for the grant registers. When
-- any bus grant is asserted, the grant registers are enabled. Then the state
-- machine checks OPB_select. If its
-- negated, the master has aborted the transaction and the grant registers
-- are enabled if any_mgrant is still asserted. If select is asserted, then
-- the state machine waits for OPB_xferAck and enables
-- the grant registers when these are asserted.
---------------------------------------------------------------------------
ENGRNTCMB_CMB_PROCESS: process (OPB_select, any_mgrant, OPB_xferAck, engrntcmb_cs)
begin
-- set defaults
en_grant_reg<= '0';
engrntcmb_ns <= engrntcmb_cs;
case engrntcmb_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until OPB_Select or any_mgrant asserts
-- negate en_grant_reg and either wait for OPB_select to assert or
-- if its asserted, wait for XferAck.
when IDLE =>
en_grant_reg<= '1';
if OPB_Select = '1' or
any_mgrant = '1' then
en_grant_reg<= '0';
engrntcmb_ns <= CHK_SELECT;
end if;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- en_grant_reg should be asserted. If OPB_select is asserted, wait
-- for OPB_xferAck to assert en_grant_reg. If any_mgrant
-- is asserted, return to IDLE, otherwise stay in this
-- state
when CHK_SELECT =>
if OPB_select = '0' then
if any_mgrant = '0' then
en_grant_reg<= '1';
engrntcmb_ns <= IDLE;
end if;
elsif OPB_xferAck = '1'then
if any_mgrant = '0' then
en_grant_reg<= '1';
engrntcmb_ns <= IDLE;
end if;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
engrntcmb_ns <= IDLE;
end case;
end process ENGRNTCMB_CMB_PROCESS;
-- ENGRNTCMB_REG_PROCESS
ENGRNTCMB_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
engrntcmb_cs <= IDLE;
else
engrntcmb_cs <= engrntcmb_ns;
end if;
end if;
end process ENGRNTCMB_REG_PROCESS;
end generate DYNAM_CMB_GRANT_GEN;
-- when dyanmic priority and registered outputs, generate enables to
-- internal grant registers based on the internal bus grants (any_grant).
DYNAM_REG_GRANT_GEN: if C_REG_GRANTS generate
ENGRNTREG_CMB_PROCESS: process (OPB_select, any_grant, OPB_xferAck, engrntreg_cs)
-- set defaults
begin
en_grant_reg <= '0';
engrntreg_ns <= engrntreg_cs;
case engrntreg_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until any_grant asserts, then enable the
-- grant registers and begin waiting through the grant pipeline
when IDLE =>
if OPB_select = '1' then
engrntreg_ns <= CHK_SELECT;
elsif any_grant = '1' then
engrntreg_ns <= WAIT1;
en_grant_reg <= '1';
end if;
-------------------------- WAIT1 State ----------------------------
-- this state represents the internal grant registers
-- wait another state before checking OPB_select
when WAIT1 =>
engrntreg_ns <= WAIT2;
-------------------------- WAIT2 State ----------------------------
-- this state represents the registers on the grant outputs
-- check OPB_select in the next clock
when WAIT2 =>
engrntreg_ns <= CHK_SELECT;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- the grant registers need to be enabled to allow the next grant
-- to flow through the pipeline. If OPB_select is asserted, wait
-- for OPB_xferAck assert. When asserted, enable the grant registers.
-- If any_grant is asserted, return to the WAIT1 state, otherwise
-- return to the IDLE state.
when CHK_SELECT =>
if OPB_select = '0' then
if any_grant = '1' then
en_grant_reg <= '1';
engrntreg_ns <= WAIT1;
else
engrntreg_ns <= IDLE;
end if;
elsif OPB_xferAck = '1' then
if any_grant = '1' then
en_grant_reg <= '1';
engrntreg_ns <= WAIT1;
else
engrntreg_ns <= IDLE;
end if;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
engrntreg_ns <= IDLE;
end case;
end process ENGRNTREG_CMB_PROCESS;
-- ENGRNTREG_REG_PROCESS
ENGRNTREG_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
engrntreg_cs <= IDLE;
else
engrntreg_cs <= engrntreg_ns;
end if;
end if;
end process ENGRNTREG_REG_PROCESS;
end generate DYNAM_REG_GRANT_GEN;
---------------------------------------------------------------------------
-- REGGRNT_PROCESS defines the registes on the arbiter grant outputs
---------------------------------------------------------------------------
REGGRNT_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
Grant <= (others => '0');
elsif en_grant_reg = '1' then
Grant <= grant_i;
else
Grant <= (others => '0');
end if;
end if;
end process;
end generate DYNAM_GRANT_GENERATE;
-------------------------------------------------------------------------------
-- Set arbitration cycle signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When combinational grant outputs, valid arbitration cycles
-- are when OPB_select = 0 or OPB_xferAck = 1
-------------------------------------------------------------------------------
CMB_ARBCYCLE_GEN: if not(C_REG_GRANTS) generate
Arb_cycle <= '1' when OPB_select = '0' or OPB_xferAck = '1'
else '0';
end generate CMB_ARBCYCLE_GEN;
-------------------------------------------------------------------------------
-- When registered grant outputs, arb_cycle is determined by
-- a state machine which waits the external bus grants to be output
-- and then checks select. Since it uses the output of the grant registers,
-- parking and locking are accounted for.
-------------------------------------------------------------------------------
REG_ARBCYCLE_GEN: if C_REG_GRANTS generate
ARBCYCLE_CMB_PROCESS: process (OPB_select, any_mgrant, OPB_xferAck,
arbcycle_cs, Bus_park)
begin
-- set defaults
Arb_cycle<= '0';
arbcycle_ns <= arbcycle_cs;
case arbcycle_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until OPB_Select or any_mgrant asserts
-- negate Arb_cycle and either wait for OPB_select to assert or
-- if its asserted, wait for XferAck.
when IDLE =>
Arb_cycle<= '1';
if (OPB_Select = '1' and OPB_xferAck = '0') or
(any_mgrant = '1') then
Arb_cycle<= '0';
arbcycle_ns <= CHK_SELECT;
end if;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- Arb_cycle should be asserted. If OPB_select is asserted, wait
-- for OPB_xferAck to assert arb_cycle.
when CHK_SELECT =>
if OPB_select = '0' then
Arb_cycle<= '1';
if bus_park = '0' then
arbcycle_ns <= IDLE;
end if;
elsif OPB_xferAck = '1'then
Arb_cycle<= '1';
arbcycle_ns <= IDLE;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
arbcycle_ns <= IDLE;
end case;
end process ARBCYCLE_CMB_PROCESS;
-- ARBCYCLE_REG_PROCESS
ARBCYCLE_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
arbcycle_cs <= IDLE;
else
arbcycle_cs <= arbcycle_ns;
end if;
end if;
end process ARBCYCLE_REG_PROCESS;
end generate REG_ARBCYCLE_GEN;
--
-------------------------------------------------------------------------------
-- LOGIC DESCRIPTION
-------------------------------------------------------------------------------
-- The arbitration logic was designed using the Xilinx FPGA primitives so that
-- the fastest speed could be achieved. LUTs (Look-Up Tables) were used as MUXs
-- and OR/AND gates to determine the request level of each Master. The outputs
-- of the LUTs were then input to the carry chain muxes to determine whether
-- grant signal for that Master would be asserted. The MUX select signals were
-- signals indicating whether any Master had asserted a request for each
-- priority level.The inputs to the muxes were signals indicating
-- the level of each master's request. For example, the
-- first mux in the carry chain for Master 0 had the LVL3_0 and the LVL2_0
-- signals as inputs and the select signal was LVL2_REQ_N indicating that a
-- LVL2 request had been received. If this signal was asserted (active low)
-- then the output of the mux would be LVL2_0 and this would be an input to the
-- next mux in the priority carry chain which would select between LVL1 and
-- LVL2 requests, etc.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Mux Selects
-------------------------------------------------------------------------------
-- The mux selects are used in the carry chain for all masters. These signals
-- indicate whether any master had a request at a particular priority level.
-- This is essentially an encoded mux with each priority ID being the selects
-- and the Master requests being the data.
-------------------------------------------------------------------------------
MASTERLOOP: for i in 0 to C_NUM_MASTERS-1 generate --4
-- need active low request signals to properly drive mux select lines
-- if bus lock is not asserted
m_request_n(i) <= not(M_request(i))
when OPB_buslock = '0'
else '1';
MASTER_4 : if C_NUM_MID_BITS = 4 generate
signal priority_ids_int : std_logic_vector(0 to 3);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "0000" => request_lvl_n(i) <= m_request_n(0);
when "0001" => request_lvl_n(i) <= m_request_n(1);
when "0010" => request_lvl_n(i) <= m_request_n(2);
when "0011" => request_lvl_n(i) <= m_request_n(3);
when "0100" => request_lvl_n(i) <= m_request_n(4);
when "0101" => request_lvl_n(i) <= m_request_n(5);
when "0110" => request_lvl_n(i) <= m_request_n(6);
when "0111" => request_lvl_n(i) <= m_request_n(7);
when "1000" => request_lvl_n(i) <= m_request_n(8);
when "1001" => request_lvl_n(i) <= m_request_n(9);
when "1010" => request_lvl_n(i) <= m_request_n(10);
when "1011" => request_lvl_n(i) <= m_request_n(11);
when "1100" => request_lvl_n(i) <= m_request_n(12);
when "1101" => request_lvl_n(i) <= m_request_n(13);
when "1110" => request_lvl_n(i) <= m_request_n(14);
when others => request_lvl_n(i) <= m_request_n(15);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_4;
MASTER_3 : if C_NUM_MID_BITS = 3 generate
signal priority_ids_int : std_logic_vector(0 to 2);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "000" => request_lvl_n(i) <= m_request_n(0);
when "001" => request_lvl_n(i) <= m_request_n(1);
when "010" => request_lvl_n(i) <= m_request_n(2);
when "011" => request_lvl_n(i) <= m_request_n(3);
when "100" => request_lvl_n(i) <= m_request_n(4);
when "101" => request_lvl_n(i) <= m_request_n(5);
when "110" => request_lvl_n(i) <= m_request_n(6);
when others => request_lvl_n(i) <= m_request_n(7);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_3;
MASTER_2 : if C_NUM_MID_BITS = 2 generate
signal priority_ids_int : std_logic_vector(0 to 1);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "00" => request_lvl_n(i) <= m_request_n(0);
when "01" => request_lvl_n(i) <= m_request_n(1);
when "10" => request_lvl_n(i) <= m_request_n(2);
when others => request_lvl_n(i) <= m_request_n(3);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_2;
MASTER_1 : if C_NUM_MID_BITS = 1 generate
signal priority_ids_int : std_logic_vector (0 to 0);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "0" => request_lvl_n(i) <= m_request_n(0);
when others => request_lvl_n(i) <= m_request_n(1);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_1;
-- for each master, determine its priority level and if its request
-- is asserted
MASTERREQ_LVL: for j in 0 to NUM_LVLS-1 generate
REQPROC: process (m_request_n(i),
Priority_ids(j*C_NUM_MID_BITS to j*C_NUM_MID_BITS+C_NUM_MID_BITS-1))
begin
if m_request_n(i) = '0' then
if Priority_ids(j*C_NUM_MID_BITS to j*C_NUM_MID_BITS+C_NUM_MID_BITS-1)
= conv_std_logic_vector(i, C_NUM_MID_BITS) then
M_req_lvl(i)(j) <= '1';
else
M_req_lvl(i)(j) <= '0';
end if;
else
M_req_lvl(i)(j) <= '0';
end if;
end process REQPROC;
end generate MASTERREQ_LVL;
-- for each master, set up carry chain
MASTER_CHAIN: for j in NUM_LVLS-2 downto 0 generate
FIRSTMUX_GEN: if j = NUM_LVLS-2 generate
FIRST_I: MUXCY
port map (
O => M_muxout(i)(j), --[out]
CI => M_req_lvl(i)(j+1),--[in]
DI => M_req_lvl(i)(j), --[in]
S => request_lvl_n(j) --[in]
);
end generate FIRSTMUX_GEN;
OTHERMUX_GEN: if j /= NUM_LVLS-2 generate
OTHERS_I: MUXCY
port map (
O => M_muxout(i)(j), --[out]
CI => M_muxout(i)(j+1), --[in]
DI => M_req_lvl(i)(j),--[in]
S => request_lvl_n(j) --[in]
);
end generate OTHERMUX_GEN;
end generate MASTER_CHAIN;
grant_i(i) <= M_muxout(i)(0);
end generate MASTERLOOP;
end implementation;
| bsd-3-clause | 2547f923269e611e135028f69b371919 | 0.48287 | 4.640792 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_hwti_minimal.vhd | 2 | 157,187 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread Interface
-- Version 3: Subinterfaces for memory, function call, and control
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
library opb_SynchManager_v1_00_c;
use opb_SynchManager_v1_00_c.common.all;
---------------------------------------------------------------------------
-- Address Space
---------------------------------------------------------------------------
-- Note: All addresses must be word addressable. ie the last two bits of
-- each address must be 0b00.
-- BASEADDR +
-- x0000 Thread ID Register
-- x0004 Timer Register (Read Only)
-- x0008 Status Register (Read Only)
-- x000C Command Register
-- x0010 Argument Register
-- x0014 Result Register (Read Only)
-- x0018 Debug System Register (Read Only)
-- x001C Debug User Register (Read Only)
-- x0020 Master Read Register (Read Only)
-- x0024 Master Write Register (Read Only)
-- x0028 Stack Pointer (Read Only)
-- x002C Frame Pointer (Read Only)
-- x0030 Heap Pointer (Read Only)
-- x0034 8B Dynamic Memory Table (Read Only)
-- x0038 32B Dynamic Memory Table (Read Only)
-- x003C 1024B Dynamic Memory Table (Read Only)
-- x0040 Unlimited Dynamic memory Address (Read Only)
-- x0044 Unused
-- x0048 Remote Procedure Call Mutex/Condvar Numbers
-- x004C Remote Procedure Call Argument Struct Address
-- x0050 Start of global address space
-- .....
-- x7FFC End of global address space
---------------------------------------------------------------------------
-- Port Declarations
---------------------------------------------------------------------------
-- Definition of Ports:
-- IPIC
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_CS -- Bus to IP chip select for user logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_PostedWrInh -- IP to Bus posted write inhibit
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
---------------------------------------------------------------------------
-- Hardware Thread Interface Entity
---------------------------------------------------------------------------
entity user_logic_hwti is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := x"6300_0000";
C_HIGHADDR : std_logic_vector(0 to 31) := x"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector := x"7600_0000"
);
port (
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Clk : in std_logic;
Bus2IP_CS : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_RdCE : in std_logic_vector(0 to 3);
Bus2IP_Reset : in std_logic;
Bus2IP_WrCE : in std_logic_vector(0 to 3);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Ack : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
IP2Bus_Error : out std_logic;
IP2Bus_PostedWrInh : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_ToutSup : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_MstBE : out std_logic_vector(0 to 3);
IP2Bus_Addr : out std_logic_vector(0 to 31);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to 31);
intrfc2thrd_address : out std_logic_vector(0 to 31);
intrfc2thrd_value : out std_logic_vector(0 to 31);
intrfc2thrd_function : out std_logic_vector(0 to 15);
intrfc2thrd_goWait : out std_logic;
thrd2intrfc_address : in std_logic_vector(0 to 31);
thrd2intrfc_value : in std_logic_vector(0 to 31);
thrd2intrfc_function : in std_logic_vector(0 to 15);
thrd2intrfc_opcode : in std_logic_vector(0 to 5)
);
end entity user_logic_hwti;
---------------------------------------------------------------------------
-- Architecture Section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwti is
---------------------------------------------------------------------------
-- Bram declaration
---------------------------------------------------------------------------
component bram_imp_dual is
port (
clk: in std_logic;
addra: in std_logic_vector(0 to 12);
dia: in std_logic_vector(0 to 31);
doa: out std_logic_vector(0 to 31);
ena: in std_logic;
wea: in std_logic;
addrb: in std_logic_vector(0 to 12);
dib: in std_logic_vector(0 to 31);
dob: out std_logic_vector(0 to 31);
enb: in std_logic;
web: in std_logic
);
end component;
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant COUNT_BITS : integer := 8;
-- Constants for conditional variable commands
constant CONDVAR_CMD_SIGNAL : std_logic_vector(0 to 3) := "0010";
constant CONDVAR_CMD_WAIT : std_logic_vector(0 to 3) := "0100";
constant CONDVAR_CMD_BCAST : std_logic_vector(0 to 3) := "0110";
constant CONDVAR_FAILED : std_logic_vector(0 to 3) := x"E";
constant CONDVAR_SUCCESS : std_logic_vector(0 to 3) := x"A";
-- Address Mapped Register Offsets
-- Please see the address map at the top of this file for further details
constant REG_THREAD_ID : std_logic_vector(0 to 13) := b"0000_0000_0000_00";
constant REG_TIMER : std_logic_vector(0 to 13) := b"0000_0000_0000_01";
constant REG_STATUS : std_logic_vector(0 to 13) := b"0000_0000_0000_10";
constant REG_COMMAND : std_logic_vector(0 to 13) := b"0000_0000_0000_11";
constant REG_ARGUMENT : std_logic_vector(0 to 13) := b"0000_0000_0001_00";
constant REG_RESULT : std_logic_vector(0 to 13) := b"0000_0000_0001_01";
constant REG_DEBUG_SYSTEM : std_logic_vector(0 to 13) := b"0000_0000_0001_10";
constant REG_DEBUG_USER : std_logic_vector(0 to 13) := b"0000_0000_0001_11";
constant REG_MASTER_READ : std_logic_vector(0 to 13) := b"0000_0000_0010_00";
constant REG_MASTER_WRITE : std_logic_vector(0 to 13) := b"0000_0000_0010_01";
constant REG_STACKPTR : std_logic_vector(0 to 13) := b"0000_0000_0010_10";
constant REG_FRAMEPTR : std_logic_vector(0 to 13) := b"0000_0000_0010_11";
constant REG_HEAPPTR : std_logic_vector(0 to 13) := b"0000_0000_0011_00";
constant REG_8B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_01";
constant REG_32B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_10";
constant REG_1024B_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_11";
constant REG_UNLIMITED_DYNAMIC_TABLE : std_logic_vector(0 to 13) := b"0000_0000_0100_00";
constant REG_RPC_MUTEXCONVAR : std_logic_vector(0 to 13) := b"0000_0000_0100_10";
constant REG_RPC_T_ADDRESS : std_logic_vector(0 to 13) := b"0000_0000_0100_11";
-- I expect these to be derived from generics someday, based on how many instantiated BRAMS
-- The readable address space is slighly larger, this is due to the dynamic memory tables.
-- The BRAM is readable from the Dynamic Table entries up, BRAM is writable from the RPC
-- address and up. Although, it should only be the system kernel writing to the RPC regs.
constant GLOBAL_BASE_ADDR : std_logic_vector(0 to 13) := b"0000_0000_0101_00";
constant GLOBAL_BASE_ADDRREADABLE : std_logic_vector(0 to 13) := b"0000_0000_0011_01";
constant GLOBAL_HIGH_ADDR : std_logic_vector(0 to 13) := b"0111_1111_1111_11";
-- Lower half of address range for dynamic memory allocation
constant BASE_ADDR_MALLOC_8B : std_logic_vector(0 to 15) := x"7FF8";
constant BASE_ADDR_MALLOC_32B : std_logic_vector(0 to 15) := x"7EE0";
constant BASE_ADDR_MALLOC_1024B : std_logic_vector(0 to 15) := x"7A00";
-- Note the base address of the unlimit malloc is the initial heap pointer
-- Alias to determine which register is being accessed by the system bus
alias reg_address : std_logic_vector(0 to 13) is Bus2IP_Addr(16 to 29);
-- Aliases for bus reads and writes responces
-- Set to the IP2IP_Addr duing a bus master read
constant master_read_respond_address : std_logic_vector(0 to 31) := C_BASEADDR(0 to 15) & REG_MASTER_READ & "00";
-- Set to the IP2IP_Addr duing a bus master write
constant master_write_respond_address : std_logic_vector(0 to 31) := C_BASEADDR(0 to 15) & REG_MASTER_WRITE & "00";
-- Function Constants
-- Unsupported functions are commented out
-- TODO Is there a way to put this into a seperate file that can be shared with the HWTUL?
-- Special function codes for user
constant FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7FFF reserved for user logic's state machine
-- Range 8000 to 9FFF reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
-- Ranged A000 to A0FF reserved for standard library stdlib.h calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- Ranged A100 to A1FF reserved for string.h library calls
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- Opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
-- system_status Constants
constant SYSTEM_STATUS_NOT_USED : std_logic_vector(0 to 7) := x"00";
constant SYSTEM_STATUS_USED : std_logic_vector(0 to 7) := x"01";
constant SYSTEM_STATUS_RUNNING : std_logic_vector(0 to 7) := x"02";
constant SYSTEM_STATUS_BLOCKED : std_logic_vector(0 to 7) := x"04";
constant SYSTEM_STATUS_EXITED : std_logic_vector(0 to 7) := x"08";
constant SYSTEM_STATUS_EXITED_ERROR : std_logic_vector(0 to 7) := x"20";
constant SYSTEM_STATUS_EXITED_OVERFLOW : std_logic_vector(0 to 7) := x"40";
-- system_command Constants
constant SYSTEM_COMMAND_INIT : std_logic_vector(0 to 3) := x"0";
constant SYSTEM_COMMAND_RUN : std_logic_vector(0 to 3) := x"1";
constant SYSTEM_COMMAND_RESET : std_logic_vector(0 to 3) := x"2";
constant SYSTEM_COMMAND_COLDBOOT : std_logic_vector(0 to 3) := x"4";
constant SYSTEM_COMMAND_NOTUSED : std_logic_vector(0 to 3) := x"8";
-- misc constants
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant TIMEOUT_CYCLES : natural := 4; -- clock cycles to wait before suppressing timeouts
-- Thread manager commandes
-- TODO: Thread manager commands should be replaced by an external file
constant THREAD_MANAGER_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant THREAD_MANAGER_READ_THREAD : std_logic_vector(0 to 5) := "000011";
-- bram interface signals
signal wea : std_logic := '0';
signal ena : std_logic := '0';
signal addra : std_logic_vector(0 to 12) := (others => '0');
signal dia : std_logic_vector(0 to 31) := (others => '0');
signal doa : std_logic_vector(0 to 31);
signal web : std_logic := '0';
signal enb : std_logic := '0';
signal addrb : std_logic_vector(0 to 12) := (others => '0');
signal dib : std_logic_vector(0 to 31) := (others => '0');
signal dob : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- State Machine States
---------------------------------------------------------------------------
type hwti_system_state is (
START,
IDLE,
COMMAND_RESET_INIT,
COMMAND_RESET_END_BUS_TRANSACTION_WAIT,
COMMAND_RUN_INIT,
GLOBAL_READ_WAIT,
GLOBAL_READ_RESPOND,
END_BUS_TRANSACTION,
END_BUS_TRANSACTION_WAIT);
type hwti_user_state is (
START,
NOT_USED,
RESET_MALLOC_TABLE,
NOT_USED_WAIT,
USED,
USED_WAIT,
RUNNING,
USER_FUNCTION_CALL,
USER_FUNCTION_CALL_2,
USER_FUNCTION_RETURN,
USER_FUNCTION_RETURN_2,
USER_FUNCTION_RETURN_3,
--LIB_FUNCTION_MEMCPY,
--LIB_FUNCTION_MEMCPY_2,
--LIB_FUNCTION_MEMCPY_3,
--LIB_FUNCTION_MEMCPY_4,
--LIB_FUNCTION_MEMCPY_5,
--LIB_FUNCTION_MEMCPY_6,
--LIB_FUNCTION_FREE,
--LIB_FUNCTION_FREE_1,
--LIB_FUNCTION_FREE_2,
--LIB_FUNCTION_FREE_3,
--LIB_FUNCTION_CALLOC,
--LIB_FUNCTION_CALLOC_2,
--LIB_FUNCTION_CALLOC_3,
--LIB_FUNCTION_CALLOC_4,
--LIB_FUNCTION_CALLOC_5,
--LIB_FUNCTION_MALLOC,
--LIB_FUNCTION_MALLOC_8a,
--LIB_FUNCTION_MALLOC_8b,
--LIB_FUNCTION_MALLOC_8c,
--LIB_FUNCTION_MALLOC_32a,
--LIB_FUNCTION_MALLOC_32b,
--LIB_FUNCTION_MALLOC_32c,
--LIB_FUNCTION_MALLOC_1024a,
--LIB_FUNCTION_MALLOC_1024b,
--LIB_FUNCTION_MALLOC_1024c,
--LIB_FUNCTION_MALLOC_UNLIMITa,
--LIB_FUNCTION_MALLOC_UNLIMITb,
--LIB_FUNCTION_MALLOC_UNLIMITc,
OVERFLOW,
HTHREAD_RPC,
HTHREAD_RPC_2,
HTHREAD_RPC_3,
HTHREAD_RPC_3a,
HTHREAD_RPC_4,
HTHREAD_RPC_5,
HTHREAD_RPC_6,
HTHREAD_RPC_7,
HTHREAD_RPC_7a,
HTHREAD_RPC_8,
HTHREAD_RPC_8a,
HTHREAD_RPC_9,
HTHREAD_RPC_10,
HTHREAD_RPC_11,
HTHREAD_RPC_12,
HTHREAD_RPC_13,
HTHREAD_RPC_14,
HTHREAD_RPC_15,
HTHREAD_RPC_15a,
HTHREAD_RPC_16,
HTHREAD_RPC_17,
HTHREAD_RPC_17a,
HTHREAD_RPC_18,
HTHREAD_RPC_19,
HTHREAD_RPC_19a,
HTHREAD_RPC_20,
HTHREAD_RPC_20a,
HTHREAD_RPC_21,
HTHREAD_RPC_22,
HTHREAD_RPC_23,
HTHREAD_RPC_24,
--HTHREAD_ATTR_INIT,
--HTHREAD_ATTR_INIT_2,
--HTHREAD_ATTR_INIT_3,
--HTHREAD_ATTR_INIT_4,
--HTHREAD_ATTR_INIT_5,
--HTHREAD_ATTR_INIT_6,
--HTHREAD_ATTR_INIT_7,
--HTHREAD_EQUAL,
--HTHREAD_EQUAL_2,
--HTHREAD_MUTEX_INIT,
--HTHREAD_MUTEX_INIT_2,
--HTHREAD_MUTEX_INIT_3,
--HTHREAD_MUTEX_INIT_4,
--HTHREAD_MUTEX_INIT_5,
--HTHREAD_MUTEX_INIT_6,
--HTHREAD_MUTEX_INIT_7,
--HTHREAD_MUTEXATTR_INIT,
--HTHREAD_MUTEXATTR_INIT_2,
--HTHREAD_MUTEXATTR_INIT_3,
--HTHREAD_MUTEXATTR_SETNUM,
--HTHREAD_MUTEXATTR_SETNUM_2,
--HTHREAD_MUTEXATTR_SETNUM_3,
--HTHREAD_MUTEXATTR_GETNUM,
--HTHREAD_MUTEXATTR_GETNUM_2,
--HTHREAD_MUTEXATTR_GETNUM_3,
--HTHREAD_MUTEXATTR_GETNUM_4,
--HTHREAD_MUTEX_UNLOCK,
--HTHREAD_MUTEX_UNLOCK_2,
--HTHREAD_MUTEX_UNLOCK_3,
--HTHREAD_MUTEX_TRYLOCK,
--HTHREAD_MUTEX_TRYLOCK_2,
--HTHREAD_MUTEX_TRYLOCK_3,
--HTHREAD_MUTEX_LOCK,
--HTHREAD_MUTEX_LOCK_2,
--HTHREAD_MUTEX_LOCK_3,
--HTHREAD_MUTEX_LOCK_4,
--HTHREAD_MUTEX_LOCK_5,
--HTHREAD_MUTEX_LOCK_6,
--HTHREAD_CONDATTR_INIT,
--HTHREAD_CONDATTR_INIT_2,
--HTHREAD_COND_WAIT,
--HTHREAD_COND_WAIT_2,
--HTHREAD_COND_WAIT_3,
--HTHREAD_COND_WAIT_4,
--HTHREAD_COND_WAIT_5,
--HTHREAD_COND_WAIT_6,
--HTHREAD_COND_WAIT_7,
--HTHREAD_COND_WAIT_7a,
--HTHREAD_COND_WAIT_8,
--HTHREAD_COND_INIT,
--HTHREAD_COND_INIT_2,
--HTHREAD_COND_INIT_3,
--HTHREAD_COND_INIT_4,
--HTHREAD_COND_INIT_5,
--HTHREAD_COND_INIT_6,
--HTHREAD_COND_SIGNAL,
--HTHREAD_COND_SIGNAL_2,
--HTHREAD_COND_SIGNAL_3,
--HTHREAD_COND_BCAST,
--HTHREAD_COND_BCAST_2,
--HTHREAD_COND_BCAST_3,
HTHREAD_EXIT,
HTHREAD_EXIT_2,
HTHREAD_EXIT_3,
WAIT_ONE_CYCLE,
POP_READ_PARAM_COUNT,
POP_READ_PARAM,
LOCAL_LOAD_RESPOND,
LOCAL_PARTIAL_LOAD,
LOCAL_PARTIAL_LOAD_1,
GLOBAL_LOAD_RETURN,
MASTER_LOAD_INIT,
MASTER_LOAD_WAIT_FOR_ACK,
MASTER_STORE_INIT,
MASTER_STORE_WAIT_FOR_ACK);
type system_request_type is (
NOOP,
CHANGE_STATUS_TO_USED,
CHANGE_STATUS_TO_RUN,
CHANGE_STATUS_TO_EXIT,
CHANGE_STATUS_TO_EXIT_ERROR,
CHANGE_STATUS_TO_EXIT_OVERFLOW,
CHANGE_STATUS_TO_BLOCK);
signal system_state, system_state_next: hwti_system_state := START;
signal user_state, user_state_next : hwti_user_state := START;
-- Registers for the System Level API
signal system_thread_id, system_thread_id_next : std_logic_vector(0 to 7);
signal system_command, system_command_next : std_logic_vector(0 to 3);
signal system_status, system_status_next : std_logic_vector(0 to 7);
signal system_argument, system_argument_next : std_logic_vector(0 to 31);
signal system_result, system_result_next : std_logic_vector(0 to 31);
-- Registers for the User Logic Level API
signal fromUser_address : std_logic_vector(0 to 31);
signal fromUser_value : std_logic_vector(0 to 31);
signal fromUser_function : std_logic_vector(0 to 15);
signal fromUser_opcode : std_logic_vector(0 to 5);
signal fromUserReg_address, fromUserReg_address_next : std_logic_vector(0 to 31);
signal fromUserReg_value, fromUserReg_value_next : std_logic_vector(0 to 31);
signal fromUserReg_function, fromUserReg_function_next : std_logic_vector(0 to 15);
signal fromUserReg_opcode, fromUserReg_opcode_next : std_logic_vector(0 to 5);
signal toUser_value, toUser_value_next : std_logic_vector(0 to 31);
signal toUser_address, toUser_address_next : std_logic_vector(0 to 31);
-- Local memory pointers
signal framePtr, framePtr_next : std_logic_vector(0 to 15);
signal stackPtr, stackPtr_next : std_logic_vector(0 to 15);
signal heapPtr, heapPtr_next : std_logic_vector(0 to 15);
signal paramCount, paramCount_next : std_logic_vector(0 to 7);
-- Temporary registers
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
-- Signals to help communicate with the system bus
signal data_address, data_address_next: std_logic_vector(0 to 31);
signal data_value, data_value_next: std_logic_vector(0 to 31);
-- Miscelaneous signals
signal cycle_count : std_logic_vector(0 to 7);
signal timer : std_logic_vector(0 to 31);
signal read_ce, write_ce : std_logic;
signal local_memory_access : std_logic;
signal stackHeapOverflow : std_logic;
signal system_request, system_request_next : system_request_type;
signal user_return_state, user_return_state_next : hwti_user_state;
signal bus_data_out, bus_data_out_next : std_logic_vector(0 to 31);
--signal debug_system, debug_system_next : std_logic_vector(0 to 31);
signal debug_user, debug_user_next : std_logic_vector(0 to 31);
------------------------------------------------------------------------
-- Functions
------------------------------------------------------------------------
------------------------------------------------------------------------
-- thread_manager_exit_thread
-- calculates the address to read to perform a exit_thread call to TM
-- TODO: move this to a common.vhd file in TM, and include it as a library
------------------------------------------------------------------------
function thread_manager_exit_thread_address( tm_base_address : in std_logic_vector;
data_width : in natural;
thread_bits : in natural;
thread_id : in std_logic_vector ) return std_logic_vector is
variable address : std_logic_vector(0 to data_width-1);
begin
address := tm_base_address;
address( data_width-thread_bits-2 to data_width-3 ) := thread_id;
address( data_width-thread_bits-8 to data_width-thread_bits-3 ) := THREAD_MANAGER_EXIT_THREAD;
return address;
end function;
------------------------------------------------------------------------
-- bit_set()
-- Determine if any bit in the array is set, if so, return 1
------------------------------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if ( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------------------------------
-- is_local_memory()
-- Determine if the passed in address lines is a reference to local memory
---------------------------------------------------------------------------
function is_local_memory( addr_lines : in std_logic_vector(0 to 31) ) return std_logic is
begin
if (addr_lines(0 to 15) = C_BASEADDR(0 to 15)
and addr_lines(16 to 29) >= GLOBAL_BASE_ADDR
and addr_lines(16 to 29) <= GLOBAL_HIGH_ADDR) then
return '1';
end if;
return '0';
end function;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture implementation
--bram instanciation
bram : bram_imp_dual port map(Bus2IP_Clk,addra,dia,doa,ena,wea,addrb,dib,dob,enb,web);
read_ce <= bit_set(Bus2IP_RdCE);
write_ce <= bit_set(Bus2IP_WrCE);
-- The next two processes work in conjunction with each other.
-- The objective is to raise the time out suppression line, if a bus transaction
-- will take longer than 8 clock cycles.
-- The CYCLE_PROC counts the number of cycles a bus transaction takes.
-- The CYCLE_CONTROL sets the timeout supporession high if going to exceed the 8 cycle count.
CYCLE_PROC : process ( Bus2IP_Clk, Bus2IP_CS ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if ( Bus2IP_CS = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_MstBE <= (others=> '1');
IP2Bus_Retry <= '0'; -- no retry
IP2Bus_Error <= '0'; -- no error
IP2Bus_PostedWrInh <= '0'; -- inhibit posted write
if cycle_count > TIMEOUT_CYCLES then
IP2Bus_ToutSup <= '1'; -- Suppress timeouts on the bus
else
IP2Bus_ToutSup <= '0'; -- Release the timeout suppress line
end if;
end process CYCLE_CONTROL;
---------------------------------------------------------------------------
-- Register Assignments
---------------------------------------------------------------------------
HWTI_STATE_PROCESS : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
system_thread_id <= system_thread_id_next;
system_command <= system_command_next;
system_status <= system_status_next;
system_argument <= system_argument_next;
system_result <= system_result_next;
fromUser_address <= thrd2intrfc_address;
fromUser_value <= thrd2intrfc_value;
fromUser_function <= thrd2intrfc_function;
fromUser_opcode <= thrd2intrfc_opcode;
fromUserReg_address <= fromUserReg_address_next;
fromUserReg_value <= fromUserReg_value_next;
fromUserReg_function <= fromUserReg_function_next;
fromUserReg_opcode <= fromUserReg_opcode_next;
local_memory_access <= is_local_memory( thrd2intrfc_address );
toUser_address <= toUser_address_next;
toUser_value <= toUser_value_next;
bus_data_out <= bus_data_out_next;
IP2Bus_Data <= bus_data_out_next;
system_request <= system_request_next;
user_return_state <= user_return_state_next;
data_address <= data_address_next;
data_value <= data_value_next;
framePtr <= framePtr_next;
stackPtr <= stackPtr_next;
heapPtr <= heapPtr_next;
paramCount <= paramCount_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--debug_system <= debug_system_next;
debug_user <= debug_user_next;
if ( Bus2IP_Reset = '1'
or system_command_next = SYSTEM_COMMAND_RESET ) then
system_state <= START;
user_state <= START;
else
system_state <= system_state_next;
if ( stackHeapOverflow = '1' ) then
user_state <= OVERFLOW;
else
user_state <= user_state_next;
end if;
end if;
end if;
end process HWTI_STATE_PROCESS;
-----------------------------------------------------------------------
-- HWTI_TIMER
-- Process to count the number of clock cycles the HWT is running for.
-- Starts counting when a RUN command is issued, ends counting when
-- status changes to exit.
-----------------------------------------------------------------------
HWTI_TIMER : process (Bus2IP_Clk) is
begin
if ( Bus2IP_Clk'event and (Bus2IP_Clk = '1') ) then
case system_status is
when SYSTEM_STATUS_NOT_USED =>
timer <= Z32;
when SYSTEM_STATUS_USED =>
timer <= Z32;
when SYSTEM_STATUS_RUNNING =>
timer <= timer + x"00000001";
when SYSTEM_STATUS_BLOCKED =>
timer <= timer + x"00000001";
when others =>
--do nothing
end case;
end if;
end process HWTI_TIMER;
---------------------------------------------------------------------------
-- Stack and Heap Overflow Detection
-- Check that the stack does not grow larger than the heap
-- or the heap does not grow into the stack
---------------------------------------------------------------------------
STACK_HEAP_OVERFLOW_DETECTION : process (Bus2IP_Clk) is
begin
if ( system_status = SYSTEM_STATUS_RUNNING
and stackPtr >= heapPtr ) then
stackHeapOverflow <= '1';
else
stackHeapOverflow <= '0';
end if;
end process STACK_HEAP_OVERFLOW_DETECTION;
---------------------------------------------------------------------------
-- System Bus Controller State Machine
---------------------------------------------------------------------------
HWTI_SYSTEM_STATE_MACHINE : process (Bus2IP_Clk) is
begin
-- Default bus output signal assignments
IP2Bus_Ack <= '0'; -- pulse(010) to end bus transaction
-- default bram port A signals
addra <= (others => '0');
dia <= (others => '0');
ena <= '0';
wea <= '0';
-- Default register assignments
system_state_next <= system_state;
system_thread_id_next <= system_thread_id;
system_command_next <= system_command;
system_status_next <= system_status;
system_argument_next <= system_argument;
bus_data_out_next <= bus_data_out;
--debug_system_next <= debug_system;
-- The state machine
case system_state is
when START =>
--Set initial values for important signals
system_thread_id_next <= Z32(0 to 7);
system_command_next <= SYSTEM_COMMAND_INIT;
system_status_next <= SYSTEM_STATUS_NOT_USED;
system_argument_next <= Z32;
system_state_next <= IDLE;
bus_data_out_next <= Z32;
--debug_system_next <= Z32;
when IDLE =>
if ( write_ce = '1' ) then
-- System is writing something to HWT
case reg_address is
when REG_THREAD_ID =>
-- system is trying to set the thread id
-- may only be written to when status is NOT_USED
if ( system_status = SYSTEM_STATUS_NOT_USED ) then
system_thread_id_next <= Bus2IP_Data(24 to 31);
end if;
system_state_next <= END_BUS_TRANSACTION;
when REG_COMMAND =>
case Bus2IP_Data(28 to 31) is
-- Note that you can not write a system command init.
when SYSTEM_COMMAND_RUN => system_state_next <= COMMAND_RUN_INIT;
when SYSTEM_COMMAND_RESET => system_state_next <= COMMAND_RESET_INIT;
when others => system_state_next <= END_BUS_TRANSACTION; -- do nothing if unreconized command
end case;
when REG_ARGUMENT =>
case system_status is
when SYSTEM_STATUS_USED =>
--set the argument register
system_argument_next <= Bus2IP_Data;
--set the value on the stack
addra <= GLOBAL_BASE_ADDR(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
when others =>
--do nothing
end case;
system_state_next <= END_BUS_TRANSACTION;
when REG_MASTER_READ =>
-- When the controller is doing a Bus Master Read, the data
-- from the bus, when its read, will be placed here. I think,
-- actually not wholy sure why this state is needed.
bus_data_out_next <= Z32;
system_state_next <= END_BUS_TRANSACTION;
when REG_RPC_MUTEXCONVAR =>
addra <= REG_RPC_MUTEXCONVAR(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
when REG_RPC_T_ADDRESS =>
addra <= REG_RPC_T_ADDRESS(1 to 13);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
when others =>
if (reg_address >= GLOBAL_BASE_ADDR and reg_address <= GLOBAL_HIGH_ADDR) then
-- System is requesting to write to the shard global address space
-- internal to the HWTI
addra <= Bus2IP_Addr(17 to 29);
dia <= Bus2IP_Data;
ena <= '1';
wea <= '1';
system_state_next <= END_BUS_TRANSACTION;
else
-- User is requesting to write to a register that can't be written to
-- Do nothing and ack the bus
system_state_next <= END_BUS_TRANSACTION;
end if;
end case;
elsif ( read_ce = '1' ) then
-- System is reading something from HWT
case reg_address is
when REG_THREAD_ID =>
bus_data_out_next <= Z32(0 to 23) & system_thread_id;
system_state_next <= END_BUS_TRANSACTION;
when REG_COMMAND =>
bus_data_out_next <= Z32(0 to 27) & system_command;
system_state_next <= END_BUS_TRANSACTION;
when REG_STATUS =>
bus_data_out_next <= Z32(0 to 23) & system_status;
system_state_next <= END_BUS_TRANSACTION;
when REG_ARGUMENT =>
bus_data_out_next <= system_argument;
system_state_next <= END_BUS_TRANSACTION;
when REG_RESULT =>
bus_data_out_next <= system_result;
system_state_next <= END_BUS_TRANSACTION;
when REG_MASTER_WRITE =>
-- When the controller is doing a Bus Master Write, need to
-- provide, to the bus, the data to write.
bus_data_out_next <= data_value;
system_state_next <= END_BUS_TRANSACTION;
-- when REG_DEBUG_SYSTEM =>
-- bus_data_out_next <= debug_system;
-- system_state_next <= END_BUS_TRANSACTION;
when REG_DEBUG_USER =>
bus_data_out_next <= debug_user;
system_state_next <= END_BUS_TRANSACTION;
when REG_TIMER =>
bus_data_out_next <= timer;
system_state_next <= END_BUS_TRANSACTION;
when REG_FRAMEPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & framePtr;
system_state_next <= END_BUS_TRANSACTION;
when REG_STACKPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & stackPtr;
system_state_next <= END_BUS_TRANSACTION;
when REG_HEAPPTR =>
bus_data_out_next <= C_BASEADDR(0 to 15) & heapPtr;
system_state_next <= END_BUS_TRANSACTION;
when others =>
-- The address space that is readable from the bus is 4 Words larger than
-- the space that is writable. This is because, the dynamic memory
-- allocation tables is readable for debug purposes.
if (reg_address >= GLOBAL_BASE_ADDRREADABLE and reg_address <= GLOBAL_HIGH_ADDR) then
--debug_system_next <= --debug_system or x"00000010";
-- System is requesting to read to the shard global address space
-- internal to the HWTI
addra <= Bus2IP_Addr(17 to 29);
ena <= '1';
system_state_next <= GLOBAL_READ_WAIT;
else
--debug_system_next <= --debug_system or x"00000020";
-- Theoritically this case shouldn't happen. But what ever, return all zeros.
bus_data_out_next <= Z32;
system_state_next <= END_BUS_TRANSACTION;
end if;
end case;
else
-- Nothing is coming in off of the bus. Check to see if the
-- controller has anything for us to do.
case system_request is
when CHANGE_STATUS_TO_USED =>
system_status_next <= SYSTEM_STATUS_USED;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_RUN =>
system_status_next <= SYSTEM_STATUS_RUNNING;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT =>
system_status_next <= SYSTEM_STATUS_EXITED;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT_ERROR =>
system_status_next <= SYSTEM_STATUS_EXITED_ERROR;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_EXIT_OVERFLOW =>
system_status_next <= SYSTEM_STATUS_EXITED_OVERFLOW;
system_state_next <= IDLE;
when CHANGE_STATUS_TO_BLOCK =>
system_status_next <= SYSTEM_STATUS_BLOCKED;
system_command_next <= SYSTEM_COMMAND_INIT; -- CHANGE ME ... maybe
system_state_next <= IDLE;
when NOOP =>
system_state_next <= IDLE;
end case;
end if;
when COMMAND_RESET_INIT =>
-- A RESET can be issued at anytime. Although, it should
-- really only be called once a thread has exited.
-- NOTE: A reset command has to be handled carefully. If we reset
-- immediatly (ie use the regular END_BUS_TRANSACTION), we will
-- get a OPB bus error, b/c the HWTI would reset before acking the bus
IP2Bus_Ack <= '1';
system_state_next <= COMMAND_RESET_END_BUS_TRANSACTION_WAIT;
when COMMAND_RESET_END_BUS_TRANSACTION_WAIT =>
-- Wait for the bus to deassert the Rd or Wr chip enable lines
if ( read_ce='0' and write_ce='0' ) then
system_command_next <= SYSTEM_COMMAND_RESET;
system_state_next <= IDLE;
bus_data_out_next <= Z32;
else
system_state_next <= system_state;
end if;
when COMMAND_RUN_INIT =>
-- For the system to issue a RUN command, status must be USED or BLOCKED
-- BLOCKED, or IDLE
case system_status is
when SYSTEM_STATUS_USED =>
--debug_system_next <= --debug_system or x"00000001";
system_command_next <= SYSTEM_COMMAND_RUN;
when SYSTEM_STATUS_BLOCKED =>
--debug_system_next <= --debug_system or x"00000002";
system_command_next <= SYSTEM_COMMAND_RUN;
when others =>
--debug_system_next <= --debug_system or x"00000004";
system_state_next <= END_BUS_TRANSACTION;
end case;
system_state_next <= END_BUS_TRANSACTION;
when GLOBAL_READ_WAIT =>
-- wait one clock cycle per the requirements of bram
system_state_next <= GLOBAL_READ_RESPOND;
when GLOBAL_READ_RESPOND =>
-- return to the system the data it requested
bus_data_out_next <= doa;
system_state_next <= END_BUS_TRANSACTION;
when END_BUS_TRANSACTION =>
-- Put the data on the bus, and 'ack' the bus.
IP2Bus_Ack <= '1';
system_state_next <= END_BUS_TRANSACTION_WAIT;
when END_BUS_TRANSACTION_WAIT =>
-- Wait for the bus to deassert the Rd or Wr chip enable lines
if ( read_ce='0' and write_ce='0' ) then
system_state_next <= IDLE;
bus_data_out_next <= Z32;
else
system_state_next <= system_state;
end if;
end case;
end process HWTI_SYSTEM_STATE_MACHINE;
-----------------------------------------------------------------------
-- The following state machine controls the HWTI, in particular does the bus master things
-----------------------------------------------------------------------
HWTI_USER_STATE_MACHINE : process (Bus2IP_clk) is
begin
-- Default register assignments for bus master signals
IP2Bus_Retry <= '0';
IP2Bus_Error <= '0';
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
IP2Bus_MstBusLock <= '0';
IP2Bus_MstBurst <= '0';
IP2Bus_Addr <= (others => '0');
IP2IP_Addr <= (others => '0');
-- Default register assignments for internal signals
user_state_next <= user_state;
system_request_next <= system_request;
system_result_next <= system_result;
user_return_state_next <= user_return_state;
data_address_next <= data_address;
data_value_next <= data_value;
debug_user_next <= debug_user;
-- Default register assignments for user interface registers
fromUserReg_address_next <= fromUserReg_address;
fromUserReg_value_next <= fromUserReg_value;
fromUserReg_opcode_next <= fromUserReg_opcode;
fromUserReg_function_next <= fromUserReg_function;
intrfc2thrd_address <= toUser_address;
intrfc2thrd_value <= toUser_value;
intrfc2thrd_function <= FUNCTION_USER_SELECT;
intrfc2thrd_goWait <= '0';
toUser_address_next <= toUser_address;
toUser_value_next <= toUser_value;
-- Default register assignment for memory pointers
framePtr_next <= framePtr;
stackPtr_next <= stackPtr;
heapPtr_next <= heapPtr;
paramCount_next <= paramCount;
-- Temporary registers for library functions
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
-- Default assignments for bram port B
addrb <= (others => '0');
enb <= '0';
web <= '0';
dib <= (others => '0');
case user_state is
-----------------------------------------------------------------------
-- States START through USED_WAIT are used to make sure the hthread
-- system sets the thread_id and command register in the correct sequence
-----------------------------------------------------------------------
when START =>
user_state_next <= NOT_USED;
system_request_next <= NOOP;
system_result_next <= Z32;
user_return_state_next <= RUNNING;
data_address_next <= Z32;
data_value_next <= Z32;
intrfc2thrd_address <= Z32;
intrfc2thrd_value <= Z32;
intrfc2thrd_function <= FUNCTION_RESET;
intrfc2thrd_goWait <= '1';
toUser_address_next <= Z32;
toUser_value_next <= Z32;
fromUserReg_address_next <= Z32;
fromUserReg_value_next <= Z32;
fromUserReg_function_next <= FUNCTION_RESET;
fromUserReg_opcode_next <= OPCODE_NOOP;
debug_user_next <= Z32;
heapPtr_next <= x"7600"; --The initial heap ptr takes into account the pre-allocated chunks of memory for malloc
reg1_next <= Z32;
reg2_next <= Z32;
reg3_next <= Z32;
reg4_next <= Z32;
when NOT_USED =>
-- Wait for the thread id to be set by the system
case system_thread_id is
when x"00" =>
user_state_next <= NOT_USED;
--Set up the memory pointers and stack frame for use
framePtr_next <= (GLOBAL_BASE_ADDR + 4) & "00";
stackPtr_next <= (GLOBAL_BASE_ADDR + 4) & "00";
--Base addr + 1 = number of parameters in call, which for thread create is always 1
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 1);
enb <= '1';
web <= '1';
dib <= Z32(0 to 30) & '1';
paramCount_next <= x"00";
-- Stop the HWTUL's reset state
intrfc2thrd_goWait <= '0';
when others =>
user_state_next <= RESET_MALLOC_TABLE;
reg1_next <= x"00000001";
system_request_next <= CHANGE_STATUS_TO_USED;
end case;
when RESET_MALLOC_TABLE =>
-- When a thread starts, need to reset malloc table
case reg1 is
when x"00000001" =>
addrb <= REG_8B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000002";
user_state_next <= RESET_MALLOC_TABLE;
when x"00000002" =>
addrb <= REG_32B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000003";
user_state_next <= RESET_MALLOC_TABLE;
when x"00000003" =>
addrb <= REG_1024B_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= x"00000004";
user_state_next <= RESET_MALLOC_TABLE;
when others =>
addrb <= REG_UNLIMITED_DYNAMIC_TABLE(1 to 13);
enb <= '1';
web <= '1';
dib <= Z32;
reg1_next <= Z32;
user_state_next <= NOT_USED_WAIT;
end case;
when NOT_USED_WAIT =>
-- Wait for the system state machine to change to used status
case system_status is
when SYSTEM_STATUS_USED =>
system_request_next <= NOOP;
user_state_next <= USED;
--Continue to set up strack frame
--base addr + 2 = return address for frame ptr, which for thread create is always, by design, 0000
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 2);
enb <= '1';
web <= '1';
dib <= Z32;
when others =>
user_state_next <= NOT_USED_WAIT;
end case;
when USED =>
-- Wait for a RUN command
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= USED_WAIT;
--Continue (again) to set up the stack frame
--base addr + 3 = return state, which for thread create is always, by design 0000
addrb <= (GLOBAL_BASE_ADDR(1 to 13) + 3);
enb <= '1';
web <= '1';
dib <= Z32;
when others =>
user_state_next <= USED;
end case;
when USED_WAIT =>
-- Wait for system state machines to update status register
case system_status is
when SYSTEM_STATUS_RUNNING =>
system_request_next <= NOOP;
intrfc2thrd_function <= FUNCTION_START;
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when others =>
user_state_next <= USED_WAIT;
end case;
-----------------------------------------------------------------------
-- Once the user_state machine reaches RUNNING, the thread has been
-- created and is expected to run. The RUNNING state waits for the
-- user thread to request an opperation. Once an opperation is
-- requested, it starts to act on it. By default, the HWTI tells the user logic
-- to do its own thing, ie FUNCTION_USER_SELECT.
-----------------------------------------------------------------------
when RUNNING =>
fromUserReg_address_next <= fromUser_address;
fromUserReg_value_next <= fromUser_value;
fromUserReg_function_next <= fromUser_function;
fromUserReg_opcode_next <= fromUser_opcode;
-- Find out what the HWTUL is requesting, if anything
case fromUser_opcode is
--------------------------------------------------------------
-- Memory sub-interface
--------------------------------------------------------------
when OPCODE_LOAD =>
if (fromUser_address(0 to 15) = C_BASEADDR(0 to 15)) then
-- HWTUL is requesting to read an address in BRAM
addrb <= fromUser_address(17 to 29);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
-- Check for a non-word-aligned read
case fromUser_address(30 to 31) is
when "00" =>
user_return_state_next <= LOCAL_LOAD_RESPOND;
when OTHERS =>
user_return_state_next <= LOCAL_PARTIAL_LOAD;
end case;
else
-- HWTUL is requesting to read an address from global address space
data_address_next <= fromUser_address;
user_return_state_next <= GLOBAL_LOAD_RETURN;
user_state_next <= MASTER_LOAD_INIT;
end if;
when OPCODE_STORE =>
if (fromUser_address(0 to 15) = C_BASEADDR(0 to 15)) then
-- HWTUL is requestiong to write an address in BRAM
addrb <= fromUser_address(17 to 29);
dib <= fromUser_value;
web <= '1';
enb <= '1';
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
else
-- HWTUL is requestiong to write an address in global address space
data_address_next <= fromUser_address;
data_value_next <= fromUser_value;
user_state_next <= MASTER_STORE_INIT;
user_return_state_next <= GLOBAL_LOAD_RETURN;
end if;
when OPCODE_DECLARE =>
-- increment the stack ptr the number of words the UL is declaring
-- TODO: check to see that param=0. If not that means the user has called push and shouldn't be calling declare again until after a function call and return.
stackPtr_next <= '0' & (stackPtr(1 to 13) + fromUser_value(19 to 31)) & "00";
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when OPCODE_READ =>
-- read the stack, based on frame ptr offset, provided by user
addrb <= framePtr(1 to 13) + fromUser_address(19 to 31);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LOCAL_LOAD_RESPOND;
when OPCODE_WRITE =>
-- write to the stack, based on frame ptr offset, provided by user
addrb <= framePtr(1 to 13) + fromUser_address(19 to 31);
dib <= fromUser_value;
web <= '1';
enb <= '1';
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when OPCODE_ADDRESSOF =>
-- return to the user frame ptr + offset
intrfc2thrd_address <= C_BASEADDR(0 to 15)
& "00"
& (framePtr(2 to 13) + fromUser_address(20 to 31))
& "00";
toUser_address_next <= C_BASEADDR(0 to 15)
& "00"
& (framePtr(2 to 13) + fromUser_address(20 to 31))
& "00";
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
--------------------------------------------------------------
-- Function sub-interface
--------------------------------------------------------------
when OPCODE_PUSH =>
-- Place the argument where the stack pointer is now, and then increment sp
addrb <= stackPtr(1 to 13);
dib <= fromUser_value;
enb <= '1';
web <= '1';
paramCount_next <= paramCount + 1;
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when OPCODE_POP =>
-- Read the number of parameters on the stack for the current function
addrb <= framePtr(1 to 13) - 3 ;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= POP_READ_PARAM_COUNT;
when OPCODE_CALL =>
case fromUser_function is
-- when FUNCTION_HTHREAD_ATTR_INIT =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously allocated thread attr struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_ATTR_INIT;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_ATTR_DESTROY =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously allocated thread attr struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_ATTR_INIT;
-- -- Note that I'm reusing the ATTR_INIT state
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
when FUNCTION_HTHREAD_CREATE =>
debug_user_next <= x"40000000";
-- Need to call the RPC code
-- Set reg1 to the opcode
reg1_next <= Z32(0 to 15) & FUNCTION_HTHREAD_CREATE;
-- Read the value of the mutex and condvar numbers
addrb <= REG_RPC_MUTEXCONVAR(1 to 13);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC;
when FUNCTION_HTHREAD_JOIN =>
debug_user_next <= x"80000000";
-- Need to call the RPC code
-- Set reg1 to the opcode
reg1_next <= Z32(0 to 15) & FUNCTION_HTHREAD_JOIN;
-- Read the value of the mutex and condvar numbers
addrb <= REG_RPC_MUTEXCONVAR(1 to 13);
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC;
-- when FUNCTION_HTHREAD_SELF =>
-- -- return the thread id to the user
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_value <= Z32(0 to 23) & system_thread_id;
-- toUser_value_next <= Z32(0 to 23) & system_thread_id;
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_YIELD =>
-- -- return to the user immediatly
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_EQUAL =>
-- --read the second paramter the user pushed
-- --which should be a hthread_t (which is the same as an int)
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_EQUAL;
when FUNCTION_HTHREAD_EXIT =>
system_request_next <= CHANGE_STATUS_TO_EXIT;
user_state_next <= HTHREAD_EXIT;
-- when FUNCTION_HTHREAD_EXIT_ERROR =>
-- system_request_next <= CHANGE_STATUS_TO_EXIT_ERROR;
-- user_state_next <= HTHREAD_EXIT;
-- when FUNCTION_HTHREAD_MUTEXATTR_INIT =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously allocated mutexattr struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEXATTR_INIT;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_MUTEXATTR_DESTROY =>
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- -- return a SUCCESS to the user
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_MUTEXATTR_SETNUM =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be mutexattr struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM;
-- when FUNCTION_HTHREAD_MUTEXATTR_GETNUM =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be mutexattr struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM;
-- when FUNCTION_HTHREAD_MUTEX_INIT =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be mutex struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEX_INIT;
-- when FUNCTION_HTHREAD_MUTEX_DESTROY =>
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- -- return a SUCCESS to the user
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_MUTEX_LOCK =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously initialized mutex struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEX_LOCK;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_MUTEX_UNLOCK =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously initialized mutex struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEX_UNLOCK;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_MUTEX_TRYLOCK =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously initialized mutex struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEX_TRYLOCK;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_CONDATTR_INIT =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously allocated condattr struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_CONDATTR_INIT;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_CONDATTR_DESTROY =>
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- -- return a SUCCESS to the user
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_CONDATTR_SETNUM =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be condattr struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- --Note that I am reusing the states for MUTEXATTR_GETNUM
-- user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM;
-- when FUNCTION_HTHREAD_CONDATTR_GETNUM =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be condattr struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- --Note that I am reusing the states for MUTEXATTR_GETNUM
-- user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM;
-- when FUNCTION_HTHREAD_COND_INIT =>
-- -- Read the second parameter the user pushed in
-- -- Parameter should be mutex struct address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_INIT;
-- when FUNCTION_HTHREAD_COND_DESTROY =>
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- -- return a SUCCESS to the user
-- intrfc2thrd_function <= fromUser_value(16 to 31);
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when FUNCTION_HTHREAD_COND_WAIT =>
-- -- Read the the first parameter the user passed in
-- -- Parameter should be previously initialized cond var struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_WAIT;
-- when FUNCTION_HTHREAD_COND_BROADCAST =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously initialized cond var struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_BCAST;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_HTHREAD_COND_SIGNAL =>
-- -- Read the parameter the user passed in
-- -- Parameter should be previously initialized cond var struct's address
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_SIGNAL;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
---------------------------------------------------------
-- stdlib.h functions
---------------------------------------------------------
-- when FUNCTION_MALLOC =>
-- User wants to allocate memory on the heap
-- Read the parameter the user (should have) passed in
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MALLOC;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when FUNCTION_CALLOC =>
-- -- User wants to allocate memory on the heap
-- -- Read the first parameter the user passed in
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_CALLOC;
-- when FUNCTION_FREE =>
-- -- User wants to de-allocate memory on the heap
-- -- Read the address of the data the user passed in
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_FREE;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
---------------------------------------------------------
-- string.h functions
---------------------------------------------------------
-- when FUNCTION_MEMCPY =>
-- -- Copy data from *dest to *src, with size n
-- -- read the first parameter *dest
-- addrb <= stackPtr(1 to 13) - 1;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
---------------------------------------------------------
-- User defined functions
---------------------------------------------------------
when others =>
-- first write the number of params to the stack
addrb <= stackPtr(1 to 13);
dib <= Z32(0 to 23) & paramCount;
enb <= '1';
web <= '1';
-- update the stack ptr and reset the num of params
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
paramCount_next <= x"00";
user_state_next <= USER_FUNCTION_CALL;
end case;
when OPCODE_RETURN =>
-- user is returning from an internal function
-- set the return value
intrfc2thrd_value <= fromUser_value;
toUser_value_next <= fromUser_value;
-- read the HWTUL return state
addrb <= framePtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN;
when others => -- ie noop
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
end case;
-----------------------------------------------------------------------
-- LIB FUNCTION MEMCPY
-- memcpy( void *dest, const void *src, size_t n )
-- Copy memory from dest to src, with size n
-- TODO use burst transacations instead of single transactions
-----------------------------------------------------------------------
-- when LIB_FUNCTION_MEMCPY =>
-- -- reg1 is the destination pointer
-- reg1_next <= dob;
-- -- read the source pointer from the stack
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY_2;
-- when LIB_FUNCTION_MEMCPY_2 =>
-- -- reg2 is the source pointer
-- reg2_next <= dob;
-- -- read the size n from the stack
-- addrb <= stackPtr(1 to 13) - 3;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY_3;
-- when LIB_FUNCTION_MEMCPY_3 =>
-- -- reg3 is the number of bytes to copy
-- -- force the number of bytes to copy to be increment of 4
-- reg3_next <= dob(0 to 29) & "00";
-- -- decrement the stack pointer 3 words
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 3) & "00";
-- -- reg4 will track if the to and from address are local or global
-- -- specifically reg4(0) is source, reg4(1) is destination
-- -- a 1 means the address is local, 0 means global
-- if ( reg2(0 to 15) = C_BASEADDR(0 to 15) ) then
-- reg4_next(0) <= '1';
-- else
-- reg4_next(0) <= '0';
-- end if;
-- if ( reg1(0 to 15) = C_BASEADDR(0 to 15) ) then
-- reg4_next(1) <= '1';
-- else
-- reg4_next(1) <= '0';
-- end if;
-- user_state_next <= LIB_FUNCTION_MEMCPY_4;
-- when LIB_FUNCTION_MEMCPY_4 =>
-- case reg3 is
-- when Z32 =>
-- -- all data is copied, return to user
-- intrfc2thrd_function <= fromUserReg_value(16 to 31);
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when others =>
-- -- there is more to read
-- -- initiate read of address stored in reg2, source of data
-- -- Determine if the address is local
-- case reg4(0) is
-- when '1' =>
-- -- read from local
-- enb <= '1';
-- addrb <= reg2(17 to 29);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY_5;
-- when others =>
-- -- read from local
-- data_address_next <= reg2;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY_5;
-- user_state_next <= MASTER_LOAD_INIT;
-- end case;
-- end case;
--
-- when LIB_FUNCTION_MEMCPY_5 =>
-- -- initiate write of data to address stored in reg1
-- -- Determine if the address is local
-- case reg4(1) is
-- when '1' =>
-- -- write to local
-- enb <= '1';
-- web <= '1';
-- addrb <= reg1(17 to 29);
-- -- if the previous read was local pull from dob, instead of data_value
-- case reg4(0) is
-- when '1' =>
-- dib <= dob;
-- when others =>
-- dib <= data_value;
-- end case;
-- user_state_next <= LIB_FUNCTION_MEMCPY_6;
-- when others =>
-- -- write to global
-- data_address_next <= reg1;
-- -- if the previous read was local pull from dob, instead of data_value
-- case reg4(0) is
-- when '1' =>
-- data_value_next <= dob;
-- when others =>
-- data_value_next <= data_value;
-- end case;
-- user_return_state_next <= LIB_FUNCTION_MEMCPY_6;
-- user_state_next <= MASTER_STORE_INIT;
-- end case;
-- when LIB_FUNCTION_MEMCPY_6 =>
-- -- increment the pointers
-- reg1_next <= reg1 + 4;
-- reg2_next <= reg2 + 4;
-- -- decrement the count one word
-- reg3_next <= reg3 - 4;
-- user_state_next <= LIB_FUNCTION_MEMCPY_4;
-----------------------------------------------------------------------
-- LIB FUNCTION FREE
-- free(void * address);
-- de-allocates space on the heap, specified by passed in parameter
-----------------------------------------------------------------------
-- when LIB_FUNCTION_FREE =>
-- -- Record the address of the data to deallocate
-- reg1_next <= dob;
-- user_state_next <= LIB_FUNCTION_FREE_1;
-- when LIB_FUNCTION_FREE_1 =>
-- -- The following is a lookup table for determine which mask to use
-- user_state_next <= LIB_FUNCTION_FREE_2;
-- case reg1(16 to 31) is
-- when x"7FF8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"7FFFFFFF";
-- when x"7FF0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"BFFFFFFF";
-- when x"7FE8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"DFFFFFFF";
-- when x"7FE0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"EFFFFFFF";
-- when x"7FD8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"F7FFFFFF";
-- when x"7FD0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FBFFFFFF";
-- when x"7FC8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FDFFFFFF";
-- when x"7FC0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FEFFFFFF";
-- when x"7FB8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FF7FFFFF";
-- when x"7FB0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFBFFFFF";
-- when x"7FA8" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFDFFFFF";
-- when x"7FA0" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFEFFFFF";
-- when x"7F98" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFF7FFFF";
-- when x"7F90" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFBFFFF";
-- when x"7F88" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFDFFFF";
-- when x"7F80" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFEFFFF";
-- when x"7F78" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFF7FFF";
-- when x"7F70" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFBFFF";
-- when x"7F68" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFDFFF";
-- when x"7F60" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFEFFF";
-- when x"7F58" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFF7FF";
-- when x"7F50" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFBFF";
-- when x"7F48" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFDFF";
-- when x"7F40" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFEFF";
-- when x"7F38" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFF7F";
-- when x"7F30" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFBF";
-- when x"7F28" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFDF";
-- when x"7F20" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFEF";
-- when x"7F18" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFF7";
-- when x"7F10" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFFB";
-- when x"7F08" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFFD";
-- when x"7F00" =>
-- reg2_next <= Z32(0 to 15) & REG_8B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FFFFFFFE";
-- when x"7EE0" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"7FFFFFFF";
-- when x"7EC0" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"BFFFFFFF";
-- when x"7EA0" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"DFFFFFFF";
-- when x"7E80" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"EFFFFFFF";
-- when x"7E60" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"F7FFFFFF";
-- when x"7E40" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FBFFFFFF";
-- when x"7E20" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FDFFFFFF";
-- when x"7E00" =>
-- reg2_next <= Z32(0 to 15) & REG_32B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"FEFFFFFF";
-- when x"7A00" =>
-- reg2_next <= Z32(0 to 15) & REG_1024B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"7FFFFFFF";
-- when x"7600" =>
-- reg2_next <= Z32(0 to 15) & REG_1024B_DYNAMIC_TABLE & "00";
-- reg3_next <= x"BFFFFFFF";
-- when others =>
-- -- should be the unlimited case
-- -- TODO check to make sure the user is de allocating this space
-- -- and not some random address
-- reg2_next <= Z32(0 to 15) & REG_UNLIMITED_DYNAMIC_TABLE & "00";
-- reg3_next <= Z32;
-- -- deallocate the space on the heap
-- heapPtr_next <= x"7600";
-- end case;
-- when LIB_FUNCTION_FREE_2 =>
-- enb <= '1';
-- addrb <= reg2(17 to 29);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_FREE_3;
-- when LIB_FUNCTION_FREE_3 =>
-- -- Mark the space as deallocated
-- enb <= '1';
-- web <= '1';
-- addrb <= reg2(17 to 29);
-- dib <= dob and reg3;
-- -- Return to the user
-- intrfc2thrd_goWait <= '1';
-- intrfc2thrd_function <= fromUserReg_value(16 to 31);
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- LIB FUNCTION CALLOC
-- malloc(size_t numBytes, size_t size);
-- Allocate space on the heap, specified by passed in parameters size*size_t
-----------------------------------------------------------------------
-- when LIB_FUNCTION_CALLOC =>
-- -- Record the first parameter in reg3
-- reg3_next <= dob;
-- -- Read the second parameter
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_CALLOC_2;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
-- when LIB_FUNCTION_CALLOC_2 =>
-- reg2_next <= dob;
-- user_state_next <= LIB_FUNCTION_CALLOC_3;
-- when LIB_FUNCTION_CALLOC_3 =>
-- -- Step 1: Multiply reg2 and reg 3, storing result in reg1
-- reg4_next <= std_logic_vector(conv_signed(signed("00"®2(16 to 31)) * signed("00"®3(16 to 31)), 32));
-- reg1_next <= std_logic_vector(conv_signed(signed("00"®2(0 to 15)) * signed("00"®3(0 to 15)), 32));
-- user_state_next <= LIB_FUNCTION_CALLOC_4;
-- when LIB_FUNCTION_CALLOC_4 =>
-- -- Step 2: Multiply reg2 and reg 3, storing result in reg1
-- reg4_next <= std_logic_vector(conv_signed(signed("00"®2(16 to 31)) * signed("00"®3(0 to 15)), 32));
-- reg1_next <= reg4 + (reg1(16 to 31)&x"0000");
-- user_state_next <= LIB_FUNCTION_CALLOC_5;
-- when LIB_FUNCTION_CALLOC_5 =>
-- -- Step 3: Multiply reg2 and reg 3, storing result in reg1
-- reg1_next <= reg4(16 to 31)&x"0000" + reg1;
-- user_state_next <= LIB_FUNCTION_MALLOC_8a;
-----------------------------------------------------------------------
-- LIB FUNCTION MALLOC
-- malloc(size_t size);
-- Allocate space on the heap, specified by passed in parameter
-----------------------------------------------------------------------
-- when LIB_FUNCTION_MALLOC =>
-- -- Record the size of the bytes to allocate in reg 1
-- reg1_next <= dob;
-- user_state_next <= LIB_FUNCTION_MALLOC_8a;
-- when LIB_FUNCTION_MALLOC_8a =>
-- -- Test to see if we should read the 8B dynamic memory table
-- if ( reg1 <= x"00000008" ) then
-- -- size of data to allocate is less than/equal to 8B
-- -- Read the dynmic memory table for 8B
-- enb <= '1';
-- addrb <= REG_8B_DYNAMIC_TABLE (1 to 13);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MALLOC_8b;
-- else
-- -- size of data to allocate is greater than 8B
-- user_state_next <= LIB_FUNCTION_MALLOC_32a;
-- end if;
-- -- Initialize reg2, the loop iterator
-- reg2_next <= x"80000000";
-- when LIB_FUNCTION_MALLOC_8b =>
-- -- reg 3 is the value of the dynamic memory table
-- reg3_next <= dob;
-- -- reg 4 is the address to send back to the user once an open chunk is found
-- -- start with the highest possible value, then decrement as we search
-- reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_8B;
-- user_state_next <= LIB_FUNCTION_MALLOC_8c;
-- when LIB_FUNCTION_MALLOC_8c =>
-- -- iterate through memory table until we find an open chunk of memory
-- if ( (reg2 or reg3) /= reg3 ) then
-- -- we have found an open chunk of memory
-- -- mark this chunk of memory as allocated
-- enb <= '1';
-- web <= '1';
-- addrb <= REG_8B_DYNAMIC_TABLE(1 to 13);
-- dib <= reg2 or reg3;
-- -- return to the user pointer to allocated memory
-- intrfc2thrd_value <= reg4;
-- toUser_value_next <= reg4;
-- intrfc2thrd_goWait <= '1';
-- intrfc2thrd_function <= fromUserReg_value(16 to 31);
-- user_state_next <= RUNNING;
-- else
-- -- need to keep looking
-- if ( reg2 = x"00000001" ) then
-- -- we reached the end of the 8B block table, and all spaces
-- -- are used, try the 32B block table
-- user_state_next <= LIB_FUNCTION_MALLOC_32a;
-- else
-- -- decrement the return address
-- reg4_next <= reg4 - 8;
-- -- shift the loop iterator
-- reg2_next <= '0' & reg2(0 to 30);
-- -- try again
-- user_state_next <= LIB_FUNCTION_MALLOC_8c;
-- end if;
-- end if;
-- when LIB_FUNCTION_MALLOC_32a =>
-- -- Test to see if we should read the 32B dynamic memory table
-- if ( reg1 <= x"00000020" ) then
-- -- size of data to allocate is less than/equal to 32B
-- -- Read the dynmic memory table for 32B
-- enb <= '1';
-- addrb <= REG_32B_DYNAMIC_TABLE (1 to 13);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MALLOC_32b;
-- else
-- -- size of data to allocate is greater than 32B
-- user_state_next <= LIB_FUNCTION_MALLOC_1024a;
-- end if;
-- when LIB_FUNCTION_MALLOC_32b =>
-- -- reg 3 is the value of the dynamic memory table
-- reg3_next <= dob;
-- -- reg 4 is the address to send back to the user once an open chunk is found
-- -- start with the highest possible value, then decrement as we search
-- reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_32B;
-- user_state_next <= LIB_FUNCTION_MALLOC_32c;
-- when LIB_FUNCTION_MALLOC_32c =>
-- -- iterate through memory table until we find an open chunk of memory
-- if ( (reg2 or reg3) /= reg3 ) then
-- -- we have found an open chunk of memory
-- -- mark this chunk of memory as allocated
-- enb <= '1';
-- web <= '1';
-- addrb <= REG_32B_DYNAMIC_TABLE(1 to 13);
-- dib <= reg2 or reg3;
-- -- return to the user pointer to allocated memory
-- intrfc2thrd_value <= reg4;
-- toUser_value_next <= reg4;
-- intrfc2thrd_goWait <= '1';
-- intrfc2thrd_function <= fromUserReg_value(16 to 31);
-- user_state_next <= RUNNING;
-- else
-- -- need to keep looking
-- if ( reg2 = x"01000000" ) then
-- -- we reached the end of the 32B block table, and all spaces
-- -- are used, try the 1024B block table
-- user_state_next <= LIB_FUNCTION_MALLOC_1024a;
-- else
-- -- decrement the return address
-- reg4_next <= reg4 - 32;
-- -- shift the loop iterator
-- reg2_next <= '0' & reg2(0 to 30);
-- -- try again
-- user_state_next <= LIB_FUNCTION_MALLOC_32c;
-- end if;
-- end if;
-- when LIB_FUNCTION_MALLOC_1024a =>
-- -- Test to see if we should read the 1024B dynamic memory table
-- if ( reg1 <= x"00000400" ) then
-- -- size of data to allocate is less than/equal to 1024B
-- -- Read the dynmic memory table for 1024B
-- enb <= '1';
-- addrb <= REG_1024B_DYNAMIC_TABLE (1 to 13);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MALLOC_1024b;
-- else
-- -- size of data to allocate is greater than 1024B
-- user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITa;
-- end if;
-- when LIB_FUNCTION_MALLOC_1024b =>
-- -- reg 3 is the value of the dynamic memory table
-- reg3_next <= dob;
-- -- reg 4 is the address to send back to the user once an open chunk is found
-- -- start with the highest possible value, then decrement as we search
-- reg4_next <= C_BASEADDR(0 to 15) & BASE_ADDR_MALLOC_1024B;
-- user_state_next <= LIB_FUNCTION_MALLOC_1024c;
-- when LIB_FUNCTION_MALLOC_1024c =>
-- iterate through memory table until we find an open chunk of memory
-- if ( (reg2 or reg3) /= reg3 ) then
-- we have found an open chunk of memory
-- mark this chunk of memory as allocated
-- enb <= '1';
-- web <= '1';
-- addrb <= REG_1024B_DYNAMIC_TABLE(1 to 13);
-- dib <= reg2 or reg3;
-- return to the user pointer to allocated memory
-- intrfc2thrd_value <= reg4;
-- toUser_value_next <= reg4;
-- intrfc2thrd_goWait <= '1';
-- intrfc2thrd_function <= fromUserReg_value(16 to 31);
-- user_state_next <= RUNNING;
-- else
-- need to keep looking
-- if ( reg2 = x"40000000" ) then
-- we reached the end of the 1024B block table, and all spaces
-- are used, try the UNLIMIT block table
-- user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITa;
-- else
-- decrement the return address
-- reg4_next <= reg4 - 1024;
-- shift the loop iterator
-- reg2_next <= '0' & reg2(0 to 30);
-- try again
-- user_state_next <= LIB_FUNCTION_MALLOC_1024c;
-- end if;
-- end if;
-- when LIB_FUNCTION_MALLOC_UNLIMITa =>
-- Test to see if we should read the UNLIMITED dynamic memory table
-- if ( reg1 <= x"00007000" ) then
-- size of data to allocate is less than/equal to x3000B
-- Read the dynmic memory table for UNLIMITED
-- enb <= '1';
-- addrb <= REG_UNLIMITED_DYNAMIC_TABLE (1 to 13);
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= LIB_FUNCTION_MALLOC_UNLIMITb;
-- else
-- size of data is too big, return NULL pointer
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end if;
-- when LIB_FUNCTION_MALLOC_UNLIMITb =>
-- if ( dob = Z32 ) then
-- -- decrement the heapPtr specifed number of parameters
-- heapPtr_next <= '0' & (heapPtr(1 to 13) - reg1(18 to 29)) & "00";
-- user_state_next <= LIB_FUNCTION_MALLOC_UNLIMITc;
-- else
-- -- already allocated unlimited data, return NULL pointer
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end if;
-- when LIB_FUNCTION_MALLOC_UNLIMITc =>
-- Write the address to the UNLIMTIED table
-- enb <= '1';
-- web <= '1';
-- addrb <= REG_UNLIMITED_DYNAMIC_TABLE (1 to 13);
-- dib <= C_BASEADDR(0 to 15) & heapPtr;
-- Tell the user to start executing again, telling it the pointer to allocated space
-- intrfc2thrd_value <= C_BASEADDR(0 to 15) & heapPtr;
-- toUser_value_next <= C_BASEADDR(0 to 15) & heapPtr;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- USER FUNCTION RETURN
-- These states are used when the HWTUL is returning from a user
-- defined function
-----------------------------------------------------------------------
when USER_FUNCTION_RETURN =>
-- check the return state address to make sure it is not 0000,
-- if it is 0000 then this is the main thread function returning
-- and we should do a hthread_exit instead.
case dob(16 to 31) is
when x"0000" =>
-- This is the return call for the main thread function
-- Need to set up the stack and state as it would appear
-- if the user called hthread_exit directly.
enb <= '1';
web <= '1';
dib <= fromUserReg_value;
addrb <= stackPtr(1 to 13);
paramCount_next <= paramCount + 1;
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
system_request_next <= CHANGE_STATUS_TO_EXIT;
user_state_next <= HTHREAD_EXIT;
when others =>
-- This is an user defined function returning
-- set the return state of the HWTUL
reg1_next <= dob; -- store return address temp in reg1
-- read the number of parameters that were involved in this function
addrb <= framePtr(1 to 13) - 3;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN_2;
end case;
when USER_FUNCTION_RETURN_2 =>
-- set the stack pointer
-- data coming off of the BRAM is number of params from previous function
stackPtr_next <= '0' & ((framePtr(1 to 13) - 3) - dob(19 to 31)) & "00";
-- read the frame pointer return address
addrb <= framePtr(1 to 13) - 2;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= USER_FUNCTION_RETURN_3;
when USER_FUNCTION_RETURN_3 =>
-- set the frame pointer
framePtr_next <= dob(16 to 31);
-- tell the user to start running again.
intrfc2thrd_function <= reg1(16 to 31);
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- USER FUNCTION_CALL
-- States are used when the HWTUL calls a function it has defined
-- or indirectly for a remote procedural call
-----------------------------------------------------------------------
when USER_FUNCTION_CALL =>
-- write the frame pointer to the stack
addrb <= stackPtr(1 to 13);
dib <= C_BASEADDR(0 to 15) & framePtr;
web <= '1';
enb <= '1';
-- increment the stack pointer
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
user_state_next <= USER_FUNCTION_CALL_2;
when USER_FUNCTION_CALL_2 =>
-- write the return state, for the HWTUL, to the stack
addrb <= stackPtr(1 to 13);
dib <= Z32(0 to 15) & fromUserReg_value(16 to 31);
web <= '1';
enb <= '1';
-- update the stack and frame ptr
stackPtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
framePtr_next <= '0' & (stackPtr(1 to 13) + 1) & "00";
-- Tell the HWTUL to run again, starting at the new function address
intrfc2thrd_function <= fromUserReg_function;
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Remote Procedural Call
-- May perform any action the software rpc thread is set up to accept
-- An RPC is a function call that the HWTI can not implement directly,
-- instead it has to call a software thread to do the work for it.
-- The SW thread is called through mutex & condition variable signalling.
-- reg1 = opcode
-- reg2 = mutex and condvar numbers, held in REG_RPC_MUTEXCONVAR
-- 0 to 0 unused
-- 8 to 15 rpc_mutex, protects the rpc thread
-- 16 to 23 rpc_signal_mutex, protects the rpc condvar
-- 24 to 31 rpc_signal, condvar
-- reg3 = rpc struct address, held in REG_RPC_T_ADDRESS
-- reg4 = temp
-----------------------------------------------------------------------
when HTHREAD_RPC =>
-- Store the value of the rpc mutexconvar to reg2
reg2_next <= dob;
-- Read the value of the rpc struct address
addrb <= REG_RPC_T_ADDRESS(1 to 13);
dib <= Z32(0 to 15) & fromUserReg_value(16 to 31);
enb <= '1';
-- Set up reg4 to hold the the rpc_mutex number
reg4_next <= Z32(0 to 23) & dob(8 to 15);
user_return_state_next <= HTHREAD_RPC_2;
user_state_next <= WAIT_ONE_CYCLE;
-- hthread_mutex_lock( rpc_mutex );
when HTHREAD_RPC_2 =>
-- Store the value of rpc struct address to reg3
reg3_next <= dob;
-- Read the register, on the mutex manager, to lock rpc_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_3 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
debug_user_next <= debug_user or x"00000001";
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when "01" =>
debug_user_next <= debug_user or x"00000002";
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_3a;
when others =>
debug_user_next <= debug_user or x"00000004";
--The Lock is ours
user_state_next <= HTHREAD_RPC_5;
end case;
when HTHREAD_RPC_3a =>
debug_user_next <= debug_user or x"00000008";
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_4;
when others =>
user_state_next <= HTHREAD_RPC_3a;
end case;
when HTHREAD_RPC_4 =>
debug_user_next <= debug_user or x"00000010";
--Wait for a run command
case system_command is
when SYSTEM_COMMAND_RUN =>
user_state_next <= HTHREAD_RPC_5;
system_request_next <= CHANGE_STATUS_TO_RUN;
when others =>
user_state_next <= HTHREAD_RPC_4;
end case;
when HTHREAD_RPC_5 =>
debug_user_next <= debug_user or x"00000020";
--Wait till status is RUNNING
--NOTE: status should already be running if we got the lock in RPC_3
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_6;
system_request_next <= NOOP;
-- Set up reg4 to hold the the rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_5;
end case;
-- hthread_mutex_lock( rpc_signal_mutex );
when HTHREAD_RPC_6 =>
debug_user_next <= debug_user or x"00000040";
-- Read the register, on the mutex manager, to lock rpc_signal_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_7;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_7 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
debug_user_next <= debug_user or x"00000080";
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when "01" =>
debug_user_next <= debug_user or x"00000100";
user_state_next <= HTHREAD_RPC_7a;
system_request_next <= CHANGE_STATUS_TO_BLOCK;
when others =>
debug_user_next <= debug_user or x"00000200";
--The Lock is ours
user_state_next <= HTHREAD_RPC_9;
end case;
when HTHREAD_RPC_7a =>
debug_user_next <= debug_user or x"00000400";
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_8;
when others =>
user_state_next <= HTHREAD_RPC_7a;
end case;
when HTHREAD_RPC_8 =>
debug_user_next <= debug_user or x"00000800";
--Wait for a run command
case system_command is
when SYSTEM_COMMAND_RUN =>
user_state_next <= HTHREAD_RPC_8a;
system_request_next <= CHANGE_STATUS_TO_RUN;
when others =>
user_state_next <= HTHREAD_RPC_8;
end case;
when HTHREAD_RPC_8a =>
debug_user_next <= debug_user or x"00001000";
--Wait till status is RUNNING
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_9;
system_request_next <= NOOP;
when others =>
user_state_next <= HTHREAD_RPC_8a;
end case;
--rpc->opcode = opcode
when HTHREAD_RPC_9 =>
--When we get to this point, the lock on rpc_mutex and rpc_signal_mutex is now ours
--Write the value of the opcode to the struct
data_address_next <= reg3;
data_value_next <= reg1;
user_return_state_next <= HTHREAD_RPC_10;
user_state_next <= MASTER_STORE_INIT;
--Set up reg4, for the next sequence of events. Namely set it to 8, which is the
--offset, from the base address of the rpc argument struct, to place the first parameter
reg4_next <= x"00000008";
--for( i=0; i<5; i++ ) rpc->args[i] = args[i]
when HTHREAD_RPC_10 =>
case paramCount is
when x"00" =>
-- have transfered all of the parameters to the rpc struct
-- Set up reg4 to hold the the rpc_signal number
reg4_next <= Z32(0 to 23) & reg2(24 to 31);
user_state_next <= HTHREAD_RPC_12;
when others =>
-- have one or more parameters than need to be transfered
-- read the parameter from the stack
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= HTHREAD_RPC_11;
-- decrement the stackPtr
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
end case;
when HTHREAD_RPC_11 =>
-- store the parameter to the rpc struct
data_address_next <= reg3(0 to 23) & (reg3(24 to 31) + reg4(24 to 31));
data_value_next <= dob;
user_return_state_next <= HTHREAD_RPC_10;
user_state_next <= MASTER_STORE_INIT;
-- increment reg4 by one word, ie 4 bytes
reg4_next <= reg4 + 4;
-- decrment paramCount
paramCount_next <= paramCount - 1;
when HTHREAD_RPC_12 =>
-- hthread_cond_signal( rpc_signal );
debug_user_next <= debug_user or x"00002000";
-- Read the register, on the cond var manager, to signal the next thread
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_SIGNAL & --bits(12 to 15) signal command
"00000000" & --bits(16 to 23) thread id
reg4(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_RPC_13;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_13 =>
--Check the return status, repeat if attempt failed
if ( data_value(28 to 31) = CONDVAR_FAILED ) then
--repeat step 2
user_state_next <= HTHREAD_RPC_12;
else
--The cond var, rpc_signal, is signaled
-- Set up reg4 to hold condvar rpc_signal number
reg4_next <= Z32(0 to 23) & reg2(24 to 31);
user_state_next <= HTHREAD_RPC_14;
end if;
when HTHREAD_RPC_14 =>
debug_user_next <= debug_user or x"00004000";
-- hthread_cond_wait( rpc_signal, rpc_signal_mutex)
-- First step in waiting is to signal the wait
-- Call to wait for cond variable signal
data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
"000000000000" &
CONDVAR_CMD_WAIT & --bits(12 to 15) broadcast command
system_thread_id & --bits(16 to 23) thread id
reg4(26 to 31) & --bits(24 to 29) con var number
"00"); --bits(30 to 31) word addressing
user_return_state_next <= HTHREAD_RPC_15;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_15 =>
-- Check return value, repeat if nessessary
case data_value(28 to 31) is
when CONDVAR_FAILED =>
--repeat previous step
user_state_next <= HTHREAD_RPC_14;
when others =>
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_15a;
end case;
when HTHREAD_RPC_15a =>
debug_user_next <= debug_user or x"00008000";
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_16;
--Set up reg4 to hold mutex rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_15a;
end case;
when HTHREAD_RPC_16 =>
-- Second step in waiting is to release the mutex, this is the signal to the
-- rest of the system that it is safe to issue hthread_signal or hthread_broadcast
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_17;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_17 =>
debug_user_next <= debug_user or x"00010000";
--Wait for a run command, which is the signal that the rpc is done
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_RPC_17a;
when others =>
user_state_next <= HTHREAD_RPC_17;
end case;
when HTHREAD_RPC_17a =>
--Wait till status is RUNNING
debug_user_next <= debug_user or x"00020000";
case system_status is
when SYSTEM_STATUS_RUNNING =>
user_state_next <= HTHREAD_RPC_18;
system_request_next <= NOOP;
--Set up reg4 to hold mutex rpc_signal_mutex number
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
when others =>
user_state_next <= HTHREAD_RPC_17a;
end case;
when HTHREAD_RPC_18 =>
-- Last step in waiting is to relock the rpc_signal_mutex
debug_user_next <= debug_user or x"00040000";
-- Read the register, on the mutex manager, to lock rpc_signal_mutex
data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_19;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_19 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
case data_value(0 to 1) is
when "10" =>
debug_user_next <= debug_user or x"00080000";
--Return an error code to the user
intrfc2thrd_value <= x"00000001";
toUser_value_next <= x"00000001";
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
when "01" =>
debug_user_next <= debug_user or x"00100000";
system_request_next <= CHANGE_STATUS_TO_BLOCK;
user_state_next <= HTHREAD_RPC_19a;
when others =>
debug_user_next <= debug_user or x"00200000";
--The Lock is ours
user_state_next <= HTHREAD_RPC_21;
end case;
when HTHREAD_RPC_19a =>
debug_user_next <= debug_user or x"00400000";
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_BLOCKED =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_20;
when others =>
user_state_next <= HTHREAD_RPC_19a;
end case;
when HTHREAD_RPC_20 =>
debug_user_next <= debug_user or x"00800000";
--Wait for a run command, which is the signal that the lock is ours
case system_command is
when SYSTEM_COMMAND_RUN =>
system_request_next <= CHANGE_STATUS_TO_RUN;
user_state_next <= HTHREAD_RPC_20a;
when others =>
user_state_next <= HTHREAD_RPC_20;
end case;
when HTHREAD_RPC_20a =>
debug_user_next <= debug_user or x"01000000";
--Wait for the system_stutus to change to BLOCKED
case system_status is
when SYSTEM_STATUS_RUNNING =>
system_request_next <= NOOP;
user_state_next <= HTHREAD_RPC_21;
when others =>
user_state_next <= HTHREAD_RPC_20a;
end case;
when HTHREAD_RPC_21 =>
debug_user_next <= debug_user or x"02000000";
--read the result from the rpc struct
data_address_next <= reg3 + 4;
user_return_state_next <= HTHREAD_RPC_22;
user_state_next <= MASTER_LOAD_INIT;
--set up reg4 to hold the rpc_signal_mutex
reg4_next <= Z32(0 to 23) & reg2(16 to 23);
--change status to RUNNING
system_request_next <= CHANGE_STATUS_TO_RUN;
when HTHREAD_RPC_22 =>
--store the result in reg1
reg1_next <= data_value;
debug_user_next <= debug_user or x"04000000";
-- hthread_mutex_unlock( rpc_signal_mutex );
-- Read the register, on the mutex manager, to unlock the specified mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_23;
user_state_next <= MASTER_LOAD_INIT;
--set up reg4 to hold the rpc_mutex
reg4_next <= Z32(0 to 23) & reg2(8 to 15);
when HTHREAD_RPC_23 =>
debug_user_next <= debug_user or x"08000000";
-- hthread_mutex_unlock( rpc_mutex );
-- Read the register, on the mutex manager, to unlock the specified mutex
data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
C_OPB_DWIDTH, -- number of bits for data bus
MUTEX_BITS, -- number of bits for mutex id
THREAD_BITS,
COUNT_BITS,
system_thread_id(8 - THREAD_BITS to 7),
reg4(32 - MUTEX_BITS to 31) );
user_return_state_next <= HTHREAD_RPC_24;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_RPC_24 =>
system_request_next <= NOOP;
-- Return the results to the user
intrfc2thrd_value <= reg1;
toUser_value_next <= reg1;
intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_ATTR_INIT
-- Hint hthread_attr_init( hthread_attr_t * attr )
-- Hint hthread_attr_destroy( hthread_attr_t * attr )
-- sets the attributes, of the passed in pointer to a thread attribute
-- to their default values. Both the init and destroy functions
-- work the same
-- Always returns an SUCCESS
-- reg1 will hold address of attr
-----------------------------------------------------------------------
-- when HTHREAD_ATTR_INIT =>
-- reg1_next <= dob;
-- --write a Hfalse, a 0, to attr->detached
-- data_address_next <= dob;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_ATTR_INIT_2;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_2 =>
-- --write a Hfalse, a 0, to attr->hardware
-- data_address_next <= reg1 + 4;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_ATTR_INIT_3;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_3 =>
-- --write a 0, to attr->hardware_addr
-- data_address_next <= reg1 + 8;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_ATTR_INIT_4;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_4 =>
-- --write a HT_DEFAULT_STACK_SIZE, 16 * 1024,, to attr->stack_size
-- data_address_next <= reg1 + 12;
-- data_value_next <= x"00004000";
-- user_return_state_next <= HTHREAD_ATTR_INIT_5;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_5 =>
-- --write a NULL, a 0, to attr->stack_addr
-- data_address_next <= reg1 + 16;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_ATTR_INIT_6;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_6 =>
-- --write a 64 priority, to attr->sched_param
-- data_address_next <= reg1 + 20;
-- data_value_next <= x"00000020";
-- user_return_state_next <= HTHREAD_ATTR_INIT_7;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_ATTR_INIT_7 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_EQUAL
-- Hint hthread_equal( hthread_t t1, hthread_2 t2 )
-- tests to see if t1 is equal to t2
-- return values are 1 if t1 == t2, else 0
-- reg1 will hold t1
-----------------------------------------------------------------------
-- when HTHREAD_EQUAL =>
-- reg1_next <= dob;
-- -- Read the value of t2
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_EQUAL_2;
-- -- Reset the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- when HTHREAD_EQUAL_2 =>
-- --Check to see if the two thread ids are equal
-- if ( dob(24 to 31) = reg1(24 to 31) ) then
-- intrfc2thrd_value <= Z32(0 to 30) & '1';
-- toUser_value_next <= Z32(0 to 30) & '1';
-- else
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- end if;
-- -- Tell the HWTUL to run again, starting at the new function address
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_CONDATTR_INIT
-- hthread_condattr_init( condattr_t * )
-- Initializes the condattr struct to default values
-----------------------------------------------------------------------
-- when HTHREAD_CONDATTR_INIT =>
-- reg1_next <= dob;
-- -- Write a 0, the default condvar number, to the condattr_t.num
-- data_address_next <= dob;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_CONDATTR_INIT_2;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_CONDATTR_INIT_2 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_COND_INIT
-- hthread_cond_init( cond_t *, hthread_condattr_t*)
-- Creates a condition variable based on either the default attributes,
-- if condattr_t is NULL, or on condattr_t.
-----------------------------------------------------------------------
-- when HTHREAD_COND_INIT =>
-- -- Store the address of the condvar in reg1;
-- reg1_next <= dob;
-- -- Read the address, that the use passed in, of condattr_t
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_INIT_2;
-- -- Reset the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- when HTHREAD_COND_INIT_2 =>
-- -- Store the address of condattr in reg2;
-- reg2_next <= dob;
-- -- Determine if the attributes are NULL or not
-- case dob is
-- when Z32 =>
-- -- Create a condition variable with default attributes
-- reg3_next <= Z32; --condvar number 0
-- user_state_next <= HTHREAD_COND_INIT_5;
-- when OTHERS =>
-- user_state_next <= HTHREAD_COND_INIT_3;
-- end case;
-- when HTHREAD_COND_INIT_3 =>
-- -- Read the value of the attr's num
-- data_address_next <= reg2;
-- user_return_state_next <= HTHREAD_COND_INIT_4;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_INIT_4 =>
-- -- Store the value of attr's num in reg3
-- reg3_next <= data_value;
-- user_state_next <= HTHREAD_COND_INIT_5;
-- when HTHREAD_COND_INIT_5 =>
-- -- Write the condvar's num
-- data_address_next <= reg1;
-- data_value_next <= reg3;
-- user_return_state_next <= HTHREAD_COND_INIT_6;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_COND_INIT_6 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_WAIT
-- hthread_cond_broadcast( hthread_cond_t *cond, hthread_mutex_t *mutex )
-- Unlocks *mutex, waits for a signal from *cond, relocks *mutex
-----------------------------------------------------------------------
-- when HTHREAD_COND_WAIT =>
-- -- reg1 will hold address of condition variable
-- reg1_next <= dob;
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_COND_WAIT_2;
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- -- decrement the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- when HTHREAD_COND_WAIT_2 =>
-- -- reg2 will hold address of mutex
-- reg2_next <= dob;
-- -- Initiate read of the cond var number
-- data_address_next <= reg1;
-- user_return_state_next <= HTHREAD_COND_WAIT_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_WAIT_3 =>
-- -- reg3 will hold cond var number
-- reg3_next <= data_value;
-- -- Initiate read of the mutex number
-- data_address_next <= reg2;
-- user_return_state_next <= HTHREAD_COND_WAIT_4;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_WAIT_4 =>
-- -- reg4 will hold mutex number
-- reg4_next <= data_value;
-- -- Call to unlock the mutex
-- data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
-- C_OPB_DWIDTH, -- number of bits for data bus
-- MUTEX_BITS, -- number of bits for mutex id
-- THREAD_BITS,
-- COUNT_BITS,
-- system_thread_id(8 - THREAD_BITS to 7),
-- data_value(32 - MUTEX_BITS to 31) );
-- user_return_state_next <= HTHREAD_COND_WAIT_5;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_WAIT_5 =>
-- -- Call to wait for cond variable signal
-- data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
-- "000000000000" &
-- CONDVAR_CMD_WAIT & --bits(12 to 15) broadcast command
-- system_thread_id & --bits(16 to 23) thread id
-- reg3(26 to 31) & --bits(24 to 29) con var number
-- "00"); --bits(30 to 31) word addressing
-- user_return_state_next <= HTHREAD_COND_WAIT_6;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_WAIT_6 =>
-- -- Check return value, if success, mark thread as blocked
-- if ( data_value(28 to 31) = CONDVAR_FAILED ) then
-- --repeat previous step
-- user_state_next <= HTHREAD_COND_WAIT_5;
-- else
-- system_request_next <= CHANGE_STATUS_TO_BLOCK;
-- user_state_next <= HTHREAD_COND_WAIT_7;
-- end if;
-- when HTHREAD_COND_WAIT_7 =>
-- -- Wait till status changes to blocked
-- case system_status is
-- when SYSTEM_STATUS_BLOCKED =>
-- system_request_next <= NOOP;
-- user_state_next <= HTHREAD_COND_WAIT_7a;
-- when others =>
-- user_state_next <= HTHREAD_COND_WAIT_7;
-- end case;
-- when HTHREAD_COND_WAIT_7a =>
-- --Wait for a run command, which is the signal another thread sent to us
-- case system_command is
-- when SYSTEM_COMMAND_RUN =>
-- system_request_next <= CHANGE_STATUS_TO_RUN;
-- user_state_next <= HTHREAD_COND_WAIT_8;
-- when others =>
-- user_state_next <= HTHREAD_COND_WAIT_7a;
-- end case;
-- when HTHREAD_COND_WAIT_8=>
-- --Wait for the system state machine to update the status
-- case system_status is
-- when SYSTEM_STATUS_RUNNING =>
-- --We've been signaled to continue, before returning, relock the mutex
-- --Note that I'm tranfering control to the mutex lock state machine
-- data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
-- C_OPB_DWIDTH, -- number of bits for data bus
-- MUTEX_BITS, -- number of bits for mutex id
-- THREAD_BITS,
-- COUNT_BITS,
-- system_thread_id(8 - THREAD_BITS to 7),
-- data_value(32 - MUTEX_BITS to 31) );
-- user_return_state_next <= HTHREAD_MUTEX_LOCK_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when others =>
-- user_state_next <= HTHREAD_COND_WAIT_8;
-- end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_BCAST
-- hthread_cond_broadcast( hthread_cond_t *cond )
-- Broadcasts, via the condition varable manager, all
-- threads waiting on cond
-----------------------------------------------------------------------
-- when HTHREAD_COND_BCAST =>
-- data_address_next <= dob;
-- -- Read the value of the cond var number
-- user_return_state_next <= HTHREAD_COND_BCAST_2;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_BCAST_2 =>
-- -- Store the cond variable in reg1
-- reg1_next <= data_value;
-- -- Read the register, on the cond var manager, to signal the next thread
-- data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
-- "000000000000" &
-- CONDVAR_CMD_BCAST & --bits(12 to 15) broadcast command
-- "00000000" & --bits(16 to 23) thread id
-- data_value(26 to 31) & --bits(24 to 29) con var number
-- "00"); --bits(30 to 31) word addressing
-- user_return_state_next <= HTHREAD_COND_BCAST_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_BCAST_3 =>
-- --Check the return status, repeat of attempt failed
-- if ( data_value(28 to 31) = CONDVAR_FAILED ) then
-- --restore value of the data value register
-- data_value_next <= reg1;
-- --repeat step 2
-- user_state_next <= HTHREAD_COND_BCAST_2;
-- else
-- --The cond var is signaled, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end if;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_COND_SIGNAL
-- hthread_cond_signal( hthread_cond_t *cond )
-- Signals, via the condition varable manager, the highest priority
-- thread waiting on cond
-----------------------------------------------------------------------
-- when HTHREAD_COND_SIGNAL =>
-- data_address_next <= dob;
-- -- Read the value of the cond var number
-- user_return_state_next <= HTHREAD_COND_SIGNAL_2;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_SIGNAL_2 =>
-- -- Store the cond variable in reg1
-- reg1_next <= data_value;
-- -- Read the register, on the cond var manager, to signal the next thread
-- data_address_next <= C_CONVAR_MANAGER_BADDR or ( --base addr of cond var mgr
-- "000000000000" &
-- CONDVAR_CMD_SIGNAL & --bits(12 to 15) signal command
-- "00000000" & --bits(16 to 23) thread id
-- data_value(26 to 31) & --bits(24 to 29) con var number
-- "00"); --bits(30 to 31) word addressing
-- user_return_state_next <= HTHREAD_COND_SIGNAL_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_COND_SIGNAL_3 =>
-- --Check the return status, repeat of attempt failed
-- if ( data_value(28 to 31) = CONDVAR_FAILED ) then
-- --restore value of the data value register
-- data_value_next <= reg1;
-- --repeat step 2
-- user_state_next <= HTHREAD_COND_SIGNAL_2;
-- else
-- --The cond var is signaled, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end if;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_SETNUM and HTHREAD_CONDATTR_SETNUM
-- hthread_mutexattr_getnum( mutexattr_t *, int num)
-- hthread_condattr_setnum( condattr_t *, int num)
-- Sets the value of mutexattr number to num
-- or sets the value of condattr number to num
-- Reusing these states work, because in both the case for the mutexattr
-- and the condattr struct, the first element in the struct is the
-- mutex/condvariable number.
-----------------------------------------------------------------------
-- when HTHREAD_MUTEXATTR_SETNUM =>
-- -- store the value of the address of mutexattr_t in reg1
-- reg1_next <= dob;
-- -- Read the second parameter the user pushed, the new value of the mutex number
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM_2;
-- -- Reset the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- when HTHREAD_MUTEXATTR_SETNUM_2 =>
-- -- Store the dob (value of num) to mutexattr
-- data_value_next <= dob;
-- data_address_next <= reg1;
-- user_return_state_next <= HTHREAD_MUTEXATTR_SETNUM_3;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEXATTR_SETNUM_3 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_GETNUM and HTHREAD_CONDATTR_GETNUM
-- hthread_mutexattr_getnum( mutexattr_t *, int* num)
-- hthread_condattr_getnum( condattr_t *, int* num)
-- Gets the value of *num to the value of the mutexattr number
-- or gets the value of condattr number to num
-- Reusing these states work, because in both the case for the mutexattr
-- and the condattr struct, the first element in the struct is the
-- mutex/condvariable number.
-----------------------------------------------------------------------
-- when HTHREAD_MUTEXATTR_GETNUM =>
-- -- store the value of the address of mutexattr_t in reg1
-- reg1_next <= dob;
-- -- Read the second parameter the user pushed, address to store the mutex number to
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_2;
-- -- Reset the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- when HTHREAD_MUTEXATTR_GETNUM_2 =>
-- -- store the value of the address of num in reg2
-- reg2_next <= dob;
-- -- Load the value of the mutex number
-- data_address_next <= reg1;
-- user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEXATTR_GETNUM_3 =>
-- -- Store the value we just read, to the num passed by the user
-- data_value_next <= data_value;
-- data_address_next <= reg2;
-- user_return_state_next <= HTHREAD_MUTEXATTR_GETNUM_4;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEXATTR_GETNUM_4 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEXATTR_INIT
-- hthread_mutexattr_init( mutexattr_t * )
-- Initializes the mutexattr struct to default values
-----------------------------------------------------------------------
-- when HTHREAD_MUTEXATTR_INIT =>
-- reg1_next <= dob;
-- -- Write a 0, the default mutex number, to the mutexattr_t.num
-- data_address_next <= dob;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_MUTEXATTR_INIT_2;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEXATTR_INIT_2 =>
-- -- Write a HTHREAD_MUTEX_DEFAULT, the default mutex type, to the mutexattr_t.type
-- data_address_next <= reg1 + 4;
-- data_value_next <= Z32;
-- user_return_state_next <= HTHREAD_MUTEXATTR_INIT_3;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEXATTR_INIT_3 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEX_INIT
-- hthread_mutex_init( mutex_t *, hthread_mutexattr_t*)
-- Creates a mutex based on either the default attributes, if mutexattr_t
-- is NULL, or on mutexattr_t.
-----------------------------------------------------------------------
-- when HTHREAD_MUTEX_INIT =>
-- -- Store the address of the mutex in reg1;
-- reg1_next <= dob;
-- -- Read the address, that the use passed in, of mutexattr_t
-- addrb <= stackPtr(1 to 13) - 2;
-- enb <= '1';
-- user_state_next <= WAIT_ONE_CYCLE;
-- user_return_state_next <= HTHREAD_MUTEX_INIT_2;
-- -- Reset the stack pointer
-- stackPtr_next <= '0' & (stackPtr(1 to 13) - 2) & "00";
-- -- Reset number of parameters
-- paramCount_next <= x"00";
-- when HTHREAD_MUTEX_INIT_2 =>
-- -- Store the address of mutexattr in reg2;
-- reg2_next <= dob;
-- -- Determine if the attributes are NULL or not
-- case dob is
-- when Z32 =>
-- -- Create a mutex with default attributes
-- reg3_next <= Z32; --mutex number 0
-- reg4_next <= Z32; --HTHREAD_MUTEX_DEFAULT
-- data_value_next <= Z32; --to conserve a state, i'm cheating and setting
-- -- data_value here. reg4 gets overwriten in MUTEX_INIT_5
-- user_state_next <= HTHREAD_MUTEX_INIT_5;
-- when OTHERS =>
-- user_state_next <= HTHREAD_MUTEX_INIT_3;
-- end case;
-- when HTHREAD_MUTEX_INIT_3 =>
-- -- Read the value of the attr's num
-- data_address_next <= reg2;
-- user_return_state_next <= HTHREAD_MUTEX_INIT_4;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_INIT_4 =>
-- -- Store the value of attr's num in reg3
-- reg3_next <= data_value;
-- -- Read the value of the attr's type
-- data_address_next <= reg2 + 4;
-- user_return_state_next <= HTHREAD_MUTEX_INIT_5;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_INIT_5 =>
-- -- Store the value of the attr's type in reg4
-- reg4_next <= data_value;
-- -- Write the mutex's num
-- data_address_next <= reg1;
-- data_value_next <= reg3;
-- user_return_state_next <= HTHREAD_MUTEX_INIT_6;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEX_INIT_6 =>
-- -- Write the mutex's type
-- data_address_next <= reg1 + 4;
-- data_value_next <= reg4;
-- user_return_state_next <= HTHREAD_MUTEX_INIT_7;
-- user_state_next <= MASTER_STORE_INIT;
-- when HTHREAD_MUTEX_INIT_7 =>
-- -- Return a SUCCESS to the user;
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- HTHREAD_MUTEX_UNLOCK
-- hthread_mutex_unlock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
-- when HTHREAD_MUTEX_UNLOCK =>
-- data_address_next <= dob;
-- -- Read the value of the mutex number
-- user_return_state_next <= HTHREAD_MUTEX_UNLOCK_2;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_UNLOCK_2 =>
-- -- Read the register, on the mutex manager, to unlock the specified mutex
-- data_address_next <= synch_unlockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
-- C_OPB_DWIDTH, -- number of bits for data bus
-- MUTEX_BITS, -- number of bits for mutex id
-- THREAD_BITS,
-- COUNT_BITS,
-- system_thread_id(8 - THREAD_BITS to 7),
-- data_value(32 - MUTEX_BITS to 31) );
-- user_return_state_next <= HTHREAD_MUTEX_UNLOCK_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_UNLOCK_3 =>
-- --The Lock is released, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_MUTEX_TRYLOCK
-- hthread_mutex_trylock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
-- when HTHREAD_MUTEX_TRYLOCK =>
-- data_address_next <= dob;
-- -- Read the value of the mutex number
-- user_return_state_next <= HTHREAD_MUTEX_TRYLOCK_2;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_TRYLOCK_2 =>
-- -- Read the register, on the mutex manager, to lock the specified mutex
-- data_address_next <= synch_trylockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
-- C_OPB_DWIDTH, -- number of bits for data bus
-- MUTEX_BITS, -- number of bits for mutex id
-- THREAD_BITS,
-- COUNT_BITS,
-- system_thread_id(8 - THREAD_BITS to 7),
-- data_value(32 - MUTEX_BITS to 31) );
-- user_return_state_next <= HTHREAD_MUTEX_TRYLOCK_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_TRYLOCK_3 =>
-- Determine if we got the lock or not
-- Possible return values are
-- if bit(0)==1 then deadlock
-- if bit(1)==1 then another thread has the lock
-- else we have the lock
-- case data_value(0 to 1) is
-- when "10" =>
-- --Return an error code to the user
-- intrfc2thrd_value <= x"00000001";
-- toUser_value_next <= x"00000001";
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when "01" =>
-- --Did not get the LOCK,
-- intrfc2thrd_value <= x"00000001";
-- toUser_value_next <= x"00000001";
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when others =>
-- --The Lock is ours, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_MUTEX_LOCK
-- hthread_mutex_lock( mutex_t * )
-- Locks the mutex specified by *mutex_t
-----------------------------------------------------------------------
-- when HTHREAD_MUTEX_LOCK =>
-- data_address_next <= dob;
-- -- Read the value of the mutex number
-- user_return_state_next <= HTHREAD_MUTEX_LOCK_2;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_LOCK_2 =>
-- -- Read the register, on the mutex manager, to lock the specified mutex
-- data_address_next <= synch_lockcmd( C_MUTEX_MANAGER_BADDR,--base address of synch manager
-- C_OPB_DWIDTH, -- number of bits for data bus
-- MUTEX_BITS, -- number of bits for mutex id
-- THREAD_BITS,
-- COUNT_BITS,
-- system_thread_id(8 - THREAD_BITS to 7),
-- data_value(32 - MUTEX_BITS to 31) );
-- user_return_state_next <= HTHREAD_MUTEX_LOCK_3;
-- user_state_next <= MASTER_LOAD_INIT;
-- when HTHREAD_MUTEX_LOCK_3 =>
-- -- Determine if we got the lock or not
-- -- Possible return values are
-- -- if bit(0)==1 then deadlock
-- -- if bit(1)==1 then another thread has the lock
-- -- else we have the lock
-- case data_value(0 to 1) is
-- when "10" =>
-- --Return an error code to the user
-- intrfc2thrd_value <= x"00000001";
-- toUser_value_next <= x"00000001";
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when "01" =>
-- --Change status to block, then wait for a RUN command
-- system_request_next <= CHANGE_STATUS_TO_BLOCK;
-- user_state_next <= HTHREAD_MUTEX_LOCK_4;
-- when others =>
-- --The Lock is ours, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- end case;
-- when HTHREAD_MUTEX_LOCK_4 =>
-- --Wait for the system_stutus to change to BLOCKED
-- case system_status is
-- when SYSTEM_STATUS_BLOCKED =>
-- system_request_next <= NOOP;
-- user_state_next <= HTHREAD_MUTEX_LOCK_5;
-- when others =>
-- user_state_next <= HTHREAD_MUTEX_LOCK_4;
-- end case;
-- when HTHREAD_MUTEX_LOCK_5 =>
-- --Wait for a run command
-- case system_command is
-- when SYSTEM_COMMAND_RUN =>
-- --TODO check to see if the lock is ours, or if this was a random RUN command
-- system_request_next <= CHANGE_STATUS_TO_RUN;
-- user_state_next <= HTHREAD_MUTEX_LOCK_6;
-- when others =>
-- user_state_next <= HTHREAD_MUTEX_LOCK_5;
-- end case;
-- when HTHREAD_MUTEX_LOCK_6 =>
-- case system_status is
-- when SYSTEM_STATUS_RUNNING =>
-- system_request_next <= NOOP;
-- --The lock is now ours, return a SUCCESS to the user
-- intrfc2thrd_value <= Z32;
-- toUser_value_next <= Z32;
-- intrfc2thrd_function <= fromUserReg_value( 16 to 31 );
-- intrfc2thrd_goWait <= '1';
-- user_state_next <= RUNNING;
-- when others =>
-- user_state_next <= HTHREAD_MUTEX_LOCK_6;
-- end case;
-----------------------------------------------------------------------
-- FUNCTION_HTHREAD_EXIT, EXIT_ERROR, OVERFLOW
-- Calls the exit_thread API on the thread manager. Once the thread
-- manager returns, wait until the HWTI receives a RESET signal.
-----------------------------------------------------------------------
when HTHREAD_EXIT =>
-- Initiate the call to the thread manager
data_address_next <= thread_manager_exit_thread_address( C_THREAD_MANAGER_BADDR, C_OPB_AWIDTH, THREAD_BITS, system_thread_id );
user_return_state_next <= HTHREAD_EXIT_2;
user_state_next <= MASTER_LOAD_INIT;
-- Simotaneously, read the parameter that the user pushed to the stack
addrb <= stackPtr(1 to 13) - 1;
enb <= '1';
when OVERFLOW =>
-- Stack and heap overflow was detected
data_address_next <= thread_manager_exit_thread_address( C_THREAD_MANAGER_BADDR, C_OPB_AWIDTH, THREAD_BITS, system_thread_id );
system_request_next <= CHANGE_STATUS_TO_EXIT_OVERFLOW;
user_return_state_next <= HTHREAD_EXIT_3;
user_state_next <= MASTER_LOAD_INIT;
when HTHREAD_EXIT_2 =>
-- Read the argument
system_result_next <= dob;
-- Decrement the stack for good measure
paramCount_next <= x"00";
stackPtr_next <= '0' & (stackPtr(1 to 13) - 1) & "00";
user_state_next <= HTHREAD_EXIT_3;
when HTHREAD_EXIT_3 =>
case system_status is
when SYSTEM_STATUS_EXITED =>
system_request_next <= NOOP;
when SYSTEM_STATUS_EXITED_ERROR =>
system_request_next <= NOOP;
when SYSTEM_STATUS_EXITED_OVERFLOW =>
system_request_next <= NOOP;
when others =>
-- do nothing
end case;
user_state_next <= HTHREAD_EXIT_3;
-----------------------------------------------------------------------
-- Read the function call parameter from the stack, and return value
-- to user.
-----------------------------------------------------------------------
when POP_READ_PARAM_COUNT =>
-- Learn the number of parameters in the function call
-- Make sure the user is not trying to exceed this number
-- Start the read for the parameter
if ( dob(24 to 31) > fromUserReg_value(24 to 31) ) then
-- pop parameter is within known parameter count
addrb <= ( framePtr(1 to 13) - fromUserReg_value(19 to 31) ) - 4 ;
dib <= fromUser_value;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= POP_READ_PARAM;
else
-- pop parameter is outside known parameter count
intrfc2thrd_value <= Z32;
toUser_value_next <= Z32;
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
end if;
when POP_READ_PARAM =>
-- return the value, and control, to the user thread
intrfc2thrd_value <= dob;
toUser_value_next <= dob;
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Helper function to wait one clock cycle. Returns to state
-- specified in return_state
-----------------------------------------------------------------------
when WAIT_ONE_CYCLE =>
-- Wait one clock cycle
user_state_next <= user_return_state;
-----------------------------------------------------------------------
-- If the user is requesting a read that is not word-aligned, need
-- to do two reads, and return a concatenation of both.
-----------------------------------------------------------------------
when LOCAL_PARTIAL_LOAD =>
reg1_next <= dob;
addrb <= fromUserReg_address(17 to 29) + 1;
enb <= '1';
user_state_next <= WAIT_ONE_CYCLE;
user_return_state_next <= LOCAL_PARTIAL_LOAD_1;
when LOCAL_PARTIAL_LOAD_1 =>
case fromUserReg_address(30 to 31) is
when "01" =>
intrfc2thrd_value <= reg1(8 to 31) & dob(0 to 7);
toUser_value_next <= reg1(8 to 31) & dob(0 to 7);
when "10" =>
intrfc2thrd_value <= reg1(16 to 31) & dob(0 to 15);
toUser_value_next <= reg1(16 to 31) & dob(0 to 15);
when OTHERS =>
intrfc2thrd_value <= reg1(24 to 31) & dob(0 to 23);
toUser_value_next <= reg1(24 to 31) & dob(0 to 23);
end case;
intrfc2thrd_goWait <= '1';
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Perform the remaning steps to read from BRAM. Since we are trying
-- to make the operation as fast as possible, it has its own special
-- states. And yes, I get to use this for both LOCAL_LOAD and
-- LOCAL_READ.
-----------------------------------------------------------------------
when LOCAL_LOAD_RESPOND =>
-- Return the data from BRAM and tell HWTUL to GO
intrfc2thrd_goWait <= '1';
intrfc2thrd_value <= dob;
toUser_value_next <= dob;
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- After the Read helper returns, this state is called, to return the
-- HWTUL to a running state. Also note that this state is being used
-- as the return state for GLOBAL_STORE. why? because I can.
-----------------------------------------------------------------------
when GLOBAL_LOAD_RETURN =>
intrfc2thrd_goWait <= '1';
intrfc2thrd_value <= data_value;
toUser_value_next <= data_value;
user_state_next <= RUNNING;
-----------------------------------------------------------------------
-- Read/load helper states
-- Performs a bus master read to data_address
-- After completion, returns to state user_return_state, data is in
-- data_value;
-----------------------------------------------------------------------
when MASTER_LOAD_INIT =>
-- Initiate read opperation
IP2Bus_Addr <= data_address;
IP2Bus_MstRdReq <= '1';
IP2IP_Addr <= master_read_respond_address;
user_state_next <= MASTER_LOAD_WAIT_FOR_ACK;
when MASTER_LOAD_WAIT_FOR_ACK =>
-- Persist with read operation until ACKed
if ( Bus2IP_MstLastAck = '1'
or Bus2IP_MstError = '1'
or Bus2IP_MstTimeOut = '1' ) then
IP2Bus_Addr <= (others=>'0');
IP2Bus_MstRdReq <= '0';
IP2IP_Addr <= (others=>'0');
data_value_next <= Bus2IP_Data;
--TODO catch an error and set a status to indicate error
user_state_next <= user_return_state;
else
IP2Bus_Addr <= data_address;
IP2Bus_MstRdReq <= '1';
IP2IP_Addr <= master_read_respond_address;
user_state_next <= MASTER_LOAD_WAIT_FOR_ACK;
end if;
---------------------------------------------------------
-- Write/store helper states
-- Perform a bus master write to data_address with data_value
---------------------------------------------------------
when MASTER_STORE_INIT =>
-- Initiate write opperation
-- Note that the data_value gets set in the RUNNING state
IP2Bus_Addr <= data_address;
IP2Bus_MstWrReq <= '1';
IP2IP_Addr <= master_write_respond_address;
user_state_next <= MASTER_STORE_WAIT_FOR_ACK;
when MASTER_STORE_WAIT_FOR_ACK =>
-- Persist with write opperation until ACKed by bus
if ( Bus2IP_MstLastAck = '1'
or Bus2IP_MstError = '1'
or Bus2IP_MstTimeOut = '1') then
IP2Bus_Addr <= (others=>'0');
IP2Bus_MstWrReq <= '0';
IP2IP_Addr <= (others=>'0');
user_state_next <= user_return_state;
else
IP2Bus_Addr <= data_address;
IP2Bus_MstWrReq <= '1';
IP2IP_Addr <= master_write_respond_address;
user_state_next <= MASTER_STORE_WAIT_FOR_ACK;
end if;
end case;
end process HWTI_USER_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 3c5bddb3ce8751592166b01a110f192e | 0.528078 | 3.873795 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/send_store.vhd | 11 | 5,763 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity send_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
siaddr : in std_logic_vector(0 to C_TWIDTH-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to C_TWIDTH-1);
sonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end send_store;
architecture behavioral of send_store is
-- Calculate the number of mutexes to use
constant THREADS : integer := pow2( C_TWIDTH );
-- Constant for the last location to be reset
constant RST_END : std_logic_vector(0 to C_TWIDTH-1) := (others => '1');
-- Declare a storage area for the mutex data
type tstore is array(0 to THREADS-1) of std_logic_vector(0 to C_TWIDTH-1);
-- Declare signals for the mutex storage area
signal store : tstore;
signal sena : std_logic;
signal swea : std_logic;
signal saddr : std_logic_vector(0 to C_TWIDTH - 1);
signal sinput : std_logic_vector(0 to C_TWIDTH - 1);
signal soutput : std_logic_vector(0 to C_TWIDTH - 1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rst_cs : rststate;
signal rena : std_logic;
signal rwea : std_logic;
signal raddr : std_logic_vector(0 to C_TWIDTH - 1);
signal raddrn : std_logic_vector(0 to C_TWIDTH - 1);
signal rnext : std_logic_vector(0 to C_TWIDTH - 1);
begin
sonext <= soutput(0 to C_TWIDTH-1);
send_mux : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
sena <= rena;
swea <= rwea;
saddr <= raddr;
sinput <= rnext;
else
sena <= siena;
swea <= siwea;
saddr <= siaddr;
sinput <= sinext;
end if;
end if;
end process send_mux;
send_reset_controller : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process send_reset_controller;
send_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rnext <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process send_reset_logic;
send_store_controller : process (clk) is
variable output : std_logic_vector(0 to C_TWIDTH-1);
begin
if( rising_edge(clk) ) then
if( sena = '1' ) then
if( swea = '1' ) then
store( conv_integer(saddr) ) <= sinput;
end if;
soutput <= store( conv_integer(saddr) );
end if;
end if;
end process send_store_controller;
end behavioral;
| bsd-3-clause | 6d0a8ff70b3e9d2f6c0c2dc779a8e078 | 0.554399 | 4.215801 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_hwti_v3_00_a/hdl/vhdl/bram_imp_dual.vhd | 2 | 2,919 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY bram_imp_dual IS
port (
clk: IN std_logic;
addra: IN std_logic_VECTOR(0 to 12);
dia: IN std_logic_VECTOR(0 to 31);
doa: OUT std_logic_VECTOR(0 to 31);
ena : IN std_logic;
wea: IN std_logic;
addrb: IN std_logic_VECTOR(0 to 12);
dib: IN std_logic_VECTOR(0 to 31);
dob: OUT std_logic_VECTOR(0 to 31);
enb : IN std_logic;
web: IN std_logic);
END bram_imp_dual;
ARCHITECTURE beh of bram_imp_dual is
--BRAM DECLARATION SIGNALS
type ram_type is array (0 to 8191) of std_logic_vector (0 to 31);
shared variable RAM : ram_type;
BEGIN
porta : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) := dia;
end if;
doa <= RAM(conv_integer(addra));
end if;
end process;
portb : process
begin
wait until rising_edge(clk);
if (enb = '1') then
if (web = '1') then
RAM(conv_integer(addrb)) := dib;
end if;
dob <= RAM(conv_integer(addrb));
end if;
end process;
END beh;
| bsd-3-clause | 2dc733e88877eee6e0d17936a27c4979 | 0.67112 | 3.912869 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_pkg.vhd | 1 | 6,925 | ---------------------------------------------------------------
-- Title : Package for flash types
-- Project :
---------------------------------------------------------------
-- File : z126_01_pkg.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--! \desid
--! \archid
--! \desbody
---------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: z126_01_pkg.vhd,v $
-- Revision 1.2 2014/11/24 16:44:14 AGeissler
-- R1: Magic numbers
-- M1: Added constants for used coded signals
--
-- Revision 1.1 2014/03/03 17:49:48 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.fpga_pkg_2.ALL;
PACKAGE z126_01_pkg IS
TYPE flash_type IS (NONE, M25P32, M25P64, M25P128);
TYPE supported_flash_types IS array (natural range <>) OF flash_type; -- for mor than one supported devices
SUBTYPE supported_flash_type IS flash_type; -- for exactly one supported device
--------------------------------------------------------------------
-- Remote update parameters
--------------------------------------------------------------------
-- CYCLONE V
CONSTANT Z126_01_RU_RECONF_CON_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "000";
CONSTANT Z126_01_RU_WDOG_VAL_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "010";
CONSTANT Z126_01_RU_WDOG_EN_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "011";
CONSTANT Z126_01_RU_PAGE_SEL_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "100";
CONSTANT Z126_01_RU_CONF_MODE_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "101";
-- CYCLONE IV and CYCLONE III
CONSTANT Z126_01_RU_STATE_MODE_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "000";
CONSTANT Z126_01_RU_CONF_DONE_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "001";
CONSTANT Z126_01_RU_WDOG_VAL_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "010";
CONSTANT Z126_01_RU_WDOG_EN_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "011";
CONSTANT Z126_01_RU_BOOT_ADR_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "100";
CONSTANT Z126_01_RU_INT_OSCI_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "110";
CONSTANT Z126_01_RU_RECONF_CON_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "111";
--------------------------------------------------------------------
-- Remote update read source (only for cyclone III and cyclone IV
--------------------------------------------------------------------
CONSTANT Z126_01_RU_RD_SRC_CURRENT : std_logic_vector(1 DOWNTO 0) := "00";
CONSTANT Z126_01_RU_RD_SRC_PREVIOUS_1 : std_logic_vector(1 DOWNTO 0) := "01";
CONSTANT Z126_01_RU_RD_SRC_PREVIOUS_2 : std_logic_vector(1 DOWNTO 0) := "10";
CONSTANT Z126_01_RU_RD_SRC_INPUT_REG : std_logic_vector(1 DOWNTO 0) := "11";
TYPE pasmi_out_type IS record
addr : std_logic_vector(23 DOWNTO 0);
bulk_erase : std_logic;
data : std_logic_vector(7 DOWNTO 0);
fast_read : std_logic;
rden : std_logic;
read_sid : std_logic;
read_rdid : std_logic;
read_status : std_logic;
sector_erase : std_logic;
sector_protect : std_logic;
shift_bytes : std_logic;
wren : std_logic;
write : std_logic;
read : std_logic;
END record;
TYPE pasmi_in_type IS record
illegal_erase : std_logic;
illegal_write : std_logic;
epcs_id : std_logic_vector(7 DOWNTO 0);
rdid : std_logic_vector(7 DOWNTO 0);
status : std_logic_vector(7 DOWNTO 0);
busy : std_logic;
data_valid : std_logic;
data : std_logic_vector(7 DOWNTO 0);
END record;
TYPE ctrl_wb2pasmi_out_type IS record
read_sid : std_logic;
sector_protect : std_logic;
write : std_logic;
read_status : std_logic;
sector_erase : std_logic;
bulk_erase : std_logic;
END record;
TYPE ctrl_wb2pasmi_in_type IS record
illegal_write : std_logic;
illegal_erase : std_logic;
busy : std_logic;
END record;
FUNCTION no_valid_device(
supported_devices : IN supported_flash_types;
device : IN flash_type )
RETURN boolean;
FUNCTION no_valid_device(
supported_device : IN supported_flash_type;
device : IN flash_type )
RETURN boolean;
END z126_01_pkg;
PACKAGE BODY z126_01_pkg IS
FUNCTION no_valid_device(
supported_devices : IN supported_flash_types;
device : IN flash_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
FOR i IN supported_devices'range LOOP
IF(device = supported_devices(i)) THEN
no_valid := FALSE;
ELSE
no_valid := no_valid;
END IF;
END LOOP;
RETURN no_valid;
END no_valid_device;
FUNCTION no_valid_device(
supported_device : IN supported_flash_type;
device : IN flash_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
IF(device = supported_device) THEN
no_valid := FALSE;
ELSE
no_valid := TRUE;
END IF;
RETURN no_valid;
END no_valid_device;
END;
| gpl-3.0 | a3c598a05ee225b07808a237f6839abe | 0.521444 | 3.923513 | false | false | false | false |
michaelmiehling/A25_VME | 16z024-01_src/Source/iram_wb.vhd | 1 | 8,239 | ---------------------------------------------------------------
-- Title : Internal RAM with Wishbone I/F
-- Project : 16z024-01
---------------------------------------------------------------
-- File : iram_wb.vhd
-- Author : Ferdinand Lenhardt
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/05/05
---------------------------------------------------------------
-- Simulator : ModelSim-Altera 5.8e
-- Synthesis : Quartus II 4.2 SP1
---------------------------------------------------------------
-- Description :
--
-- This module includes an arbitrary number of FPGA block RAMs.
-- A HEX (Intel-Format) file can be used to initialize the RAM.
-- For ACEX this module can be used only as a ROM.
---------------------------------------------------------------
-- Hierarchy:
--
-- iram_wb
-- lpm_ram_dq
-- altsyncram
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: iram_wb.vhd,v $
-- Revision 1.8 2017/05/10 Greg Daniluk <[email protected]>
-- Generalized to instantiate altsyncram (for Cyclone, Cyclone2, Cyclone3,
-- Cyclone4, Cyclone 5, Arria GX) and lpm_ram_dq (for Acex).
--
-- Revision 1.7 2014/11/20 14:45:22 AGeissler
-- R1: Missing Cyclone V support
-- M1: Added Cyclone V support
--
-- Revision 1.6 2010/12/17 17:04:48 FWombacher
-- Added Cyclone IV RAM instance
--
-- Revision 1.5 2009/01/27 14:30:13 FLenhardt
-- Added support for fpga_pkg_2 (ACEX,ARRIA_GX,CYCLONE2,CYCLONE3)
--
-- Revision 1.4 2007/11/21 13:46:01 FLenhardt
-- Added a commentary to generic USEDW_WIDTH
-- Added ERR output to Wishbone interface
--
-- Revision 1.3 2006/02/27 16:49:39 TWickleder
-- Added read_only as generic to disable the we signal
--
-- Revision 1.2 2005/11/28 15:05:45 mmiehling
-- bug fix: (stb_i AND cyc_i) = '1' => (stb_i = '1' AND cyc_i = '1')
--
-- Revision 1.1 2005/05/30 09:43:02 flenhardt
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.ALL;
library lpm;
use lpm.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_wb IS
GENERIC
(
FPGA_FAMILY: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,CYCLONE4,CYCLONE5,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
USEDW_WIDTH: positive := 6; -- 2**(USEDW_WIDTH + 2) bytes
LOCATION: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
err_o : OUT std_logic; -- error
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((USEDW_WIDTH + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_wb;
ARCHITECTURE iram_wb_arch OF iram_wb IS
CONSTANT SUPPORTED_DEVICES : supported_family_types := (ACEX,CYCLONE,CYCLONE2,CYCLONE3,CYCLONE4,CYCLONE5,ARRIA_GX);
COMPONENT lpm_ram_dq
GENERIC (
lpm_address_control : STRING;
lpm_file : STRING;
lpm_indata : STRING;
lpm_outdata : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthad : NATURAL);
PORT (
address : IN STD_LOGIC_VECTOR ((USEDW_WIDTH - 1) DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
we : IN STD_LOGIC);
END COMPONENT;
SIGNAL ack_o_int: std_logic;
SIGNAL we_int: std_logic;
SIGNAL sel_int: std_logic_vector(3 DOWNTO 0);
SIGNAL dat_int: std_logic_vector(31 DOWNTO 0);
BEGIN
gen_we: IF read_only = 0 GENERATE
we_control: PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
we_int <= '0';
ELSIF(clk'EVENT AND clk = '1') THEN
IF((stb_i = '1' AND cyc_i = '1') AND ack_o_int = '0') THEN
we_int <= we_i;
ELSE
we_int <= '0';
END IF;
END IF;
END PROCESS we_control;
sel_int <= sel_i;
dat_int <= dat_i;
END GENERATE;
dis_we: IF read_only = 1 GENERATE
we_int <= '0';
dat_int <= (OTHERS => '0');
END GENERATE;
dis_sel: IF(read_only = 1 AND FPGA_FAMILY /= ACEX) GENERATE
sel_int <= (OTHERS => '0');
END GENERATE dis_sel;
gen_acex: IF(FPGA_FAMILY = ACEX) GENERATE
gen_acex_rom: IF(read_only = 1) GENERATE
lpm_ram_dq_component : lpm_ram_dq
GENERIC MAP (
lpm_address_control => "REGISTERED",
lpm_file => LOCATION,
lpm_indata => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_type => "LPM_RAM_DQ",
lpm_width => 32,
lpm_widthad => USEDW_WIDTH)
PORT MAP (
address => adr_i,
inclock => clk,
data => dat_int,
we => we_int,
q => dat_o);
END GENERATE gen_acex_rom;
ASSERT(read_only = 1) REPORT "IRAM: Read only for ACEX!" SEVERITY failure;
END GENERATE gen_acex;
gen_cyc: IF(FPGA_FAMILY = CYCLONE) GENERATE
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
outdata_aclr_a => "NONE",
width_byteena_a => 4,
byte_size => 8,
byteena_aclr_a => "NONE",
init_file => LOCATION,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram")
PORT MAP (
wren_a => we_int,
clock0 => clk,
byteena_a => sel_int,
address_a => adr_i,
data_a => dat_int,
q_a => dat_o);
END GENERATE gen_cyc;
gen_cyclones: if(FPGA_FAMILY=CYCLONE2 or FPGA_FAMILY=CYCLONE3 or
FPGA_FAMILY=CYCLONE4 or FPGA_FAMILY=CYCLONE5 or FPGA_FAMILY=ARRIA_GX) generate
altsyncram_component : altsyncram
GENERIC MAP (
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => LOCATION,
intended_device_family => altera_device_family(FPGA_FAMILY),
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**USEDW_WIDTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
widthad_a => USEDW_WIDTH,
width_a => 32,
width_byteena_a => 4
)
PORT MAP (
wren_a => we_int,
clock0 => clk,
byteena_a => sel_int,
address_a => adr_i,
data_a => dat_int,
q_a => dat_o);
end generate;
ASSERT NOT NO_VALID_DEVICE(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "IRAM: No valid DEVICE!" SEVERITY failure;
control_logic: PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
ack_o_int <= '0';
ELSIF(clk'EVENT AND clk = '1') THEN
IF((stb_i = '1' AND cyc_i = '1') AND ack_o_int = '0') THEN
ack_o_int <= '1';
ELSE
ack_o_int <= '0';
END IF;
END IF;
END PROCESS control_logic;
ack_o <= ack_o_int;
err_o <= '0';
END iram_wb_arch;
| gpl-3.0 | c912fbb52cad86f0ad1af9fa72e57846 | 0.583809 | 3.219617 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_huffmanEncode.vhd | 2 | 21,738 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
READ_ARGS_4,
READ_ARGS_5,
FORLOOP_1,
FORLOOP_2,
FORLOOP_3,
FORLOOP_4,
WHILE_A_1,
WHILE_A_2,
WHILE_A_3,
WHILE_B_1,
WHILE_B_2,
WHILE_B_3,
WHILE_B_4,
WHILE_B_5,
WHILE_B_6,
FLUSH_1,
FLUSH_2,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant MAX_SIZE : std_logic_vector(0 to 31) := x"00000400";
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal bufer, buffer_next : std_logic_vector(0 to 31);
signal bufLen, bufLen_next : std_logic_vector(0 to 31);
signal outputIndex, outputIndex_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal len, len_next : std_logic_vector(0 to 31);
signal pos, pos_next : std_logic_vector(0 to 31);
signal inputData, inputData_next : std_logic_vector(0 to 31);
signal outputData, outputData_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
bufer <= buffer_next;
bufLen <= bufLen_next;
outputIndex <= outputIndex_next;
index <= index_next;
len <= len_next;
pos <= pos_next;
inputData <= inputData_next;
outputData <= outputData_next;
count <= count_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
buffer_next <= bufer;
bufLen_next <= bufLen;
outputIndex_next <= outputIndex;
index_next <= index;
len_next <= len;
pos_next <= pos;
inputData_next <= inputData;
outputData_next <= outputData;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
buffer_next <= Z32;
bufLen_next <= Z32;
outputIndex_next <= Z32;
index_next <= Z32;
len_next <= Z32;
pos_next <= Z32;
inputData_next <= Z32;
outputData_next <= Z32;
count_next <= Z32;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
-- int Code[MAX_SIZE]
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Declare an array of MAX_SIZE on the stack
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= MAX_SIZE;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
-- struct HuffmanStructure * huffman = (struct HuffmanStructure *)arg;
when READ_ARGS_2 =>
-- Read value of inputData pointer
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
when READ_ARGS_3 =>
inputData_next <= toUser_value;
-- Read value of outputData pointer
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_4;
next_state <= WAIT_STATE;
when READ_ARGS_4 =>
outputData_next <= toUser_value;
-- Read value of count
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
return_state_next <= READ_ARGS_5;
next_state <= WAIT_STATE;
when READ_ARGS_5 =>
count_next <= toUser_value;
next_state <= FORLOOP_1;
-- for ( index = 0; index < huffman->count; index++ );
when FORLOOP_1 =>
-- index was initialized in the start state
-- check to see if index is less than count
if ( index < count ) then
next_state <= FORLOOP_2;
else
next_state <= FLUSH_1;
end if;
-- Len = 0;
-- Pos = huffman->inputData[Index];
when FORLOOP_2 =>
-- len was initialized in the start state
-- read the character to encode
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= inputData + (index(2 to 31) & "00");
return_state_next <= FORLOOP_3;
next_state <= WAIT_STATE;
when FORLOOP_3 =>
pos_next <= toUser_value;
next_state <= WHILE_A_1;
-- while ((pos < MAX_SIZE) && (huffman->code.Parent[Pos] >= 0 ))
when WHILE_A_1 =>
-- check to see if pos < MAX_SIZE
if ( pos < MAX_SIZE ) then
-- read the value of huffman->code.Parent[pos]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000100C" + (pos(2 to 31) & "00");
return_state_next <= WHILE_A_2;
next_state <= WAIT_STATE;
else
next_state <= WHILE_B_1;
end if;
-- code[len++] = huffman->code.bit[pos]
-- pos = huffman->code.parent[pos]
when WHILE_A_2 =>
-- check to see of huffman->code.Parent[pos] >= 0
-- can check this by inspecting the bit 0
case toUser_value(0) is
when '0' =>
-- this is a positive number or zero
pos_next <= toUser_value;
-- read the value of huffman->code.bit[pos]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000400C" + (pos(2 to 31) & "00");
return_state_next <= WHILE_A_3;
next_state <= WAIT_STATE;
when others =>
-- this is a negative number
next_state <= WHILE_B_1;
end case;
when WHILE_A_3 =>
-- set code[len] to the value of huffman->code.bit[pos]
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_value <= toUser_value;
thrd2intrfc_address <= len;
-- increment len
len_next <= len + x"00000001";
return_state_next <= WHILE_A_1;
next_state <= WAIT_STATE;
-- end of while loop
-- while( len > 0 )
when WHILE_B_1 =>
case len is
when x"00000000" =>
-- len is = 0
next_state <= FORLOOP_4;
when others =>
-- len is > 0
-- decrement len in preparation for next step
len_next <= len - x"00000001";
next_state <= WHILE_B_2;
end case;
-- Buffer = (Buffer << 1) | Code[--Len];
when WHILE_B_2 =>
-- read the value of code[len]
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_value <= toUser_value;
thrd2intrfc_address <= len;
return_state_next <= WHILE_B_3;
next_state <= WAIT_STATE;
-- BufLen++;
when WHILE_B_3 =>
-- set the value of buffer
--buffer_next <= (bufer(1 to 31) & '0') | toUser_value;
buffer_next <= bufer(1 to 31) & toUser_value(31);
-- increment buflen
buflen_next <= bufLen + x"00000001";
next_state <= WHILE_B_4;
-- if ( BufLen == 32 )
-- huffman->outputData[outputIndex] = Buffer
when WHILE_B_4 =>
-- check to see if BufLen == 32, do this by checking bit 26
case bufLen(26) is
when '0' =>
-- bufLen is less than 32
next_state <= WHILE_B_1;
when others =>
-- bufLen is 32
-- store the value of outputData[outputIndex]
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= bufer;
thrd2intrfc_address <= outputData + (outputIndex(2 to 31) & "00");
return_state_next <= WHILE_B_5;
next_state <= WAIT_STATE;
end case;
-- outputIndex++;
-- Buffer = 0;
-- BufLen = 0;
when WHILE_B_5 =>
outputIndex_next <= outputIndex + x"00000001";
buffer_next <= Z32;
bufLen_next <= Z32;
next_state <= WHILE_B_1;
-- end if statement
-- end while loop
when FORLOOP_4 =>
-- increment index
index_next <= index + x"00000001";
next_state <= FORLOOP_1;
-- end for loop
-- if ( bufLen != 0 )
-- Buffer = Buffer << (32 - BufLen)
when FLUSH_1 =>
-- check to see if bufLen is equal to 0, only have to check last 6 bits
-- if it is not 0, check the value to know how much to shift buffer
case bufLen(26 to 31) is
when "000000" =>
next_state <= EXIT_THREAD;
when "000001" =>
buffer_next <= bufer(31) & Z32(0 to 30);
next_state <= FLUSH_2;
when "000010" =>
buffer_next <= bufer(30 to 31) & Z32(0 to 29);
next_state <= FLUSH_2;
when "000011" =>
buffer_next <= bufer(29 to 31) & Z32(0 to 28);
next_state <= FLUSH_2;
when "000100" =>
buffer_next <= bufer(28 to 31) & Z32(0 to 27);
next_state <= FLUSH_2;
when "000101" =>
buffer_next <= bufer(27 to 31) & Z32(0 to 26);
next_state <= FLUSH_2;
when "000110" =>
buffer_next <= bufer(26 to 31) & Z32(0 to 25);
next_state <= FLUSH_2;
when "000111" =>
buffer_next <= bufer(25 to 31) & Z32(0 to 24);
next_state <= FLUSH_2;
when "001000" =>
buffer_next <= bufer(24 to 31) & Z32(0 to 23);
next_state <= FLUSH_2;
when "001001" =>
buffer_next <= bufer(23 to 31) & Z32(0 to 22);
next_state <= FLUSH_2;
when "001010" =>
buffer_next <= bufer(22 to 31) & Z32(0 to 21);
next_state <= FLUSH_2;
when "001011" =>
buffer_next <= bufer(21 to 31) & Z32(0 to 20);
next_state <= FLUSH_2;
when "001100" =>
buffer_next <= bufer(20 to 31) & Z32(0 to 19);
next_state <= FLUSH_2;
when "001101" =>
buffer_next <= bufer(19 to 31) & Z32(0 to 18);
next_state <= FLUSH_2;
when "001110" =>
buffer_next <= bufer(18 to 31) & Z32(0 to 17);
next_state <= FLUSH_2;
when "001111" =>
buffer_next <= bufer(17 to 31) & Z32(0 to 16);
next_state <= FLUSH_2;
when "010000" =>
buffer_next <= bufer(16 to 31) & Z32(0 to 15);
next_state <= FLUSH_2;
when "010001" =>
buffer_next <= bufer(15 to 31) & Z32(0 to 14);
next_state <= FLUSH_2;
when "010010" =>
buffer_next <= bufer(14 to 31) & Z32(0 to 13);
next_state <= FLUSH_2;
when "010011" =>
buffer_next <= bufer(13 to 31) & Z32(0 to 12);
next_state <= FLUSH_2;
when "010100" =>
buffer_next <= bufer(12 to 31) & Z32(0 to 11);
next_state <= FLUSH_2;
when "010101" =>
buffer_next <= bufer(11 to 31) & Z32(0 to 10);
next_state <= FLUSH_2;
when "010110" =>
buffer_next <= bufer(10 to 31) & Z32(0 to 9);
next_state <= FLUSH_2;
when "010111" =>
buffer_next <= bufer(9 to 31) & Z32(0 to 8);
next_state <= FLUSH_2;
when "011000" =>
buffer_next <= bufer(8 to 31) & Z32(0 to 7);
next_state <= FLUSH_2;
when "011001" =>
buffer_next <= bufer(7 to 31) & Z32(0 to 6);
next_state <= FLUSH_2;
when "011010" =>
buffer_next <= bufer(6 to 31) & Z32(0 to 5);
next_state <= FLUSH_2;
when "011011" =>
buffer_next <= bufer(5 to 31) & Z32(0 to 4);
next_state <= FLUSH_2;
when "011100" =>
buffer_next <= bufer(4 to 31) & Z32(0 to 3);
next_state <= FLUSH_2;
when "011101" =>
buffer_next <= bufer(3 to 31) & Z32(0 to 2);
next_state <= FLUSH_2;
when "011110" =>
buffer_next <= bufer(2 to 31) & Z32(0 to 1);
next_state <= FLUSH_2;
when "011111" =>
buffer_next <= bufer(1 to 31) & Z32(0);
next_state <= FLUSH_2;
when others =>
-- should never get to this state
next_state <= EXIT_THREAD;
end case;
-- huffman->outputData[outputIndex] = Buffer
when FLUSH_2 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= bufer;
thrd2intrfc_address <= outputData + (outputIndex(2 to 31) & "00");
return_state_next <= EXIT_THREAD;
next_state <= WAIT_STATE;
-- end if statement
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fbec0aa7627c60f83f5dd45e738b7153 | 0.557733 | 3.659596 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/plb_fsmlang_special_pic.vhd | 2 | 34,941 | ------------------------------------------------------------------------------
-- plb_fsmlang_special_pic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_fsmlang_special_pic.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
library plbv46_master_single_v1_00_a;
use plbv46_master_single_v1_00_a.plbv46_master_single;
library plb_fsmlang_special_pic_v1_00_a;
use plb_fsmlang_special_pic_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_fsmlang_special_pic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := X"11000000";
C_NUM_INTERRUPTS : integer := 8;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS-1);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_fsmlang_special_pic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_fsmlang_special_pic is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_00_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_fsmlang_special_pic_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_TM_BASE => C_TM_BASE,
C_IID_WIDTH => log2(C_NUM_INTERRUPTS),
C_REG_SIZE => C_REG_SIZE,
C_CMD_WIDTH => C_CMD_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
interrupts_in => interrupts_in ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
end IMP;
| bsd-3-clause | c6a909cbfffa1b8b18c6d58c35247637 | 0.461693 | 4.238869 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/watchdog_timer.vhd | 3 | 12,783 | -------------------------------------------------------------------------------
-- $Id: watchdog_timer.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- watchdog_timer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: watchdog_timer.vhd
-- Version: v1.02e
-- Description:
-- This file contains the watchdog timer and generates the
-- OPB_timeout signal if OPB_retry, OPB_xferAck, or
-- OPB_toutSup are not asserted within 15 clock cycles after
-- OPB_select is asserted.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- Registered Opb_timeout, therefore OPB_XferAck, OPB_Retry, and OPB_toutSup MUST
-- be asserted in 15 clocks instead of 16
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
--Package file that contains constant definition for RESET_ACTIVE
--and OPB_TIMEOUT_CNT
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity
--
-- -- OPB Interface Signals
-- input OPB_select; -- master select
-- input OPB_xferAck; -- slave transfer acknowledge
-- input OPB_retry; -- slave retry
-- input OPB_toutSup; -- slave timeout suppress
-- output OPB_timeout; -- timeout asserted OPB_TIMEOUT_CNT
-- -- clocks after OPB_select asserts
-- -- Clock and Reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity watchdog_timer is
port (
OPB_select : in std_logic;
OPB_xferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_timeout : out std_logic;
Clk : in std_logic;
Rst : in std_logic
);
end watchdog_timer;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of watchdog_timer is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in opb_arbiter_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal timeout_cnt : unsigned(0 to 3 ); -- output from counter
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- WATCHDOG_TIMER_PROCESS
-------------------------------------------------------------------------------
-- This process counts clocks after OPB_select is asserted while OPB_xferAck
-- and OPB_retry are negated. The assertion of OPB_toutSup suspends the counter.
-------------------------------------------------------------------------------
WATCHDOG_TIMER_PROCESS:process (Clk, Rst, OPB_select, OPB_retry, OPB_xferAck,
OPB_toutSup, timeout_cnt)
begin
if Clk'event and Clk = '1' then
-- active high, synchronous reset
if Rst = RESET_ACTIVE then
timeout_cnt <= (others => '0');
elsif OPB_select = '1' and OPB_retry = '0' and OPB_xferAck = '0' then
-- Enable timeout counter once OPB_select asserts
-- and OPB_retry and OPB_xferAck are negated.
-- Reset counter if either OPB_retry or
-- OPB_xferAck assert while OPB_select
-- is asserted
if OPB_toutSup = '0' then
timeout_cnt <= timeout_cnt + 1;
else
timeout_cnt <= timeout_cnt;
end if;
else
timeout_cnt <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- TIMEOUT_PROCESS
-------------------------------------------------------------------------------
-- This process asserts the OPB_timeout signal when the output of the watchdog
-- timer is OPB_TIMEOUTCNT-2 (0-14=15 clocks) and OPB_toutSup is negated.
-- OPB_timeout is registered to improve FPGA implementation timing
-------------------------------------------------------------------------------
TIMEOUT_PROCESS:process (Clk,Rst)
begin -- process
-- Assert OPB_timeout OPB_TIMEOUT_CNT-2 clocks
-- after OPB_select asserts if OPB_toutSup is negated
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
OPB_Timeout <= '0';
elsif timeout_cnt = OPB_TIMEOUT_CNT -2 and OPB_toutSup = '0' and
OPB_select = '1' and OPB_retry = '0' and OPB_xferAck = '0'then
OPB_timeout <= '1';
else
OPB_timeout <= '0';
end if;
end if;
end process;
end implementation;
| bsd-3-clause | 23ec93b3d59e30f70091a94c4c230afe | 0.416256 | 5.355258 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/self_1.vhd | 2 | 15,079 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- self_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_t * thread = (hthread_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- if ( *thread == hthread_self() ) retVal = SUCCESS;
-- else retVal = FAILURE;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Call hthread_self
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_2;
next_state <= WAIT_STATE;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Load the value of *thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
if ( reg1 = intrfc2thrd_value ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 862e56379d9e5c16f812bd00607835ad | 0.536839 | 3.85258 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/example_design/FiFo512Core32W32R_exdes.vhd | 1 | 5,592 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity FiFo512Core32W32R_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end FiFo512Core32W32R_exdes;
architecture xilinx of FiFo512Core32W32R_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component FiFo512Core32W32R is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : FiFo512Core32W32R
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | cf51fb9426d54f2770a4773c51052174 | 0.501609 | 4.640664 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_scheduler_smp_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 119,458 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_NUM_CPUS : integer := 2;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
-- current_thread for CPU 0 = TM2SCH_current_cpu_tid(0 to 7)
-- current_thread for CPU 1 = TM2SCH_current_cpu_tid(8 to 15)
-- current_thread for CPU N = TM2SCH_current_cpu_tid(8*(N-1) to 8*N-1)
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 8*C_NUM_CPUS - 1);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
-- preempt for CPU 0 = Preemption_Interrupt(0)
-- preempt for CPU 1 = Preemption_Interrupt(1)
-- preempt for CPU N = Preemption_Interrupt(N-1)
Preemption_Interrupt : out std_logic_vector(0 to C_NUM_CPUS - 1);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Local copy of port signal SCH2TM_next_tid_valid
signal Next_Thread_Valid_reg : std_logic;
signal Next_Thread_Valid_next : std_logic;
-- Store temporary value of Next_Thread_Valid_reg
signal temp_valid : std_logic;
signal temp_valid_next : std_logic;
-- Local copy of cpu specific preemption signals
signal Preemption_Interrupt_Line : std_logic_vector(0 to C_NUM_CPUS - 1);
signal Preemption_Interrupt_Enable : std_logic_vector(0 to C_NUM_CPUS - 1);
signal Preemption_Interrupt_Enable_next : std_logic_vector(0 to C_NUM_CPUS - 1);
-- Local copy of port signal TM2SCH_current_cpu_tid
signal current_thread_id_reg : std_logic_vector(0 to 8*C_NUM_CPUS - 1);
-- Track the priorities of threads executing on all CPU's
-- 0 to 7 implies CPU 0, 8 to 15 implies CPU 1
-- 16 to 23 implies CPU 2, 24 to 31 implies CPU 4
signal current_priority_reg : std_logic_vector(0 to 7*C_NUM_CPUS - 1);-- := (others => '1');
signal current_priority_next : std_logic_vector(0 to 7*C_NUM_CPUS - 1);-- := (others => '1');
-- Local copy of port signal SCH2TM_next_cpu_tid
signal next_thread_id_reg : std_logic_vector(0 to 7);
signal next_thread_id_next : std_logic_vector(0 to 7);
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- Track idle_thread information for each processor
signal idle_thread_id : std_logic_vector(0 to 8*C_NUM_CPUS - 1);
signal idle_thread_id_next : std_logic_vector(0 to 8*C_NUM_CPUS - 1);
signal idle_thread_valid : std_logic_vector(0 to C_NUM_CPUS - 1);
signal idle_thread_valid_next : std_logic_vector(0 to C_NUM_CPUS - 1);
-- This signal stores information about which CPU we are currently using
signal current_CPU : integer := 0;
signal current_CPU_next : integer := 0;
-- Define the memory map for each command register, Address[24 to 31]
-- This value is the offset from the base address assigned to this module
constant C_SYSCALL_LOCK : std_logic_vector(0 to 7) := "00111100"; -- 0x3C
constant C_MALLOC_LOCK : std_logic_vector(0 to 7) := "01000100"; -- 0x44
constant C_SET_PREEMPTION : std_logic_vector(0 to 7) := "01001000"; -- 0x48
constant C_GET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010000"; -- 0x50
constant C_SET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010100"; -- 0x54
constant C_READ_DEBUG_0 : std_logic_vector(0 to 7) := "01011000"; -- 0x58
constant C_SET_SCHEDPARAM : std_logic_vector(0 to 7) := "01011100"; -- 0x5C
constant C_GET_ENTRY : std_logic_vector(0 to 7) := "01100000"; -- 0x60
constant C_GET_SCHEDPARAM : std_logic_vector(0 to 7) := "01100100"; -- 0x64
constant C_CHECK_SCHEDPARAM : std_logic_vector(0 to 7) := "01101000"; -- 0x68
constant C_MASTER_READ_DATA : std_logic_vector(0 to 7) := "01110000"; -- 0x70
constant C_READ_DEBUG_1 : std_logic_vector(0 to 7) := "01110100"; -- 0x74
constant C_READ_DEBUG_2 : std_logic_vector(0 to 7) := "01111000"; -- 0x78
constant C_READ_CURRENT : std_logic_vector(0 to 7) := "10000000"; -- 0x80
constant C_READ_NEXT : std_logic_vector(0 to 7) := "10000100"; -- 0x84
constant C_READ_PRIORITY : std_logic_vector(0 to 7) := "10001000"; -- 0x88
-- TM Command Opcodes
constant ENQUEUE_OPCODE : std_logic_vector(0 to 5) := "000010";
constant DEQUEUE_OPCODE : std_logic_vector(0 to 5) := "000011";
constant IS_QUEUED_OPCODE : std_logic_vector(0 to 5) := "000001";
constant IS_EMPTY_OPCODE : std_logic_vector(0 to 5) := "000110";
constant IDLE_ID_REQ_OPCODE : std_logic_vector(0 to 5) := "001100";
-- HW Thread Opcodes
constant HW_THREAD_START : std_logic_vector(0 to 3) := "0001";
-- Initialization Strings & Constants
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant BRAM_init_string : std_logic_vector(0 to 31) := Z32(0 to 31);
-- Busy Signals
signal sched_busy : std_logic;
signal sched_busy_next : std_logic;
-- Reset Signals
signal reset_addr : std_logic_vector(0 to 8);
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- TM Output Controller signals
signal TM_data_ready : std_logic;
signal TM_data_out : std_logic_vector (0 to 7);
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Debug Registers
-- debug_reg_0: Unchanged from previous design
--
-- debug_reg_1 definition:
-- bit(s) signal
-- 0-7 current_thread_id_reg(CPUID)
-- 8-15 next_thread_id_reg(CPUID)
-- 16-23 idle_thread_id(CPUID)
-- 24 '0'
-- 25-31 current_priority_reg(CPUID)
--
-- debug_reg_2 definition:
-- bit(s) signal
-- 0-22 variable
-- 23 Preemption_Interrupt_Line(CPUID)
-- 24 Preemption_Interrupt_Enable(CPUID)
-- 25 temp_valid
-- 26 '0'
-- 27 Next_Thread_Valid_reg
-- 28 idle_thread_valid(CPUID)
-- 29-31 CPUID
signal debug_reg_0 : std_logic_vector(0 to 31);
signal debug_reg_next_0 : std_logic_vector(0 to 31);
signal debug_reg_1 : std_logic_vector(0 to 31);
signal debug_reg_2 : std_logic_vector(0 to 31);
-- Lock/Mutex signals
signal lock_op : std_logic;
signal lock_op_next : std_logic;
signal lock_count : std_logic_vector(0 to 3);
signal lock_count_next : std_logic_vector(0 to 3);
signal syscall_mutex : std_logic;
signal syscall_mutex_next : std_logic;
signal malloc_mutex : std_logic;
signal malloc_mutex_next : std_logic;
signal syscall_mutex_holder : std_logic_vector(0 to 1);
signal syscall_mutex_holder_next : std_logic_vector(0 to 1);
signal malloc_mutex_holder : std_logic_vector(0 to 7);
signal malloc_mutex_holder_next : std_logic_vector(0 to 7);
-- Reset Signals
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Set_SchedParam_Request : std_logic;
signal Get_SchedParam_Request : std_logic;
signal Check_SchedParam_Request : std_logic;
signal Preemption_Request : std_logic;
signal Get_IdleThread_Request : std_logic;
signal Set_IdleThread_Request : std_logic;
signal Is_Queued_Request : std_logic;
signal Is_Empty_Request : std_logic;
signal Get_Entry_Request : std_logic;
signal SYSCALL_Lock_Request : std_logic;
signal MALLOC_Lock_Request : std_logic;
signal Idle_Id_Request : std_logic;
signal Current_Request : std_logic;
signal Next_Request : std_logic;
signal Priority_Request : std_logic;
signal Debug_0_Request : std_logic;
signal Debug_1_Request : std_logic;
signal Debug_2_Request : std_logic;
signal Error_Request : std_logic;
-- State Machine data signals
signal lookup_entry : std_logic_vector(0 to 31);
signal lookup_entry_next : std_logic_vector(0 to 31);
signal dequeue_entry : std_logic_vector(0 to 31);
signal dequeue_entry_next : std_logic_vector(0 to 31);
signal enqueue_entry : std_logic_vector(0 to 31);
signal enqueue_entry_next : std_logic_vector(0 to 31);
signal enqueue_pri_entry : std_logic_vector(0 to 31);
signal enqueue_pri_entry_next : std_logic_vector(0 to 31);
signal deq_pri_entry : std_logic_vector(0 to 31);
signal deq_pri_entry_next : std_logic_vector(0 to 31);
signal sched_param : std_logic_vector(0 to 31);
signal sched_param_next : std_logic_vector(0 to 31);
signal old_tail_ptr : std_logic_vector(0 to 7);
signal old_tail_ptr_next : std_logic_vector(0 to 7);
signal old_priority : std_logic_vector(0 to 6);
signal old_priority_next : std_logic_vector(0 to 6);
signal new_priority : std_logic_vector(0 to 6);
signal new_priority_next : std_logic_vector(0 to 6);
signal lookup_id : std_logic_vector(0 to 7);
signal lookup_id_next : std_logic_vector(0 to 7);
signal temp_id : std_logic_vector(0 to 7);
signal temp_id_next : std_logic_vector(0 to 7);
signal temp_idle_id : std_logic_vector(0 to 7);
signal temp_idle_id_next : std_logic_vector(0 to 7);
-- BRAM Constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- BRAM signals (THREAD_DATA)
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENA : std_logic := '0';
signal WEA : std_logic := '0';
-- BRAM signals (PRIORITY_DATA)
signal DOB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRB : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENB : std_logic := '0';
signal WEB : std_logic := '0';
-- BRAM signals (PARAM_DATA)
signal DOU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRU : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENU : std_logic := '0';
signal WEU : std_logic := '0';
-- Priority Encoder Constants & Signals
constant INPUT_BITS : integer := 128;
constant OUTPUT_BITS : integer := 7;
constant CHUNK_BITS : integer := 32;
signal encoder_reset : std_logic;
signal encoder_input : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_input_next : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_output : std_logic_vector(0 to OUTPUT_BITS - 1);
signal encoder_enable_next : std_logic;
signal encoder_enable : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_BRAM,
reset_wait_4_ack,
-- enqueue states
ENQ_begin,
ENQ_check_idle,
ENQ_lookup_enqueue_entry_idle,
ENQ_lookup_enqueue_entry_finished,
ENQ_start_hw_thread_begin,
ENQ_start_hw_thread_finished,
ENQ_lookup_enqueue_pri_entry_idle,
ENQ_lookup_enqueue_pri_entry_finished,
ENQ_init_head_pointer,
ENQ_init_tail_pointer,
ENQ_wait_for_encoder_0,
ENQ_lookup_old_tail_ptr,
ENQ_lookup_old_tail_ptr_idle,
ENQ_lookup_old_tail_ptr_finished,
ENQ_write_back_entries,
ENQ_lookup_highest_pri_entry,
ENQ_lookup_highest_pri_entry_idle,
ENQ_lookup_highest_pri_entry_finished,
ENQ_preemption_check,
ENQ_preemption_check_idle,
-- dequeue states
DEQ_begin,
DEQ_get_CPU_idle,
DEQ_lookup_dequeue_entry,
DEQ_lookup_dequeue_entry_idle,
DEQ_lookup_dequeue_entry_finished,
DEQ_lookup_deq_pri_entry_idle,
DEQ_lookup_deq_pri_entry_finished,
DEQ_lookup_old_head_ptr_idle,
DEQ_lookup_old_head_ptr_finished,
DEQ_write_back_entries,
DEQ_wait_for_encoder_0,
DEQ_wait_for_encoder_1,
DEQ_wait_for_encoder_2,
DEQ_check_encoder_output,
DEQ_lookup_highest_pri_entry_idle,
DEQ_lookup_highest_pri_entry_finished,
-- set_sched_param states
SET_SCHED_PARAM_begin,
SET_SCHED_PARAM_revalidate,
SET_SCHED_PARAM_lookup_setpri_entries_begin,
SET_SCHED_PARAM_lookup_setpri_entries_idle,
SET_SCHED_PARAM_lookup_setpri_entries_finished,
SET_SCHED_PARAM_lookup_old_pri_entry_idle,
SET_SCHED_PARAM_lookup_old_pri_entry_finished,
SET_SCHED_PARAM_priority_field_check,
SET_SCHED_PARAM_lookup_old_head_ptr_idle,
SET_SCHED_PARAM_lookup_old_head_ptr_finished,
SET_SCHED_PARAM_lookup_old_tail_ptr_idle,
SET_SCHED_PARAM_lookup_old_tail_ptr_finished,
SET_SCHED_PARAM_lookup_prev_ptr_idle,
SET_SCHED_PARAM_lookup_prev_ptr_finished,
SET_SCHED_PARAM_write_back_deq_pri_entry,
SET_SCHED_PARAM_begin_add_to_new_pri_queue,
SET_SCHED_PARAM_init_tail_ptr,
SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle,
SET_SCHED_PARAM_update_enqueue_info,
SET_SCHED_PARAM_write_back_entries,
SET_SCHED_PARAM_wait_for_encoder_0,
SET_SCHED_PARAM_wait_for_encoder_1,
SET_SCHED_PARAM_last_wait_0,
SET_SCHED_PARAM_last_wait_1,
SET_SCHED_PARAM_check_encoder,
SET_SCHED_PARAM_lookup_highest_pri_entry_idle,
SET_SCHED_PARAM_lookup_highest_pri_entry_finished,
SET_SCHED_PARAM_preemption_check,
SET_SCHED_PARAM_preemption_check_idle,
SET_SCHED_PARAM_return_with_error,
SET_SCHED_PARAM_return_with_no_error,
SET_SCHED_PARAM_check_if_current,
SET_SCHED_PARAM_update_current_priorities,
-- get_sched_param states
GET_SCHED_PARAM_begin,
GET_SCHED_PARAM_lookup_entry,
GET_SCHED_PARAM_lookup_entry_idle,
GET_SCHED_PARAM_lookup_entry_finished,
-- check_sched_param states
CHECK_SCHED_PARAM_begin,
CHECK_SCHED_PARAM_lookup_entries,
CHECK_SCHED_PARAM_lookup_entries_idle,
CHECK_SCHED_PARAM_lookup_entries_finished,
-- toggle_preemption states
SET_PREEMPTION_begin,
SET_PREEMPTION_idle,
SET_PREEMPTION_finished,
-- get_idle_thread states
GET_IDLE_THREAD_begin,
GET_IDLE_THREAD_idle,
GET_IDLE_THREAD_finished,
-- set_idle_thread states
SET_IDLE_THREAD_begin,
SET_IDLE_THREAD_lookup_entries_idle,
SET_IDLE_THREAD_lookup_entries_finished,
SET_IDLE_THREAD_return_with_error,
SET_IDLE_THREAD_return_with_no_error,
-- is_queued states
IS_QUEUED_begin,
IS_QUEUED_lookup_entry,
IS_QUEUED_lookup_entry_idle,
IS_QUEUED_lookup_entry_finished,
-- is_empty states
IS_EMPTY_check,
IS_EMPTY_finished,
-- get_entry states
GET_ENTRY_begin,
GET_ENTRY_lookup_entry,
GET_ENTRY_lookup_entry_idle,
GET_ENTRY_lookup_entry_finished,
SYSCALL_LOCK,
SYSCALL_LOCK_idle,
SYSCALL_LOCK_idle_finished,
SYSCALL_LOCK_ACQUIRE,
SYSCALL_LOCK_RELEASE,
MALLOC_LOCK,
MALLOC_LOCK_idle,
MALLOC_LOCK_idle_finished,
MALLOC_LOCK_ACQUIRE,
MALLOC_LOCK_ACQUIRE_RETURN,
MALLOC_LOCK_RELEASE,
MALLOC_LOCK_RELEASE_next,
MALLOC_LOCK_RELEASE_RETURN,
IDLE_ID_DEQ,
IDLE_ID_DEQ_CPU_idle,
IDLE_ID_DEQ_return,
READ_CURRENT,
READ_NEXT,
READ_PRIORITY,
READ_DEBUG_0,
READ_DEBUG_1,
READ_DEBUG_2
);
signal current_state_master, next_state_master : master_state_type := idle;
---------------------------------------------------
-- is_encoder_bit_zero()
--********************
-- Function used to check an encoder bit
-- Returns booleans:
-- * '0' --> True
-- * '1' --> False
---------------------------------------------------
function is_encoder_bit_zero(pri_index : integer; e_entry : std_logic_vector(0 to INPUT_BITS-1)) return boolean is
begin
if (e_entry(pri_index) = '0') then
return true;
else
return false;
end if;
end function is_encoder_bit_zero;
---------------------------------------------------
---------------------------------------------------
-- set_encoder_bit()
-- *******************
-- Function used to set an encoder bit
---------------------------------------------------
function set_encoder_bit(e_bit : std_logic; pri : integer; e_entry : std_logic_vector(0 to INPUT_BITS - 1)) return std_logic_vector is
variable temp_entry : std_logic_vector(0 to INPUT_BITS-1);
begin
temp_entry := e_entry; -- make a copy of the entry
temp_entry(pri) := e_bit; -- update bit in entry
return temp_entry; -- return new entry
end function set_encoder_bit;
---------------------------------------------------
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
---------------------------------------------------
-- get_head_pointer()
-- *******************
-- function to extract the head_pointer field from a
-- priority attribute entry
---------------------------------------------------
function get_head_pointer(entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7);
end function get_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_head_pointer()
-- *******************
-- function to set the head_pointer field for a
-- priority attribute entry
---------------------------------------------------
function set_head_pointer(head_ptr : std_logic_vector(0 to 7); entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return head_ptr & entry(8 to 31);
end function set_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_tail_pointer()
-- *******************
-- function to extract the tail_pointer field from a
-- priority attribute entry
---------------------------------------------------
function get_tail_pointer(entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(8 to 15);
end function get_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_tail_pointer()
-- *******************
-- function to set the tail_pointer field for a
-- priority attribute entry
---------------------------------------------------
function set_tail_pointer(tail_ptr : std_logic_vector(0 to 7); entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7) & tail_ptr & entry(16 to 31);
end function set_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_priority()
-- *******************
-- function to extract the priority field from a
-- scheduler attribute entry
---------------------------------------------------
function get_priority(entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(9 to 15);
end function get_priority;
---------------------------------------------------
---------------------------------------------------
-- set_priority()
-- *******************
-- function to set the priority field for a
-- scheduler attribute entry
---------------------------------------------------
function set_priority(priority : std_logic_vector(0 to 6); entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 8) & priority & entry(16 to 31);
end function set_priority;
---------------------------------------------------
---------------------------------------------------
-- get_next_pointer()
-- *******************
-- function to extract the next_pointer field from a
-- scheduler attribute entry
---------------------------------------------------
function get_next_pointer(entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(1 to 8);
end function get_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_next_pointer()
-- *******************
-- function to set the next_pointer field for a
-- scheduler attribute entry
---------------------------------------------------
function set_next_pointer(next_ptr : std_logic_vector(0 to 7); entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0) & next_ptr & entry(9 to 31);
end function set_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_prev_pointer()
-- *******************
-- function to extract the prev_pointer field from a
-- scheduler attribute entry
---------------------------------------------------
function get_prev_pointer(entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(16 to 23);
end function get_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_prev_pointer()
-- *******************
-- function to set the prev_pointer field for a
-- scheduler attribute entry
---------------------------------------------------
function set_prev_pointer(prev_ptr : std_logic_vector(0 to 7); entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 15) & prev_ptr & entry(24 to 31);
end function set_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_queue_bit()
-- *******************
-- function to extract the queue bit field from a
-- scheduler attribute entry
---------------------------------------------------
function get_queue_bit(entry : std_logic_vector(0 to 31)) return std_logic is
begin
return entry(0);
end function get_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- set_queue_bit()
-- *******************
-- function to set the queue bit field for a
-- scheduler attribute entry
---------------------------------------------------
function set_queue_bit(q_bit : std_logic; entry : std_logic_vector(0 to 31)) return std_logic_vector is
begin
return q_bit & entry(1 to 31);
end function set_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- check_preempt()
-- *******************
-- Check to see if we need to preempt a processor with a higher priority thread.
-- This function is called when either a new thread is added to the R2RQ or the
-- priority of a thread has changed due to a call to SET_SCHED_PARAM. This
-- function will determine the lowest priority thread that is interruptable.
-- For example, in a 4 CPU system with priorities 5 10 15 20 and the new thread
-- being added to the R2RQ has a priority of 12, it would be inefficient to
-- preempt the thread with a priority of 15 because this thread would just turn
-- around and preempt the thread with a priority of 20
---------------------------------------------------
function check_preempt(entry : std_logic_vector(0 to 6); compare : std_logic_vector(0 to 7*C_NUM_CPUS - 1)) return integer is
variable diff : integer := 0;
variable prev_diff : integer := 0;
variable ret_val : integer := conv_integer(C_NUM_CPUS);
begin
for i in 0 to (C_NUM_CPUS - 1) loop
if(compare((i * 7) to ((i * 7) + 6)) > entry) then
diff := conv_integer(compare((i * 7) to ((i * 7) + 6)) - entry);
if(diff > prev_diff) then
prev_diff := diff;
ret_val := i;
end if;
end if;
end loop;
return ret_val;
end function check_preempt;
---------------------------------------------------
-- check_if_current()
-- *******************
-- Check to see if the thread is "currently running", or equal to any of the currently running thread IDs
function check_if_current(entry : std_logic_vector(0 to 7); compare : std_logic_vector(0 to 8*C_NUM_CPUS - 1)) return integer is
variable diff : integer := 0;
variable prev_diff : integer := 0;
variable ret_val : integer := conv_integer(C_NUM_CPUS);
begin
for i in 0 to (C_NUM_CPUS - 1) loop
if(compare((i * 8) to ((i * 8) + 7)) = entry) then
ret_val := i;
end if;
end loop;
return ret_val;
end function check_if_current;
---------------------------------------------------
-- Component Instantiation of the Priority Encoder
---------------------------------------------------
component parallel
generic
(
INPUT_BITS : integer := 128;
OUTPUT_BITS : integer := 7;
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to 127);
enable : in std_logic;
output : out std_logic_vector(0 to 6)
);
end component parallel;
---------------------------------------------------
-- Component Instantiation of the Inferred BRAM entity
---------------------------------------------------
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port
(
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_BRAM;
---------------------------------------------------
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
---------------------------------------------------
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstWrReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin -- architecture IMP
---------------------------------------------------
-- Entity Instantiation of the Priority Encoder
---------------------------------------------------
priority_encoder : parallel
generic map
(
INPUT_BITS => INPUT_BITS,
OUTPUT_BITS => OUTPUT_BITS,
CHUNK_BITS => CHUNK_BITS
)
port map
(
clk => Bus2IP_Clk,
rst => encoder_reset,
input => encoder_input,
enable => encoder_enable,
output => encoder_output
);
---------------------------------------------------
-- Entity Instantiation of the THREAD_DATA BRAM
---------------------------------------------------
thread_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA
);
---------------------------------------------------
-- Entity Instantiation of the PRIORITY_DATA BRAM
---------------------------------------------------
priority_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENB,
WEA => WEB,
ADDRA => ADDRB,
DIA => DIB,
DOA => DOB
);
---------------------------------------------------
-- Entity Instantiation of the PARAM_DATA BRAM
---------------------------------------------------
param_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENU,
WEA => WEU,
ADDRA => ADDRU,
DIA => DIU,
DOA => DOU
);
-- Connect registers to external port signals...
SCH2TM_next_cpu_tid <= next_thread_id_reg;
SCH2TM_next_tid_valid <= Next_Thread_Valid_reg;
-- Connect port signals to registers...
current_thread_id_reg <= TM2SCH_current_cpu_tid;
-- AND the Preemption Interrupt Enable w/ the Interrupt line
-- Preemption is system wide and therefore not unique to each processor
Preemption_Interrupt <= Preemption_Interrupt_Line and Preemption_Interrupt_Enable;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- Connect registers to external port signals...
SCH2TM_busy <= sched_busy;
-- Toggle on/off timeout suppression with read/write requests
--IP2Bus_ToutSup <= (Bus2IP_RdCE_concat) or (Bus2IP_WrCE_concat);
-- ***************************************************
-- Bus Master FSM
-- ***************************************************
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= IP2Bus_MstWrReq;
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '0'; -- Perform a write (rd = '0', wr = '1')
mst_cmd_sm_wr_req <= '1';
mst_cmd_sm_ip2bus_addr <= IP2Bus_Addr; -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- *************************************************************************
-- Process: TM_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to TM
-- * Can be controlled using TM_data_ready and TM_data_out signals.
-- *************************************************************************
TM_OUTPUT_CONTROLLER : process( Bus2IP_Clk, tm_data_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( TM_data_ready = '1' ) then
SCH2TM_data <= TM_data_out; -- put data out to TM
end if;
end if;
end process TM_OUTPUT_CONTROLLER;
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- FIXME: This process should be incorporated into the FSM
-- *************************************************************************
-- Process: RESET_ADDR_INC
-- Purpose: Process to increment the "reset" address so that each element of
-- the BRAMs can be indexed and initialized
-- *************************************************************************
RESET_ADDR_INC : process( Bus2IP_Clk, Soft_Reset, inside_reset, ENA ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
reset_addr <= (others => '0');
elsif( ENA = '1' ) then
reset_addr <= reset_addr + 1;
end if;
end if;
end process RESET_ADDR_INC;
-- *************************************************************************
-- Process: TM_CMD_PROC
-- Purpose: Controller and decoder for incoming TM operations (requests)
-- *************************************************************************
TM_CMD_PROC : process (Bus2IP_Clk, TM2SCH_opcode, TM2SCH_data, TM2SCH_request ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Is_Queued_Request <= '0';
Is_Empty_Request <= '0';
Idle_Id_Request <= '0';
if (TM2SCH_request = '1') then
case (TM2SCH_opcode) is
when ENQUEUE_OPCODE => Enqueue_Request <= '1';
when DEQUEUE_OPCODE => Dequeue_Request <= '1';
when IS_QUEUED_OPCODE => Is_Queued_Request <= '1';
when IS_EMPTY_OPCODE => Is_Empty_Request <= '1';
when IDLE_ID_REQ_OPCODE => Idle_Id_Request <= '1';
when others => null;
end case;
end if;
end if;
end process TM_CMD_PROC;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
SYSCALL_Lock_Request <= '0';
MALLOC_Lock_Request <= '0';
Current_Request <= '0';
Next_Request <= '0';
Priority_Request <= '0';
Debug_0_Request <= '0';
Debug_1_Request <= '0';
Debug_2_Request <= '0';
Set_SchedParam_Request <= '0';
Get_SchedParam_Request <= '0';
Check_SchedParam_Request <= '0';
Preemption_Request <= '0';
Get_IdleThread_Request <= '0';
Set_IdleThread_Request <= '0';
Get_Entry_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_SET_SCHEDPARAM => Set_SchedParam_Request <= '1';
when C_SET_PREEMPTION => Preemption_Request <= '1';
when others => Error_Request <= '1';
end case;
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_GET_SCHEDPARAM => Get_SchedParam_Request <= '1';
when C_CHECK_SCHEDPARAM => Check_SchedParam_Request <= '1';
when C_GET_IDLE_THREAD => Get_IdleThread_Request <= '1';
when C_SET_IDLE_THREAD => Set_IdleThread_Request <= '1';
when C_GET_ENTRY => Get_Entry_Request <= '1';
when C_SYSCALL_LOCK => SYSCALL_Lock_Request <= '1';
when C_MALLOC_LOCK => MALLOC_Lock_Request <= '1';
when C_READ_CURRENT => Current_Request <= '1';
when C_READ_NEXT => Next_Request <= '1';
when C_READ_PRIORITY => Priority_Request <= '1';
when C_READ_DEBUG_0 => Debug_0_Request <= '1';
when C_READ_DEBUG_1 => Debug_1_Request <= '1';
when C_READ_DEBUG_2 => Debug_2_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC : process(
Bus2IP_Clk, Soft_Reset, inside_reset, next_state_master, encoder_enable_next, enqueue_pri_entry_next,
deq_pri_entry_next, old_tail_ptr_next, encoder_input_next, next_thread_id_next, lookup_entry_next,
sched_param_next, dequeue_entry_next, enqueue_entry_next, old_priority_next, new_priority_next, lookup_id_next,
idle_thread_id_next, idle_thread_valid_next, inside_reset_next, Preemption_Interrupt_Enable_next,
sched_busy_next, Next_Thread_Valid_next, lock_op_next, lock_count_next, syscall_mutex_next,
malloc_mutex_next, syscall_mutex_holder_next, malloc_mutex_holder_next, debug_reg_next_0,
temp_valid_next, current_CPU_next, current_priority_next, temp_id_next, temp_idle_id_next) is
variable temp_CPUID : std_logic_vector(0 to 2);
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state_master <= reset;
encoder_enable <= '0';
inside_reset <= '1';
sched_busy <= '0';
Next_Thread_Valid_reg <= '0';
temp_valid <= '0';
Preemption_Interrupt_Enable <= (others => '0');
idle_thread_valid <= (others => '0');
enqueue_pri_entry <= (others => '0');
deq_pri_entry <= (others => '0');
old_tail_ptr <= (others => '0');
encoder_input <= (others => '0');
next_thread_id_reg <= (others => '0');
lookup_entry <= (others => '0');
sched_param <= (others => '0');
dequeue_entry <= (others => '0');
enqueue_entry <= (others => '0');
old_priority <= (others => '0');
new_priority <= (others => '0');
lookup_id <= (others => '0');
idle_thread_id <= (others => '0');
lock_count <= (others => '0');
lock_op <= '0';
syscall_mutex <= '0';
malloc_mutex <= '0';
syscall_mutex_holder <= (others => '1');
malloc_mutex_holder <= x"FF";
debug_reg_0 <= (others => '0');
debug_reg_1 <= (others => '0');
debug_reg_2 <= (others => '0');
temp_CPUID := (others => '0');
current_priority_reg <= (others => '1');
temp_id <= (others => '0');
temp_idle_id <= (others => '0');
else
-- Assign all signals to their next state...
current_state_master <= next_state_master;
encoder_enable <= encoder_enable_next;
enqueue_pri_entry <= enqueue_pri_entry_next;
deq_pri_entry <= deq_pri_entry_next;
old_tail_ptr <= old_tail_ptr_next;
encoder_input <= encoder_input_next;
next_thread_id_reg <= next_thread_id_next;
lookup_entry <= lookup_entry_next;
sched_param <= sched_param_next;
dequeue_entry <= dequeue_entry_next;
enqueue_entry <= enqueue_entry_next;
old_priority <= old_priority_next;
new_priority <= new_priority_next;
lookup_id <= lookup_id_next;
idle_thread_id <= idle_thread_id_next;
lock_count <= lock_count_next;
lock_op <= lock_op_next;
syscall_mutex <= syscall_mutex_next;
malloc_mutex <= malloc_mutex_next;
syscall_mutex_holder <= syscall_mutex_holder_next;
malloc_mutex_holder <= malloc_mutex_holder_next;
debug_reg_0 <= debug_reg_next_0;
current_priority_reg <= current_priority_next;
temp_id <= temp_id_next;
temp_idle_id <= temp_idle_id_next;
debug_reg_1 <= current_thread_id_reg((8 * current_CPU) to (8 * current_CPU + 7)) &
next_thread_id_reg((8 * current_CPU) to (8 * current_CPU + 7)) &
idle_thread_id((8 * current_CPU) to (8 * current_CPU + 7)) & '0' &
current_priority_reg((7 * current_CPU) to (7 * current_CPU + 6));
case current_CPU is
when 0 => temp_CPUID := "000";
when 1 => temp_CPUID := "001";
when 2 => temp_CPUID := "010";
when 3 => temp_CPUID := "011";
when others => temp_CPUID := "111";
end case;
debug_reg_2 <= Z32(0 to 22) & Preemption_Interrupt_Line(current_CPU) & Preemption_Interrupt_Enable(current_CPU) &
temp_valid & '0' & Next_Thread_Valid_reg & idle_thread_valid(current_CPU) & temp_CPUID;
idle_thread_valid <= idle_thread_valid_next;
temp_valid <= temp_valid_next;
inside_reset <= inside_reset_next;
Preemption_Interrupt_Enable <= Preemption_Interrupt_Enable_next;
sched_busy <= sched_busy_next;
Next_Thread_Valid_reg <= Next_Thread_Valid_next;
current_CPU <= current_CPU_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC : process (
reset_addr, next_thread_id_reg, lookup_entry, sched_param, dequeue_entry, enqueue_entry, old_priority,
new_priority, lookup_id, idle_thread_id, idle_thread_valid, temp_valid, current_state_master, inside_reset,
Preemption_Interrupt_Enable, Enqueue_Request, Dequeue_Request, Is_Queued_Request, Is_Empty_Request, Idle_Id_Request,
SYSCALL_Lock_Request, MALLOC_Lock_Request, Current_Request, Next_Request, Priority_Request,
Debug_0_Request, Debug_1_Request, Debug_2_Request, Error_Request, Set_SchedParam_Request, Get_SchedParam_Request,
Check_SchedParam_Request, Preemption_Request, Bus2IP_Data, Get_IdleThread_Request, Set_IdleThread_Request,
Get_Entry_Request, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, DOA, lock_op, syscall_mutex, malloc_mutex,
lock_count, syscall_mutex_holder, malloc_mutex_holder, debug_reg_0, current_thread_id_reg, TM2SCH_current_cpu_tid, Bus2IP_Addr,
sched_busy, Next_Thread_Valid_reg, SWTM_DOB, encoder_input, encoder_output, encoder_enable, enqueue_pri_entry, deq_pri_entry,
old_tail_ptr, DOB, DOU, TM2SCH_data,current_priority_reg, current_CPU, temp_id, temp_idle_id, mst_cmd_sm_busy, debug_reg_1, debug_reg_2) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 20);
-- Checks the validity of the SET_SCHED_PARAM request
variable check_valid : std_logic_vector(0 to 7);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
encoder_reset <= '0';
encoder_enable_next <= '0';
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
TM_data_out <= (others => '0');
TM_data_ready <= '0';
ADDRA <= (others => '0');
DIA <= (others => '0');
ENA <= '0';
WEA <= '0';
ADDRB <= (others => '0');
DIB <= (others => '0');
ENB <= '0';
WEB <= '0';
ADDRU <= (others => '0');
DIU <= (others => '0');
ENU <= '0';
WEU <= '0';
SWTM_ADDRB <= (others => '0');
SWTM_DIB <= (others => '0');
SWTM_ENB <= '0';
SWTM_WEB <= '0';
enqueue_pri_entry_next <= enqueue_pri_entry;
deq_pri_entry_next <= deq_pri_entry;
old_tail_ptr_next <= old_tail_ptr;
encoder_input_next <= encoder_input;
next_state_master <= current_state_master;
next_thread_id_next <= next_thread_id_reg;
lookup_entry_next <= lookup_entry;
sched_param_next <= sched_param;
dequeue_entry_next <= dequeue_entry;
enqueue_entry_next <= enqueue_entry;
old_priority_next <= old_priority;
new_priority_next <= new_priority;
lookup_id_next <= lookup_id;
idle_thread_id_next <= idle_thread_id;
lock_count_next <= lock_count;
lock_op_next <= lock_op;
syscall_mutex_next <= syscall_mutex;
malloc_mutex_next <= malloc_mutex;
syscall_mutex_holder_next <= syscall_mutex_holder;
malloc_mutex_holder_next <= malloc_mutex_holder;
debug_reg_next_0 <= debug_reg_0;
idle_thread_valid_next <= idle_thread_valid;
temp_valid_next <= temp_valid;
inside_reset_next <= inside_reset;
sched_busy_next <= sched_busy;
Next_Thread_Valid_next <= Next_Thread_Valid_reg;
current_CPU_next <= current_CPU;
current_priority_next <= current_priority_reg;
temp_id_next <= temp_id;
temp_idle_id_next <= temp_idle_id;
Preemption_Interrupt_Line <= (others => '0');
Preemption_Interrupt_Enable_next <= Preemption_Interrupt_Enable;
case current_state_master is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Set_SchedParam_Request & Get_SchedParam_Request & Check_SchedParam_Request &
Preemption_Request & Get_IdleThread_Request & Set_IdleThread_Request & Is_Queued_Request & Is_Empty_Request &
Get_Entry_Request & SYSCALL_Lock_Request & MALLOC_Lock_Request & Idle_Id_Request & Current_Request &
Next_Request & Priority_Request & Debug_0_Request & Debug_1_Request & Debug_2_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "100000000000000000000" => next_state_master <= ENQ_begin; -- Enqueue
when "010000000000000000000" => next_state_master <= DEQ_begin; -- Dequeue
when "001000000000000000000" => next_state_master <= SET_SCHED_PARAM_begin; -- Set_SchedParam
when "000100000000000000000" => next_state_master <= GET_SCHED_PARAM_begin; -- Get_SchedParam
when "000010000000000000000" => next_state_master <= CHECK_SCHED_PARAM_begin; -- Check_SchedParam
when "000001000000000000000" => next_state_master <= SET_PREEMPTION_begin; -- SET_Preemption
when "000000100000000000000" => next_state_master <= GET_IDLE_THREAD_begin; -- Get_IdleThread
when "000000010000000000000" => next_state_master <= SET_IDLE_THREAD_begin; -- Set_IdleThread
when "000000001000000000000" => next_state_master <= IS_QUEUED_begin; -- Is_Queued
when "000000000100000000000" => next_state_master <= IS_EMPTY_check; -- Is_Empty
when "000000000010000000000" => next_state_master <= GET_ENTRY_begin; -- Get_Entry
when "000000000001000000000" => next_state_master <= SYSCALL_LOCK; -- Lock syscalls
when "000000000000100000000" => next_state_master <= MALLOC_LOCK; -- Lock context switches
when "000000000000010000000" => next_state_master <= IDLE_ID_DEQ; -- Run Idle Thread
when "000000000000001000000" => next_state_master <= READ_CURRENT; -- Read Current Thread ID's
when "000000000000000100000" => next_state_master <= READ_NEXT; -- Read Next Thread ID
when "000000000000000010000" => next_state_master <= READ_PRIORITY; -- Read Priority Register
when "000000000000000001000" => next_state_master <= READ_DEBUG_0; -- Read Debug Reg 0
when "000000000000000000100" => next_state_master <= READ_DEBUG_1; -- Read Debug Reg 1
when "000000000000000000010" => next_state_master <= READ_DEBUG_2; -- Read Debug Reg 2
when "000000000000000000001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when others => next_state_master <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state_master <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
WEA <= '0'; -- Turn off any BRAM access that was active
ENA <= '0';
WEB <= '0';
ENB <= '0';
WEU <= '0';
ENU <= '0';
SWTM_WEB <= '0';
SWTM_ENB <= '0';
encoder_reset <= '1'; -- Reset priority encoder
TM_data_out <= (others => '0'); -- Reset TM data out
TM_data_ready <= '1';
Reset_Done <= '0'; -- De-assert Reset_Done
next_state_master <= reset_BRAM;
when reset_BRAM =>
ADDRA <= reset_addr; -- setup BRAM write to init. THREAD_DATA entry
DIA <= set_priority("1000000", BRAM_init_string(0 to 22) & reset_addr);
ENA <= '1';
WEA <= '1';
ADDRB <= reset_addr; -- setup BRAM write to init. PRIORITY_DATA entry
DIB <= BRAM_init_string;
ENB <= '1';
WEB <= '1';
ADDRU <= reset_addr; -- setup BRAM write to init. PARAM_DATA entry
DIU <= BRAM_init_string;
ENU <= '1';
WEU <= '1';
if( reset_addr = "011111111" ) then
next_state_master <= reset_wait_4_ack;
end if;
when reset_wait_4_ack =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
ENB <= '0'; -- turn off BRAM access
WEB <= '0';
ENU <= '0'; -- turn off BRAM access
WEU <= '0';
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
debug_reg_next_0 <= x"AAAAAAAA";
-- Default values for system locks
lock_count_next <= (others => '0');
syscall_mutex_next <= '0';
malloc_mutex_next <= '0';
syscall_mutex_holder_next <= (others => '1');
malloc_mutex_holder_next <= x"FF";
next_state_master <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when ENQ_begin =>
debug_reg_next_0 <= TM2SCH_data & Z32(8 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
lookup_id_next <= TM2SCH_data; -- store threadID to ENQ
ADDRA <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from THREAD_DATA
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from PARAM_DATA
ENU <= '1';
WEU <= '0';
next_state_master <= ENQ_lookup_enqueue_entry_idle;
when ENQ_lookup_enqueue_entry_idle =>
-- idle stage
next_state_master <= ENQ_check_idle;
when ENQ_check_idle =>
-- Default assumes not an idle thread
next_state_master <= ENQ_lookup_enqueue_entry_finished;
for i in 0 to (C_NUM_CPUS - 1) loop
if(lookup_id = idle_thread_id((i * 8) to ((i * 8) + 7))) then
-- TM is trying to add an idle thread to the R2RQ, abort ENQUEUE operation
TM_data_out <= x"80";
TM_data_ready <= '1';
sched_busy_next <= '0';
next_state_master <= idle;
end if;
end loop;
when ENQ_lookup_enqueue_entry_finished =>
-- DOA has THREAD_DATA entry for tid to ENQ
-- DOU has PARAM_DATA entry for tid to ENQ
-- Check scheduling paramter:
-- If HW range: start HW thread
-- If SW range: add thread to ready-to-run queue
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" =>
-- SW-valid range, proceed with ENQ operation...
debug_reg_next_0 <= debug_reg_0(0 to 27) & "1000";
Next_Thread_Valid_next <= '0'; -- Invalidate next_thread register
enqueue_entry_next <= set_queue_bit('1', DOA); -- Set as queued and store entry
new_priority_next <= get_priority(DOA); -- Assigned priority to this signal b/c used to address encoder_input
ADDRB <= "00" & get_priority(DOA); -- setup BRAM read to get PRIORITY_DATA entry for the enq'd thread
ENB <= '1';
WEB <= '0';
next_state_master <= ENQ_lookup_enqueue_pri_entry_idle;
when others =>
-- HW-valid range, proceed with start HW thread operation...
debug_reg_next_0 <= debug_reg_0(0 to 27) & "1110";
sched_param_next <= DOU; -- store scheduling param. (base addr. of HW thread)
TM_data_out <= Z32(0 to 7); -- return status to the TM, so the TM will continue processing
TM_data_ready <= '1'; -- and unlock the bus
sched_busy_next <= '0';
bus_data_out <= Z32(0 to 27) & HW_THREAD_START; -- put data on bus w/o ACK (for the upcoming write operation)
bus_data_ready <= '1';
bus_ack_ready <= '0';
next_state_master <= ENQ_start_hw_thread_begin;
end case;
-- ***************************************************************************************************
when ENQ_start_hw_thread_begin =>
-- Start a bus write transaction to start HW thread
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
when ENQ_start_hw_thread_finished =>
if (mst_cmd_sm_busy = '0') then
-- Master FSM has finished our request, de-assert request lines, and continue on
-- HW thread has been started
-- TM has already been ACK'ed
-- now just return to idle
IP2Bus_Addr <= (others => '0'); -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0'); -- put data to write on bus w/o ACK
next_state_master <= idle;
else
-- Master FSM has not yet detected the request, persist
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
end if;
-- ***************************************************************************************************
when ENQ_lookup_enqueue_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_enqueue_pri_entry_finished;
when ENQ_lookup_enqueue_pri_entry_finished =>
enqueue_pri_entry_next <= DOB; -- store pri_entry
if(is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- Queue is empty for this priority level
-- set encoder_input bit for given priority
encoder_input_next <= set_encoder_bit('1', conv_integer(get_priority(enqueue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= ENQ_init_head_pointer;
else
-- Queue is not empty for this priority level
old_tail_ptr_next <= get_tail_pointer(DOB); -- store old tail_ptr
next_state_master <= ENQ_lookup_old_tail_ptr;
end if;
when ENQ_init_head_pointer =>
-- Set head_ptr to the lookup_id
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_init_tail_pointer;
when ENQ_init_tail_pointer =>
-- Set tail_ptr to the lookup_id
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_wait_for_encoder_0;
when ENQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= ENQ_write_back_entries;
when ENQ_lookup_old_tail_ptr =>
ADDRA <= '0' & old_tail_ptr; -- setup read of old tail_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= ENQ_lookup_old_tail_ptr_idle;
when ENQ_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= ENQ_lookup_old_tail_ptr_finished;
when ENQ_lookup_old_tail_ptr_finished =>
-- setup write to make old_tail_ptr's next_ptr point to newly enq'd thread
ADDRA <= '0' & old_tail_ptr;
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update enqueue_entry's prev. ptr to point to old_tail_ptr
enqueue_entry_next <= set_prev_pointer(old_tail_ptr, enqueue_entry);
-- Update priority entry's tail_ptr to be newly enq'd thread
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_write_back_entries;
when ENQ_write_back_entries =>
ADDRA <= '0' & lookup_id; -- Write back enqueue_entry
ENA <= '1';
WEA <= '1';
DIA <= enqueue_entry;
ADDRB <= "00" & get_priority(enqueue_entry); -- Write back enqueue_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= ENQ_lookup_highest_pri_entry;
when ENQ_lookup_highest_pri_entry =>
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
--ADDRA <= '0' & TM2SCH_current_cpu_tid_reg; -- setup read of currently running thread
--ENA <= '1';
--WEA <= '0';
next_state_master <= ENQ_lookup_highest_pri_entry_idle;
when ENQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_highest_pri_entry_finished;
when ENQ_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
--current_entry_pri_value_next <= get_priority(DOA); -- store current_entry's priority
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
current_CPU_next <= check_preempt(encoder_output, current_priority_reg);
next_state_master <= ENQ_preemption_check_idle;
when ENQ_preemption_check_idle =>
-- idle state
next_state_master <= ENQ_preemption_check;
when ENQ_preemption_check =>
if(current_CPU < C_NUM_CPUS) then
-- If we make it here then we have found a processor that should be preempted in favor of the
-- newly enqueued thread. This means that a thread with a 'better' priority exists in the R2RQ
-- than what is currently executing on current_CPU. When this occurs, preempt the corresponding CPU.
debug_reg_next_0 <= debug_reg_0(0 to 7) & get_head_pointer(DOB) & encoder_output & '1' & debug_reg_0(24 to 31);
-- Preempt the corresponding processor
Preemption_Interrupt_Line(current_CPU) <= '1';
else
debug_reg_next_0 <= debug_reg_0(0 to 7) & get_head_pointer(DOB) & encoder_output & '0' & debug_reg_0(24 to 31);
end if;
TM_data_out <= get_queue_bit(enqueue_entry) & Z32(1 to 7); -- return 0x80 to TM
TM_data_ready <= '1';
Next_Thread_Valid_next <= '1'; -- Revalidate
sched_busy_next <= '0';
next_state_master <= idle;
----------------------------
-- ENQ: end
----------------------------
----------------------------
-- DEQ: begin
----------------------------
when DEQ_begin =>
debug_reg_next_0 <= debug_reg_0(0 to 16) & TM2SCH_data & Z32(25 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
Next_Thread_Valid_next <= '0';
-- Get CPU to Dequeue from the ThreadManager
current_CPU_next <= conv_integer(TM2SCH_data);
next_state_master <= DEQ_get_CPU_idle;
when DEQ_get_CPU_idle =>
-- idle state
next_state_master <= DEQ_lookup_dequeue_entry;
when DEQ_lookup_dequeue_entry =>
-- Dequeue thread from processor current_CPU
ADDRA <= '0' & TM2SCH_current_cpu_tid((8 * current_CPU) to (8 * current_CPU + 7)); -- setup BRAM read of thread to dequeue
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_dequeue_entry_idle;
when DEQ_lookup_dequeue_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_dequeue_entry_finished;
when DEQ_lookup_dequeue_entry_finished =>
dequeue_entry_next <= set_queue_bit('0', DOA); -- store entry in variable and clear queue-bit
ADDRB <= "00" & get_priority(DOA); -- setup read of deq_pri_entry
ENB <= '1';
WEB <= '0';
-- Update priorities!!!
current_priority_next((7 * current_CPU) to (7 * current_CPU + 6)) <= get_priority(DOA);
next_state_master <= DEQ_lookup_deq_pri_entry_idle;
when DEQ_lookup_deq_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_deq_pri_entry_finished;
when DEQ_lookup_deq_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store deq entry from PRIORITY_DATA
if(get_head_pointer(DOB) = get_tail_pointer(DOB)) then
-- If list priority Q has 1 element (head = tail) then list will now be empty
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(get_priority(dequeue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= DEQ_wait_for_encoder_0;
else
-- Otherwise...
ADDRA <= '0' & get_head_pointer(DOB); -- setup read of head_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_old_head_ptr_idle;
end if;
when DEQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_1;
when DEQ_wait_for_encoder_1 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_2;
when DEQ_wait_for_encoder_2 =>
-- idle stage
next_state_master <= DEQ_write_back_entries;
when DEQ_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= DEQ_lookup_old_head_ptr_finished;
when DEQ_lookup_old_head_ptr_finished =>
-- DOA has old_head_ptr entry
-- update head_ptr to be next_ptr of old head_ptr
deq_pri_entry_next <= set_head_pointer(get_next_pointer(DOA), deq_pri_entry);
next_state_master <= DEQ_write_back_entries;
when DEQ_write_back_entries =>
ADDRA <= '0' & TM2SCH_current_cpu_tid((8 * current_CPU) to (8 * current_CPU) + 7);
ENA <= '1';
WEA <= '1';
DIA <= dequeue_entry;
ADDRB <= "00" & get_priority(dequeue_entry); -- setup write to update deq_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= DEQ_check_encoder_output;
when DEQ_check_encoder_output =>
if(encoder_input = 0 ) then
debug_reg_next_0 <= debug_reg_0(0 to 29) & "01";
-- No queued threads in the system: finish with invalid next thread
Next_Thread_Valid_next <= '0';
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
else
-- Queued threads exist...
ADDRB <= "00" & encoder_output; -- setup read of highest priority (PRIORITY_DATA) entry
ENB <= '1';
WEB <= '0';
next_state_master <= DEQ_lookup_highest_pri_entry_idle;
end if;
when DEQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_highest_pri_entry_finished;
when DEQ_lookup_highest_pri_entry_finished =>
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
debug_reg_next_0 <= debug_reg_0(0 to 29) & "11";
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
Next_Thread_Valid_next <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
----------------------------
-- DEQ: end
----------------------------
----------------------------
-- SET_sched_param: begin
----------------------------
when SET_SCHED_PARAM_begin =>
temp_valid_next <= Next_Thread_Valid_reg;
Next_Thread_Valid_next <= '0'; -- Invalidate ALL current threads
-- Get CPU info from the bus
current_CPU_next <= conv_integer(Bus2IP_Addr(14 to 15));
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store tid
sched_param_next <= Bus2IP_Data(0 to 31); -- store sched_param
new_priority_next <= Bus2IP_Data(25 to 31); -- store priority (low 7 bits of sched_param)
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM write to update sched param value in PARAM_DATA
DIU <= Bus2IP_Data(0 to 31);
ENU <= '1';
WEU <= '1';
-- Check to see if sched param is in SW-valid range
case ( Bus2IP_Data(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, proceed with a set_priority operation
debug_reg_next_0 <= "10" & Z32(2 to 31);
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_begin;
when others => -- HW-valid range, simply end, no error checks
debug_reg_next_0 <= "01" & Z32(2 to 31);
next_state_master <= SET_SCHED_PARAM_revalidate;
end case;
when SET_SCHED_PARAM_revalidate =>
Next_Thread_Valid_next <= temp_valid; -- Revalidate ALL current threads
next_state_master <= SET_SCHED_PARAM_return_with_no_error;
when SET_SCHED_PARAM_lookup_setpri_entries_begin =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of thread_id
ENA <= '1';
WEA <= '0';
ADDRB <= "00" & new_priority; -- setup BRAM read of new_priority_entry
ENB <= '1';
WEB <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- setup SWTM_BRAM read of thread_id
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_idle;
when SET_SCHED_PARAM_lookup_setpri_entries_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_finished;
when SET_SCHED_PARAM_lookup_setpri_entries_finished =>
old_priority_next <= get_priority(DOA); -- store old_priority value
lookup_entry_next <= DOA; -- store setpri_entry
enqueue_pri_entry_next <= DOB; -- store new_priority_entry
-- Check Validity of Set_Priority operation
check_valid := TM2SCH_current_cpu_tid((8 * current_CPU) to ((8 * current_CPU) + 7));
-- Commented line out below - Maximum frequency changed from 130 MHz to 119 MHz
--if((SWTM_DOB(26) = '1') and ((lookup_id or SWTM_DOB(16 to 23)) = check_valid)) then
if((SWTM_DOB(26) = '1') and ((lookup_id = check_valid) or (SWTM_DOB(16 to 23) = check_valid))) then
if(get_queue_bit(DOA) = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 1) & "10" & check_valid & Z32(12 to 31);
-- If QUEUED...
ADDRB <= "00" & get_priority(DOA); -- setup read of old_pri_entry
ENB <= '1';
WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_idle;
else
debug_reg_next_0 <= debug_reg_0(0 to 1) & "01" & check_valid & Z32(12 to 31);
-- IF ~QUEUED...
ADDRA <= '0' & lookup_id; -- setup BRAM write to update priority value in THREAD_DATA
DIA <= set_priority(new_priority, DOA);
ENA <= '1';
WEA <= '1';
-- Skip the preemption check
current_CPU_next <= C_NUM_CPUS;
-- Finish by merging back into path of queued thread
--next_state_master <= SET_SCHED_PARAM_revalidate;
next_state_master <= SET_SCHED_PARAM_check_if_current;
end if;
else
-- Otherwise, return with an error b/c operation cannot be completed...
next_state_master <= SET_SCHED_PARAM_return_with_error;
end if;
when SET_SCHED_PARAM_check_if_current =>
current_CPU_next <= check_if_current(lookup_id, current_thread_id_reg);
next_state_master <= SET_SCHED_PARAM_update_current_priorities;
when SET_SCHED_PARAM_update_current_priorities =>
-- Update current priority field if this thread is currently running
if (current_CPU < C_NUM_CPUS) then
current_priority_next((7 * current_CPU) to (7 * current_CPU + 6)) <= new_priority;
end if;
next_state_master <= SET_SCHED_PARAM_check_encoder;
when SET_SCHED_PARAM_lookup_old_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_finished;
when SET_SCHED_PARAM_lookup_old_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store old_priority_entry
next_state_master <= SET_SCHED_PARAM_priority_field_check;
when SET_SCHED_PARAM_priority_field_check =>
-- update priority value to new_priority
lookup_entry_next <= set_priority(new_priority, lookup_entry);
-- If (head_ptr = tail_ptr) then Q will now be empty
if(get_tail_pointer(deq_pri_entry) = get_head_pointer(deq_pri_entry)) then
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(old_priority), encoder_input);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
else -- If the Q will not be empty
-- If the head is being deq'd
if(lookup_id = get_head_pointer(deq_pri_entry)) then
-- Setup BRAM read of old head_ptr's entry
ADDRA <= '0' & get_head_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_idle;
-- If the tail is being deq'd
elsif ( lookup_id = get_tail_pointer(deq_pri_entry) ) then
-- Setup BRAM read of old tail_ptr's entry
ADDRA <= '0' & get_tail_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_idle;
-- If an item in the "middle" of the list is being deq'd
else
-- Setup BRAM read of prev_ptr's entry
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_idle;
end if;
end if;
when SET_SCHED_PARAM_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_finished;
when SET_SCHED_PARAM_lookup_old_head_ptr_finished =>
-- DOA has old head_ptr entry on it
deq_pri_entry_next <= set_head_pointer(get_next_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_finished;
when SET_SCHED_PARAM_lookup_old_tail_ptr_finished =>
-- DOA has old tail_ptr entry on it
deq_pri_entry_next <= set_tail_pointer(get_prev_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_prev_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_finished;
when SET_SCHED_PARAM_lookup_prev_ptr_finished =>
-- DOA has prev_ptr entry on it
-- set next_ptr of prev_ptr to that of next_ptr of setpri_entry (AKA lookup_entry)
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(get_next_pointer(lookup_entry), DOA);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_write_back_deq_pri_entry =>
-- Write back old_priority entry (AKA deq_pri_entry)
ADDRB <= "00" & old_priority;
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_begin_add_to_new_pri_queue =>
-- If the new priority Q is empty...
if(is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- update head_ptr to that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
-- set encoder input bit for new_priority to '1'
encoder_input_next <= set_encoder_bit('1', conv_integer(new_priority), encoder_input);
-- now update the tail_ptr to that of lookup_id (AKA setpri_ID)
next_state_master <= SET_SCHED_PARAM_init_tail_ptr;
else -- new priority Q is not empty
-- Setup read of old tail_ptr in new Q
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle;
end if;
when SET_SCHED_PARAM_init_tail_ptr =>
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1a
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle =>
-- idle stage
-- Change the prev_ptr of lookup_id (AKA setpri_ID) to that of old_tail_ptr
lookup_entry_next <= set_prev_pointer(get_tail_pointer(enqueue_pri_entry), lookup_entry);
next_state_master <= SET_SCHED_PARAM_update_enqueue_info;
when SET_SCHED_PARAM_update_enqueue_info =>
-- DOA has old tail_ptr info for new Q
-- Change & Write-back the old tail_ptr's next_ptr to that of lookup_id (AKA setpri_ID)
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update the tail_ptr of new priority Q to be that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1b
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_write_back_entries =>
-- Write back lookup_entry (AKA setpri_entry)
ADDRA <= '0' & lookup_id;
ENA <= '1';
WEA <= '1';
DIA <= lookup_entry;
-- Write back enqueue_pri_entry (AKA new_priority_entry)
ADDRB <= "00" & new_priority;
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_0;
when SET_SCHED_PARAM_wait_for_encoder_0 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_1;
when SET_SCHED_PARAM_wait_for_encoder_1 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_0;
when SET_SCHED_PARAM_last_wait_0 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_1;
when SET_SCHED_PARAM_last_wait_1 =>
next_state_master <= SET_SCHED_PARAM_check_encoder;
when SET_SCHED_PARAM_check_encoder =>
debug_reg_next_0 <= debug_reg_0(0 to 11) & new_priority & encoder_output & Z32(26 to 31);
-- Continue to find highest priority thread in the system...
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_idle;
when SET_SCHED_PARAM_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_finished;
when SET_SCHED_PARAM_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
current_CPU_next <= check_preempt(encoder_output, current_priority_reg);
-- We now know that we have a valid thread in the next_thread register
Next_Thread_Valid_next <= temp_valid; -- '1';
next_state_master <= SET_SCHED_PARAM_preemption_check_idle;
when SET_SCHED_PARAM_preemption_check_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_preemption_check;
when SET_SCHED_PARAM_preemption_check =>
if(current_CPU < C_NUM_CPUS) and (temp_valid = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 25) & '1' & Z32(27 to 31);
-- Preempt the corresponding processor
Preemption_Interrupt_Line(current_CPU) <= '1';
end if;
next_state_master <= SET_SCHED_PARAM_return_with_no_error; -- return to idle stage
when SET_SCHED_PARAM_return_with_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next_0 <= debug_reg_0(0 to 30) & '1';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with error status (not possible with write op's, so just return all 0's)
bus_data_ready <= '1';
bus_ack_ready <= '1';
Next_Thread_Valid_next <= temp_valid; -- Revalidate ALL current threads
next_state_master <= wait_trans_done;
when SET_SCHED_PARAM_return_with_no_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next_0 <= debug_reg_0(0 to 30) & '0';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with successful status
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SET_sched_param: end
----------------------------
----------------------------
-- GET_sched_param: begin
----------------------------
when GET_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= GET_SCHED_PARAM_lookup_entry;
when GET_SCHED_PARAM_lookup_entry =>
ADDRU <= '0' & lookup_id; -- setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
next_state_master <= GET_SCHED_PARAM_lookup_entry_idle;
when GET_SCHED_PARAM_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_SCHED_PARAM_lookup_entry_finished;
when GET_SCHED_PARAM_lookup_entry_finished =>
-- DOU has sched_param on it
bus_data_out <= DOU(0 to 31); -- return sched_param on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_sched_param: end
----------------------------
----------------------------
-- CHECK_sched_param: begin
----------------------------
when CHECK_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= CHECK_SCHED_PARAM_lookup_entries;
when CHECK_SCHED_PARAM_lookup_entries =>
ADDRA <= '0' & lookup_id; -- Setup read from THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & lookup_id; -- Setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- Setup read from SWTM_DATA[tid]
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_idle;
when CHECK_SCHED_PARAM_lookup_entries_idle =>
-- idle stage
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_finished;
when CHECK_SCHED_PARAM_lookup_entries_finished =>
-- DOA, DOU, and SWTM DOB have entries on them
-- Error check for properness of sched_param:
-- * If queued : sched_param must in the SW-valid range (less than 128)
-- * If not-queued : sched param can be in any range
if(get_queue_bit(DOA) = '1') then
-- thread is QUEUED
-- then check to see if Most Significant 25 bits of sched_param are 0's => in SW-valid range
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, return all 0's
bus_data_out <= Z32(0 to 31);
when others => -- Not in SW-valid range, return LSB=1, error bit
bus_data_out <= Z32(0 to 30) & '1';
end case;
else
-- thread is ~QUEUED, return all 0's
bus_data_out <= Z32(0 to 31);
end if;
bus_data_ready <= '1'; -- ACK Bus, with data put on it
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- CHECK_sched_param: end
----------------------------
----------------------------
-- SET_PREEMPTION: begin
----------------------------
-- Communication - BusCOM
-- Enables or Disable system wide preemption
-- returns 0
when SET_PREEMPTION_begin =>
-- Get CPU info from the processor off the bus (bits 14 and 15)
current_CPU_next <= conv_integer(Bus2IP_Addr(14 to 15));
next_state_master <= SET_PREEMPTION_idle;
when SET_PREEMPTION_idle =>
-- idle state
next_state_master <= SET_PREEMPTION_finished;
when SET_PREEMPTION_finished =>
-- Enable or Disable preemption based on value sent in Bus2IP_Data
if(Bus2IP_Data(0) = '0') then
Preemption_Interrupt_Enable_next <= (others => '0');
else
Preemption_Interrupt_Enable_next <= (others => '1');
end if;
-- This code allows the user to manually generate an interrupt to the specified processor (debug only)
if(Bus2IP_Addr(13) = '1') then
Preemption_Interrupt_Line(current_CPU) <= '1';
end if;
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SET_PREEMPTION: end
----------------------------
----------------------------
-- GET_IDLE_THREAD: begin
----------------------------
when GET_IDLE_THREAD_begin =>
-- Get CPU info from the processor off the bus (bits 14 and 15)
current_CPU_next <= conv_integer(Bus2IP_Addr(14 to 15));
next_state_master <= GET_IDLE_THREAD_idle;
when GET_IDLE_THREAD_idle =>
-- idle state
next_state_master <= GET_IDLE_THREAD_finished;
when GET_IDLE_THREAD_finished =>
bus_data_out <= Z32(0 to 22) & idle_thread_id((8 * current_CPU) to ((8 * current_CPU) + 7)) & idle_thread_valid(current_CPU);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_IDLE_THREAD: end
----------------------------
----------------------------
-- SET_IDLE_THREAD: begin
----------------------------
when SET_IDLE_THREAD_begin =>
-- Get CPU info from the processor off the bus (bits 14 and 15)
current_CPU_next <= conv_integer(Bus2IP_Addr(14 to 15));
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store thread_id
ADDRA <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & Bus2IP_Addr(16 to 23); -- setup SWTM_BRAM read of thread_id to set_pri
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_IDLE_THREAD_lookup_entries_idle;
when SET_IDLE_THREAD_lookup_entries_idle =>
-- idle stage
next_state_master <= SET_IDLE_THREAD_lookup_entries_finished;
when SET_IDLE_THREAD_lookup_entries_finished =>
-- Check to see if this thread can become the idle thread
-- * TID must be ~queued
-- * TID must be created and used.
-- * TID must not have a HW sched param.
if(get_queue_bit(DOA) = '0' and
SWTM_DOB(26) = '1' and
DOU(0 to 24) = "0000000000000000000000000") then
idle_thread_id_next((8 * current_CPU) to (8 * current_CPU + 7)) <= lookup_id;
idle_thread_valid_next(current_CPU) <= '1';
debug_reg_next_0 <= Z32(0 to 21) & '0' & '1' & idle_thread_id_next((8 * current_CPU) to (8 * current_CPU + 7));
next_state_master <= SET_IDLE_THREAD_return_with_no_error;
else
debug_reg_next_0 <= Z32(0 to 21) & '0' & '0' & idle_thread_id_next((8 * current_CPU) to (8 * current_CPU + 7));
-- This thread cannot become the idle thread
next_state_master <= SET_IDLE_THREAD_return_with_error;
end if;
when SET_IDLE_THREAD_return_with_error =>
bus_data_out <= Z32(0 to 30) & '1'; -- return LSB=1, error bit, on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when SET_IDLE_THREAD_return_with_no_error =>
bus_data_out <= Z32(0 to 31); -- return all 0's on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SET_IDLE_THREAD: end
----------------------------
----------------------------
-- IS_QUEUED: begin
----------------------------
when IS_QUEUED_begin =>
debug_reg_next_0 <= "00" & IS_QUEUED_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that operation is busy
lookup_id_next <= TM2SCH_data; -- latch thread_id to lookup
next_state_master <= IS_QUEUED_lookup_entry;
when IS_QUEUED_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= IS_QUEUED_lookup_entry_idle;
when IS_QUEUED_lookup_entry_idle =>
-- idle stage
next_state_master <= IS_QUEUED_lookup_entry_finished;
when IS_QUEUED_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
TM_data_out <= Z32(0 to 6) & get_queue_bit(DOA); -- return data to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
----------------------------
-- IS_QUEUED: end
----------------------------
----------------------------
-- IS_EMPTY: begin
----------------------------
when IS_EMPTY_check =>
debug_reg_next_0 <= "00" & IS_EMPTY_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
next_state_master <= IS_EMPTY_finished;
when IS_EMPTY_finished =>
-- Check to see if all queues are empty
if (encoder_input = 0) then
TM_data_out <= Z32(0 to 6) & '1'; -- set data_out to true, (LSB = 1)
else
TM_data_out <= Z32(0 to 6) & '0'; -- set data_out to false, (LSB = 0)
end if;
sched_busy_next <= '0'; -- de-assert busy signal
TM_data_ready <= '1'; -- return results to TM
next_state_master <= idle;
----------------------------
-- IS_EMPTY: end
----------------------------
----------------------------
-- GET_ENTRY: begin
----------------------------
when GET_ENTRY_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23); -- latch thread_id to lookup
next_state_master <= GET_ENTRY_lookup_entry;
when GET_ENTRY_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= GET_ENTRY_lookup_entry_idle;
when GET_ENTRY_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_ENTRY_lookup_entry_finished;
when GET_ENTRY_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
bus_data_out <= DOA; -- return entry on bus
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_ENTRY: end
----------------------------
----------------------------
-- SYSCALL_LOCK: begin
----------------------------
-- Communication - BusCom
-- Submit a request to acquire or release the system call lock
-- returns zero if the request was denied, one if the request was granted
when SYSCALL_LOCK =>
-- Bus2IP_Addr(13) = 0 : RELEASE lock
-- Bus2IP_Addr(13) = 1 : ACQUIRE lock
lock_op_next <= Bus2IP_Addr(13);
-- Get CPU info from the processor off the bus (bits 14 and 15)
current_CPU_next <= conv_integer(Bus2IP_Addr(14 to 15));
next_state_master <= SYSCALL_LOCK_IDLE;
when SYSCALL_LOCK_idle =>
-- idle state
next_state_master <= SYSCALL_LOCK_idle_finished;
when SYSCALL_LOCK_idle_finished =>
-- default next state
next_state_master <= SYSCALL_LOCK_ACQUIRE;
if(lock_op = '0') then
-- Override default next state
next_state_master <= SYSCALL_LOCK_RELEASE;
end if;
when SYSCALL_LOCK_ACQUIRE =>
if(syscall_mutex = '0') then
-- Set the mutex
syscall_mutex_holder_next <= Bus2IP_Addr(14 to 15);
syscall_mutex_next <= '1';
bus_data_out <= Z32(0 to 30) & '1';
else
-- Otherwise return zero on the bus
bus_data_out <= Z32(0 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when SYSCALL_LOCK_RELEASE =>
if(syscall_mutex_holder = Bus2IP_Addr(14 to 15)) then
-- Release the lock
syscall_mutex_holder_next <= (others => '1');
syscall_mutex_next <= '0';
bus_data_out <= Z32(0 to 30) & '1';
else
bus_data_out <= Z32(0 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SYSCALL_LOCK: end
----------------------------
----------------------------
-- MALLOC_LOCK: begin
----------------------------
-- Communication - BusCom
-- Submit a request to acquire or release the malloc lock
-- returns zero if the request was denied, one if the request was granted
when MALLOC_LOCK =>
-- Bus2IP_Addr(13) = 0 : RELEASE lock
-- Bus2IP_Addr(13) = 1 : ACQUIRE lock
lock_op_next <= Bus2IP_Addr(13);
-- Store tid requesting the lock
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= MALLOC_LOCK_IDLE;
when MALLOC_LOCK_idle =>
-- idle state
next_state_master <= MALLOC_LOCK_idle_finished;
when MALLOC_LOCK_idle_finished =>
-- default next state
next_state_master <= MALLOC_LOCK_ACQUIRE;
if(lock_op = '0') then
-- Override default next state
next_state_master <= MALLOC_LOCK_RELEASE;
end if;
when MALLOC_LOCK_ACQUIRE =>
if(malloc_mutex = '0') then
malloc_mutex_holder_next <= lookup_id;
lock_count_next <= lock_count + 1;
malloc_mutex_next <= '1';
elsif(malloc_mutex = '1' AND malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count + 1;
end if;
next_state_master <= MALLOC_LOCK_ACQUIRE_RETURN;
when MALLOC_LOCK_ACQUIRE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when MALLOC_LOCK_RELEASE =>
if(malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count - 1;
end if;
next_state_master <= MALLOC_LOCK_RELEASE_next;
when MALLOC_LOCK_RELEASE_next =>
if(lock_count = x"0") then
-- Release the lock
malloc_mutex_next <= '0';
malloc_mutex_holder_next <= x"FF";
end if;
next_state_master <= MALLOC_LOCK_RELEASE_RETURN;
when MALLOC_LOCK_RELEASE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- MALLOC_LOCK: end
----------------------------
----------------------------
-- IDLE_ID_DEQ: begin
----------------------------
-- Communication - TMCom
-- This call is similar to get_idle_thread however it is used by the thread manager only
-- The purpose of this call is to do a pseudo-dequeue of the idle thread, pseudo because idle thread's
-- are not allowed on the R2RQ
-- returns the idle thread id for the requesting processor
when IDLE_ID_DEQ =>
-- assert that scheduler is busy
sched_busy_next <= '1';
-- Get CPU to Dequeue from the ThreadManager
current_CPU_next <= conv_integer(TM2SCH_data);
next_state_master <= IDLE_ID_DEQ_CPU_idle;
when IDLE_ID_DEQ_CPU_idle =>
-- idle state
next_state_master <= IDLE_ID_DEQ_return;
when IDLE_ID_DEQ_return =>
-- This must always be true!!
--if(idle_thread_valid(current_CPU) = '1') then
TM_data_out <= idle_thread_id((8*current_CPU) to (8*current_CPU + 7));
-- Set the priority to the default idle thread priority
current_priority_next((7 * current_CPU) to (7 * current_CPU + 6)) <= x"7F";
--else
-- Return an error to the thread manager
--TM_data_out <= x"FF";
--end if;
TM_data_ready <= '1';
sched_busy_next <= '0';
next_state_master <= idle;
----------------------------
-- IDLE_ID_DEQ: end
----------------------------
----------------------------
----------------------------
-- DEBUG STATES
----------------------------
----------------------------
----------------------------
-- READ_CURRENT: begin
----------------------------
when READ_CURRENT =>
bus_data_out <= current_thread_id_reg(0 to 15) & Z32(16 to 31);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_CURRENT: end
----------------------------
----------------------------
-- READ_NEXT: begin
----------------------------
when READ_NEXT =>
bus_data_out <= next_thread_id_reg(0 to 7) & Z32(8 to 31);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_NEXT: end
----------------------------
----------------------------
-- READ_PRIORITY: begin
----------------------------
when READ_PRIORITY =>
bus_data_out <= current_priority_reg(0 to 13) & Z32(14 to 31);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_PRIORITY: end
----------------------------
----------------------------
-- READ_DEBUG_0: begin
----------------------------
when READ_DEBUG_0 =>
bus_data_out <= debug_reg_0;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_DEBUG_0: end
----------------------------
----------------------------
-- READ_DEBUG_1: begin
----------------------------
when READ_DEBUG_1 =>
bus_data_out <= debug_reg_1;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_DEBUG_1: end
----------------------------
----------------------------
-- READ_DEBUG_2: begin
----------------------------
when READ_DEBUG_2 =>
bus_data_out <= debug_reg_2;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- READ_DEBUG_2: end
----------------------------
----------------------------
----------------------------
-- END OF DEBUG STATES
----------------------------
----------------------------
when others =>
ENA <= '0'; -- turn off any BRAM access
WEA <= '0';
ENB <= '0';
WEB <= '0';
ENU <= '0';
WEU <= '0';
next_state_master <= idle;
end case; -- END CASE (current_state_master)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | bd5e1eaa2b37fa10a7b0febdf3ce74cc | 0.505106 | 3.893931 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/interrupt_control.vhd | 2 | 37,168 | -------------------------------------------------------------------------------
-- $Id: interrupt_control.vhd,v 1.1 2003/02/18 19:16:01 ostlerf Exp $
-------------------------------------------------------------------------------
--interrupt_control.vhd version v1.00b
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need 'conv_std_logic_vector' conversion function
library proc_common_v1_00_b;
Use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.all;
use ipif_common_v1_00_c.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_INTERRUPT_REG_NUM : INTEGER := 16;
-- Number of IPIF Interrupt sources (not including IP or the
-- two latched IPIF ISR inputs)
C_NUM_IPIF_IRPT_SRC : INTEGER := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
C_INCLUDE_DEV_PENCODER : BOOLEAN := true;-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : Boolean := true; -- Specifies device ISC hierarchy
--Exclusion of Device ISC requires exclusion of Priority encoder
C_IRPT_DBUS_WIDTH : INTEGER := 32
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk_i : In std_logic; -- Master timing clock from the IPIF
Bus2IP_Data_sa : In std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Bus2IP_RdReq_sa : In std_logic;
Bus2IP_Reset_i : In std_logic; -- Master Reset from the IPIF reset block
Bus2IP_WrReq_sa : In std_logic;
Interrupt_RdCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
Interrupt_WrCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Interrupt inputs from the IPIF sources that will get registered in this design
IPIF_Lvl_Interrupts : In std_logic_vector(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Level Interrupt inputs from the IPIF sources
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Interrupt inputs from the IP
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Device interrupt output to the Master Interrupt Controller
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end interrupt_control ;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
--TYPES
-- no Types
-- CONSTANTS
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer range 0 to 15 := 0;
Constant DEVICE_IPR : integer range 0 to 15 := 1;
Constant DEVICE_IER : integer range 0 to 15 := 2;
Constant DEVICE_IAR : integer range 0 to 15 := 3;
Constant DEVICE_SIE : integer range 0 to 15 := 4;
Constant DEVICE_CIE : integer range 0 to 15 := 5;
Constant DEVICE_IIR : integer range 0 to 15 := 6;
Constant DEVICE_GIE : integer range 0 to 15 := 7;
Constant IP_ISR : integer range 0 to 15 := 8;
Constant IP_IPR : integer range 0 to 15 := 9;
Constant IP_IER : integer range 0 to 15 := 10;
Constant IP_IAR : integer range 0 to 15 := 11;
Constant IP_SIE : integer range 0 to 15 := 12;
Constant IP_CIE : integer range 0 to 15 := 13;
Constant IP_IIR : integer range 0 to 15 := 14;
Constant IP_GIE : integer range 0 to 15 := 15;
-- Generic to constant mapping
Constant IRPT_DBUS_WIDTH : Integer := C_IRPT_DBUS_WIDTH - 1;
Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
--INTERNAL SIGNALS
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector(IRPT_DBUS_WIDTH downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector(PRIORITY_ENC_WIDTH-1 downto 0);
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start architecture logic -------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_RdAck <= irpt_rdack;
Intr2Bus_WrAck <= irpt_wrack;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to IRPT_DBUS_WIDTH loop
Intr2Bus_DBus(IRPT_DBUS_WIDTH-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1') Then -- toggle selected ISR bits from the DBus inputs
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data_sa(IRPT_DBUS_WIDTH-irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1') Then -- load input data from the DBus inputs
ip_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IP_IRPT_HIGH_INDEX
to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1') Then -- load input data from the DBus inputs
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= (Bus2IP_Data_sa(IRPT_DBUS_WIDTH-i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1') Then -- load input data from the DBus inputs
ipif_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IPIF_IRPT_HIGH_INDEX to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1') Then -- load input data from the DBus inputs
ipif_glbl_irpt_enable_reg <= Bus2IP_Data_sa(0);
-- Enable bit is loaded from the DBus MSB
--Placed at bit-0 MSB by Glenn Baxter
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= conv_std_logic_vector(irpt_position, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= conv_std_logic_vector(NO_INTR_VALUE, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_ISR) or
Interrupt_WrCE(DEVICE_IER) or
Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1') Then
irpt_read_data(PRIORITY_ENC_WIDTH-1 downto 0) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_rdack <= ipif_pri_encode_present; -- set the acknowledge handshake depending on
-- priority encoder presence
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| bsd-3-clause | 675aec61bdd4f6b468585125f0108027 | 0.452082 | 4.798348 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd | 2 | 14,599 | -------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
| bsd-3-clause | 8b3baee4981d4663ff516ae652d16aae | 0.446263 | 4.208417 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/master_attachment.vhd | 3 | 43,378 | -------------------------------------------------------------------------------
-- $Id: master_attachment.vhd,v 1.13 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- Master Attachment - entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: master_attachment.vhd
--
-- Description: Master attachment for Xilinx OPB
--
-------------------------------------------------------------------------------
--
-- master_attachment.vhd
-- addr_load_and_incr.vhd
--
-------------------------------------------------------------------------------
-- Author: MLL
-- History:
-- MLL 05/09/01 -- First version
--
-- MLL 09/18/01 -- Changed construct from if-then to state machine
--
-- FLO 12/13/01
-- ^^^^^^
-- Fixed component declaration addr_load_and_incr.
-- ~~~~~~
--
-- FLO 1/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
-- FLO 5/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
--
-- FLO 5/14/02
-- ^^^^^^
-- Retained-state retry optimization.
-- ~~~~~~
-- FLO 06/24/02
-- ^^^^^^
-- Implemented dynamic byte-enable capability.
-- ~~~~~~
-- FLO 06/28/02
-- ^^^^^^
-- Moved the contents of mst_module.vhd into a block in this file.
-- ~~~~~~
-- FLO 09/24/02
-- ^^^^^^
-- Changed the implementation of signal DMA_Request_HasPriority
-- so that master arbitration has a least recently serviced
-- grant behavior. Previous to the change, one master could
-- lock out the other for as long as it immediately re-requested.
-- ~~~~~~
-- FLO 10/11/02
-- ^^^^^^
-- Added state and logic to remember the outgoing master address that
-- is destroyed by the act of release of the bus (see Note, below)
-- and to use the remembered "shadow" address when restarting transactions under
-- retained-state retry. Adds about 33 FF and 34 LUT.
--
-- Note: Destroyed by using the reset of the address counter as a
-- way of driving zero to the bus.)
-- ~~~~~~
-- FLO 11/06/02
-- ^^^^^^
-- Added signal retained_state_retry_active to the sensitivity list for
-- the state-machine combinatorial process.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Master read operations do not start until new signal SA2MA_PostedWrInh
-- is false.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added generic C_MASTER_ARB_MODEL, which allows for user-parameterized
-- arbitration behavior when there are both DMA and IP masters. Supports
-- fair, DMA-priority and IP-priority modes.
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- Master read operations from the IP master do *not* wait until
-- SA2MA_PostedWrInh is false. (See first 11/19/02, above.)
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- - Toggle priority when retry is not handled as retained-state.
-- - Added handling when SA reports that a master write operation
-- has received a retry on the first IPIC read.
-- ~~~~~~
-- FLO 01/07/03
-- ^^^^^^
-- - Added one clock cycle of delay to Bus2IP_MstRdAck and Bus2IP_MstLastAck
-- for a burst master read. This change makes these two signals assert
-- on the same cycle that the corresponding IPIC posted write is
-- taking place. Note that this behavior is dependent on the slave
-- attachment implementation; any change to the slave attachment's
-- MA2SA_XferAck to Bus2IP_WrReq timing needs a corresponding adjustment
-- here.
-- ~~~~~~
-- FLO 02/21/03
-- ^^^^^^
-- - Fixed incompatibility with grant parking onto this master.
-- Details: Several places OPB_MnGrant was used under the assumption that
-- it would only assert when Mn_request was true. Under parking, this
-- assumption doesn't hold. The fix is to qualify OPB_MnGrant by
-- anding it with Mn_request to produce qualified grant signal
-- bus_mngrant_i. This qualified signal is used locally in the
-- master attachment and is passed as Bus_MnGrant to the slave attachment.
-- ~~~~~~
-- FLO 05/18/2003
-- ^^^^^^
-- Changed the ack_counter to automatically adjust its required range
-- from the C_MA2SA_NUM_WIDTH parameter. Previously this was hard-coded
-- for size 8 bursts.
-- ~~~~~~
-- FLO 05/21/2004
-- ^^^^^^
-- The signal XXX2Bus_MstBE is now available one cycle earlier so that it
-- will be valid when Mst_rd_starting_pulse pulses for one clock. This
-- fixes a problem where, if both DMA and IP masters are present,
-- the wrong MstBE values would be placed into the "BE FIFO" for
-- locally mastered read operations.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Added signal SA2MA_TimeOut to the interface. Assertion of this new
-- signal will terminate a master transaction with Bus2IP_MstTimeOut.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Drive the low-order two Mn_Abus bits to match the numerically lowest
-- Mn_BE bit that is asserted.
-- ~~~~~~
-- FLO 05/27/2004
-- ^^^^^^
-- Removal of an VHDL alias construct.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added ouput port MA2SA_RSRA (retained_state_retry_active).
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- Changed from up to down counter for counting acks.
-- (Part of v2_00_i 1.1 -> 1.3)
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added signal SA2MA_BufOccMinus1.
-- -Implemented write of any read data to the OPB before responding with
-- Bus2IP_MstRetry if the retry is signaled via SA2MA_Retry.
-- -Distinguish "clean retry" (all data, which is partial, is written
-- before retry) and "dirty retry" (some data read from IPIC but not
-- written to OPB before retry. Use Bus2IP_MstLastAck asserted concurrently
-- with Bus2IP_MstRetry as the indication of clean retry.
-- -Using bus2ip_msttimeout_i to exit state
-- Wait_for_Rdrdy on the timeout event.
-- ~~~~~~
-- FLO 10/27/2004
-- ^^^^^^
-- - On locally mastered writes, mn_seqaddr gets asserted if and only if
-- multiple beats have been buffered.
-- ~~~~~~
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."=";
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.ld_arith_reg;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity master_attachment is
generic (
C_OPB_ABUS_WIDTH : integer; -- 32 bits
C_OPB_DBUS_WIDTH : integer; -- Only 32 bits is
--supported due to the fact the the DMA registers
--were only defined for a 32-bit bus
C_MA2SA_NUM_WIDTH : integer :=4; -- 4 bits
C_DMA_ONLY : boolean; -- No IP-Master function
C_IP_MSTR_ONLY : boolean; -- No DMA-Master function
--Only one of C_DMA_ONLY or C_IP_MSTR_ONLY can be true
C_MASTER_ARB_MODEL : integer := 0
-- 0:FAIR 1:DMA_PRIORITY 2:IP_PRIORITY
);
port(
Reset : in STD_LOGIC;
--OPB ports
OPB_Clk : in STD_LOGIC;
OPB_MnGrant : in STD_LOGIC;
OPB_XferAck : in STD_LOGIC;
OPB_ErrAck : in STD_LOGIC;
OPB_TimeOut : in STD_LOGIC;
OPB_Retry : in STD_LOGIC;
--Master Attachment to OPB ports
Mn_Request : out STD_LOGIC;
Mn_Select : out STD_LOGIC;
Mn_RNW : out STD_LOGIC;
Mn_SeqAddr : out STD_LOGIC;
Mn_BusLock : out STD_LOGIC;
Mn_BE : out STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1);
Mn_ABus : out STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1);
--Master Attachment to SA ports
Bus_MnGrant : out STD_LOGIC;
MA2SA_Select : out STD_LOGIC;
MA2SA_XferAck : out STD_LOGIC;
MA2SA_Retry : out STD_LOGIC;
MA2SA_RSRA : out STD_LOGIC;
MA2SA_Rd : out STD_LOGIC;
MA2SA_Num : out STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
SA2MA_RdRdy : in STD_LOGIC;
SA2MA_WrAck : in STD_LOGIC;
SA2MA_Retry : in STD_LOGIC;
SA2MA_Error : in STD_LOGIC;
SA2MA_FifoRd : in STD_LOGIC;
SA2MA_FifoWr : in STD_LOGIC;
SA2MA_FifoBu : in STD_LOGIC;
SA2MA_PostedWrInh : in STD_LOGIC;
SA2MA_TimeOut : in STD_LOGIC;
SA2MA_BufOccMinus1 : in STD_LOGIC_VECTOR(0 to 4);
--Master Attachment from IP ports
Mstr_Sel_ma : out STD_LOGIC;
--Master Attachment from IP ports
IP2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
IP2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
IP2Bus_MstWrReq : in STD_LOGIC := '0';
IP2Bus_MstRdReq : in STD_LOGIC := '0';
IP2Bus_MstBurst : in STD_LOGIC := '0';
IP2Bus_MstBusLock : in STD_LOGIC := '0';
--Master Attachment to IP ports
Bus2IP_MstWrAck_ma : out STD_LOGIC;
Bus2IP_MstRdAck_ma : out STD_LOGIC;
Bus2IP_MstRetry : out STD_LOGIC;
Bus2IP_MstError : out STD_LOGIC;
Bus2IP_MstTimeOut : out STD_LOGIC;
Bus2IP_MstLastAck : out STD_LOGIC;
--Master Attachment from DMA ports
DMA2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
DMA2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
DMA2Bus_MstWrReq : in STD_LOGIC := '0';
DMA2Bus_MstRdReq : in STD_LOGIC := '0';
DMA2Bus_MstNum : in STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : in STD_LOGIC := '0';
DMA2Bus_MstBusLock : in STD_LOGIC := '0'
);
end master_attachment;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of master_attachment is
constant ZEROES : std_logic_vector(0 to 256) := (others => '0');
constant RESET_ACTIVE: std_logic := '1';
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
constant RETAIN_ADDRESS_OVER_RETRY : boolean := not C_DMA_ONLY;
-- The dma_sg takes the responsibility of keeping the presented
-- master address up-to-date with successful bus transfers;
-- extra logic to maintain the address under retained-state-retry
-- operation can be ommitted if dma_sg is the only master.
constant FAIR : integer := 0;
constant DMA_PRIORITY : integer := 0;
constant IP_PRIORITY : integer := 0;
--signals
signal MA2SA_XferAck_i : std_logic;
signal Mst_SM_cs_EQ_Wait_state : std_logic;
signal Mst_SM_cs_EQ_Wait_For_Req : std_logic;
signal Bus2IP_MstLastAck_i : std_logic;
signal MA2SA_Num_i : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal DMA_sel_IP_sel_not : std_logic;
signal DMA_sel_IP_sel_not_p1 : std_logic;
signal DMA_Request_HasPriority : std_logic;
signal Reset_withNotReqs : std_logic;
signal XXX2Bus_MstBurst : std_logic;
signal XXX2Bus_MstBusLock : std_logic;
signal XXX2Bus_MstRdReq : std_logic;
signal XXX2Bus_MstWrReq : std_logic;
signal XXX2Bus_RNW : std_logic;
signal XXX2Bus_MstBE : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal xxx2bus_mstbe_fifo : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal XXX2Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal Xfer_in_progress : std_logic;
signal FDRE_CE : std_logic;
signal FDRE_Reset : std_logic;
signal FDRE_SeqAddr_BusLock_Reset: std_logic;
signal Incr_N_Load : std_logic;
signal FDRE_MA2SA_Rd_Reset : std_logic;
signal Get_off_OPB_nxt_clk : std_logic;
signal Clear_SeqAddr_BusLock : std_logic;
signal Mst_rd_starting_pulse : std_logic;
signal be_fifo_wr : std_logic;
signal ma2sa_rd_i : std_logic;
signal bus_mngrant_i : std_logic;
signal mn_request_i : std_logic;
signal be_fifo_bu : std_logic_vector(0 to 3 --ToDo, eventually from generics
) := "0000";
signal loadable_Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_i : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_shadow : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal retained_state_retry_active : std_logic;
signal retained_state_retry_active_p1 : std_logic;
signal FDRE_CE_d1 : std_logic;
signal toggle_priority : std_logic;
signal sa2ma_bufocc_eq0 : std_logic;
signal sa2ma_bufocc_eq1 : std_logic;
signal ipic_rd_was_retried : std_logic;
signal all_buffered_data_written : std_logic;
signal ma2sa_rd_i_set : std_logic;
signal bus2ip_msttimeout_i : std_logic;
signal mn_seqaddr_cmb : std_logic;
signal multiple_beats : std_logic;
begin
--Combinatorial operations
Mstr_Sel_ma <= DMA_sel_IP_sel_not;
FDRE_CE <= bus_mngrant_i or MA2SA_XferAck_i;
MA2SA_XferAck <= MA2SA_XferAck_i;
Bus2IP_MstLastAck <= Bus2IP_MstLastAck_i;
sa2ma_bufocc_eq0 <= SA2MA_BufOccMinus1(0);
sa2ma_bufocc_eq1 <= bo2sl(SA2MA_BufOccMinus1(1 to 4) = "0000");
FDRE_Reset <= Get_off_OPB_nxt_clk or Reset_withNotReqs;
I_LUT4: LUT4
--Generate reset signal to force reset when master aborts request
generic map(
INIT => X"AAAE"
)
port map(
O => Reset_withNotReqs,
I0 => Reset,
I1 => Xfer_in_progress,
I2 => XXX2Bus_MstWrReq,
I3 => XXX2Bus_MstRdReq
);
Mn_ABus <= mn_abus_i;
I_Addr_ld_inc: entity opb_ipif_v2_00_h.addr_load_and_incr
--Instantiate module to load word address bus and increment when bursting
generic map(
C_BUS_WIDTH => C_OPB_ABUS_WIDTH-2
)
port map(
Bus_Clk => OPB_Clk,
FDRE_CE => FDRE_CE,
FDRE_Reset => FDRE_Reset,
Incr_N_Load => Incr_N_Load,
Bus_input => loadable_Bus_Addr(0 to C_OPB_ABUS_WIDTH-3),
Bus_output => mn_abus_i(0 to C_OPB_ABUS_WIDTH-3)
);
Mn_ABus_byte_bits_vector_Generate_0: for j in C_OPB_ABUS_WIDTH-2 to
C_OPB_ABUS_WIDTH-2 generate
--Instantiate FF to load high byte-lane bit in 32-bit bus
signal bit0 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the high bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 2 or 3.
bit0 <= ( not X(0) and not X(1) and X(3) )
or ( not X(0) and not X(1) and X(2) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit0,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_0;
Mn_ABus_byte_bits_vector_Generate_1: for j in C_OPB_ABUS_WIDTH-1 to
C_OPB_ABUS_WIDTH-1 generate
--Instantiate FF to load low byte-lane bit in 32-bit bus
signal bit1 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the low bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 1 or 3.
bit1 <= ( not X(0) and X(1) )
or ( not X(0) and not X(2) and X(3) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit1,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_1;
--------------------------------------------------------------------------------
-- The update clock cycle for the mn_abus_shadow is one clock after the
-- update of mn_abus. This timing relationship is established here.
--------------------------------------------------------------------------------
I_RDRE_CE_D1: FDE
port map(
Q => FDRE_CE_d1,
D => FDRE_CE,
C => OPB_Clk,
CE => '1'
);
--------------------------------------------------------------------------------
-- Register to shadow the Mn_ABus; can be used to restore the address under
-- retained-state retry. All changes are shadowed except the clear caused by
-- FDRE_Reset for the purpose of releasing opb_abus.
--------------------------------------------------------------------------------
INCLUDE_MN_ABUS_SHADOW: if RETAIN_ADDRESS_OVER_RETRY generate
MN_ABUS_SHADOW_GEN: for i in 0 to C_OPB_ABUS_WIDTH-1 generate
FDE_I: FDE
port map(
Q => mn_abus_shadow(i),
D => mn_abus_i(i),
C => OPB_Clk,
CE => FDRE_CE_d1
);
end generate;
end generate;
I_SeqAddr_BusLock_LUT2: LUT2
--Generate reset signal to force reset of Mn_SeqAddr and Mn_BusLock
generic map(
INIT => X"E"
)
port map(
O => FDRE_SeqAddr_BusLock_Reset,
I0 => FDRE_Reset,
I1 => Clear_SeqAddr_BusLock
);
I_FDRE_Mn_BusLock: FDRE
--Instantiate module to gate BusLock signal
port map(
Q => Mn_BusLock,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_MstBusLock,
R => FDRE_SeqAddr_BusLock_Reset
);
MULTIPLE_BEATS_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = '1' then
multiple_beats <= '0';
elsif SA2MA_RdRdy = '1' then
multiple_beats <= not sa2ma_bufocc_eq0
and not sa2ma_bufocc_eq1; -- Two or more
-- beats have been buffered for
-- transfer to the OPB.
end if;
end if;
end process;
mn_seqaddr_cmb <= XXX2Bus_MstBurst
and ( XXX2Bus_MstRdReq
or multiple_beats
);
I_FDRE_Mn_SeqAddr: FDRE
--Instantiate module to gate Sequential address signal
port map(
Q => Mn_SeqAddr,
C => OPB_Clk,
CE => FDRE_CE,
D => mn_seqaddr_cmb,
R => FDRE_SeqAddr_BusLock_Reset
);
Set_RNW_signal_PROCESS: process(XXX2Bus_MstRdReq)
--Process to set XXX2Bus_RNW
begin
if(XXX2Bus_MstRdReq = '1') then
XXX2Bus_RNW <= '1';
else
XXX2Bus_RNW <= '0';
end if;
end process Set_RNW_signal_PROCESS;
I_FDRE_Mn_RNW: FDRE
--Instantiate module to gate RNW signal
port map(
Q => Mn_RNW,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_RNW,
R => FDRE_Reset
);
Bit_Enable_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
--Instantiate modules to gate Byte enable signals
begin
I_FDRE_Mn_BE: FDRE
port map(
Q => Mn_BE(j),
C => OPB_Clk,
CE => FDRE_CE,
D => xxx2bus_mstbe_fifo(j),
R => FDRE_Reset
);
end generate Bit_Enable_vector_Generate;
MA2SA_RD_I_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if FDRE_MA2SA_Rd_Reset = '1' then ma2sa_rd_i <= '0';
elsif ma2sa_rd_i_set = '1' then ma2sa_rd_i <= '1';
else null;
end if;
end if;
end process;
MA2SA_Rd <= ma2sa_rd_i;
FDRE_MA2SA_Rd_Reset <= Reset_withNotReqs
or Bus2IP_MstLastAck_i
or Mst_SM_cs_EQ_Wait_state;
-- Instantiate the FIFO
be_fifo_wr <= SA2MA_FifoWr or Mst_rd_starting_pulse;
be_fifo_bu(0 to be_fifo_bu'length-2) <= (others => '0');
be_fifo_bu(be_fifo_bu'length-1) <= SA2MA_FifoBu;
--ToDo, eventually use a generic and generate to exclude
-- this fifo and associated logic when the system does not
-- use dynamic byte enables.
SLN_DBUS_FIFO: entity proc_common_v1_00_b.srl_fifo_rbu
generic map (
C_DWIDTH => C_OPB_DBUS_WIDTH/8,
C_DEPTH => 16
)
port map (
Clk => OPB_Clk,
Reset => Mst_SM_cs_EQ_Wait_state,
FIFO_Write => be_fifo_wr,
Data_In => XXX2Bus_MstBe,
FIFO_Read => SA2MA_FifoRd,
Data_Out => xxx2bus_mstbe_fifo,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open,
Num_To_Reread => be_fifo_bu,
Underflow => open,
Overflow => open
);
Bus_MnGrant <= bus_mngrant_i;
Mn_Request <= mn_request_i;
--*************************************************
Include_IP_or_DMA_MUXing: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
--Muxing of IP master or DMA master signals
XXX2Bus_MstRdReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstRdReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstRdReq);
XXX2Bus_MstWrReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstWrReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstWrReq);
XXX2Bus_MstBurst <= ( DMA_sel_IP_sel_not and DMA2Bus_MstBurst) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBurst);
XXX2Bus_MstBusLock <= XXX2Bus_MstBurst or
( DMA_sel_IP_sel_not and DMA2Bus_MstBusLock) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBusLock);
XXX2Bus_MstBE_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
begin
XXX2Bus_MstBE(j) <= DMA2Bus_MstBE(j) when (DMA_sel_IP_sel_not_p1) = '1'
else
IP2Bus_MstBE(j);
end generate XXX2Bus_MstBE_vector_Generate;
XXX2Bus_MstABus_vector_Generate: for j in 0 to
(C_OPB_ABUS_WIDTH-1) generate
begin
XXX2Bus_Addr(j) <= ( DMA_sel_IP_sel_not and DMA2Bus_Addr(j)) or
(not DMA_sel_IP_sel_not and IP2Bus_Addr(j));
end generate XXX2Bus_MstABus_vector_Generate;
end generate Include_IP_or_DMA_MUXing;
loadable_Bus_Addr <= mn_abus_shadow when RETAIN_ADDRESS_OVER_RETRY and
retained_state_retry_active='1'
else
XXX2Bus_Addr;
DMA_Master_Only: if(C_DMA_ONLY) generate
begin
XXX2Bus_MstRdReq <= DMA2Bus_MstRdReq;
XXX2Bus_MstWrReq <= DMA2Bus_MstWrReq;
XXX2Bus_Addr <= DMA2Bus_Addr;
XXX2Bus_MstBE <= DMA2Bus_MstBE;
XXX2Bus_MstBurst <= DMA2Bus_MstBurst;
XXX2Bus_MstBusLock <= DMA2Bus_MstBusLock or DMA2Bus_MstBurst;
end generate DMA_Master_Only;
IP_Master_Only: if(C_IP_MSTR_ONLY) generate
begin
XXX2Bus_MstRdReq <= IP2Bus_MstRdReq;
XXX2Bus_MstWrReq <= IP2Bus_MstWrReq;
XXX2Bus_Addr <= IP2Bus_Addr;
XXX2Bus_MstBE <= IP2Bus_MstBE;
XXX2Bus_MstBurst <= IP2Bus_MstBurst;
XXX2Bus_MstBusLock <= IP2Bus_MstBusLock or IP2Bus_MstBurst;
end generate IP_Master_Only;
Set_Value_of_MA2SA_Num_PROCESS: process(
DMA_sel_IP_sel_not, IP2Bus_MstBurst, DMA2Bus_MstNum
)
begin
if(DMA_sel_IP_sel_not = '0') then
MA2SA_Num_i <= (others => '0');
MA2SA_Num_i(MA2SA_Num'right-3) <= IP2Bus_MstBurst;
MA2SA_Num_i(MA2SA_Num'right ) <= not IP2Bus_MstBurst;
else
MA2SA_Num_i <= DMA2Bus_MstNum;
end if;
end process Set_Value_of_MA2SA_Num_PROCESS;
MA2SA_Num <= MA2SA_Num_i;
No_Arbiter_DMA_Only: if(C_DMA_ONLY) generate
--Fix DMA_sel_IP_sel_not if DMA only
begin
DMA_sel_IP_sel_not <= '1';
DMA_sel_IP_sel_not_p1 <= '1';
DMA_Request_HasPriority <= '1';
end generate No_Arbiter_DMA_Only;
No_Arbiter_IP_Master_Only: if(C_IP_MSTR_ONLY) generate
--Fix DMA_sel_IP_sel_not if IP master only
begin
DMA_sel_IP_sel_not <= '0';
DMA_sel_IP_sel_not_p1 <= '0';
DMA_Request_HasPriority <= '0';
end generate No_Arbiter_IP_Master_Only;
Insert_Arbiter: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
Priority_Arbitration_PROCESS: process(OPB_Clk)
--Process to set priority for IP and DMA requests that occur at the
--same time
begin
if(OPB_Clk'event and OPB_Clk = '1') then
-----------------------------------------------------------------------
-- Keep track of priority.
-----------------------------------------------------------------------
if(Reset = RESET_ACTIVE) then
DMA_Request_HasPriority <= '0';
elsif toggle_priority = '1' then
DMA_Request_HasPriority <= not(DMA_Request_HasPriority);
elsif (C_MASTER_ARB_MODEL = DMA_PRIORITY) then
DMA_Request_HasPriority <= '1';
elsif (C_MASTER_ARB_MODEL = IP_PRIORITY) then
DMA_Request_HasPriority <= '0';
elsif (C_MASTER_ARB_MODEL = FAIR) and (Bus2IP_MstLastAck_i = '1') then
DMA_Request_HasPriority <= not(DMA_sel_IP_sel_not);
end if;
-----------------------------------------------------------------------
-- Master selection.
-----------------------------------------------------------------------
end if;
end process Priority_Arbitration_PROCESS;
DMA_sel_IP_sel_not_p1 <=
not bo2sl(C_MASTER_ARB_MODEL = IP_PRIORITY)
--
when (Reset = RESET_ACTIVE) else -- Reset condition
(DMA2Bus_MstWrReq or (DMA2Bus_MstRdReq and not SA2MA_PostedWrInh)) and
(DMA_Request_HasPriority or not (IP2Bus_MstWrReq or IP2Bus_MstRdReq))
-------------------------------------------------------------
-- Above, new value is true when
-- DMA requesting and either DMA has priority or IP not
-- requesting.
-------------------------------------------------------------
--
when (Mst_SM_cs_EQ_Wait_For_Req and -- Condition to compute new
(DMA2Bus_MstWrReq or DMA2Bus_MstRdReq or
IP2Bus_MstWrReq or IP2Bus_MstRdReq)
) = '1' else
DMA_sel_IP_sel_not; -- Otherwise, retain state
ARB_REG_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
DMA_sel_IP_sel_not <= DMA_sel_IP_sel_not_p1;
end if;
end process;
end generate Insert_Arbiter;
FSM_AND_RELATED_LOGIC: block
constant RESET_ACTIVE: std_logic := '1';
--signals
signal Mn_Select_i : std_logic;
signal Mn_Select_p1 : std_logic;
signal Bus2IP_MstLastAck_i_p1: std_logic;
signal last_mstrd_burst_ack_d1 : std_logic;
signal Bus2IP_MstWrAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1_d1: std_logic;
signal either_ack : std_logic;
signal acks_left : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal acks_left_eq1 : std_logic;
signal acks_left_eq2 : std_logic;
signal acks_left_ld : std_logic;
signal Bus2IP_MstError_Flag : std_logic;
signal bus2ip_mstretry_i : std_logic;
signal bus2ip_mstretry_i_p1 : std_logic;
signal Mst_SM_cs_EQ_Wait_state_i : std_logic;
type Master_Attach_SMtype is (Wait_state,
Wait_For_Req,
Wait_for_RdRdy,
Mn_Req,
Burst_Count_Acks,
Check_Retry_Type
);
signal Mst_SM_cs, Mst_SM_ns : Master_Attach_SMtype;
begin
--Combinatorial operations
Incr_N_Load <= not bus_mngrant_i;
bus_mngrant_i <= OPB_MnGrant and mn_request_i;
MA2SA_XferAck_i <= OPB_XferAck and Mn_Select_i;
MA2SA_Retry <= OPB_Retry and Mn_Select_i;
MA2SA_RSRA <= retained_state_retry_active;
Mn_Select <= Mn_Select_i;
MA2SA_Select <= Mn_Select_i;
Mst_SM_cs_EQ_Wait_state <= Mst_SM_cs_EQ_Wait_state_i;
Bus2IP_MstError <= Bus2IP_MstError_Flag;
Get_off_OPB_nxt_clk <= not mn_select_p1;
-- State machine combinational process
Mst_SM: process (Mst_SM_cs, XXX2Bus_MstWrReq,
XXX2Bus_MstRdReq, SA2MA_RdRdy, OPB_TimeOut,
OPB_Retry, bus_mngrant_i, MA2SA_XferAck_i,
MA2SA_Num_i, Mn_Select_i,
bus2ip_msttimeout_i, Bus2IP_MstLastAck_i, Bus2IP_MstRetry_i,
DMA2Bus_MstRdReq, DMA2Bus_MstWrReq, SA2MA_PostedWrInh,
IP2Bus_MstRdReq, IP2Bus_MstWrReq, retained_state_retry_active,
SA2MA_TimeOut, acks_left_eq1, acks_left_eq2,
DMA_sel_IP_sel_not_p1,
ma2sa_rd_i, sa2ma_bufocc_eq0, sa2ma_bufocc_eq1, all_buffered_data_written)
begin
-- Set default values
Mst_SM_ns <= Mst_SM_cs;
mn_request_i <= '0';
mn_select_p1 <= '0';
Xfer_in_progress <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '0';
Mst_SM_cs_EQ_Wait_For_Req <= '0';
Clear_SeqAddr_BusLock <= '0';
Mst_rd_starting_pulse <= '0';
retained_state_retry_active_p1 <= retained_state_retry_active;
toggle_priority <= '0';
acks_left_ld <= '0';
ma2sa_rd_i_set <= '0';
case Mst_SM_cs is
when Wait_state =>
Mst_SM_ns <= Wait_For_Req;
Clear_SeqAddr_BusLock <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '1';
Xfer_in_progress <= '0';
retained_state_retry_active_p1 <= '0';
when Wait_For_Req =>
Mst_SM_cs_EQ_Wait_For_Req <= '1';
Xfer_in_progress <= '0';
if ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstWrReq) or
( DMA_sel_IP_sel_not_p1 and DMA2Bus_MstWrReq)) = '1' then
ma2sa_rd_i_set <= '1';
Mst_SM_ns <= Wait_for_RdRdy;
elsif ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstRdReq) or
( DMA_sel_IP_sel_not_p1 and (DMA2Bus_MstRdReq and
not SA2MA_PostedWrInh))
) = '1' then
-- DMA reads do not proceed until posted writes
-- can be accepted because the slave sets the rate
-- for this data, which can be at one per clock.
-- An IP master read proceeds without checking
-- posted write inhibit, so, the IP master read request
-- may occur only if IPIC posted writes will succeed and
-- such posted writes will occur without regard to the
-- state of the PostedWrInh signal.
Mst_rd_starting_pulse <= '1';
Mst_SM_ns <= Mn_Req;
end if;
when Wait_for_RdRdy =>
if(SA2MA_RdRdy and not sa2ma_bufocc_eq0) = '1' then
Mst_SM_ns <= Mn_Req;
elsif (bus2ip_mstretry_i or bus2ip_msttimeout_i) = '1' then
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
when Mn_Req =>
mn_request_i <= '1';
acks_left_ld <= not retained_state_retry_active;
if(bus_mngrant_i = '1') then
Mst_SM_ns <= Burst_Count_Acks;
mn_select_p1 <= '1';
end if; -- mn_request_i must deassert in response
-- to OPB_MnGrant to assure that bus_mngrant_i
-- is asserted for exactly one clock.
-- In this state bus_mngrant_i is asserted iff
-- OPB_MnGrant is asserted (since mn_request_i = '1').
when Check_Retry_Type =>
if (XXX2Bus_MstRdReq or XXX2Bus_MstWrReq)='1' then
Mst_SM_ns <= Mn_Req; -- Transaction continued.
retained_state_retry_active_p1 <= '1';
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state; -- Transaction aborted.
end if;
when Burst_Count_Acks =>
mn_select_p1 <= Mn_Select_i
and not ( ( MA2SA_XferAck_i -- End transaction
and (acks_left_eq1 or -- if done or ...
(ma2sa_rd_i and sa2ma_bufocc_eq0)
)
)
or OPB_Retry -- retry response or
or OPB_TimeOut -- timeout response.
);
if(bus2ip_mstretry_i = '1') then
if not (ma2sa_rd_i and all_buffered_data_written) = '1' then
Mst_SM_ns <= Check_Retry_Type;
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
elsif(bus2ip_msttimeout_i = '1') then
Mst_SM_ns <= Wait_state;
elsif(Bus2IP_MstLastAck_i = '1') then
Mst_SM_ns <= Wait_state;
end if;
if(MA2SA_XferAck_i = '1') then
if (acks_left_eq2 or (ma2sa_rd_i and sa2ma_bufocc_eq1)) = '1' then
Clear_SeqAddr_BusLock <= '1';
end if;
end if;
when others =>
Mst_SM_ns <= Wait_state;
end case;
end process Mst_SM;
Mst_SM_Reg: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset_withNotReqs = RESET_ACTIVE) then
Mst_SM_cs <= Wait_state;
else
Mst_SM_cs <= Mst_SM_ns;
end if;
retained_state_retry_active <= retained_state_retry_active_p1;
end if;
end process Mst_SM_Reg;
ms_select_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
Mn_Select_i <= '0';
else
Mn_Select_i <= mn_select_p1;
end if;
end if;
end process ms_select_REG;
Register_ErrAck_Flag_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE or Mst_SM_cs_EQ_Wait_state_i = '1') then
Bus2IP_MstError_Flag <= '0';
elsif((OPB_ErrAck = '1' and Mn_Select_i = '1') or
(SA2MA_Error = '1' and Xfer_in_progress = '1')) then
Bus2IP_MstError_Flag <= '1'; -- Flag error to be noted with LastAck
-- to local master
end if;
end if;
end process Register_ErrAck_Flag_PROCESS;
RETRY_HELP_PROC: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if (bus2ip_mstretry_i_p1 and Bus2IP_MstLastAck_i_p1) = '1' or
(Reset = RESET_ACTIVE) then
-- As bus2ip_mstretry_i is set, ipic_rd_was_retried is cleared. This
-- makes bus2ip_mstretry_i a one-clock pulse when it is caused in part
-- by ipic_rd_was_retried.
ipic_rd_was_retried <= '0';
elsif (SA2MA_RdRdy) = '1' then
ipic_rd_was_retried <= SA2MA_Retry;
end if;
--
if (SA2MA_RdRdy) = '1' or (Reset = RESET_ACTIVE) then
all_buffered_data_written <= sa2ma_bufocc_eq0; -- If there is
-- no buffered data at RdRdy, then there is none to write.
elsif (sa2ma_bufocc_eq0 and MA2SA_XferAck_i) = '1' then -- This captures
-- the point at which all buffered data is written because the
-- buffer proper (fifo) is empty so the only word left is in
-- the output register, and it is being ack'ed.
all_buffered_data_written <= '1';
end if;
end if;
end process;
bus2ip_mstretry_i_p1 <= (OPB_Retry and Mn_Select_i) or
(ipic_rd_was_retried and all_buffered_data_written) or
(XXX2Bus_MstRdReq and SA2MA_Retry);
Register_OPB_Retry_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then bus2ip_mstretry_i <= '0';
else bus2ip_mstretry_i <= bus2ip_mstretry_i_p1;
end if;
end if;
end process Register_OPB_Retry_PROCESS;
Bus2IP_MstRetry <= bus2ip_mstretry_i;
Register_Time_Out_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then
bus2ip_msttimeout_i <= '0';
else
bus2ip_msttimeout_i <= (OPB_TimeOut and Mn_Select_i) or SA2MA_TimeOut;
end if;
end if;
end process Register_Time_Out_PROCESS;
Bus2IP_MstTimeOut <= bus2ip_msttimeout_i;
either_ack <= Bus2IP_MstRdAck_ma_p1 or Bus2IP_MstWrAck_ma_p1;
--
ACKS_LEFT_I : entity proc_common_v1_00_b.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => MA2SA_Num_i'length,
C_RESET_VALUE => ZEROES(0 to MA2SA_Num_i'length-1),
C_LD_WIDTH => MA2SA_Num_i'length,
C_AD_WIDTH => 1
)
port map (
CK => OPB_Clk,
RST => '0',
Q => acks_left,
LD => MA2SA_Num_i,
AD => "1",
LOAD => acks_left_ld,
OP => either_ack
);
--
acks_left_eq1 <= bo2sl(UNSIGNED(acks_left) = 1);
acks_left_eq2 <= bo2sl(UNSIGNED(acks_left) = 2);
Mst_Ack_COMB_PROCESS: process(XXX2Bus_MstRdReq, XXX2Bus_MstWrReq,
XXX2Bus_MstBurst,
SA2MA_WrAck, MA2SA_XferAck_i,
acks_left_eq1, acks_left_eq2, MA2SA_Num_i)
begin
Bus2IP_MstWrAck_ma_p1 <= '0';
Bus2IP_MstRdAck_ma_p1 <= '0';
if(XXX2Bus_MstRdReq = '1') then
if(XXX2Bus_MstBurst = '1') then --Fire and forget with Burst
Bus2IP_MstRdAck_ma_p1 <= MA2SA_XferAck_i;
else --Wait for local Write Ack
Bus2IP_MstRdAck_ma_p1 <= SA2MA_WrAck; --when single Xfer
end if;
elsif(XXX2Bus_MstWrReq = '1') then
Bus2IP_MstWrAck_ma_p1 <= MA2SA_XferAck_i;
end if;
end process Mst_Ack_COMB_PROCESS;
RD_BURST_ACK_DELAY_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
Bus2IP_MstRdAck_ma_p1_d1 <= Bus2IP_MstRdAck_ma_p1;
last_mstrd_burst_ack_d1 <= XXX2Bus_MstRdReq and XXX2Bus_MstBurst and
MA2SA_XferAck_i and acks_left_eq1;
end if;
end process;
Bus2IP_MstLastAck_i_p1 <= last_mstrd_burst_ack_d1 -- When MstRd, burst
or ( XXX2Bus_MstRdReq
and not XXX2Bus_MstBurst
and SA2MA_WrAck -- When MstRd, ~burst
and acks_left_eq1)
or ( XXX2Bus_MstWrReq
and MA2SA_XferAck_i -- When MstWr
and acks_left_eq1)
or ( bus2ip_mstretry_i_p1 -- When retry
and ( ( XXX2Bus_MstWrReq
and all_buffered_data_written)
or ( XXX2Bus_MstRdReq
and SA2MA_Retry)));
-- Note, for retries Bus2IP_MstLastAck serves
-- as a qualifier. It is asserted iff
-- no data is "in limbo", i.e. all data that
-- has been read from the IPIC/OPB has
-- been written to the OPB/IPIC or that
-- any read data that has been discarded
-- is rereadable (aka idempotent,
-- non-destructive readable, pre-fetchable).
-- For loccally mastered writes,
-- (XXX2Bus_MstWrReq = '1'), Bus2IP_MstLastAck
-- is asserted iff buffered data has been
-- written.
-- For loccally mastered reads,
-- (XXX2Bus_MstRdReq = '1'), Bus2IP_MstLastAck
-- is always asserted even though the data read
-- from the OPB (and not accepted by the IPIC)
-- is discarded. The consequence is that any
-- OPB data read as the first part of a locally
-- mastered read operation must either be
-- re-readable or there must be a guarantee
-- that the IPIC will not refuse it by
-- replying with retry.
MSTLASTACK_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstLastAck_i <= '0';
else
Bus2IP_MstLastAck_i <= Bus2IP_MstLastAck_i_p1;
end if;
end if;
end process;
Mst_Ack_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstRdAck_ma <= '0';
Bus2IP_MstWrAck_ma <= '0';
else
Bus2IP_MstWrAck_ma <= Bus2IP_MstWrAck_ma_p1;
if (XXX2Bus_MstRdReq and XXX2Bus_MstBurst) = '0' then
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1;
else
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1_d1;
end if;
end if;
end if;
end process Mst_Ack_REG_PROCESS;
end block FSM_AND_RELATED_LOGIC;
---
end implementation;
| bsd-3-clause | 642be8524ef04202a831e382fd601c10 | 0.531836 | 3.590002 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_1.vhd | 2 | 16,995 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_1.c
-- reg6 = * function
-- reg7 = thread
-- reg8 = * attr
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread, data->attr, data->function, (void *) data );
when STATE_3 =>
reg8_next <= intrfc2thrd_value;
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg8;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b72510f444e1bd7ad5beb05c1dbf2cc0 | 0.544337 | 3.801163 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/Eth_Tx_HighPriority/Eth_Tx_HighPriority.vhd | 1 | 6,660 | --=============================================================================
-- Project: DFE_TDD
-- Author: Zhao Yifei
-- Data: April/09/2008
-- Module Name: Eth_Tx_HighPriority
-- Revision: 1.0
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision History:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity Eth_Tx_HighPriority is
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end Eth_Tx_HighPriority;
architecture arch_Eth_Tx_HighPriority of Eth_Tx_HighPriority is
component zcpsm2DSP
port(
clk : in std_logic;
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0);
interrupt : out std_logic;
dsp_io : out std_logic;
dsp_rw : out std_logic;
dsp_a : out std_logic_vector(7 downto 0);
dsp_din : out std_logic_vector(7 downto 0);
dsp_dout : in std_logic_vector(7 downto 0);
dsp_int : in std_logic
);
end component;
component ASYNCWRITE
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic
);
end component;
signal s_DSP_IO : std_logic;
signal s_DSP_RW : std_logic;
signal m8_DSP_A : std_logic_vector( 7 downto 0 );
signal m8_DSP_DIn : std_logic_vector( 7 downto 0 );
signal m8_DSP_DOut : std_logic_vector( 7 downto 0 );
signal s_DSP_CE : std_logic := '0';
signal s_SyncWE : std_logic := '0';
signal s_AsyncWE : std_logic := '0';
signal m4_AsyncAddrReg : std_logic_vector( 3 downto 0 );
signal m4_SyncAddrReg : std_logic_vector( 3 downto 0 );
signal s_Req : std_logic;
signal m48_Tx_Req_DesMac_Reg : std_logic_vector( 47 downto 0 );
signal m16_Tx_Req_Addr_Reg : std_logic_vector( 15 downto 0 );
signal m16_Tx_Req_Data_Reg : std_logic_vector( 15 downto 0 );
begin
mo_DspInterface : zcpsm2DSP
port map(
clk => clk_zcpsm,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => open, --in_port,
interrupt => open,
dsp_io => s_DSP_IO,
dsp_rw => s_DSP_RW,
dsp_a => m8_DSP_A,
dsp_din => m8_DSP_DIn,
dsp_dout => m8_DSP_DOut,
dsp_int => '0'
);
s_DSP_CE <= '1' when ( m8_DSP_A( 7 downto 4 ) = PORT_ETH_TX_HIGHPRI_CE ) else
'0';
mo_AsyncWrite_DSPInterface : ASYNCWRITE
port map(
reset => reset,
async_clk => s_DSP_IO,
sync_clk => clk,
async_wren => s_AsyncWE,
trigger => '1',
sync_wren => s_SyncWE,
over => open,
flag => open
);
s_AsyncWE <= ( not s_DSP_RW ) and s_DSP_CE;
AsyncReg : process( reset, s_DSP_IO )
begin
if ( reset = '1' ) then
m4_AsyncAddrReg <= ( others => '0' );
elsif ( rising_edge( s_DSP_IO ) ) then
if ( ( s_DSP_CE = '1' ) and ( s_AsyncWE = '1' ) ) then
m4_AsyncAddrReg <= m8_DSP_A( 3 downto 0 );
end if;
end if;
end process;
SyncReg : process( reset, clk )
begin
if ( reset = '1' ) then
m4_SyncAddrReg <= ( others => '0' );
elsif ( rising_edge( clk ) ) then
m4_SyncAddrReg <= m4_AsyncAddrReg;
end if;
end process;
Req : process( reset, clk )
begin
if ( reset = '1' ) then
s_Req <= '0';
m48_Tx_Req_DesMac_Reg <= ( others => '0' );
m16_Tx_Req_Addr_Reg <= ( others => '0' );
m16_Tx_Req_Data_Reg <= ( others => '0' );
elsif ( rising_edge( clk ) ) then
if ( ( s_SyncWE = '1' ) and ( m4_SyncAddrReg = PORT_ETH_TX_HIGHPRI_REQ ) ) then
s_Req <= '0';
elsif ( s_Tx_Req = '1' ) then
s_Req <= '1';
end if;
if ( s_Tx_Req = '1' ) then
m48_Tx_Req_DesMac_Reg <= m48_Tx_Req_DesMac;
m16_Tx_Req_Addr_Reg <= m16_Tx_Req_Addr;
m16_Tx_Req_Data_Reg <= m16_Tx_Req_Data;
end if;
end if;
end process;
in_port <= ( "0000000" & s_Req ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_REQ ) ) else
m16_Tx_Req_Addr_Reg( 7 downto 0 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_ADDR_L ) ) else
m16_Tx_Req_Addr_Reg( 15 downto 8 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_ADDR_H ) ) else
m16_Tx_Req_Data_Reg( 7 downto 0 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DATA_L ) ) else
m16_Tx_Req_Data_Reg( 15 downto 8 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DATA_H ) ) else
m48_Tx_Req_DesMac_Reg( 47 downto 40 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_0 ) ) else
m48_Tx_Req_DesMac_Reg( 39 downto 32 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_1 ) ) else
m48_Tx_Req_DesMac_Reg( 31 downto 24 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_2 ) ) else
m48_Tx_Req_DesMac_Reg( 23 downto 16 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_3 ) ) else
m48_Tx_Req_DesMac_Reg( 15 downto 8 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_4 ) ) else
m48_Tx_Req_DesMac_Reg( 7 downto 0 ) when ( ( s_DSP_CE = '1' ) and ( s_DSP_RW = '1' ) and ( m8_DSP_A( 3 downto 0 ) = PORT_ETH_TX_HIGHPRI_DESMAC_5 ) ) else
( others => 'Z' );
end arch_Eth_Tx_HighPriority;
| gpl-2.0 | 51332f28047ee92ad10b467ab22eebec | 0.538438 | 2.55957 | false | false | false | false |
iocoder/graduation | hardware/cpu/cachearray.vhd | 1 | 1,836 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.cpu_pkg.all;
entity cachearray is
Port (
CLK : in STD_LOGIC;
-- bus interface
RW : in STD_LOGIC;
RD_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
WR_ADDR : in STD_LOGIC_VECTOR (9 downto 0);
-- inputs
Vin : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (31 downto 0);
TAGin : in STD_LOGIC_VECTOR (19 downto 0);
-- outputs
Vout : out STD_LOGIC;
Dout : out STD_LOGIC_VECTOR (31 downto 0);
TAGout : out STD_LOGIC_VECTOR (19 downto 0)
);
end entity;
architecture Behavioral of cachearray is
type cache_v_t is array (0 to 1023) of std_logic;
type cache_data_t is array (0 to 1023) of std_logic_vector(31 downto 0);
type cache_tag_t is array (0 to 1023) of std_logic_vector(19 downto 0);
signal cache_arr_v : cache_v_t := (others => '0');
signal cache_arr_data : cache_data_t;
signal cache_arr_tag : cache_tag_t;
attribute ram_style: string;
attribute ram_style of cache_arr_v : signal is "block";
attribute ram_style of cache_arr_data : signal is "block";
attribute ram_style of cache_arr_tag : signal is "block";
begin
process (CLK)
begin
if ( CLK = '0' and CLK'event ) then
if (RW = '1') then
cache_arr_v(conv_integer(WR_ADDR)) <= Vin;
cache_arr_data(conv_integer(WR_ADDR)) <= Din;
cache_arr_tag(conv_integer(WR_ADDR)) <= TAGin;
else
Vout <= cache_arr_v(conv_integer(RD_ADDR));
Dout <= cache_arr_data(conv_integer(RD_ADDR));
TAGout <= cache_arr_tag(conv_integer(RD_ADDR));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 77c0367cf9ff39093d08097a57e731d3 | 0.596405 | 3.149228 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter_top.vhd | 2 | 12,634 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v3_00_a.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| bsd-3-clause | cf3a1e012d460f40b6ee7a2c2f256ca4 | 0.432325 | 4.559365 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.