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Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/edge_detector.vhd | 1 | 1,400 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:27:16 11/11/2015
-- Design Name:
-- Module Name: edge_detector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity edge_detector is
Port ( e_clk : in STD_LOGIC;
WR_signal : in STD_LOGIC;
w_ready, w_ready2 : out STD_LOGIC);--
end edge_detector;
architecture Behavioral of edge_detector is
signal signal_d:STD_LOGIC;
begin
process(e_clk)
begin
-- if e_reset <= '1' then
--w_ready <= '0';
-- w_ready2 <= '0';
if e_clk= '1' and e_clk'event then
signal_d <= WR_signal;
end if;
end process;
w_ready <= (not signal_d) and WR_signal;
w_ready2 <= (not signal_d) and WR_signal;
end Behavioral;
| unlicense | ee90e5abcb0e15dd1664dcdc06b0601e | 0.553571 | 3.733333 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/lock_fsm.vhd | 11 | 8,253 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity lock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end lock_fsm;
architecture behavioral of lock_fsm is
-- A type for the states in the lock fsm
type lock_state is
(
IDLE,
READ,
DONE,
UPDATE
);
-- Declare signals for the lock fsm
signal lock_cs : lock_state;
signal lock_ns : lock_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
lock_update : process(clk,rst,sysrst,lock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
lock_cs <= IDLE;
else
lock_cs <= lock_ns;
end if;
end if;
end process lock_update;
lock_controller : process(lock_cs,start,mutex,thread,micount,mikind,miowner,milast,minext) is
begin
lock_ns <= lock_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case lock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
lock_ns <= READ;
end if;
when READ =>
lock_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
else
if( mikind = SYNCH_ERROR and miowner = thread ) then
data(0) <= '1';
finish <= '1';
lock_ns <= IDLE;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
finish <= '1';
lock_ns <= IDLE;
elsif( minext = miowner ) then
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= thread;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
else
toaddr <= milast;
toena <= '1';
towea <= '1';
tonext <= thread;
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= thread;
mocount <= micount;
mokind <= mikind;
finish <= '0';
lock_ns <= UPDATE;
end if;
end if;
when UPDATE =>
toaddr <= thread;
toena <= '1';
towea <= '1';
tonext <= thread;
finish <= '1';
data(1) <= '1';
lock_ns <= IDLE;
end case;
end process lock_controller;
end behavioral;
| bsd-3-clause | 2a767c7f1b5bfdf47067dc97abad06cf | 0.44711 | 4.644344 | false | false | false | false |
iocoder/graduation | hardware/cpu/cpu_pkg.vhd | 1 | 13,468 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
package cpu_pkg is
-- signed/unsigned extension
function unsiext1 (input : in STD_LOGIC_VECTOR( 7 downto 0))
return STD_LOGIC_VECTOR;
function unsiext2 (input : in STD_LOGIC_VECTOR(15 downto 0))
return STD_LOGIC_VECTOR;
function signext1 (input : in STD_LOGIC_VECTOR( 7 downto 0))
return STD_LOGIC_VECTOR;
function signext2 (input : in STD_LOGIC_VECTOR(15 downto 0))
return STD_LOGIC_VECTOR;
-- alu functions
function alu_cpy (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_add (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_sub (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_and (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_ior (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_xor (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_nor (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_lts (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_ltu (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_sll (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_srl (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_sra (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_mul (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_mulu(alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_div (alu1: in integer;
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
function alu_rem (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR;
-- decoding functions
function is_alureg (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_branchregimm (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_jmp (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_branch (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_aluimm (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_memload (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_memstore (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
function is_cop0 (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean;
end package;
package body cpu_pkg is
-- unsigned extend 8-bit to 32-bit
function unsiext1 (input : in STD_LOGIC_VECTOR( 7 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := x"000000" & input;
return output;
end unsiext1;
-- unsigned extend 16-bit to 32-bit
function unsiext2 (input : in STD_LOGIC_VECTOR(15 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := x"0000" & input;
return output;
end unsiext2;
-- signed extend 8-bit to 32-bit
function signext1 (input : in STD_LOGIC_VECTOR( 7 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
if (input(7) = '1') then
output := x"FFFFFF" & input;
else
output := x"000000" & input;
end if;
return output;
end signext1;
-- signed extend 16-bit to 32-bit
function signext2 (input : in STD_LOGIC_VECTOR(15 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
if (input(15) = '1') then
output := x"FFFF" & input;
else
output := x"0000" & input;
end if;
return output;
end signext2;
-- alu cpy
function alu_cpy (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := alu2;
return output;
end alu_cpy;
-- alu add
function alu_add (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := std_logic_vector(unsigned(alu1) + unsigned(alu2));
return output;
end alu_add;
-- alu sub
function alu_sub (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := std_logic_vector(unsigned(alu1) - unsigned(alu2));
return output;
end alu_sub;
-- alu and
function alu_and (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := alu1 AND alu2;
return output;
end alu_and;
-- alu ior
function alu_ior (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := alu1 OR alu2;
return output;
end alu_ior;
-- alu xor
function alu_xor (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := alu1 XOR alu2;
return output;
end alu_xor;
-- alu nor
function alu_nor (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := alu1 NOR alu2;
return output;
end alu_nor;
-- alu lts
function alu_lts (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
if (signed(alu1) < signed(alu2)) then
output := x"00000001";
else
output := x"00000000";
end if;
return output;
end alu_lts;
-- alu ltu
function alu_ltu (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
if (unsigned(alu1) < unsigned(alu2)) then
output := x"00000001";
else
output := x"00000000";
end if;
return output;
end alu_ltu;
-- alu sll
function alu_sll (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := std_logic_vector(
shift_left(unsigned(alu2),
to_integer(unsigned(alu1(4 downto 0)))));
return output;
end alu_sll;
-- alu srl
function alu_srl (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := std_logic_vector(
shift_right(unsigned(alu2),
to_integer(unsigned(alu1(4 downto 0)))));
return output;
end alu_srl;
-- alu sra
function alu_sra (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output := std_logic_vector(
shift_right(signed(alu2),
to_integer(unsigned(alu1(4 downto 0)))));
return output;
end alu_sra;
-- alu mul
function alu_mul (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(63 downto 0);
begin
output := std_logic_vector(signed(alu1) * signed(alu2));
return output;
end alu_mul;
-- alu mulu
function alu_mulu(alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(63 downto 0);
begin
output := std_logic_vector(unsigned(alu1) * unsigned(alu2));
return output;
end alu_mulu;
-- alu div
function alu_div (alu1: in integer;
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable first : STD_LOGIC_VECTOR(31 downto 0) := x"00000001";
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
output :=
std_logic_vector(
signed(shift_left(unsigned(first),alu1))/
signed(alu2));
return output;
end alu_div;
-- alu rem
function alu_rem (alu1: in STD_LOGIC_VECTOR(31 downto 0);
alu2: in STD_LOGIC_VECTOR(31 downto 0))
return STD_LOGIC_VECTOR is
variable output : STD_LOGIC_VECTOR(31 downto 0);
begin
--output := std_logic_vector(signed(alu1) rem signed(alu2));
return output;
end alu_rem;
-- is alureg opcode
function is_alureg (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode = "000000" then
return true;
else
return false;
end if;
end is_alureg;
-- is branchregimm opcode
function is_branchregimm (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode = "000001" then
return true;
else
return false;
end if;
end is_branchregimm;
-- is jmp opcode
function is_jmp (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode = "000010" or opcode = "000011" then
return true;
else
return false;
end if;
end is_jmp;
-- is branch opcode
function is_branch (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode(5 downto 2) = "0001" then
return true;
else
return false;
end if;
end is_branch;
-- is aluimm opcode
function is_aluimm (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode(5 downto 3) = "001" then
return true;
else
return false;
end if;
end is_aluimm;
-- is memload opcode
function is_memload (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode(5 downto 3) = "100" then
return true;
else
return false;
end if;
end is_memload;
-- is memstore opcode
function is_memstore (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode(5 downto 3) = "101" then
return true;
else
return false;
end if;
end is_memstore;
-- is cop0 opcode
function is_cop0 (opcode: in STD_LOGIC_VECTOR(5 downto 0))
return boolean is
begin
if opcode(5 downto 0) = "010000" then
return true;
else
return false;
end if;
end is_cop0;
end cpu_pkg;
| gpl-3.0 | 111dc850eb48e3c0705fc54eb12b3650 | 0.570389 | 3.925386 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_double_buffer.vhd | 2 | 5,400 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:24:19 11/08/2013
-- Design Name:
-- Module Name: double_buffer - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_double_buffer is
generic( wb_add_width: positive := 16; --! width of the address bus
wb_data_width : positive := 16; --! width of the data bus
buffer_size : positive := 64 --! buffer size
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_add_width-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_add_width-1 downto 0);
wbs_readdata : out std_logic_vector( wb_add_width-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
buffer_index : out std_logic ; -- index of buffer currently in use
free_buffer : in std_logic ; -- indicate that written buffer is free to switch
write_buffer : in std_logic ;
buffer_input : in std_logic_vector(15 downto 0);
buffer_address : in std_logic_vector(15 downto 0)
);
end wishbone_double_buffer;
architecture Behavioral of wishbone_double_buffer is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
signal buffer_use : std_logic_vector(1 downto 0);
signal buffer_read_data : std_logic_vector(15 downto 0);
signal read_address, write_address : std_logic_vector(12 downto 0);
signal buffer_locked : std_logic ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
-- need to implement write to the status register somewhere
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
-- need to implement read of the status register somewhere
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0';
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
buffer_locked <= read_ack ;
wbs_readdata <= buffer_read_data ;
-- ram being used to implement the double buffer memory
ram0 : dpram_NxN
generic map(SIZE => (buffer_size*2), NBIT => wb_data_width, ADDR_WIDTH=> 13) -- need to be computed
port map(
clk => gls_clk,
we => write_buffer ,
di => buffer_input,
a => write_address ,
dpra => read_address,
spo => open,
dpo => buffer_read_data
);
-- highest bit select buffer to write to
write_address(write_address'high) <= buffer_use(1) ;
write_address(write_address'high-1 downto 0) <= buffer_address(write_address'high-1 downto 0);
read_address(read_address'high) <= buffer_use(0) ;
read_address(read_address'high-1 downto 0) <= wbs_address(read_address'high-1 downto 0);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
buffer_use <= "01" ;
elsif gls_clk'event and gls_clk = '1' then
if free_buffer = '1' and buffer_locked = '0' then -- if write and one buffer at least is available
buffer_use <= not buffer_use ;
end if ;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 | a3be033632759798e5912d8635e4b006 | 0.626667 | 3.472669 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/or_bits.vhd | 3 | 11,965 | -------------------------------------------------------------------------------
-- $Id: or_bits.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- or_bits.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_bits.vhd
-- Version: v1.02e
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- OPB_ARB_PKG contains the pad_power2 function
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-- UNISIM library contains Xilinx primitives
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
-- C_START_BIT -- starting bit location of bits to OR
-- C_BUS_SIZE -- total size of the bus
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- input Sig -- another signal not in the bus to be ORd with the
-- -- bus section
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity or_bits is
generic (
C_NUM_BITS : integer := 8;
C_START_BIT : integer := 0;
C_BUS_SIZE : integer := 8);
port (
In_bus : in std_logic_vector(0 to C_BUS_SIZE-1);
Sig : in std_logic;
Or_out : out std_logic
);
end or_bits;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of or_bits is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := pad_4(C_NUM_BITS);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If the number of bits to OR is 4 or less (including Sig), a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 4 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= Sig or In_bus(C_START_BIT);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(C_START_BIT + i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more (including Sig), then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 4 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(C_START_BIT to C_START_BIT+C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
--CI => '0' , --[in]
CI => Sig , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| bsd-3-clause | db03a492b29e8f0b86f02867972d4250 | 0.40585 | 4.950352 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_scheduler_v1_00_a/hdl/vhdl/axi_scheduler.vhd | 2 | 28,962 | ------------------------------------------------------------------------------
-- axi_scheduler.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_scheduler.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Jun 26 14:24:54 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_lite_v1_00_a;
use axi_master_lite_v1_00_a.axi_master_lite;
library axi_scheduler_v1_00_a;
use axi_scheduler_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_LITE_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_LITE_DATA_WIDTH -- Master-Intf data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_lite_aclk -- AXI4LITE master: Clock
-- m_axi_lite_aresetn -- AXI4LITE master: Reset
-- md_error -- AXI4LITE master: Error
-- m_axi_lite_arready -- AXI4LITE master: Read address ready
-- m_axi_lite_arvalid -- AXI4LITE master: read address valid
-- m_axi_lite_araddr -- AXI4LITE master: read address protection
-- m_axi_lite_arprot -- AXI4LITE master: Read address protection
-- m_axi_lite_rready -- AXI4LITE master: Read data ready
-- m_axi_lite_rvalid -- AXI4LITE master: Read data valid
-- m_axi_lite_rdata -- AXI4LITE master: Read data
-- m_axi_lite_rresp -- AXI4LITE master: read data response
-- m_axi_lite_awready -- AXI4LITE master: write address ready
-- m_axi_lite_awvalid -- AXI4LITE master: write address valid
-- m_axi_lite_awaddr -- AXI4LITE master: write address valid
-- m_axi_lite_awprot -- AXI4LITE master: write address protection
-- m_axi_lite_wready -- AXI4LITE master: write data ready
-- m_axi_lite_wvalid -- AXI4LITE master: write data valid
-- m_axi_lite_wdata -- AXI4LITE master: write data
-- m_axi_lite_wstrb -- AXI4LITE master: write data strobe
-- m_axi_lite_bready -- AXI4LITE master: read response ready
-- m_axi_lite_bvalid -- AXI4LITE master: read response valid
-- m_axi_lite_bresp -- AXI4LITE master: read response
------------------------------------------------------------------------------
entity axi_scheduler is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"00FFFFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_M_AXI_LITE_ADDR_WIDTH : integer := 32;
C_M_AXI_LITE_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_lite_aclk : in std_logic;
m_axi_lite_aresetn : in std_logic;
md_error : out std_logic;
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_araddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_arprot : out std_logic_vector(2 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_rdata : in std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_rresp : in std_logic_vector(1 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_awprot : out std_logic_vector(2 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
m_axi_lite_wdata : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_wstrb : out std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
m_axi_lite_bready : out std_logic;
m_axi_lite_bvalid : in std_logic;
m_axi_lite_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_lite_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_lite_aresetn : signal is "10000";
attribute SIGIS of m_axi_lite_aclk : signal is "Clk";
attribute SIGIS of m_axi_lite_aresetn : signal is "Rst";
end entity axi_scheduler;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_scheduler is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector(0 to 31) := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector(0 to 31) := C_BASEADDR or X"000000FF";
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
);
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
-- 1 => (USER_MST_NUM_REG) -- number of ce for user logic master space
);
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_M_AXI_LITE_ADDR_WIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_M_AXI_LITE_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1);
signal ipif_ip2bus_mst_be : std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate axi_master_lite
------------------------------------------
AXI_MASTER_LITE_I : entity axi_master_lite_v1_00_a.axi_master_lite
generic map
(
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_lite_aclk => m_axi_lite_aclk,
m_axi_lite_aresetn => m_axi_lite_aresetn,
md_error => md_error,
m_axi_lite_arready => m_axi_lite_arready,
m_axi_lite_arvalid => m_axi_lite_arvalid,
m_axi_lite_araddr => m_axi_lite_araddr,
m_axi_lite_arprot => m_axi_lite_arprot,
m_axi_lite_rready => m_axi_lite_rready,
m_axi_lite_rvalid => m_axi_lite_rvalid,
m_axi_lite_rdata => m_axi_lite_rdata,
m_axi_lite_rresp => m_axi_lite_rresp,
m_axi_lite_awready => m_axi_lite_awready,
m_axi_lite_awvalid => m_axi_lite_awvalid,
m_axi_lite_awaddr => m_axi_lite_awaddr,
m_axi_lite_awprot => m_axi_lite_awprot,
m_axi_lite_wready => m_axi_lite_wready,
m_axi_lite_wvalid => m_axi_lite_wvalid,
m_axi_lite_wdata => m_axi_lite_wdata,
m_axi_lite_wstrb => m_axi_lite_wstrb,
m_axi_lite_bready => m_axi_lite_bready,
m_axi_lite_bvalid => m_axi_lite_bvalid,
m_axi_lite_bresp => m_axi_lite_bresp,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_scheduler_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
Soft_Stop => Soft_Stop ,
SWTM_DOB => SWTM_DOB ,
SWTM_ADDRB => SWTM_ADDRB ,
SWTM_DIB => SWTM_DIB ,
SWTM_ENB => SWTM_ENB ,
SWTM_WEB => SWTM_WEB ,
TM2SCH_current_cpu_tid => TM2SCH_current_cpu_tid ,
TM2SCH_opcode => TM2SCH_opcode ,
TM2SCH_data => TM2SCH_data ,
TM2SCH_request => TM2SCH_request ,
SCH2TM_busy => SCH2TM_busy ,
SCH2TM_data => SCH2TM_data ,
SCH2TM_next_cpu_tid => SCH2TM_next_cpu_tid ,
SCH2TM_next_tid_valid => SCH2TM_next_tid_valid ,
Preemption_Interrupt => Preemption_Interrupt ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_WrCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
-- user_Bus2IP_RdCE(USER_NUM_REG-1 downto USER_NUM_REG-USER_MST_NUM_REG) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
-- user_Bus2IP_WrCE(USER_NUM_REG-1 downto USER_NUM_REG- USER_MST_NUM_REG) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
| bsd-3-clause | e17fa6986a0d943e6606b259dee671a8 | 0.49009 | 3.727893 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_wait_3.vhd | 2 | 20,487 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_wait_2.c
-- reg2 = * mutex
-- reg3 = * cond
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
-- hthread_mutex_lock( data->mutex );
when STATE_4 =>
reg6_next <= intrfc2thrd_value;
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread, NULL, data->function, (void *) data );
when STATE_6 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- retVal = hthread_cond_wait( data->cond, data->mutex );
when STATE_11 =>
-- Puth data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- Puth data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_cond_wait
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_14 =>
retVal_next <= intrfc2thrd_value;
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_16;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_16 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
when STATE_20 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 1d0d724083d45ce4e3e18bfe36275a30 | 0.545029 | 3.724232 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmProgRom.vhd | 1 | 1,452 | ---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmProgRom
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity zcpsmProgRom is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 )
);
end zcpsmProgRom;
architecture syn of zcpsmProgRom is
type RamType is array( 0 to (2**AWIDTH-1) ) of bit_vector( 17 downto 0 );
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile(PROG);
begin
process (clk)
begin
if clk'event and clk = '1' then
dout <= to_stdlogicvector(RAM(conv_integer(addr)));
end if;
end process;
end syn;
| gpl-2.0 | 4e899d275143d0917d9f8979aa0d65e2 | 0.508264 | 4.022161 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/counter.vhd | 2 | 9,045 | -------------------------------------------------------------------------------
-- Counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter.vhd
--
-- Description: Implements a parameterizable N-bit counter
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- 1 - LUT per bit plus 3 LUTS for extra features
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter.vhd
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- KC 2002-01-23 First Version
-- LCW 2004-10-08 Updated for NCSim
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity Counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of Counter is
signal alu_cy : std_logic_vector(C_NUM_BITS downto 0);
signal iCount_Out : std_logic_vector(C_NUM_BITS - 1 downto 0);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(0) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for I in 0 to (C_NUM_BITS - 1) generate
begin
Counter_Bit_I : entity proc_common_v3_00_a.counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(I), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(I), -- [out]
Carry_Out => alu_cy(I+1) -- [out]
);
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(C_NUM_BITS) xor Count_Down;
CARRY_OUT_I: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture imp;
| bsd-3-clause | f5ab6c4afd77c12b1eb9eafd775e158d | 0.399226 | 5.264843 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/dma_sg_sim.vhd | 2 | 137,995 | -------------------------------------------------------------------------------
-- $Id: dma_sg_sim.vhd,v 1.3 2003/03/12 01:04:29 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg sim architecture (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_sim.vhd
--
-- Description: See file dma_sg.vhd for a description of this function.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg_sim.vhd
-- |
-- |- dma_sg.vhd
-- |
-- |- dma_sg_pkg.vhd
-- |
-- |- dma_sg_cmp.vhd
-- |
-- |- ctrl_reg.vhd
-- |
-- |- ld_arith_reg.vhd
-- |
-- |- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- FLO 07/17/02
-- ^^^^^^
-- Workaround for XST F.23 bug that affects dma_sg,
-- e.g. "XGR_tmp <= dma_cs(cco)"
-- ~~~~~~
--
-- FLO 10/22/02
-- ^^^^^^
-- Put a generate statement around the clock divider so that it
-- is included only if there is a packet channel with interrupt
-- coalescing enabled.
-- ~~~~~~
--
-- FLO 01/10/03
-- ^^^^^^
-- Removed earlier XST workaround restriction that status fifo
-- entries for packet channels had to be on either channel 0 or 1.
--
-- FLO 01/30/03
-- ^^^^^^
-- Added constant DMA_DWIDTH = 32, then made values that depend on the
-- fact that DMASG is a 32-bit device to depend on this constant. Most
-- of these were previously depending on C_OPB_DWIDTH. But, we want to
-- be able to have C_OPB_DWIDTH be 64 bits so that DMA data transfers
-- and bursts work on 64-bit buses such as the PLB.
--
-- Added constant BPBT_BITS and eliminated some places where BPST was
-- assumed to be 4 and BPBT was assumed to be 32.
-- ~~~~~~
--
-- FLO 01/31/03
-- ^^^^^^
-- Changed the Generation of DMA2Bus_MstBE so that it handles both
-- 32-bit (DMA_DWIDTH) master operations that it performs relative
-- to its own registers and DMA operations at the full Bus width, i.e.,
-- the width given by C_OPB_AWIDTH.
--
-- Added assertions to check the validity of some of the assumptions
-- upon which the implementation depends.
-- ~~~~~~
--
-- FLO 02/01/03
-- ^^^^^^
-- Fixed generation of dma2bus_addr_sg and dma2ip_addr_sg, which were using
-- BPST_BITS as a way of getting a constant 2. This constant is 2 only if
-- C_OPB_DWIDTH is 32, so the problem appeared with the first attempt
-- to use C_OPB_DWIDTH=64.
-- ~~~~~~
--
-- FLO 02/02/03
-- ^^^^^^
-- Correction to generation of DMA2Bus_MstBE.
-- More corrections of BPST_BITS being used where 2 should have been used.
-- ~~~~~~
--
-- FLO 02/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 03/03/11
-- ^^^^^^
-- Changed constant DMA_TO_OPB_DWIDTH_FACTOR_BITS from type positive to natural.
-- This was needed to have the C_OPB_DWIDTH = 32 case elaborate properly
-- since the value of this constant is zero for this case.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--ToDo (x = done)
-- x(1) implement the software, per-channel reset.
-- x(2) implement the MIR.
-- x(3) put the right constant in the MIR.
-- (4) Implement the Freeze behavior.
-- x(5) Reverse the ISR bits so that they are on low-order bits.
-- x(6) Implement SGDA and SGEND.
-- x(7) Generate the clear of the bda_written bit when the
-- sgGo=0 condition is interpreted.
-- x(8) Interrupt coalescing, UPC, PCT, PWB and interrupts.
-- x(9) Make SG stop on packet boundaries (including all SR values
-- for started packets being written).
-- x(10) For SG Rx packet, make writing the SR the last activity
-- to complete a packet.
-- (11) Error conditions to detect:
-- (a) SGS=1 but not at end of Tx packet.
-- (b) SGS=1 but not enough buffer space to finish current Rx packet.
-- (c) Underflow or overflow of UPC.
-- (d) Exactly one of SLOCAL, DLOCAL set.
-- (e) Status value becomes available from the IP but there
-- is not a corresponding address saved in the SRAddr FIFO to
-- which to write it.
-- x(12) Implement the PD interrupt.
-- (13) Change pwb_clk so that the first pulse is a period, not
-- a half period, after reset.
-- x(14) num_stages parameterization working with synplify.
-- x(15) Remove the logic that assures that a write to a DMA register is
-- complete before going on after the "LastAck" signal changes to
-- imply this.
-- x(16) Add the SG_BSY status bit to the DMASR at bit 4 and rename
-- BSY (DMASR(0)) to DMA_BSY.
-- x(17) For SG packet tx channels, make DMASR.L a copy of DMACR.L. (Rick
-- Moleres)
-- x(18) Convert PLENGTH to structural.
-- x(19) Convert LENGTH to structural.
-- x(20) Convert SA to structural.
-- x(21) Convert DA to structural.
-- (22) Convert UPC to structural? (appears to be inferring okay)
-- (23) Convert pw_timer to structural?
-- x(24) Handle the case where a Bus2IP_MstRetry is the response to
-- a master operation (DMA and SG not yet covered).
-- (25) Handle the case where a Bus2IP_MstError or Bus2IP_MstTimeout
-- is the response to a master operation (SG not yet covered).
-- x(26) Option to have a synchronous divider for the packet-wait-count
-- time base. (Used to investigate the possibility that the
-- ripple divider was causing clock buffers to be inserted
-- because tools may have been using global buffers for the divider
-- Q-to-Clk signals. The investigation found no such correlation.)
-- (27) Check that UPC, PCT, PWB are excluded when channel is not
-- type 2 or 3 or interrupt coalescing is disabled for the channel.
--
--ToDo. Conditions regarding SG operation.
-- x (a) Go to the next BD if not SGS and (SGE or (not first and
-- "pkt style"))
-- x (b) sg_active asserts when not SGS and SGE and maintains until
-- (SGS or not SGE)
-- and idle
-- and (not "pkt style" or (not SRAddrFIFO_nonempty and first))
-- x (c) Signal SGEND and SGDA interrupts on change from sg_active to
-- not sg_active.
--
-- x (1) Introduce the is_idle signal for when dma_sm is waiting to start
-- processing the next BD or to start a simple DMA operation.
-- x (2) Consider renaming BSY(i) to dma_active(i) and assigning to BSY(i) on
-- register readout.
-- x (3) See if sg_busy can be eliminated as a separate signal.
library ieee;
use ieee.numeric_std.all;
-- VisualHDL gives compile errors when using the explicitly named
-- use clauses, below.
--use ieee.numeric_std.UNSIGNED;
--use ieee.numeric_std.TO_UNSIGNED
--use ieee.numeric_std.TO_INTEGER;
--use ieee.numeric_std."=";
--use ieee.numeric_std."+";
--use ieee.numeric_std."-";
--use ieee.numeric_std."<";
--use ieee.numeric_std.RESIZE;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.dma_sg_cmp.all;
use ipif_common_v1_00_c.dma_sg_pkg.ceil_log2;
use ipif_common_v1_00_c.dma_sg_pkg.r_RSTMIR;
use ipif_common_v1_00_c.dma_sg_pkg.r_DMACR;
use ipif_common_v1_00_c.dma_sg_pkg.r_SA;
use ipif_common_v1_00_c.dma_sg_pkg.r_DA;
use ipif_common_v1_00_c.dma_sg_pkg.r_LENGTH;
use ipif_common_v1_00_c.dma_sg_pkg.r_DMASR;
use ipif_common_v1_00_c.dma_sg_pkg.r_BDA;
use ipif_common_v1_00_c.dma_sg_pkg.r_SWCR;
use ipif_common_v1_00_c.dma_sg_pkg.r_UPC;
use ipif_common_v1_00_c.dma_sg_pkg.r_PCT;
use ipif_common_v1_00_c.dma_sg_pkg.r_PWB;
use ipif_common_v1_00_c.dma_sg_pkg.r_ISR;
use ipif_common_v1_00_c.dma_sg_pkg.r_IER;
use ipif_common_v1_00_c.dma_sg_pkg.r_PLENGTH;
use ipif_common_v1_00_c.dma_sg_pkg.b_BSY;
use ipif_common_v1_00_c.dma_sg_pkg.b_SINC;
use ipif_common_v1_00_c.dma_sg_pkg.b_DINC;
use ipif_common_v1_00_c.dma_sg_pkg.b_SLOCAL;
use ipif_common_v1_00_c.dma_sg_pkg.b_DLOCAL;
use ipif_common_v1_00_c.dma_sg_pkg.b_SGS;
use ipif_common_v1_00_c.dma_sg_pkg.b_L_dmacr;
use ipif_common_v1_00_c.dma_sg_pkg.b_SGE;
use ipif_common_v1_00_c.dma_sg_pkg.b_DD;
use ipif_common_v1_00_c.dma_sg_pkg.b_DE;
use ipif_common_v1_00_c.dma_sg_pkg.b_PD;
use ipif_common_v1_00_c.dma_sg_pkg.b_PCTR;
use ipif_common_v1_00_c.dma_sg_pkg.b_PWBR;
use ipif_common_v1_00_c.dma_sg_pkg.b_SGDA;
use ipif_common_v1_00_c.dma_sg_pkg.b_SGEND;
use ipif_common_v1_00_c.dma_sg_pkg.bo2sl;
use ipif_common_v1_00_c.dma_sg_pkg.Div_Stages;
use ipif_common_v1_00_c.dma_sg_pkg.UPCB;
use ipif_common_v1_00_c.dma_sg_pkg.PWBB;
library proc_common_v1_00_b;
architecture sim of dma_sg is
constant RESET_ACTIVE : std_logic := '1';
constant C_M : natural := C_IPIF_ABUS_WIDTH - 2;
-- Bus2IP_Addr and DMA2IP_Addr are word addresses;
-- the low-order two bits of the byte address
-- are not included.
-- ToDo, eventually, this should probably change so that
-- they are byte addresses.
constant MAJOR_VERSION : natural := 1;
constant MINOR_VERSION : natural := 1;
constant HW_SW_COMPATIBILITY_REVISION : natural := 0;
constant LAST_CHAN : natural := C_DMA_CHAN_TYPE'length - 1;
constant NUM_CHANS : natural := LAST_CHAN+1;
constant NUM_CHAN_BITS : natural := ceil_log2(NUM_CHANS);
-- There are NUM_CHANS channels, numbered 0 .. LAST_CHAN.
constant RPB : natural := 4; -- Register-pitch bits = the number of bits
-- needed to encode the word addresses
-- of all registers (and reserved register
-- addresses) for a channel. The number
-- of registers and reserved addresses
-- per channel is 2^RPB, so the
-- word address of a register on one channel
-- is separated from the word address of
-- of the same register on the next higher
-- channel by 2^RPB.
constant BPST : natural := C_OPB_DWIDTH / 8;
-- Bytes per single transfer on the bus.
constant BPST_BITS : natural := ceil_log2(BPST);
-- Number of bits needed to encode
-- the range 0 to BPST-1.
constant TPB : natural := 8; -- Transfers per burst (burst length).
-- Make this a power of two or, ToDo,
-- make sure it works for a non p-of-2.
constant BPBT : natural := BPST * TPB;
-- Bytes per burst transfer on the bus.
constant BPBT_BITS : natural := ceil_log2(BPBT);
constant RIPPLE_PW_DIVIDER : boolean := true;
constant DMA_DWIDTH : natural := 32; -- DMASG is a 32-bit device.
-- Registers
type DMACR_t
is array (natural range <>) of std_logic_vector(b_SINC to
b_L_dmacr);
signal tmp_C_DMA_BASEADDR : std_logic_vector(0 to 63);
-- XST workaround
signal DMACR : DMACR_t(0 to LAST_CHAN);
type UNSIGNED_t
is array (natural range <>) of UNSIGNED(0 to DMA_DWIDTH-1);
signal SA : UNSIGNED_t(0 to LAST_CHAN);
signal DA : UNSIGNED_t(0 to LAST_CHAN);
signal LENGTH : UNSIGNED_t(0 to LAST_CHAN);
signal BDA : UNSIGNED_t(0 to LAST_CHAN);
-- XGR_E33 type SWCR_t
-- XGR_E33 is array (natural range <>) of std_logic_vector(b_SGE to b_SGE);
-- XGR_E33 signal SWCR : SWCR_t(0 to LAST_CHAN);
signal SWCR : std_logic_vector(0 to LAST_CHAN);
type UPC_t
is array (natural range <>) of UNSIGNED(DMA_DWIDTH-UPCB to
DMA_DWIDTH-1);
signal UPC : UPC_t(0 to LAST_CHAN);
signal PCT : UPC_t(0 to LAST_CHAN);
type PWB_t
is array (natural range <>) of UNSIGNED(DMA_DWIDTH-PWBB to
DMA_DWIDTH-1);
signal PWB : PWB_t(0 to LAST_CHAN); -- Packet Wait Bound
signal pw_timer : PWB_t(0 to LAST_CHAN); -- Timer used in generating
-- PWBR interrupt.
signal PLENGTH : UNSIGNED_t(0 to LAST_CHAN);
signal LENGTH_cco : UNSIGNED(0 to DMA_DWIDTH-1);
signal PLENGTH_cco : UNSIGNED(0 to DMA_DWIDTH-1);
-- Per-channel reset
signal reset : std_logic_vector (0 to LAST_CHAN);
signal prog_reset : std_logic_vector (0 to LAST_CHAN);
-- Enables
signal chan_num : natural; -- The channel addressed by Bus2IP_Addr.
signal chan_sel : std_logic_vector (0 to LAST_CHAN);
-- Decode of chan_num to one-hot.
signal cco : natural range 0 to LAST_CHAN;
-- The channel currently operating.
signal cco_onehot : std_logic_vector (0 to LAST_CHAN);
-- cco decoded to onehot.
signal RSTMIR_sel : std_logic;
signal DMACR_sel : std_logic;
signal SA_sel : std_logic;
signal DA_sel : std_logic;
signal LENGTH_sel : std_logic;
signal dmasr_sel : std_logic;
signal BDA_sel : std_logic;
signal SWCR_sel : std_logic;
signal UPC_sel : std_logic;
signal PCT_sel : std_logic;
signal PWB_sel : std_logic;
signal ISR_sel : std_logic;
signal IER_sel : std_logic;
signal PLENGTH_sel : std_logic;
-- Read back register muxing
signal ver_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal dcr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal sa_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal da_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal lnt_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal dsr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal bda_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal sge_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal upc_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal pct_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal pwb_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal isr_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal ier_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal ple_i : std_logic_vector(0 to DMA_DWIDTH-1);
signal adj : UNSIGNED(0 to BPST_BITS); -- Amt to add or subtr when updating
-- LENGTH and PLENGTH.
signal LENGTH_ge_2BPST: std_logic; -- Used in calculating adj.
signal PLENGTH_ge_2BPST: std_logic; -- Used in calculating adj.
signal LENGTH_ge_BPBT : std_logic; -- Used for deciding burst transaction.
signal PLENGTH_ge_BPBT : std_logic; -- Used for deciding burst transaction.
--ToDo. dec_LENGTH, inc_SA and inc_DA can be combined into a common signal.
signal dec_LENGTH : std_logic;
signal inc_SA : std_logic;
signal inc_DA : std_logic;
signal dec_PLENGTH : std_logic;
signal inc_PLENGTH : std_logic;
signal clr_PLENGTH : std_logic;
--Register bits and bit fields
signal SINC : std_logic_vector(0 to LAST_CHAN);
signal DINC : std_logic_vector(0 to LAST_CHAN);
signal SLOCAL : std_logic_vector(0 to LAST_CHAN);
signal DLOCAL : std_logic_vector(0 to LAST_CHAN);
signal SGS : std_logic_vector(0 to LAST_CHAN);
signal L_tx : std_logic_vector(0 to LAST_CHAN);
signal dma_active : std_logic_vector(0 to LAST_CHAN);
signal DBE : std_logic_vector(0 to LAST_CHAN);
signal DBT : std_logic_vector(0 to LAST_CHAN);
signal L_rx : std_logic_vector(0 to LAST_CHAN);
signal L : std_logic_vector(0 to LAST_CHAN);
signal SGE : std_logic_vector(0 to LAST_CHAN);
signal DD : std_logic_vector(0 to LAST_CHAN);
signal DE : std_logic_vector(0 to LAST_CHAN);
signal PD : std_logic_vector(0 to LAST_CHAN);
signal SGDA : std_logic_vector(0 to LAST_CHAN);
signal SGEND : std_logic_vector(0 to LAST_CHAN);
signal PCTR : std_logic_vector(0 to LAST_CHAN);
signal PWBR : std_logic_vector(0 to LAST_CHAN);
signal EDD : std_logic_vector(0 to LAST_CHAN);
signal EDE : std_logic_vector(0 to LAST_CHAN);
signal EPD : std_logic_vector(0 to LAST_CHAN);
signal ESGDA : std_logic_vector(0 to LAST_CHAN);
signal ESGEND : std_logic_vector(0 to LAST_CHAN);
signal EPCTR : std_logic_vector(0 to LAST_CHAN);
signal EPWBR : std_logic_vector(0 to LAST_CHAN);
-- Other signals.
signal sgGo : std_logic_vector(0 to LAST_CHAN);
-- SG is enabled and not at end.
signal dma2bus_wrack_i : std_logic;
signal dma2bus_rdack_i : std_logic;
-- is_idle: The DMA state machine is waiting to start processing the next
-- BD or to start a simple DMA operation.
signal is_idle : std_logic_vector(0 to LAST_CHAN);
-- sg_active: SG has been enabled
-- and started and has not yet reached the point where it is stopped
-- or disabled and has cleanly finished the work that it started
-- while active. Cleanly finishing its work includes, for SG packet
-- Rx and SG packet Tx channels, that all packets that were started
-- have finished and their status is recorded.
signal sg_active : std_logic_vector(0 to LAST_CHAN);
signal sg_active_d1 : std_logic_vector(0 to LAST_CHAN);
signal dma_completing : std_logic;
signal dma_starting : std_logic;
signal set_DBE, set_DBT, set_L_rx : std_logic;
signal rx, tx : std_logic_vector(0 to LAST_CHAN);
-- rx(i) iff channel i is for Rx; tx(i) iff channel i is for Tx
signal dest_is_a_fifo : std_logic; -- The DMA destination for cco is a fifo.
signal dma_sel : std_logic; -- Master transaction is for dma i/o.
signal sg_sel : std_logic; -- Master transaction is for sg BD i/o.
signal pl_sel : std_logic; -- Master transaction is for PLENGTH i/o.
signal sr_sel : std_logic;
signal dma2bus_addr_dma : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal dma2ip_addr_dma : std_logic_vector(0 to C_M-1);
signal dma2bus_mstwrreq_dma : std_logic;
signal dma2bus_mstrdreq_dma : std_logic;
signal dma2bus_mstburst_dma : std_logic;
signal burst_cond_dma : std_logic; -- The condition on which the decision
-- to burst is based.
signal dma2bus_addr_sg : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal dma2ip_addr_sg : std_logic_vector(0 to C_M-1);
signal dma2bus_mstwrreq_sg : std_logic;
signal dma2bus_mstrdreq_sg : std_logic;
signal dma2bus_mstburst_sg : std_logic;
signal dma2bus_mstwrreq_sr : std_logic;
signal dma2bus_mstwrreq_pl : std_logic;
signal first : std_logic_vector(0 to LAST_CHAN);
-- Channel cco is on its first
-- DMA operation of a packet.
signal update_first : std_logic; -- Update first for the cco.
signal no_bda_link : std_logic_vector(0 to LAST_CHAN);
-- The BDA for the corresponding channel has been written while
-- not sg_active and an operation under the next sg_active tenure has not
-- started.
signal load_length : std_logic_vector(0 to LAST_CHAN);
signal load_bda : std_logic_vector(0 to LAST_CHAN);
signal wr_SRAddrFIFO : std_logic_vector(0 to LAST_CHAN);
signal rd_SRAddrFIFO : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_full : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_nonempty : std_logic_vector(0 to LAST_CHAN);
type SRAddrFIFO_out_t
is array (natural range <>) of std_logic_vector(
0 to
C_OPB_AWIDTH-1
);
signal SRAddrFIFO_out : SRAddrFIFO_out_t(0 to LAST_CHAN);
type sg_offset_t
is array (natural range <>) of UNSIGNED(0 to RPB-1);
signal sg_offset : sg_offset_t(0 to LAST_CHAN);
signal reset_sg_offset : std_logic;
signal inc_sg_offset : std_logic_vector(0 to LAST_CHAN);
signal SRAddrFIFO_cco_hasroom : std_logic;
signal DMA2Intr_Intr_i : std_logic_vector(0 to LAST_CHAN);
signal pw_enable_pulse : std_logic;
-- An enable pulse of one Bus2IP_Clk period at the frequency
-- of required PWB update.
signal pwb_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal pw_timer_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal upc_eq_0 : std_logic_vector(0 to LAST_CHAN);
signal pwb_loaded : std_logic_vector(0 to LAST_CHAN);
-- Bitwise "or" of an UNSIGNED value.
function or_UNSIGNED(s: UNSIGNED) return std_logic is
variable result: std_logic := '0';
begin
if s'ascending then
for i in s'left to s'right loop
result := result or s(i);
end loop;
else
for i in s'left downto s'right loop
result := result or s(i);
end loop;
end if;
return result;
end or_UNSIGNED;
-- Find the leftmost bit over the LENGTH registers of all channels.
function min_length_left(nv: INTEGER_ARRAY_TYPE) return natural is
variable largest_width : natural := 0;
begin
for i in 0 to LAST_CHAN loop
if nv(i) > largest_width then largest_width := nv(i); end if;
end loop;
return C_OPB_AWIDTH - largest_width;
end min_length_left;
-- LENGTHS_LEFT gives the minimum left index over all channels.
-- It corresponds to the widest LENGTH register required.
constant LENGTHS_LEFT : natural := min_length_left(C_DMA_LENGTH_WIDTH);
function zero_vector(n: natural) return UNSIGNED is
variable result : UNSIGNED(0 to n-1) := (others => '0');
begin
return result;
end zero_vector;
function clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE: INTEGER_ARRAY_TYPE)
return boolean is
begin
for i in C_DMA_CHAN_TYPE'range loop
if (C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3)
and C_INTR_COALESCE(i) = 1 then
return true;
end if;
end loop;
return false;
end clock_divider_needed;
function to_string(n: natural) return STRING is
variable s : string(20 downto 1);
variable j : natural := 1;
variable m : natural := n;
type decimal_digit_to_char is array (natural range 0 to 9) of character;
constant tab : decimal_digit_to_char :=
('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
begin
loop
s(j) := tab(m mod 10);
m := m / 10;
exit when m = 0;
j := j+1;
end loop;
return s(j downto 1);
end to_string;
function is_power_of_2(n: positive) return boolean is
begin
if n = 1 then return true;
elsif n mod 2 = 1 then return false;
else return is_power_of_2(n/2);
end if;
end is_power_of_2;
begin --( architecture
----------------------------------------------------------------------------
-- Checks on parameters and interface signals.
----------------------------------------------------------------------------
assert Bus2IP_Data'length = DMA_DWIDTH
report "Bus2IP_Data is a vector of size " &
to_string(Bus2IP_Data'length) &
", which is not equal, as required, to " &
to_string(DMA_DWIDTH) & "."
severity failure;
--
--ToDo, Add checks for C_OPB_DWIDTH and DMA_DWIDTH a power of two in bytes.
-- When asserts, below, have been proven, remove this ToDo comment.
assert is_power_of_2(C_OPB_DWIDTH)
report "C_OPB_DWIDTH is " &
to_string(C_OPB_DWIDTH) &
", which is not a power of two, as required."
severity failure;
assert is_power_of_2(DMA_DWIDTH)
report "DMA_DWIDTH is " &
to_string(DMA_DWIDTH) &
", which is not a power of two, as required."
severity failure;
--
--ToDo, Add check that TPB is a power of two...or study and remove
-- any implementation features that require TBP and BPBT to be
-- a power of two.
-- When assert, below, has been proven, remove this ToDo comment
-- but leave note that allowing TBP to be non power of two is
-- possible if the implementation is adjusted.
assert is_power_of_2(TPB)
report "TPB is " &
to_string(TPB) &
", which is not a power of two, as required."
severity failure;
--
--ToDo, add check that C_OPB_DWIDTH >= DMA_DWIDTH;
tmp_C_DMA_BASEADDR <= C_DMA_BASEADDR; -- ToDo, XST workaround
--ToDo, handle byte enable signals (probably return error on non BE=1111)
-- Assignment of register bits and bit fields
SINC_GENERATE: for i in 0 to LAST_CHAN generate
SINC(i) <= DMACR(i)(0);
end generate;
DINC_GENERATE: for i in 0 to LAST_CHAN generate
DINC(i) <= DMACR(i)(1);
end generate;
SLOCAL_GENERATE: for i in 0 to LAST_CHAN generate
SLOCAL(i) <= DMACR(i)(2);
end generate;
DLOCAL_GENERATE: for i in 0 to LAST_CHAN generate
DLOCAL(i) <= DMACR(i)(3);
end generate;
SGS_GENERATE: for i in 0 to LAST_CHAN generate
--ToDo. Check that DMACR(i)(4) gets optimized away by synthesis for
-- C_DMA_CHAN_TYPE(i) = 0.
SGS(i) <= '1' when C_DMA_CHAN_TYPE(i) = 0 else
DMACR(i)(4);
end generate;
SGE_GENERATE: for i in 0 to LAST_CHAN generate
--ToDo. Check that SWCR(i)(0) gets optimized away by synthesis for
-- C_DMA_CHAN_TYPE(i) = 0.
-- XGR_E33 SGE(i) <= '0' when C_DMA_CHAN_TYPE(i) = 0 else
-- XGR_E33 SWCR(i)(0);
SGE(i) <= '0' when C_DMA_CHAN_TYPE(i) = 0 else
SWCR(i);
end generate;
SGGO_GENERATE: for i in 0 to LAST_CHAN generate
sgGo(i) <= (not SGS(i) and SGE(i))
or -- If pkt SG, then get to a packet boundary.
( not first(i)
and bo2sl( C_DMA_CHAN_TYPE(i) = 2
or C_DMA_CHAN_TYPE(i) = 3
)
);
end generate;
L_TX_GEN: for i in 0 to LAST_CHAN generate
L_tx(i) <= '0' when (C_DMA_CHAN_TYPE(i) /= 2) else DMACR(i)(b_L_dmacr);
end generate;
--- Address decoding
-- channel selects
chan_num <= TO_INTEGER(UNSIGNED(Bus2IP_Addr( C_M-RPB-NUM_CHAN_BITS
to C_M-RPB-1 )));
CHAN_SELECTION: process (chan_num)
begin
for i in 0 to LAST_CHAN loop
chan_sel(i) <= bo2sl(chan_num = i);
end loop;
end process;
CCO_ONEHOT_PROCESS: process (cco)
begin
for i in 0 to LAST_CHAN loop
cco_onehot(i) <= bo2sl(cco = i);
end loop;
end process;
RX_GEN: for i in 0 to LAST_CHAN generate
rx(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 3) and (sgGo(i) or sg_active(i));
-- A sg rx packet channel can be used for simple DMA when it is not
-- operating under SG.
end generate;
dest_is_a_fifo <= bo2sl( C_DMA_CHAN_TYPE(cco) = 2 -- ToDo. Might want to
and sg_active(cco) = '1'); -- consider how this info
-- is gotten. Perhaps it
-- should be a dmacr bit
-- or if not, perhaps the
-- DA should be
-- read-only. hmmmn.
TX_GEN: for i in 0 to LAST_CHAN generate
tx(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 2) and (sgGo(i) or sg_active(i));
-- A sg tx packet channel can be used for simple DMA when it is not
-- operating under SG.
end generate;
-- register selects
RSTMIR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_RSTMIR, RPB)));
DMACR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DMACR, RPB)));
SA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_SA, RPB)));
DA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DA, RPB)));
LENGTH_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_LENGTH, RPB)));
DMASR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_DMASR, RPB)));
BDA_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_BDA, RPB)));
SWCR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_SWCR, RPB)));
UPC_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_UPC, RPB)));
PCT_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PCT, RPB)));
PWB_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PWB, RPB)));
ISR_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_ISR, RPB)));
IER_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_IER, RPB)));
PLENGTH_sel <= bo2sl(Bus2IP_Addr(C_M-RPB to C_M-1) =
std_logic_vector(TO_UNSIGNED(r_PLENGTH, RPB)));
--= end, Address decoding
--- Various logic
----------------------------------------------------------------------------
-- These statements calculate adj.
-- Either LENGTH or PLENGTH is the evaluated value, depending on whether the
-- channel is rx. If the evaluated value is >= BPST, adj is BPST, which
-- means that the low-order two bits may need to be masked. Otherwise,
-- adj is the two low-order bits of the evaluated value.
----------------------------------------------------------------------------
LENGTH_ge_BPBT<= or_UNSIGNED( LENGTH_cco(LENGTHS_LEFT to
DMA_DWIDTH - BPBT_BITS - 1));
PLENGTH_ge_BPBT<= or_UNSIGNED(PLENGTH_cco(LENGTHS_LEFT to
DMA_DWIDTH - BPBT_BITS - 1));
LENGTH_ge_2BPST <= LENGTH_ge_BPBT or
or_UNSIGNED( LENGTH_cco(DMA_DWIDTH - BPBT_BITS to
DMA_DWIDTH - BPST_BITS - 2));
PLENGTH_ge_2BPST <= PLENGTH_ge_BPBT or
or_UNSIGNED(PLENGTH_cco(DMA_DWIDTH - BPBT_BITS to
DMA_DWIDTH - BPST_BITS - 2));
----------------------------------------------------------------------------
-- The next process maintains the global adj value with
-- respect to the cco.
-- Notes:
-- (1) Whenever adj is to be used to update channel n, cco=n must hold
-- for both the previous and current cycles.
-- (2) adj is sourced from FFs to reduce path time.
-- (3) When dec_length is true, we are looking ahead by
-- an extra BPST, which is the reason for the >= 2*BPST check
-- instead of a >= BPST check.
-- (4) It is required that BPST be a power of 2.
----------------------------------------------------------------------------
ADJ_PROCESS: process (Bus2IP_Clk)
variable len : UNSIGNED(0 to LENGTH_cco'length-1);
variable len_ge_2BPST : std_logic;
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if rx(cco)='0' then
len := LENGTH_cco;
len_ge_2BPST := LENGTH_ge_2BPST;
else
len := PLENGTH_cco;
len_ge_2BPST := PLENGTH_ge_2BPST;
end if;
adj(0) <= len_ge_2BPST
or (not dec_length and len( DMA_DWIDTH
- BPST_BITS
- 1)
);
for i in 1 to BPST_BITS LOOP
-- The following expression zeroes non high-order adj bits
-- when the next transfer will be BPST, otherwise
-- adj becomes what is left to transfer, i.e. the corresponding
-- adj bit is taken from the corresponding len bit.
adj(i) <= not( len_ge_2BPST
or (not dec_length and len( DMA_DWIDTH
- BPST_BITS
- 1)
)
)
and len(DMA_DWIDTH - BPST_BITS + i - 1);
end loop;
end if;
end process;
DMA2Bus_Error <= '0';
DMA2Bus_Retry <= '0';
Bus2IP_DMA_Ack <= '0';
DMA2Bus_ToutSup <= '0';
DMA2INTR_GENERATE: for i in 0 to LAST_CHAN generate
DMA2Intr_Intr_i(i) <= (DD(i) and EDD(i))
or (DE(i) and EDE(i))
or (PD(i) and EPD(i))
or (PCTR(i) and EPCTR(i))
or (PWBR(i) and EPWBR(i))
or (SGDA(i) and ESGDA(i))
or (SGEND(i) and ESGEND(i));
DMA2Intr_Intr(i) <= DMA2Intr_Intr_i(i);
end generate;
L_GEN: for i in 0 to LAST_CHAN generate
L(i) <= ( (tx(i) and L_tx(i))
or (rx(i) and L_rx(i))
);
end generate;
FIRST_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if reset(i) = '1' then
first(i) <= bo2sl(C_DMA_CHAN_TYPE(i) = 2 or
C_DMA_CHAN_TYPE(i) = 3);
elsif update_first = '1' and cco = i then
first(i) <= L(i);
end if;
end loop;
end if;
end process;
SG_OFFSET_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if (reset(i) or (reset_sg_offset and cco_onehot(i))) = '1' then
sg_offset(i) <= (others => '0');
elsif inc_sg_offset(i) = '1' then
sg_offset(i) <= sg_offset(i) + 1;
end if;
end loop;
end if;
end process;
SRAddrFIFO_cco_hasroom <= '1' when (C_DMA_CHAN_TYPE(cco) = 2 or
C_DMA_CHAN_TYPE(cco) = 3)
and SRAddrFIFO_full(cco) = '0'
else '0';
--= end, Various logic
--- Clock divider.
INCLUDE_CLOCK_DIVIDER: if clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE) generate
constant num_stages : natural
:= Div_Stages(base_period => C_CLK_PERIOD_PS,
target_period=> C_PACKET_WAIT_UNIT_NS
* 1000
);
begin
--------------------------------------------------------------------------
-- This option implements the packet-wait timebase divider using a
-- Q-to-Clk ripple counter.
--------------------------------------------------------------------------
GEN_RIPPLE_PW_DIVIDER: if RIPPLE_PW_DIVIDER generate
signal divby2to : std_logic_vector(0 to num_stages);
signal ripout, ripout_d1, ripout_d2, ripout_d3 : std_logic;
begin
divby2to(0) <= Bus2IP_Clk;
ripout <= divby2to(num_stages);
------------------------------------------------------------------------
-- Clock division via a ripple counter.
------------------------------------------------------------------------
DIVIDE_CLK: for i in 1 to num_stages generate
DIV_FF: process(divby2to(i-1), Bus2IP_Reset)
begin
if Bus2IP_Reset = RESET_ACTIVE then
divby2to(i) <= '0';
else
if divby2to(i-1)'event and divby2to(i-1) = '1' then
divby2to(i) <= not divby2to(i);
end if;
end if;
end process;
end generate;
------------------------------------------------------------------------
-- This process syncronizes the output of the ripple counter into
-- the Bus2IP_Clk domain and sets up edge detection.
------------------------------------------------------------------------
SYNC_AND_ENABLE: process(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
ripout_d1 <= '0';
ripout_d2 <= '0';
ripout_d3 <= '0';
else
ripout_d1 <= divby2to(num_stages);
ripout_d2 <= ripout_d1;
ripout_d3 <= ripout_d2;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Edge detection gives a one-pulse signal in the Bus2IP_Clk domain.
------------------------------------------------------------------------
pw_enable_pulse <= not ripout_d2 and ripout_d3;
end generate GEN_RIPPLE_PW_DIVIDER;
--------------------------------------------------------------------------
-- This option implements the packet-wait timebase divider using a
-- synchronous counter.
--------------------------------------------------------------------------
GEN_SYNC_PW_DIVIDER: if not RIPPLE_PW_DIVIDER generate
constant ZERO_NUM_STAGES : std_logic_vector(0 to num_stages-1)
:= (others => '0');
signal sdivby2to : std_logic_vector(num_stages downto 1);
signal sdivby2to_num_stages_d1 : std_logic;
begin
SYNC_PW_DIVIDER : PROCESS(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
sdivby2to <= (others => '0');
else
sdivby2to <= std_logic_vector(UNSIGNED(sdivby2to) + 1);
end if;
end if;
end process;
OUPUT_D1: process(Bus2IP_Clk, Bus2IP_Reset)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = RESET_ACTIVE then
sdivby2to_num_stages_d1 <= '0';
else
sdivby2to_num_stages_d1 <= sdivby2to(num_stages);
end if;
end if;
end process;
pw_enable_pulse <= not sdivby2to(num_stages)
and sdivby2to_num_stages_d1;
end generate GEN_SYNC_PW_DIVIDER;
end generate INCLUDE_CLOCK_DIVIDER;
EXCLUDE_CLOCK_DIVIDER: if not clock_divider_needed(C_DMA_CHAN_TYPE,
C_INTR_COALESCE) generate
pw_enable_pulse <= '0';
end generate EXCLUDE_CLOCK_DIVIDER;
--= end, Clock divider.
--- Register implementations
---------------------------------------------------------------------
-- These processes generate the DMA2Bus_WrAck.
---------------------------------------------------------------------
DMA2BUS_WRACK_I_PROCESS: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = RESET_ACTIVE) then
dma2bus_wrack_i <= '0';
--ToDo. The last conjunct probably not needed.
elsif ((DMA_WrCE and Bus2IP_WrReq)='1' and dma2bus_wrack_i='0') then
dma2bus_wrack_i <= '1';
else
dma2bus_wrack_i <= '0';
end if;
end if;
end process;
DMA2Bus_WrAck <= dma2bus_wrack_i;
---------------------------------------------------------------------
-- These processes implement the channel reset "register".
---------------------------------------------------------------------
PERP_CHANNEL_RESET_GEN: for i in 0 to LAST_CHAN generate
prog_reset(i) <=
bo2sl( (chan_sel(i) and RSTMIR_sel and dma2bus_wrack_i) = '1'
and (Bus2IP_Data(DMA_DWIDTH-4 to
DMA_DWIDTH-1)) = "1010"
);
reset(i) <= bo2sl(Bus2IP_Reset = RESET_ACTIVE)
or prog_reset(i);
end generate;
---------------------------------------------------------------------
-- This process implements a DMACR register for each channel.
---------------------------------------------------------------------
-- DMACR_REG_PROCESS: process (Bus2IP_Clk)
-- begin
-- for i in 0 to LAST_CHAN loop
-- if Bus2IP_Clk'event and Bus2IP_Clk='1' then
-- if (reset(i) = RESET_ACTIVE) then
-- DMACR(i)(0 to 6) <= "1001000";
-- elsif (chan_sel(i) and DMACR_sel and dma2bus_wrack_i) = '1' then
-- DMACR(i)(0 to 6) <= Bus2IP_Data(0 to 6);
-- end if;
-- end if;
-- end loop;
-- end process;
DMACR_GENERATE: for i in 0 to LAST_CHAN generate
I_DMACR: ctrl_reg_0_to_6
-- I_DMACR: entity ctrl_reg(sim)
generic map ("1001100")
port map (
clk => Bus2IP_Clk,
rst => reset(i),
chan_sel => chan_sel(i),
reg_sel => DMACR_sel,
wr_ce => dma2bus_wrack_i,
d => Bus2IP_Data(b_SINC to b_L_dmacr),
q => DMACR(i)(b_SINC to b_L_dmacr)
);
end generate;
SWCR_GENERATE: for i in 0 to LAST_CHAN generate
I_SWCR: ctrl_reg_0_to_0
generic map ("0")
port map (
clk => Bus2IP_Clk,
rst => reset(i),
chan_sel => chan_sel(i),
reg_sel => SWCR_sel,
wr_ce => dma2bus_wrack_i,
-- XGR_E33 d => Bus2IP_Data(b_SGE to b_SGE),
-- XGR_E33 q => SWCR(i)(b_SGE to b_SGE)
d => Bus2IP_Data(b_SGE),
q => SWCR(i)
);
end generate;
--r ---------------------------------------------------------------------
--r -- This process implements a SA register for each channel.
--r ---------------------------------------------------------------------
--r SA_REG_PROCESS: process (Bus2IP_Clk)
--r begin
--r for i in 0 to LAST_CHAN loop
--r if Bus2IP_Clk'event and Bus2IP_Clk='1' then
--r if (reset(i) = RESET_ACTIVE) then
--r SA(i) <= (others => '0');
--r elsif (cco_onehot(i) and SINC(i) and inc_SA) = '1' then
--r SA(i) <= SA(i) + BPST;
--r elsif (chan_sel(i) and SA_sel and dma2bus_wrack_i) = '1' then
--r SA(i) <= UNSIGNED(Bus2IP_Data);
--r end if;
--r end if;
--r end loop;
--r end process;
---------------------------------------------------------------------
-- The below implements a SA for each channel.
---------------------------------------------------------------------
SA_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(SA(i)'range);
begin
--
RST_EF <= reset(i);
LOAD_EF <= (chan_sel(i) and SA_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and SINC(i) and inc_SA);
--
I_SA : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => true,
C_REG_WIDTH => SA(i)'length,
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => SA(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => BPST_BITS
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(SA(i)'range),
LD => Bus2IP_Data(0 to DMA_DWIDTH-1),
AD => "1",
LOAD => LOAD_EF,
OP => OP_EF
);
--
SA(i)(SA(i)'range) <=
UNSIGNED(qslv(SA(i)'range));
end generate;
end generate;
---------------------------------------------------------------------
-- The below implements a DA for each channel.
---------------------------------------------------------------------
DA_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(DA(i)'range);
begin
--
RST_EF <= reset(i);
LOAD_EF <= (chan_sel(i) and DA_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and DINC(i) and inc_DA);
--
I_DA : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => true,
C_REG_WIDTH => DA(i)'length,
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => DA(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => BPST_BITS
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DA(i)'range),
LD => Bus2IP_Data(0 to DMA_DWIDTH-1),
AD => "1",
LOAD => LOAD_EF,
OP => OP_EF
);
--
DA(i)(DA(i)'range) <=
UNSIGNED(qslv(DA(i)'range));
end generate;
end generate;
LOAD_LENGTH_GENERATE: for i in 0 to LAST_CHAN generate
load_length(i) <= chan_sel(i) and LENGTH_sel and dma2bus_wrack_i;
end generate;
LOAD_BDA_GENERATE: for i in 0 to LAST_CHAN generate
load_bda(i) <= chan_sel(i) and BDA_sel and dma2bus_wrack_i;
end generate;
---------------------------------------------------------------------
-- The below implements a LENGTH register of the correct size for
-- each channel.
---------------------------------------------------------------------
LENGTH_REG_GEN: for i in 0 to LAST_CHAN generate
T_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 or
C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3
generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(0 to DMA_DWIDTH-1);
begin
--
RST_EF <= reset(i) or ((cco_onehot(i) and clr_PLENGTH));
LOAD_EF <= (chan_sel(i) and LENGTH_sel and dma2bus_wrack_i);
OP_EF <= (cco_onehot(i) and dec_LENGTH);
--
I_LENGTH : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_LD_OFFSET => 0,
--ToDo C_AD_WIDTH => 3,
C_AD_WIDTH => adj'length,
C_AD_OFFSET => 0
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
LD => Bus2IP_Data(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
AD => std_logic_vector(adj),
LOAD => LOAD_EF,
OP => OP_EF
);
--
LENGTH(i)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1) <=
unsigned(qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1));
LENGTH(i)(0 to DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i)-1) <=
(others => '0');
end generate;
end generate;
---------------------------------------------------------------------
-- The below implements a PLENGTH register of the correct size for
-- each channel that requires one.
---------------------------------------------------------------------
PLENGTH_REG_GEN: for i in 0 to LAST_CHAN generate
T0or1_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 generate
PLENGTH(i) <= (others => '0');
end generate;
T2_GEN: if C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3 generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OP_EF, LOAD_EF, RST_EF : std_logic;
signal qslv : std_logic_vector(0 to DMA_DWIDTH-1);
begin
--
RST_EF <= reset(i) or ((cco_onehot(i) and clr_PLENGTH));
LOAD_EF <= (chan_sel(i) and PLENGTH_sel and dma2bus_wrack_i);
OP_ADD_GEN: if C_DMA_CHAN_TYPE(i) = 2 generate
OP_EF <= (cco_onehot(i) and inc_PLENGTH);
end generate;
OP_SUB_GEN: if C_DMA_CHAN_TYPE(i) = 3 generate
OP_EF <= (cco_onehot(i) and dec_PLENGTH);
end generate;
--
I_PLENGTH : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => C_DMA_CHAN_TYPE(i) = 2,
C_REG_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_RESET_VALUE => "00000000000000000000000000000000",
C_LD_WIDTH => C_DMA_LENGTH_WIDTH(i),
C_LD_OFFSET => 0,
--ToDo C_AD_WIDTH => 3,
C_AD_WIDTH => adj'length,
C_AD_OFFSET => 0
)
port map (
CK => Bus2IP_Clk,
RST => RST_EF,
Q => qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
LD => Bus2IP_Data(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1),
AD => std_logic_vector(adj),
LOAD => LOAD_EF,
OP => OP_EF
);
--
PLENGTH(i)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1) <=
unsigned(qslv(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i) to
DMA_DWIDTH-1));
PLENGTH(i)(0 to DMA_DWIDTH-C_DMA_LENGTH_WIDTH(i)-1)
<= (others => '0');
end generate;
end generate;
---------------------------------------------------------------------
-- dma_active bit (set when LENGTH loaded, cleared by dma state machine).
---------------------------------------------------------------------
DMA_ACTIVE_BIT_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
dma_active(i) <= '0';
elsif load_length(i) = '1' then
dma_active(i) <= '1';
elsif dma_completing = '1' and cco = i then
dma_active(i) <= '0';
end if;
end if;
end loop;
end process;
---------------------------------------------------------------------
-- This process implements a DMASR register for each channel.
-- (note: DMA_BSY and SG_BSY implemented separately.)
---------------------------------------------------------------------
DMASR_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DBE(i) <= '0';
DBT(i) <= '0';
L_rx(i) <= '0';
elsif cco = i then
if dma_starting = '1' then
DBE(i) <= '0';
DBT(i) <= '0';
L_rx(i) <= '0';
elsif set_DBE = '1' then
DBE(i) <= '1';
elsif set_DBT = '1' then
DBT(i) <= '1';
elsif set_L_rx= '1' then
L_rx(i) <= '1';
end if;
end if;
end if;
end loop;
end process;
---------------------------------------------------------------------
-- This process implements a BDA register for each channel that
-- supports scatter/gather.
---------------------------------------------------------------------
BDA_REG_PROCESS: process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
for i in 0 to LAST_CHAN loop
if C_DMA_CHAN_TYPE(i) = 1
or C_DMA_CHAN_TYPE(i) = 2
or C_DMA_CHAN_TYPE(i) = 3 then
if (reset(i) = RESET_ACTIVE) then
BDA(i) <= ( others => '0');
no_bda_link(i) <= '0';
elsif load_bda(i) = '1' then
BDA(i) <= UNSIGNED(Bus2IP_Data);
no_bda_link(i) <= not sg_active(i);
elsif (cco_onehot(i) and sg_active(i) and not is_idle(i)) = '1' then
no_bda_link(i) <= '0';
end if;
else
no_bda_link(i) <= '0';
end if;
end loop;
end if;
end process;
----------------------------------------------------------------------------
-- The processes below implement the ISR interrupt bits for each channel.
----------------------------------------------------------------------------
DD_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DD(i) <= '0';
elsif dma_completing = '1' and cco_onehot(i) = '1' then
DD(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
DD(i) <= DD(i) xor Bus2IP_Data(b_DD); -- Tog on wr.
end if;
end if;
end loop;
end process;
DE_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
DE(i) <= '0';
elsif (set_DBE or set_DBT) = '1' and cco_onehot(i) = '1' then
DE(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
DE(i) <= DE(i) xor Bus2IP_Data(b_DE); -- Tog on wr.
end if;
end if;
end loop;
end process;
PD_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PD(i) <= '0';
elsif rd_SRAddrFIFO(i) = '1' then
PD(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PD(i) <= PD(i) xor Bus2IP_Data(b_PD); -- Tog on wr.
end if;
end if;
end loop;
end process;
PCTR_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PCTR(i) <= '0';
elsif (UPC(i) >= PCT(i)) and (PCT(i) /= 0) then
PCTR(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PCTR(i) <= PCTR(i) xor Bus2IP_Data(b_PCTR); -- Tog on wr.
end if;
end if;
end loop;
end process;
PWBR_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PWBR(i) <= '0';
elsif C_DMA_CHAN_TYPE(i) > 1 and
C_INTR_COALESCE(i) = 1 and
(pw_timer_eq_0(i)) = '1' then
PWBR(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
PWBR(i) <= PWBR(i) xor Bus2IP_Data(b_PWBR); -- Tog on wr.
end if;
end if;
end loop;
end process;
SGDA_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
SGDA(i) <= '0';
elsif (not sg_active(i) and sg_active_d1(i) and not SGE(i)) = '1'
then
SGDA(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
SGDA(i) <= SGDA(i) xor Bus2IP_Data(b_SGDA); -- Tog on wr.
end if;
end if;
end loop;
end process;
SGDEND_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
SGEND(i) <= '0';
elsif (not sg_active(i) and sg_active_d1(i) and SGS(i)) = '1' then
SGEND(i) <= '1';
elsif (chan_sel(i) and ISR_sel and dma2bus_wrack_i) = '1' then
SGEND(i) <= SGEND(i) xor Bus2IP_Data(b_SGEND); -- Tog on wr.
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the IER for each channel.
----------------------------------------------------------------------------
IER_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
EDD(i) <= '0';
EDE(i) <= '0';
EPD(i) <= '0';
EPCTR(i) <= '0';
EPWBR(i) <= '0';
ESGDA(i) <= '0';
ESGEND(i) <= '0';
elsif (chan_sel(i) and IER_sel and dma2bus_wrack_i) = '1' then
EDD(i) <= Bus2IP_Data(b_DD);
EDE(i) <= Bus2IP_Data(b_DE);
EPD(i) <= Bus2IP_Data(b_PD);
EPCTR(i) <= Bus2IP_Data(b_PCTR);
EPWBR(i) <= Bus2IP_Data(b_PWBR);
ESGDA(i) <= Bus2IP_Data(b_SGDA);
ESGEND(i) <= Bus2IP_Data(b_SGEND);
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the UPC register for each channel.
----------------------------------------------------------------------------
UPC_REG_PROCESS: process (Bus2IP_Clk)
variable add1 : UNSIGNED(DMA_DWIDTH-UPCB to DMA_DWIDTH-1);
variable sub1 : natural;
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
add1 := (others => rd_SRAddrFIFO(i)); -- zero or minus 1
if (chan_sel(i) and UPC_sel and dma2bus_wrack_i and
Bus2IP_Data(DMA_DWIDTH-1)) = '1' then
sub1 := 1;
else sub1 := 0;
end if;
if (reset(i) = RESET_ACTIVE) then
UPC(i) <= (others => '0');
else
UPC(i) <= (UPC(i) - add1) - sub1;
-- This will increment if rd_SRAddrFIFO(i), decrement if
-- writing a one in LSB, stay unchanged if both or neither.
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the PCT register for each channel.
----------------------------------------------------------------------------
PCT_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if (reset(i) = RESET_ACTIVE) then
PCT(i) <= (others => '0');
elsif (chan_sel(i) and PCT_sel and dma2bus_wrack_i) = '1' then
PCT(i) <= UNSIGNED(Bus2IP_Data(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1)
);
end if;
end if;
end loop;
end process;
----------------------------------------------------------------------------
-- This process implements the PWB register for each channel.
----------------------------------------------------------------------------
PWB_REG_PROCESS: process (Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
pwb_loaded(i) <= '0';
if (reset(i) = RESET_ACTIVE) then
PWB(i) <= (others => '0');
elsif (chan_sel(i) and PWB_sel and dma2bus_wrack_i) = '1' then
PWB(i) <= UNSIGNED(Bus2IP_Data(DMA_DWIDTH - PWBB to
DMA_DWIDTH - 1)
);
pwb_loaded(i) <= '1';
end if;
end if;
end loop;
end process;
PWB_EQ_0_GEN: for i in 0 to LAST_CHAN generate
pwb_eq_0(i) <= not or_UNSIGNED(PWB(i));
pw_timer_eq_0(i) <= not or_UNSIGNED(pw_timer(i));
upc_eq_0(i) <= not or_UNSIGNED(UPC(i));
end generate;
---------------------------------------------------------------------
-- The below implements a pw_timer register of each channel
-- that requires one.
---------------------------------------------------------------------
-- XGR issue on generic context
LENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0)) &
LENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0) to
DMA_DWIDTH-1);
PLENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0)) &
PLENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(0) to
DMA_DWIDTH-1);
-- XGR
PW_TIMER_REG_GEN: for i in 0 to LAST_CHAN generate
T0or1_GEN: if C_DMA_CHAN_TYPE(i) = 0 or C_DMA_CHAN_TYPE(i) = 1 generate
pw_timer(i) <= (others => '0');
end generate;
T2or3_GEN: if C_DMA_CHAN_TYPE(i) = 2 or C_DMA_CHAN_TYPE(i) = 3 generate
--------------------------------------------------------------------
-- XGR WA (OP, LOAD and RST renamed to
-- OP_EF, LOAD_EF and RST_EF ... t0111.44) [XST workaround]
--------------------------------------------------------------------
signal OPxx, LOADxx, RSTxx : std_logic;
signal qslv : std_logic_vector(pw_timer(i)'range);
begin
--
RSTxx <= reset(i) or pwb_eq_0(i);
LOADxx <= upc_eq_0(i) or DMA2Intr_Intr_i(i) or pw_timer_eq_0(i) or pwb_loaded(i);
OPxx <= pw_enable_pulse;
--
i_pw_timer : component ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => pw_timer(i)'length,
C_RESET_VALUE => "11111111111111111111111111111111",
C_LD_WIDTH => pw_timer(i)'length,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Bus2IP_Clk,
RST => RSTxx,
Q => qslv(pw_timer(i)'range),
LD => std_logic_vector(PWB(i)),
AD => "1",
LOAD => LOADxx,
OP => OPxx
);
--
pw_timer(i) <= unsigned(qslv(pw_timer(i)'range));
end generate;
end generate;
--= end, Register implementations
--- Some register values selected by cco.
-- XGR LENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco)) &
-- XGR LENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco) to
-- XGR DMA_DWIDTH-1);
-- XGR PLENGTH_cco <= zero_vector(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco)) &
-- XGR PLENGTH(cco)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(cco) to
-- XGR DMA_DWIDTH-1);
--= end, Some register values selected by cco.
--- Register readback
---------------------------------------------------------------------
-- This process enables the selected register onto DMA2Bus_Data
-- on slave reads.
-- ToDo, this may generate extra "priority encode" logic, so
-- check this and adjust the implementation, if necessary.
---------------------------------------------------------------------
READ_REGISTER_PROCESS:process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
DMA2Bus_Data(0) <=
(ver_i(0) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(0) and DMA_RdCE and DMACR_sel) or
( sa_i(0) and DMA_RdCE and SA_sel) or
( da_i(0) and DMA_RdCE and DA_sel) or
(lnt_i(0) and DMA_RdCE and LENGTH_sel) or
(dsr_i(0) and DMA_RdCE and DMASR_sel) or
(bda_i(0) and DMA_RdCE and BDA_sel) or
(sge_i(0) and DMA_RdCE and SWCR_sel) or
-- (upc_i(0) and DMA_RdCE and UPC_sel) or
-- (pct_i(0) and DMA_RdCE and PCT_sel) or
-- (pwb_i(0) and DMA_RdCE and PWB_sel) or
-- (isr_i(0) and DMA_RdCE and ISR_sel) or
-- (ier_i(0) and DMA_RdCE and IER_sel) or
(ple_i(0) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(1) <=
(ver_i(1) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(1) and DMA_RdCE and DMACR_sel) or
( sa_i(1) and DMA_RdCE and SA_sel) or
( da_i(1) and DMA_RdCE and DA_sel) or
(lnt_i(1) and DMA_RdCE and LENGTH_sel) or
(dsr_i(1) and DMA_RdCE and DMASR_sel) or
(bda_i(1) and DMA_RdCE and BDA_sel) or
-- (sge_i(1) and DMA_RdCE and SWCR_sel) or
-- (upc_i(1) and DMA_RdCE and UPC_sel) or
-- (pct_i(1) and DMA_RdCE and PCT_sel) or
-- (pwb_i(1) and DMA_RdCE and PWB_sel) or
-- (isr_i(1) and DMA_RdCE and ISR_sel) or
-- (ier_i(1) and DMA_RdCE and IER_sel) or
(ple_i(1) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(2) <=
(ver_i(2) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(2) and DMA_RdCE and DMACR_sel) or
( sa_i(2) and DMA_RdCE and SA_sel) or
( da_i(2) and DMA_RdCE and DA_sel) or
(lnt_i(2) and DMA_RdCE and LENGTH_sel) or
(dsr_i(2) and DMA_RdCE and DMASR_sel) or
(bda_i(2) and DMA_RdCE and BDA_sel) or
-- (sge_i(2) and DMA_RdCE and SWCR_sel) or
-- (upc_i(2) and DMA_RdCE and UPC_sel) or
-- (pct_i(2) and DMA_RdCE and PCT_sel) or
-- (pwb_i(2) and DMA_RdCE and PWB_sel) or
-- (isr_i(2) and DMA_RdCE and ISR_sel) or
-- (ier_i(2) and DMA_RdCE and IER_sel) or
(ple_i(2) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(3) <=
(ver_i(3) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(3) and DMA_RdCE and DMACR_sel) or
( sa_i(3) and DMA_RdCE and SA_sel) or
( da_i(3) and DMA_RdCE and DA_sel) or
(lnt_i(3) and DMA_RdCE and LENGTH_sel) or
(dsr_i(3) and DMA_RdCE and DMASR_sel) or
(bda_i(3) and DMA_RdCE and BDA_sel) or
-- (sge_i(3) and DMA_RdCE and SWCR_sel) or
-- (upc_i(3) and DMA_RdCE and UPC_sel) or
-- (pct_i(3) and DMA_RdCE and PCT_sel) or
-- (pwb_i(3) and DMA_RdCE and PWB_sel) or
-- (isr_i(3) and DMA_RdCE and ISR_sel) or
-- (ier_i(3) and DMA_RdCE and IER_sel) or
(ple_i(3) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(4) <=
(ver_i(4) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(4) and DMA_RdCE and DMACR_sel) or
( sa_i(4) and DMA_RdCE and SA_sel) or
( da_i(4) and DMA_RdCE and DA_sel) or
(lnt_i(4) and DMA_RdCE and LENGTH_sel) or
(dsr_i(4) and DMA_RdCE and DMASR_sel) or
(bda_i(4) and DMA_RdCE and BDA_sel) or
-- (sge_i(4) and DMA_RdCE and SWCR_sel) or
-- (upc_i(4) and DMA_RdCE and UPC_sel) or
-- (pct_i(4) and DMA_RdCE and PCT_sel) or
-- (pwb_i(4) and DMA_RdCE and PWB_sel) or
-- (isr_i(4) and DMA_RdCE and ISR_sel) or
-- (ier_i(4) and DMA_RdCE and IER_sel) or
(ple_i(4) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(5) <=
(ver_i(5) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(5) and DMA_RdCE and DMACR_sel) or
( sa_i(5) and DMA_RdCE and SA_sel) or
( da_i(5) and DMA_RdCE and DA_sel) or
(lnt_i(5) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(5) and DMA_RdCE and DMASR_sel) or
(bda_i(5) and DMA_RdCE and BDA_sel) or
-- (sge_i(5) and DMA_RdCE and SWCR_sel) or
-- (upc_i(5) and DMA_RdCE and UPC_sel) or
-- (pct_i(5) and DMA_RdCE and PCT_sel) or
-- (pwb_i(5) and DMA_RdCE and PWB_sel) or
-- (isr_i(5) and DMA_RdCE and ISR_sel) or
-- (ier_i(5) and DMA_RdCE and IER_sel) or
(ple_i(5) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(6) <=
(ver_i(6) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(6) and DMA_RdCE and DMACR_sel) or
( sa_i(6) and DMA_RdCE and SA_sel) or
( da_i(6) and DMA_RdCE and DA_sel) or
(lnt_i(6) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(6) and DMA_RdCE and DMASR_sel) or
(bda_i(6) and DMA_RdCE and BDA_sel) or
-- (sge_i(6) and DMA_RdCE and SWCR_sel) or
-- (upc_i(6) and DMA_RdCE and UPC_sel) or
-- (pct_i(6) and DMA_RdCE and PCT_sel) or
-- (pwb_i(6) and DMA_RdCE and PWB_sel) or
-- (isr_i(6) and DMA_RdCE and ISR_sel) or
-- (ier_i(6) and DMA_RdCE and IER_sel) or
(ple_i(6) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(7) <=
(ver_i(7) and DMA_RdCE and RSTMIR_sel) or
(dcr_i(7) and DMA_RdCE and DMACR_sel) or
( sa_i(7) and DMA_RdCE and SA_sel) or
( da_i(7) and DMA_RdCE and DA_sel) or
(lnt_i(7) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(7) and DMA_RdCE and DMASR_sel) or
(bda_i(7) and DMA_RdCE and BDA_sel) or
-- (sge_i(7) and DMA_RdCE and SWCR_sel) or
-- (upc_i(7) and DMA_RdCE and UPC_sel) or
-- (pct_i(7) and DMA_RdCE and PCT_sel) or
-- (pwb_i(7) and DMA_RdCE and PWB_sel) or
-- (isr_i(7) and DMA_RdCE and ISR_sel) or
-- (ier_i(7) and DMA_RdCE and IER_sel) or
(ple_i(7) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(8) <=
(ver_i(8) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(8) and DMA_RdCE and DMACR_sel) or
( sa_i(8) and DMA_RdCE and SA_sel) or
( da_i(8) and DMA_RdCE and DA_sel) or
(lnt_i(8) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(8) and DMA_RdCE and DMASR_sel) or
(bda_i(8) and DMA_RdCE and BDA_sel) or
-- (sge_i(8) and DMA_RdCE and SWCR_sel) or
-- (upc_i(8) and DMA_RdCE and UPC_sel) or
-- (pct_i(8) and DMA_RdCE and PCT_sel) or
-- (pwb_i(8) and DMA_RdCE and PWB_sel) or
-- (isr_i(8) and DMA_RdCE and ISR_sel) or
-- (ier_i(8) and DMA_RdCE and IER_sel) or
(ple_i(8) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(9) <=
(ver_i(9) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(9) and DMA_RdCE and DMACR_sel) or
( sa_i(9) and DMA_RdCE and SA_sel) or
( da_i(9) and DMA_RdCE and DA_sel) or
(lnt_i(9) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(9) and DMA_RdCE and DMASR_sel) or
(bda_i(9) and DMA_RdCE and BDA_sel) or
-- (sge_i(9) and DMA_RdCE and SWCR_sel) or
-- (upc_i(9) and DMA_RdCE and UPC_sel) or
-- (pct_i(9) and DMA_RdCE and PCT_sel) or
-- (pwb_i(9) and DMA_RdCE and PWB_sel) or
-- (isr_i(9) and DMA_RdCE and ISR_sel) or
-- (ier_i(9) and DMA_RdCE and IER_sel) or
(ple_i(9) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(10) <=
(ver_i(10) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(10) and DMA_RdCE and DMACR_sel) or
( sa_i(10) and DMA_RdCE and SA_sel) or
( da_i(10) and DMA_RdCE and DA_sel) or
(lnt_i(10) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(10) and DMA_RdCE and DMASR_sel) or
(bda_i(10) and DMA_RdCE and BDA_sel) or
-- (sge_i(10) and DMA_RdCE and SWCR_sel) or
-- (upc_i(10) and DMA_RdCE and UPC_sel) or
-- (pct_i(10) and DMA_RdCE and PCT_sel) or
-- (pwb_i(10) and DMA_RdCE and PWB_sel) or
-- (isr_i(10) and DMA_RdCE and ISR_sel) or
-- (ier_i(10) and DMA_RdCE and IER_sel) or
(ple_i(10) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(11) <=
(ver_i(11) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(11) and DMA_RdCE and DMACR_sel) or
( sa_i(11) and DMA_RdCE and SA_sel) or
( da_i(11) and DMA_RdCE and DA_sel) or
(lnt_i(11) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(11) and DMA_RdCE and DMASR_sel) or
(bda_i(11) and DMA_RdCE and BDA_sel) or
-- (sge_i(11) and DMA_RdCE and SWCR_sel) or
-- (upc_i(11) and DMA_RdCE and UPC_sel) or
-- (pct_i(11) and DMA_RdCE and PCT_sel) or
-- (pwb_i(11) and DMA_RdCE and PWB_sel) or
-- (isr_i(11) and DMA_RdCE and ISR_sel) or
-- (ier_i(11) and DMA_RdCE and IER_sel) or
(ple_i(11) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(12) <=
(ver_i(12) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(12) and DMA_RdCE and DMACR_sel) or
( sa_i(12) and DMA_RdCE and SA_sel) or
( da_i(12) and DMA_RdCE and DA_sel) or
(lnt_i(12) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(12) and DMA_RdCE and DMASR_sel) or
(bda_i(12) and DMA_RdCE and BDA_sel) or
-- (sge_i(12) and DMA_RdCE and SWCR_sel) or
-- (upc_i(12) and DMA_RdCE and UPC_sel) or
-- (pct_i(12) and DMA_RdCE and PCT_sel) or
-- (pwb_i(12) and DMA_RdCE and PWB_sel) or
-- (isr_i(12) and DMA_RdCE and ISR_sel) or
-- (ier_i(12) and DMA_RdCE and IER_sel) or
(ple_i(12) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(13) <=
(ver_i(13) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(13) and DMA_RdCE and DMACR_sel) or
( sa_i(13) and DMA_RdCE and SA_sel) or
( da_i(13) and DMA_RdCE and DA_sel) or
(lnt_i(13) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(13) and DMA_RdCE and DMASR_sel) or
(bda_i(13) and DMA_RdCE and BDA_sel) or
-- (sge_i(13) and DMA_RdCE and SWCR_sel) or
-- (upc_i(13) and DMA_RdCE and UPC_sel) or
-- (pct_i(13) and DMA_RdCE and PCT_sel) or
-- (pwb_i(13) and DMA_RdCE and PWB_sel) or
-- (isr_i(13) and DMA_RdCE and ISR_sel) or
-- (ier_i(13) and DMA_RdCE and IER_sel) or
(ple_i(13) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(14) <=
(ver_i(14) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(14) and DMA_RdCE and DMACR_sel) or
( sa_i(14) and DMA_RdCE and SA_sel) or
( da_i(14) and DMA_RdCE and DA_sel) or
(lnt_i(14) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(14) and DMA_RdCE and DMASR_sel) or
(bda_i(14) and DMA_RdCE and BDA_sel) or
-- (sge_i(14) and DMA_RdCE and SWCR_sel) or
-- (upc_i(14) and DMA_RdCE and UPC_sel) or
-- (pct_i(14) and DMA_RdCE and PCT_sel) or
-- (pwb_i(14) and DMA_RdCE and PWB_sel) or
-- (isr_i(14) and DMA_RdCE and ISR_sel) or
-- (ier_i(14) and DMA_RdCE and IER_sel) or
(ple_i(14) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(15) <=
(ver_i(15) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(15) and DMA_RdCE and DMACR_sel) or
( sa_i(15) and DMA_RdCE and SA_sel) or
( da_i(15) and DMA_RdCE and DA_sel) or
(lnt_i(15) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(15) and DMA_RdCE and DMASR_sel) or
(bda_i(15) and DMA_RdCE and BDA_sel) or
-- (sge_i(15) and DMA_RdCE and SWCR_sel) or
-- (upc_i(15) and DMA_RdCE and UPC_sel) or
-- (pct_i(15) and DMA_RdCE and PCT_sel) or
-- (pwb_i(15) and DMA_RdCE and PWB_sel) or
-- (isr_i(15) and DMA_RdCE and ISR_sel) or
-- (ier_i(15) and DMA_RdCE and IER_sel) or
(ple_i(15) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(16) <=
(ver_i(16) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(16) and DMA_RdCE and DMACR_sel) or
( sa_i(16) and DMA_RdCE and SA_sel) or
( da_i(16) and DMA_RdCE and DA_sel) or
(lnt_i(16) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(16) and DMA_RdCE and DMASR_sel) or
(bda_i(16) and DMA_RdCE and BDA_sel) or
-- (sge_i(16) and DMA_RdCE and SWCR_sel) or
-- (upc_i(16) and DMA_RdCE and UPC_sel) or
-- (pct_i(16) and DMA_RdCE and PCT_sel) or
-- (pwb_i(16) and DMA_RdCE and PWB_sel) or
-- (isr_i(16) and DMA_RdCE and ISR_sel) or
-- (ier_i(16) and DMA_RdCE and IER_sel) or
(ple_i(16) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(17) <=
(ver_i(17) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(17) and DMA_RdCE and DMACR_sel) or
( sa_i(17) and DMA_RdCE and SA_sel) or
( da_i(17) and DMA_RdCE and DA_sel) or
(lnt_i(17) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(17) and DMA_RdCE and DMASR_sel) or
(bda_i(17) and DMA_RdCE and BDA_sel) or
-- (sge_i(17) and DMA_RdCE and SWCR_sel) or
-- (upc_i(17) and DMA_RdCE and UPC_sel) or
-- (pct_i(17) and DMA_RdCE and PCT_sel) or
-- (pwb_i(17) and DMA_RdCE and PWB_sel) or
-- (isr_i(17) and DMA_RdCE and ISR_sel) or
-- (ier_i(17) and DMA_RdCE and IER_sel) or
(ple_i(17) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(18) <=
(ver_i(18) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(18) and DMA_RdCE and DMACR_sel) or
( sa_i(18) and DMA_RdCE and SA_sel) or
( da_i(18) and DMA_RdCE and DA_sel) or
(lnt_i(18) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(18) and DMA_RdCE and DMASR_sel) or
(bda_i(18) and DMA_RdCE and BDA_sel) or
-- (sge_i(18) and DMA_RdCE and SWCR_sel) or
-- (upc_i(18) and DMA_RdCE and UPC_sel) or
-- (pct_i(18) and DMA_RdCE and PCT_sel) or
-- (pwb_i(18) and DMA_RdCE and PWB_sel) or
-- (isr_i(18) and DMA_RdCE and ISR_sel) or
-- (ier_i(18) and DMA_RdCE and IER_sel) or
(ple_i(18) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(19) <=
(ver_i(19) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(19) and DMA_RdCE and DMACR_sel) or
( sa_i(19) and DMA_RdCE and SA_sel) or
( da_i(19) and DMA_RdCE and DA_sel) or
(lnt_i(19) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(19) and DMA_RdCE and DMASR_sel) or
(bda_i(19) and DMA_RdCE and BDA_sel) or
-- (sge_i(19) and DMA_RdCE and SWCR_sel) or
-- (upc_i(19) and DMA_RdCE and UPC_sel) or
-- (pct_i(19) and DMA_RdCE and PCT_sel) or
-- (pwb_i(19) and DMA_RdCE and PWB_sel) or
-- (isr_i(19) and DMA_RdCE and ISR_sel) or
-- (ier_i(19) and DMA_RdCE and IER_sel) or
(ple_i(19) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(20) <=
(ver_i(20) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(20) and DMA_RdCE and DMACR_sel) or
( sa_i(20) and DMA_RdCE and SA_sel) or
( da_i(20) and DMA_RdCE and DA_sel) or
(lnt_i(20) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(20) and DMA_RdCE and DMASR_sel) or
(bda_i(20) and DMA_RdCE and BDA_sel) or
-- (sge_i(20) and DMA_RdCE and SWCR_sel) or
-- (upc_i(20) and DMA_RdCE and UPC_sel) or
-- (pct_i(20) and DMA_RdCE and PCT_sel) or
-- (pwb_i(20) and DMA_RdCE and PWB_sel) or
-- (isr_i(20) and DMA_RdCE and ISR_sel) or
-- (ier_i(20) and DMA_RdCE and IER_sel) or
(ple_i(20) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(21) <=
(ver_i(21) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(21) and DMA_RdCE and DMACR_sel) or
( sa_i(21) and DMA_RdCE and SA_sel) or
( da_i(21) and DMA_RdCE and DA_sel) or
(lnt_i(21) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(21) and DMA_RdCE and DMASR_sel) or
(bda_i(21) and DMA_RdCE and BDA_sel) or
-- (sge_i(21) and DMA_RdCE and SWCR_sel) or
-- (upc_i(21) and DMA_RdCE and UPC_sel) or
-- (pct_i(21) and DMA_RdCE and PCT_sel) or
-- (pwb_i(21) and DMA_RdCE and PWB_sel) or
-- (isr_i(21) and DMA_RdCE and ISR_sel) or
-- (ier_i(21) and DMA_RdCE and IER_sel) or
(ple_i(21) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(22) <=
(ver_i(22) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(22) and DMA_RdCE and DMACR_sel) or
( sa_i(22) and DMA_RdCE and SA_sel) or
( da_i(22) and DMA_RdCE and DA_sel) or
(lnt_i(22) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(22) and DMA_RdCE and DMASR_sel) or
(bda_i(22) and DMA_RdCE and BDA_sel) or
-- (sge_i(22) and DMA_RdCE and SWCR_sel) or
(upc_i(22) and DMA_RdCE and UPC_sel) or
(pct_i(22) and DMA_RdCE and PCT_sel) or
(pwb_i(22) and DMA_RdCE and PWB_sel) or
-- (isr_i(22) and DMA_RdCE and ISR_sel) or
-- (ier_i(22) and DMA_RdCE and IER_sel) or
(ple_i(22) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(23) <=
(ver_i(23) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(23) and DMA_RdCE and DMACR_sel) or
( sa_i(23) and DMA_RdCE and SA_sel) or
( da_i(23) and DMA_RdCE and DA_sel) or
(lnt_i(23) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(23) and DMA_RdCE and DMASR_sel) or
(bda_i(23) and DMA_RdCE and BDA_sel) or
-- (sge_i(23) and DMA_RdCE and SWCR_sel) or
(upc_i(23) and DMA_RdCE and UPC_sel) or
(pct_i(23) and DMA_RdCE and PCT_sel) or
(pwb_i(23) and DMA_RdCE and PWB_sel) or
-- (isr_i(23) and DMA_RdCE and ISR_sel) or
-- (ier_i(23) and DMA_RdCE and IER_sel) or
(ple_i(23) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(24) <=
(ver_i(24) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(24) and DMA_RdCE and DMACR_sel) or
( sa_i(24) and DMA_RdCE and SA_sel) or
( da_i(24) and DMA_RdCE and DA_sel) or
(lnt_i(24) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(24) and DMA_RdCE and DMASR_sel) or
(bda_i(24) and DMA_RdCE and BDA_sel) or
-- (sge_i(24) and DMA_RdCE and SWCR_sel) or
(upc_i(24) and DMA_RdCE and UPC_sel) or
(pct_i(24) and DMA_RdCE and PCT_sel) or
(pwb_i(24) and DMA_RdCE and PWB_sel) or
(isr_i(24) and DMA_RdCE and ISR_sel) or
(ier_i(24) and DMA_RdCE and IER_sel) or
(ple_i(24) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(25) <=
(ver_i(25) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(25) and DMA_RdCE and DMACR_sel) or
( sa_i(25) and DMA_RdCE and SA_sel) or
( da_i(25) and DMA_RdCE and DA_sel) or
(lnt_i(25) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(25) and DMA_RdCE and DMASR_sel) or
(bda_i(25) and DMA_RdCE and BDA_sel) or
-- (sge_i(25) and DMA_RdCE and SWCR_sel) or
(upc_i(25) and DMA_RdCE and UPC_sel) or
(pct_i(25) and DMA_RdCE and PCT_sel) or
(pwb_i(25) and DMA_RdCE and PWB_sel) or
(isr_i(25) and DMA_RdCE and ISR_sel) or
(ier_i(25) and DMA_RdCE and IER_sel) or
(ple_i(25) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(26) <=
(ver_i(26) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(26) and DMA_RdCE and DMACR_sel) or
( sa_i(26) and DMA_RdCE and SA_sel) or
( da_i(26) and DMA_RdCE and DA_sel) or
(lnt_i(26) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(26) and DMA_RdCE and DMASR_sel) or
(bda_i(26) and DMA_RdCE and BDA_sel) or
-- (sge_i(26) and DMA_RdCE and SWCR_sel) or
(upc_i(26) and DMA_RdCE and UPC_sel) or
(pct_i(26) and DMA_RdCE and PCT_sel) or
(pwb_i(26) and DMA_RdCE and PWB_sel) or
(isr_i(26) and DMA_RdCE and ISR_sel) or
(ier_i(26) and DMA_RdCE and IER_sel) or
(ple_i(26) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(27) <=
(ver_i(27) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(27) and DMA_RdCE and DMACR_sel) or
( sa_i(27) and DMA_RdCE and SA_sel) or
( da_i(27) and DMA_RdCE and DA_sel) or
(lnt_i(27) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(27) and DMA_RdCE and DMASR_sel) or
(bda_i(27) and DMA_RdCE and BDA_sel) or
-- (sge_i(27) and DMA_RdCE and SWCR_sel) or
(upc_i(27) and DMA_RdCE and UPC_sel) or
(pct_i(27) and DMA_RdCE and PCT_sel) or
(pwb_i(27) and DMA_RdCE and PWB_sel) or
(isr_i(27) and DMA_RdCE and ISR_sel) or
(ier_i(27) and DMA_RdCE and IER_sel) or
(ple_i(27) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(28) <=
(ver_i(28) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(28) and DMA_RdCE and DMACR_sel) or
( sa_i(28) and DMA_RdCE and SA_sel) or
( da_i(28) and DMA_RdCE and DA_sel) or
(lnt_i(28) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(28) and DMA_RdCE and DMASR_sel) or
(bda_i(28) and DMA_RdCE and BDA_sel) or
-- (sge_i(28) and DMA_RdCE and SWCR_sel) or
(upc_i(28) and DMA_RdCE and UPC_sel) or
(pct_i(28) and DMA_RdCE and PCT_sel) or
(pwb_i(28) and DMA_RdCE and PWB_sel) or
(isr_i(28) and DMA_RdCE and ISR_sel) or
(ier_i(28) and DMA_RdCE and IER_sel) or
(ple_i(28) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(29) <=
(ver_i(29) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(29) and DMA_RdCE and DMACR_sel) or
( sa_i(29) and DMA_RdCE and SA_sel) or
( da_i(29) and DMA_RdCE and DA_sel) or
(lnt_i(29) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(29) and DMA_RdCE and DMASR_sel) or
(bda_i(29) and DMA_RdCE and BDA_sel) or
-- (sge_i(29) and DMA_RdCE and SWCR_sel) or
(upc_i(29) and DMA_RdCE and UPC_sel) or
(pct_i(29) and DMA_RdCE and PCT_sel) or
(pwb_i(29) and DMA_RdCE and PWB_sel) or
(isr_i(29) and DMA_RdCE and ISR_sel) or
(ier_i(29) and DMA_RdCE and IER_sel) or
(ple_i(29) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(30) <=
(ver_i(30) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(30) and DMA_RdCE and DMACR_sel) or
( sa_i(30) and DMA_RdCE and SA_sel) or
( da_i(30) and DMA_RdCE and DA_sel) or
(lnt_i(30) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(30) and DMA_RdCE and DMASR_sel) or
(bda_i(30) and DMA_RdCE and BDA_sel) or
-- (sge_i(30) and DMA_RdCE and SWCR_sel) or
(upc_i(30) and DMA_RdCE and UPC_sel) or
(pct_i(30) and DMA_RdCE and PCT_sel) or
(pwb_i(30) and DMA_RdCE and PWB_sel) or
(isr_i(30) and DMA_RdCE and ISR_sel) or
(ier_i(30) and DMA_RdCE and IER_sel) or
(ple_i(30) and DMA_RdCE and PLENGTH_sel);
DMA2Bus_Data(31) <=
(ver_i(31) and DMA_RdCE and RSTMIR_sel) or
-- (dcr_i(31) and DMA_RdCE and DMACR_sel) or
( sa_i(31) and DMA_RdCE and SA_sel) or
( da_i(31) and DMA_RdCE and DA_sel) or
(lnt_i(31) and DMA_RdCE and LENGTH_sel) or
-- (dsr_i(31) and DMA_RdCE and DMASR_sel) or
(bda_i(31) and DMA_RdCE and BDA_sel) or
-- (sge_i(31) and DMA_RdCE and SWCR_sel) or
(upc_i(31) and DMA_RdCE and UPC_sel) or
(pct_i(31) and DMA_RdCE and PCT_sel) or
(pwb_i(31) and DMA_RdCE and PWB_sel) or
(isr_i(31) and DMA_RdCE and ISR_sel) or
(ier_i(31) and DMA_RdCE and IER_sel) or
(ple_i(31) and DMA_RdCE and PLENGTH_sel);
end if;
end process;
-- Module Identification Register 0 - 31 used
ver_i <= std_logic_vector(TO_UNSIGNED(MAJOR_VERSION , 4)) &
std_logic_vector(TO_UNSIGNED(MINOR_VERSION , 7)) &
std_logic_vector(TO_UNSIGNED(HW_SW_COMPATIBILITY_REVISION, 5)) &
std_logic_vector(TO_UNSIGNED(C_DEV_BLK_ID, 8)) &
std_logic_vector(TO_UNSIGNED(C_DMA_CHAN_TYPE(chan_num)+4, 8));
-- DMA Control Register 0 - 7 used
dcr_i <= DMACR(chan_num) & "0000000000000000000000000";
-- Source Address 0 - 31 used
sa_i <= std_logic_vector(SA(chan_num));
-- Destination Address 0 - 31 used
da_i <= std_logic_vector(DA(chan_num));
-- DMA Length 0 - 31 used
-- lnt_i <= std_logic_vector(RESIZE(LENGTH(chan_num)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
-- DMA_DWIDTH-1),DMA_DWIDTH));
lnt_i <= std_logic_vector(RESIZE(LENGTH(chan_num)(LENGTHS_LEFT to
DMA_DWIDTH-1),DMA_DWIDTH));
-- DMA Status Register 0 - 3 used
dsr_i <= dma_active(chan_num) & DBE(chan_num) & DBT(chan_num) & L(chan_num)
& sg_active(chan_num) & "000000000000000000000000000";
-- Buffer Descriptor Address 0 - 31 used
bda_i <= std_logic_vector(BDA(chan_num));
-- Software Control Register 0 - 0 used
sge_i <= SGE(chan_num) & "0000000000000000000000000000000";
-- Unserviced Packet Count 22 - 31 used
upc_i <= std_logic_vector(RESIZE(UPC(chan_num)(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1),32));
-- Packet Count Threshold 22 - 31 used
pct_i <= std_logic_vector(RESIZE(PCT(chan_num)(DMA_DWIDTH - UPCB to
DMA_DWIDTH - 1),DMA_DWIDTH));
-- Packet Wait Bound 22 - 31 used
pwb_i <= std_logic_vector(RESIZE(PWB(chan_num)(DMA_DWIDTH - PWBB to
DMA_DWIDTH - 1),DMA_DWIDTH));
-- Interrupt Status Register 24 - 31 used
isr_i <= "0000000000000000000000000" & SGEND(chan_num) & SGDA(chan_num)
& PWBR(chan_num) & PCTR(chan_num) & PD(chan_num)
& DE(chan_num) & DD(chan_num);
-- Interrupt Enable Register 24 - 31 used
ier_i <= "0000000000000000000000000" & ESGEND(chan_num) & ESGDA(chan_num)
& EPWBR(chan_num) & EPCTR(chan_num) & EPD(chan_num)
& EDE(chan_num) & EDD(chan_num);
-- ple_i <= std_logic_vector(RESIZE(PLENGTH(chan_num)(DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
-- DMA_DWIDTH-1),DMA_DWIDTH));
ple_i <= std_logic_vector(RESIZE(PLENGTH(chan_num)(LENGTHS_LEFT to
DMA_DWIDTH-1),DMA_DWIDTH));
--p DMA2Bus_Data <= --p
--p std_logic_vector(TO_UNSIGNED(MAJOR_VERSION , 4)) & --p
--p std_logic_vector(TO_UNSIGNED(MINOR_VERSION , 7)) & --p
--p std_logic_vector(TO_UNSIGNED(HW_SW_COMPATIBILITY_REVISION, 5)) & --p
--p std_logic_vector(TO_UNSIGNED(C_DEV_BLK_ID, 8)) & --p
--p std_logic_vector(TO_UNSIGNED(C_DMA_CHAN_TYPE(chan_num)+4, 8)) --p
--p when (RSTMIR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p DMACR(chan_num) --p
--p & "0000000000000000000000000" when ( DMACR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(SA(chan_num)) when ( SA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(DA(chan_num)) when ( DA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p LENGTH(chan_num)( --p
--p DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
--p DMA_DWIDTH-1), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when (LENGTH_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p dma_active(chan_num) -- DMA_BSY --p
--p & DBE(chan_num) --p
--p & DBT(chan_num) --p
--p & L(chan_num) --p
--p & sg_active(chan_num) -- SG_BSY --p
--p & "000000000000000000000000000" when ( DMASR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector(BDA(chan_num)) when ( BDA_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p SGE(chan_num) & --p
--p "0000000000000000000000000000000" when ( SWCR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p UPC(chan_num)( --p
--p DMA_DWIDTH - UPCB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p 32 --p
--p ) --p
--p ) when ( UPC_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PCT(chan_num)( --p
--p DMA_DWIDTH - UPCB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when ( PCT_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PWB(chan_num)( --p
--p DMA_DWIDTH - PWBB to --p
--p DMA_DWIDTH - 1 --p
--p ), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when ( PWB_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "0000000000000000000000000" --p
--p & SGEND(chan_num) & SGDA(chan_num) --p
--p & PWBR(chan_num) & PCTR(chan_num) --p
--p & PD(chan_num) --p
--p & DE(chan_num) & DD(chan_num) when ( ISR_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "0000000000000000000000000" --p
--p & ESGEND(chan_num) & ESGDA(chan_num) --p
--p & EPWBR(chan_num) & EPCTR(chan_num) --p
--p & EPD(chan_num) --p
--p & EDE(chan_num) & EDD(chan_num) --p
--p when ( IER_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p std_logic_vector( --p
--p RESIZE( --p
--p PLENGTH(chan_num)( --p
--p DMA_DWIDTH-C_DMA_LENGTH_WIDTH(chan_num) to
--p DMA_DWIDTH-1), --p
--p DMA_DWIDTH --p
--p ) --p
--p ) when (PLENGTH_sel and DMA_RdCE) --p
--p = '1' --p
--p else --p
--p "00000000000000000000000000000000"; --p
DMA2BUS_RDACK_I_PROCESS: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = RESET_ACTIVE) then
dma2bus_rdack_i <= '0';
else
dma2bus_rdack_i <= DMA_RdCE and Bus2IP_RdReq and not dma2bus_rdack_i;
end if;
end if;
end process;
DMA2Bus_RdAck <= dma2bus_rdack_i;
--= end, Register readback
--- Master arbitration and concentration.
MASTER_CONCENTRATION: block
begin
DMA2Bus_MstBusLock <= '0'; -- Bus-lock capability not used.
--ToDo, rmv
-- DMA2Bus_MstBE <= "1111"; -- Word transfers, only.
REG_MQ_PROCESS : process (Bus2IP_Clk) is
variable dma_sg_sr_pl : std_logic_vector(0 to 3);
variable Debug_TEMP : std_logic_vector(0 to C_OPB_AWIDTH-1);
variable dma2bus_addr_var : std_logic_vector(DMA2Bus_Addr'range);
constant DMA_TO_OPB_DWIDTH_FACTOR : positive
:= C_OPB_DWIDTH / DMA_DWIDTH;
constant DMA_TO_OPB_DWIDTH_FACTOR_BITS : natural
:= ceil_log2(DMA_TO_OPB_DWIDTH_FACTOR);
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
dma_sg_sr_pl := dma_sel & sg_sel & sr_sel & pl_sel;
if Bus2IP_MstLastAck = '1' then
dma2bus_addr_var := (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstWrReq <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
--ToDo, include DMA2Bus_MstBE here or, alternatively,
--consider if taking out all but WrReq and RdReq
--would be adantageous.
else
--ToDo. May want to use encoded select (regular mux) here.
case dma_sg_sr_pl is
when "1000" =>
dma2bus_addr_var := dma2bus_addr_dma;
DMA2IP_Addr <= dma2ip_addr_dma;
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_dma;
DMA2Bus_MstRdReq <= dma2bus_mstrdreq_dma;
DMA2Bus_MstBurst <= dma2bus_mstburst_dma;
-- DMA2Bus_MstBurst <= burst_cond_dma;
DMA2Bus_MstNum <= (others => '0');
-- ToDo, allow bursts other than size 8.
DMA2Bus_MstNum(DMA2Bus_MstNum'right-3) <=
dma2bus_mstburst_dma;
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <=
not dma2bus_mstburst_dma;
DMA2Bus_MstLoc2Loc <= '0';
when "0100" =>
dma2bus_addr_var := dma2bus_addr_sg;
DMA2IP_Addr <= dma2ip_addr_sg;
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_sg;
DMA2Bus_MstRdReq <= dma2bus_mstrdreq_sg;
DMA2Bus_MstBurst <= dma2bus_mstburst_sg;
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right-3) <=
dma2bus_mstburst_sg;
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <=
not dma2bus_mstburst_sg;
DMA2Bus_MstLoc2Loc <= '0';
when "0010" =>
dma2bus_addr_var := std_logic_vector(SRAddrFIFO_out(cco));
Debug_TEMP := C_STAT_FIFO_ADDR(cco)(
C_STAT_FIFO_ADDR(0)'length-C_OPB_AWIDTH
to
C_STAT_FIFO_ADDR(0)'length-1
);
--ToDo, rmv DMA2IP_Addr <= Debug_TEMP (C_OPB_AWIDTH - BPST_BITS - C_M to
--ToDo, rmv C_OPB_AWIDTH - BPST_BITS - 1);
DMA2IP_Addr <= Debug_TEMP (C_OPB_AWIDTH - 2 - C_M to
C_OPB_AWIDTH - 2 - 1);
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_sr;
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '0';
when "0001" =>
dma2bus_addr_var := C_LEN_FIFO_ADDR(cco)(
C_LEN_FIFO_ADDR(0)'length-C_OPB_AWIDTH to
C_LEN_FIFO_ADDR(0)'length-1
);
DMA2IP_Addr <= tmp_C_DMA_BASEADDR(
tmp_C_DMA_BASEADDR'length - C_M
- 2
to tmp_C_DMA_BASEADDR'length - NUM_CHAN_BITS
- RPB
- 2
- 1
)
& std_logic_vector(TO_UNSIGNED(cco, NUM_CHAN_BITS))
& std_logic_vector(TO_UNSIGNED(r_PLENGTH, RPB));
DMA2Bus_MstWrReq <= dma2bus_mstwrreq_pl;
DMA2Bus_MstRdReq <= not dma2bus_mstwrreq_pl;
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '1';
when others =>
dma2bus_addr_var := (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstWrReq <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstNum <= (others => '0');
DMA2Bus_MstNum(DMA2Bus_MstNum'right) <= '1';
DMA2Bus_MstLoc2Loc <= '0';
end case;
------------------------------------------------------------------
-- If DMA_WIDTH = C_OPB_DWIDTH or this master transaction is to
-- move DMA data, then enable all byte lanes...
------------------------------------------------------------------
DMA2Bus_MstBE <= (others => '1');
------------------------------------------------------------------
-- ... otherwise, enable only the 4 byte lanes
-- implied by the address.
------------------------------------------------------------------
if DMA_TO_OPB_DWIDTH_FACTOR > 1 and dma_sel = '0' then
for i in 0 to DMA_TO_OPB_DWIDTH_FACTOR-1 loop
if UNSIGNED(dma2bus_addr_var(
C_OPB_AWIDTH - 2 - DMA_TO_OPB_DWIDTH_FACTOR_BITS to --ToDo, give the 2 and symbolic name
C_OPB_AWIDTH - 2 - 1
)
) /= i
then
DMA2Bus_MstBE(4*i to 4*(i+1)-1) <= "0000";
end if;
end loop;
end if;
--
end if;
DMA2Bus_Addr <= dma2bus_addr_var;
end if; -- Bus2IP_Clk'event and Bus2IP_Clk = '1'
end process;
end block;
--= end, Master arbitration and concentration.
--- SRAddrFIFO for each rx pkt or tx pkt channel.
SRAddrFIFO_GEN: for i in 0 to LAST_CHAN generate
SRAddrFIFO_GEN: if C_DMA_CHAN_TYPE(i) = 2 or
C_DMA_CHAN_TYPE(i) = 3 generate
I_SRL_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => DMA_DWIDTH, -- ToDo, C_OPB_AWIDTH /= DMA_DWIDTH
-- would need some attention in places
-- where a data value becomes an address.
C_DEPTH => 16
)
port map (
Clk => Bus2IP_Clk,
Reset => reset(i),
FIFO_Write => wr_SRAddrFIFO(i),
Data_In => dma2bus_addr_sg,
FIFO_Read => rd_SRAddrFIFO(i),
Data_Out => SRAddrFIFO_out(i),
FIFO_Full => SRAddrFIFO_full(i),
Data_Exists => SRAddrFIFO_nonempty(i),
Addr => open
);
end generate;
-- Tie off outputs for non-existent instances.
SRAddrFIFO_TIEOFF_GEN: if C_DMA_CHAN_TYPE(i) = 0 or
C_DMA_CHAN_TYPE(i) = 1 generate
SRAddrFIFO_out(i) <= (others => '0');
SRAddrFIFO_full(i) <= '0';
SRAddrFIFO_nonempty(i) <= '0';
end generate;
end generate;
--= end, SRAddrFIFO for each rx pkt or tx pkt channel.
--- DMA state machine.
DMA_SM: block
type dma_state is (
IDLE,
DONECHK, -- Done check. Test for end of DMA operation.
XACTION, -- Perform a bus transaction.
GET_BDA,
HANDLE_SRA, -- If required, save the address of where SR will go.
GET_DMACR,
GET_SA,
GET_DA,
GET_LENGTH,
GET_PLENGTH,
PUT_LENGTH, -- Write the completion LENGTH.
PUT_DMASR, -- Write the DMA completion status.
LQCHK,
PUT_PLENGTH,
HALT,
A_WRITE_SR,
B_WRITE_SR,
C_WRITE_SR
);
type dma_state_array is array(0 to LAST_CHAN) of dma_state;
signal dma_cs : dma_state_array;
signal dma_ns : dma_state;
signal block_chan_muxing : std_logic;
signal dma_sel_ns : std_logic;
signal sg_sel_ns : std_logic;
signal pl_sel_ns : std_logic;
signal sr_sel_ns : std_logic;
signal dma2bus_mstburst_dma_ns : std_logic;
signal mstr_op_done : std_logic;
signal mstr_op_done_ns : std_logic;
signal wr_cond, rd_cond : std_logic; -- direction of the mem xfer
-- XGR wa F.23 bug
signal XGR_tmp : dma_state;
begin
-- XGR wa F.23 bug
XGR_tmp <= dma_cs(cco);
DMA_SM_COM_PROCESS: process(
dma_cs, dma_active, LENGTH_cco, PLENGTH_cco,
cco, rx, tx, LENGTH_ge_BPBT, WFIFO2DMA_Vacancy,
Bus2IP_MstWrAck, Bus2IP_MstRdAck, Mstr_sel_ma,
Bus2IP_MstError, Bus2IP_MstTimeOut, Bus2IP_MstLastAck,
burst_cond_dma, dest_is_a_fifo,
first, no_bda_link, sg_active, sgGo, L_tx,
IP2DMA_TxLength_Full, IP2DMA_RxLength_Empty,
IP2DMA_TxStatus_Empty, SRAddrFIFO_nonempty,
XGR_tmp, -- XGR wa F.23 bug
SRAddrFIFO_cco_hasroom, dma2bus_mstburst_dma, dma_completing
)
variable incdec : std_logic;
variable rx_pkt_complete : std_logic;
begin
-- Default assignments for dma_ns and state machine outputs.
dma_starting <= '0';
dma_completing <= '0';
block_chan_muxing <= '0';
set_L_rx <= '0';
set_DBE <= '0';
set_DBT <= '0';
inc_SA <= '0';
inc_DA <= '0';
dec_LENGTH <= '0';
inc_PLENGTH <= '0';
dec_PLENGTH <= '0';
clr_PLENGTH <= '0';
dma_sel_ns <= '0';
sg_sel_ns <= '0';
pl_sel_ns <= '0';
sr_sel_ns <= '0';
dma2bus_mstburst_dma_ns <= '0';
reset_sg_offset <= '0';
inc_sg_offset <= (others => '0');
dma2bus_mstwrreq_sg <= '0';
dma2bus_mstwrreq_sr <= '0';
dma2bus_mstwrreq_pl <= '0';
mstr_op_done_ns <= '0';
update_first <= '0';
wr_SRAddrFIFO <= (others => '0');
rd_SRAddrFIFO <= (others => '0');
is_idle <= (others => '0');
rx_pkt_complete := bo2sl(rx(cco)='1' and (PLENGTH_cco=0));
-- Next state and output logic.
--case dma_cs(cco) is
case XGR_tmp is
--ToDo. There may be only one rx or tx channel because there is just one
-- each of IP2DMA_RxStatus_Empty and IP2DMA_TxStatus_Empty.
when IDLE =>
is_idle(cco) <= '1';
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1'
or (rx_pkt_complete and SRAddrFIFO_nonempty(cco)) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= A_WRITE_SR;
else
if sgGo(cco) = '1' then
if (not rx(cco) or not IP2DMA_RxLength_Empty
or not first(cco)
) = '1' then -- ToDo. IP2DMA_RxLength_Empty being
-- scalar allows for just one Rx chan.
if (not no_bda_link(cco)) = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_BDA;
elsif (rx(cco) and first(cco)) = '1' then
pl_sel_ns <= '1';
block_chan_muxing <= '1';
reset_sg_offset <= '1';
dma_ns <= GET_PLENGTH;
else
block_chan_muxing <= '1'; -- Optional.
reset_sg_offset <= '1';
dma_ns <= HANDLE_SRA;
end if;
else
dma_ns <= IDLE;
end if;
else
if dma_active(cco) = '1' then -- Simple DMA.
dma_starting <= '1';
dma_ns <= DONECHK;
else
dma_ns <= IDLE;
end if;
end if;
end if;
when GET_BDA =>
-- This implementation assumes that the Bus2IP_MstLastAck
-- is concurrent with or follows the IP2Bus_WrAck that actually
-- writes the PLENGTH register. (An earlier implementation
-- assumed the opposite order--allowing the MasterAttachment/
-- SlaveAttachment to do a posted write. When that
-- implementation actually experienced the opposite during
-- operation, then state GET_BDA's successor state,
-- GET_PLENGTH, would respond to the Bus2IP_MstLastAck
-- that corresponds to state GET_BDA!)
-- State GET_LENGTH has similar considerations.
if Bus2IP_MstLastAck = '1' then
if (rx(cco) and first(cco)) = '1' then
pl_sel_ns <= '1';
block_chan_muxing <= '1';
reset_sg_offset <= '1';
dma_ns <= GET_PLENGTH;
else
block_chan_muxing <= '1'; -- Optional.
reset_sg_offset <= '1';
dma_ns <= HANDLE_SRA;
end if;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_BDA;
end if;
when GET_PLENGTH =>
if Bus2IP_MstLastAck = '1' then
block_chan_muxing <= '1'; -- Optional.
dma_ns <= HANDLE_SRA;
else
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= GET_PLENGTH;
end if;
when HANDLE_SRA =>
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= C_WRITE_SR;
elsif ((rx(cco) or tx(cco)) and first(cco)) = '1' then
--ToDo. Does first(cco) imply (rx(cco) or tx(cco))? If so,
-- (rx(cco) or tx(cco)) could be removed here.
if (SRAddrFIFO_cco_hasroom = '1') then
wr_SRAddrFIFO(cco) <= '1';
inc_sg_offset(cco) <= '1';
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_DMACR;
else
dma_ns <= HANDLE_SRA;
end if;
else
inc_sg_offset(cco) <= '1';
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_DMACR;
end if;
when GET_DMACR =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_SA;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_DMACR;
end if;
when GET_SA =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_DA;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_SA;
end if;
when GET_DA =>
if Bus2IP_MstLastAck = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= GET_LENGTH;
else
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= GET_DA;
end if;
when GET_LENGTH =>
if Bus2IP_MstLastAck = '1' then
-- See the comment of state GET_ BDA for considerations
-- that also apply to this state. The load of the LENGTH
-- register needs be complete before proceeding to the
-- next state. (A "MstLastAck" indication ahead of the
-- completion of a posted write will not work. An earlier
-- version had such posted write behavior. In that version,
-- this state was not exited until the LENGTH register
-- actually loaded; signal load_length(cco) was used.)
dma_starting <= '1';
dma_ns <= DONECHK;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= GET_LENGTH;
end if;
when DONECHK =>
dma_completing <= bo2sl(LENGTH_cco = 0) or rx_pkt_complete;
if (tx(cco) and not IP2DMA_TxStatus_Empty) = '1' then
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= B_WRITE_SR;
elsif dma_completing = '1' then
set_L_rx <= rx_pkt_complete;
if sg_active(cco) = '1' then
sg_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= PUT_LENGTH;
else
dma_ns <= IDLE;
end if;
elsif
-- We go to do a bus transaction when we are not at the normal
-- end of a DMA operation and there is not a condition
-- that keeps us from proceeding.
-- The condition that could keep us from proceeding is that
-- we are writing to a FIFO and it doesn't have vacancy
-- to (1) accomodate a single transfer in the case there isn't
-- enough left to do a burst or, otherwise, to (2) accomodate
-- a burst.
( dma_completing = '0'
and not ( (dest_is_a_fifo = '1')
and ( ( LENGTH_ge_BPBT = '0'
and UNSIGNED(WFIFO2DMA_Vacancy) = 0
)
or ( LENGTH_ge_BPBT = '1'
and UNSIGNED(WFIFO2DMA_Vacancy) < TPB
)
)
)
) then
dma_sel_ns <= '1';
block_chan_muxing <= '1';
dma2bus_mstburst_dma_ns <= burst_cond_dma;
dma_ns <= XACTION;
else
dma_ns <= DONECHK;
end if;
when XACTION =>
incdec :=
(Bus2IP_MstWrAck or Bus2IP_MstRdAck) and Mstr_sel_ma;
inc_SA <= incdec;
inc_DA <= incdec;
dec_LENGTH <= incdec;
inc_PLENGTH <= incdec and tx(cco);
dec_PLENGTH <= incdec and rx(cco);
if (Bus2IP_MstError or Bus2IP_MstTimeOut) = '1' then
set_DBE <= Bus2IP_MstError;
set_DBT <= Bus2IP_MstTimeOut;
dma_completing <= '1';
if sg_active(cco) = '1' then
dma_ns <= HALT;
else
dma_ns <= IDLE;
end if;
elsif (Bus2IP_MstLastAck) = '1' then
--block_chan_muxing <= '1'; -- Optional, no blocking for
-- find-grain switching
-- between channels.
dma_ns <= DONECHK;
else
dma_sel_ns <= '1';
block_chan_muxing <= '1';
dma2bus_mstburst_dma_ns <= dma2bus_mstburst_dma;
dma_ns <= XACTION;
end if;
when PUT_LENGTH =>
dma2bus_mstwrreq_sg <= '1';
if Bus2IP_MstLastAck = '1' then
block_chan_muxing <= '1';
sg_sel_ns <= '1';
inc_sg_offset(cco) <= '1';
dma_ns <= PUT_DMASR;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= PUT_LENGTH;
end if;
when PUT_DMASR =>
dma2bus_mstwrreq_sg <= '1';
if Bus2IP_MstLastAck = '1' then
inc_sg_offset(cco) <= '1';
dma_ns <= LQCHK;
else
block_chan_muxing <= '1';
sg_sel_ns <= '1';
dma_ns <= PUT_DMASR;
end if;
when LQCHK =>
update_first <= '1';
if (not tx(cco) or not L_tx(cco)) = '1' then
dma_ns <= IDLE;
elsif (not IP2DMA_TXLength_Full) = '1' then
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= PUT_PLENGTH;
else
dma_ns <= LQCHK;
end if;
when PUT_PLENGTH =>
dma2bus_mstwrreq_pl <= '1';
if Bus2IP_MstLastAck = '1' then
clr_PLENGTH <= '1';
dma_ns <= IDLE;
else
block_chan_muxing <= '1';
pl_sel_ns <= '1';
dma_ns <= PUT_PLENGTH;
end if;
when HALT =>
dma_ns <= HALT;
when A_WRITE_SR =>
is_idle(cco) <= '1';
--ToDo. Perhaps can eliminate this sig and drive dma2bus_mstwrreq to '1' when sr_sel
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
dma_ns <= IDLE;
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= A_WRITE_SR;
end if;
when B_WRITE_SR =>
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
block_chan_muxing <= '1';
dma_ns <= DONECHK;
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= B_WRITE_SR;
end if;
when C_WRITE_SR =>
dma2bus_mstwrreq_sr <= '1';
if Bus2IP_MstLastAck = '1' then
rd_SRAddrFIFO(cco) <= '1';
block_chan_muxing <= '1';
dma_ns <= HANDLE_SRA;
else
sr_sel_ns <= '1';
block_chan_muxing <= '1';
dma_ns <= C_WRITE_SR;
end if;
end case;
end process;
DMA_SM_DMA_CS_REG_PROCESS: process(Bus2IP_Clk)
begin
for i in 0 to LAST_CHAN loop
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if reset(i) = '1' then
dma_cs(i) <= IDLE;
elsif cco = i then
dma_cs(i) <= dma_ns;
end if;
end if;
end loop;
end process;
DMA_SM_OTHER_REG_PROCESS: process(Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset='1' then
dma_sel <= '0';
sg_sel <= '0';
pl_sel <= '0';
sr_sel <= '0';
dma2bus_mstburst_dma <= '0';
mstr_op_done <= '0';
cco <= 0;
else
dma_sel <= dma_sel_ns;
sg_sel <= sg_sel_ns;
pl_sel <= pl_sel_ns;
sr_sel <= sr_sel_ns;
dma2bus_mstburst_dma <= dma2bus_mstburst_dma_ns;
mstr_op_done <= mstr_op_done_ns;
if block_chan_muxing = '0' then
if cco = LAST_CHAN then
cco <= 0;
else
cco <= cco+1;
end if;
end if;
end if;
end if;
end process;
wr_cond <= SLOCAL(cco) and not DLOCAL(cco);
rd_cond <= DLOCAL(cco) and not SLOCAL(cco);
dma2bus_addr_dma <= std_logic_vector(SA(cco)) when rd_cond = '1' else
std_logic_vector(DA(cco));
--ToDo. Change 29, below, to symbolic constant.
-- Results from the fact that the low-order two (byte) bits are not
-- passed out on DMA2IP_Addr.
--
-- dma2ip_addr_dma <= std_logic_vector(DA(cco)(29-C_M+1 to 29))
-- when rd_cond = '1'
-- else
-- std_logic_vector(SA(cco)(29-C_M+1 to 29));
dma2ip_addr_dma <= std_logic_vector(DA(cco)(DMA_DWIDTH-2-C_M to
DMA_DWIDTH-2-1))
when rd_cond = '1'
else
std_logic_vector(SA(cco)(DMA_DWIDTH-2-C_M to
DMA_DWIDTH-2-1));
dma2bus_mstwrreq_dma <= wr_cond;
dma2bus_mstrdreq_dma <= rd_cond;
burst_cond_dma <= bo2sl(C_DMA_ALLOW_BURST) and
( (rx(cco) and PLENGTH_ge_BPBT and LENGTH_ge_BPBT)
or (not rx(cco) and LENGTH_ge_BPBT)
);
-- Note for burst_cond_dma: We pass up the opportunity to include
-- in a burst a last word that has padding and whose padding would
-- bring the total to exactly BPBT. This allows a simpler test.
-- For example, with BPBT = 32, we use a "length" >= 32 test, and
-- we are passing up optimization of the 29, 30 and 31 cases
-- in order to have a simpler test.
SG_ACTIVE_PROCESS: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
for i in 0 to LAST_CHAN loop
if reset(i) = '1' then
sg_active(i) <= '0';
sg_active_d1(i) <= '0';
else
sg_active_d1(i) <= sg_active(i);
if (SGE(i) and not SGS(i)) = '1' then
sg_active(i) <= '1';
elsif is_idle(i) = '1'
and ( ( C_DMA_CHAN_TYPE(i) /=2
and C_DMA_CHAN_TYPE(i) /=3
)
or ( SRAddrFIFO_nonempty(i) = '0'
and first(i) = '1'
)
) then
sg_active(i) <= '0';
end if;
end if;
end loop;
end if;
end process;
end block;
--= end, DMA state machine.
--- SG MQ bundle.
SG_SM: block
begin
dma2bus_addr_sg <= std_logic_vector(
--ToDo, rmv BDA(cco)(0 to BDA(cco)'length - BPST_BITS -1)
BDA(cco)(0 to BDA(cco)'length - 2 - 1)
+ sg_offset(cco)
) & "00";
dma2ip_addr_sg <= tmp_C_DMA_BASEADDR(
--ToDo, rmv tmp_C_DMA_BASEADDR'length - BPST_BITS
tmp_C_DMA_BASEADDR'length - 2
- C_M
--ToDo, rmv to tmp_C_DMA_BASEADDR'length - BPST_BITS
to tmp_C_DMA_BASEADDR'length - 2
- NUM_CHAN_BITS
- RPB
- 1
)
& std_logic_vector(TO_UNSIGNED(cco, NUM_CHAN_BITS))
& std_logic_vector(sg_offset(cco));
dma2bus_mstrdreq_sg <= not dma2bus_mstwrreq_sg;
dma2bus_mstburst_sg <= '0';
end block;
--= end, SG MQ bundle.
end sim; --)
| bsd-3-clause | d91484f51e80f61633dfd78a44d0e9ed | 0.445234 | 3.815495 | false | false | false | false |
jevinskie/aes-over-pcie | source/state_filter_out.vhd | 1 | 7,834 | -- File name: state_filter_out.vhd
-- Created: 2009-03-30
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael state filter for subblock outputs
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_filter_out is
port (
current_state : in state_type;
sub_bytes_out : in byte;
shift_rows_out : in row;
mix_columns_out : in col;
add_round_key_out : in byte;
load_out : in byte;
subblock : in subblock_type;
i : in g_index;
next_state : out state_type
);
end entity state_filter_out;
architecture tristate of state_filter_out is
begin
identity_proc : process(subblock, i, current_state)
begin
for x in index loop
for y in index loop
case subblock is
when identity =>
-- select all the current bytes
next_state(x, y) <= current_state(x, y);
when sub_bytes =>
-- dont select the indexed byte
if (x + y * 4 /= i) then
next_state(x, y) <= current_state(x, y);
else
next_state(x, y) <= (others => 'Z');
end if;
when shift_rows =>
-- dont select the indexed row
if (x /= i / 4) then
next_state(x, y) <= current_state(x, y);
else
next_state(x, y) <= (others => 'Z');
end if;
when mix_columns =>
-- dont select the indexed column
if (y /= to_integer(to_unsigned(i, 2))) then
next_state(x, y) <= current_state(x, y);
else
next_state(x, y) <= (others => 'Z');
end if;
when add_round_key =>
-- dont select the indexed byte
if (x + y * 4 /= i) then
next_state(x, y) <= current_state(x, y);
else
next_state(x, y) <= (others => 'Z');
end if;
when load_pt =>
-- dont select the indexed byte
if (x + y * 4 /= i) then
next_state(x, y) <= current_state(x, y);
else
next_state(x, y) <= (others => 'Z');
end if;
when store_ct =>
-- select all the current bytes
next_state(x, y) <= current_state(x, y);
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process identity_proc;
sub_bytes_proc : process(subblock, i, current_state, sub_bytes_out)
begin
for x in index loop
for y in index loop
case subblock is
when sub_bytes =>
-- select just the indexed byte
if (x + y * 4 = i) then
next_state(x, y) <= sub_bytes_out;
else
next_state(x, y) <= (others => 'Z');
end if;
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process sub_bytes_proc;
shift_rows_proc : process(subblock, i, current_state, shift_rows_out)
begin
for x in index loop
for y in index loop
case subblock is
when shift_rows =>
-- select just the indexed row
if (x = i) then
next_state(x, y) <= shift_rows_out(y);
else
next_state(x, y) <= (others => 'Z');
end if;
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process shift_rows_proc;
mix_columns_proc : process(subblock, i, current_state, mix_columns_out)
begin
for x in index loop
for y in index loop
case subblock is
when mix_columns =>
-- select just the indexed column
if (y = i) then
next_state(x, y) <= mix_columns_out(x);
else
next_state(x, y) <= (others => 'Z');
end if;
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process mix_columns_proc;
add_round_key_proc : process(subblock, i, current_state, add_round_key_out)
begin
for x in index loop
for y in index loop
case subblock is
when add_round_key =>
-- select just the indexed byte
if (x + y * 4 = i) then
next_state(x, y) <= add_round_key_out;
else
next_state(x, y) <= (others => 'Z');
end if;
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process add_round_key_proc;
load_pt_proc : process(subblock, i, current_state, load_out)
begin
for x in index loop
for y in index loop
case subblock is
when load_pt =>
-- select just the indexed byte
if (x + y * 4 = i) then
next_state(x, y) <= load_out;
else
next_state(x, y) <= (others => 'Z');
end if;
when others =>
next_state(x, y) <= (others => 'Z');
end case;
end loop;
end loop;
end process load_pt_proc;
end architecture tristate;
architecture mux of state_filter_out is
begin
process(current_state, sub_bytes_out, shift_rows_out,
mix_columns_out, add_round_key_out, load_out, subblock, i)
begin
for x in index loop
for y in index loop
next_state(x, y) <= current_state(x, y);
case subblock is
when identity =>
-- select all the current bytes (already done)
when sub_bytes =>
-- select just the indexed byte
if (x + y * 4 = i) then
next_state(x, y) <= sub_bytes_out;
end if;
when shift_rows =>
-- select just the indexed row
if (x = i) then
next_state(x, y) <= shift_rows_out(y);
end if;
when mix_columns =>
-- select just the indexed column
if (y = i) then
next_state(x, y) <= mix_columns_out(x);
end if;
when add_round_key =>
-- select just the index byte
if (x + y * 4 = i) then
next_state(x, y) <= add_round_key_out;
end if;
when load_pt =>
-- select just the index byte
if (x + y * 4 = i) then
next_state(x, y) <= load_out;
end if;
when store_ct =>
-- select all the current bytes (already done)
when others =>
-- select all the current bytes (already done)
end case;
end loop;
end loop;
end process;
end architecture mux;
| bsd-3-clause | 6d499646240359fe6e85c0a7e7b5baaa | 0.430942 | 4.313877 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/user_logic.vhd | 10 | 12,147 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | 71e3f9a077f745f0fe54db6876e64377 | 0.485552 | 4.030192 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd | 2 | 12,541 | -------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
| bsd-3-clause | 95d88f8076e7bb20df0fd5931fb97973 | 0.407543 | 5.370878 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd | 2 | 9,929 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: valid_be.vhd
-- Version: v1.00a
-- Description: Determines valid OPB access for memory devices
--
-------------------------------------------------------------------------------
-- Structure:
--
-- valid_be.vhd
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 09/21/01 -- First version
-- ^^^^^^
-- First version of valid_be created from BLT's file, valid_access. Made
-- modifications to support a target data bus width and a host data bus
-- width.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity valid_be is
generic (
C_HOST_DW : integer range 8 to 256 := 32;
C_TARGET_DW : integer range 8 to 32 := 32
);
port (
OPB_BE_Reg : in std_logic_vector(0 to C_HOST_DW/8-1);
Valid : out std_logic
);
end entity valid_be;
architecture implementation of valid_be is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant HOST_LOGVAL : integer := log2(C_HOST_DW/8); -- log value for host bus
constant TAR_LOGVAL : integer := log2(C_TARGET_DW/8); -- log value for target bus
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- VALID_ACCESS_PROCESS: this is a general purpose process that returns
-- whether or not a particular byte enable code is valid for a particular host
-- bus size and target bus size. The byte enable bus can be up to 32 bits wide,
-- supporting host bus widths up to 256 bits.
--
-- Example:
-- HOST BUS SIZE(OPB) TARGET BUS SIZE (SRAM) Valid BE
-- ----------------- ---------------------- --------
-- 8 8 '1'
-- 16 8 "01"
-- "10"
-- 16 16 "01"
-- "10"
-- "11"
-- 32 8 "0001"
-- "0010"
-- "0100"
-- "1000"
-- 32 16 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- 32 32 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- "1111"
-------------------------------------------------------------------------------
VALID_ACCESS_PROCESS: process (OPB_BE_Reg) is
variable compare_Val : integer := 0;
begin
Valid <= '0';
for i in 0 to TAR_LOGVAL loop -- loop for bits in target data bus
compare_Val := pwr(2,pwr(2,i))-1;
for j in 0 to pwr(2,HOST_LOGVAL-i) loop
if Conv_integer('0' & OPB_BE_Reg) = compare_Val then Valid <= '1'; end if;
compare_Val := compare_Val*pwr(2,pwr(2,i));
end loop;
end loop;
end process VALID_ACCESS_PROCESS;
end architecture implementation;
| bsd-3-clause | 0710a9dc23b1abf7a31304915759bacc | 0.371739 | 5.641477 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/srl16_fifo.vhd | 3 | 13,095 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_adder;
use opb_v20_v1_10_d.pf_counter_top;
use opb_v20_v1_10_d.pf_occ_counter_top;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_v20_v1_10_d.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| bsd-3-clause | 50a9082ff489b7a8a48008bbed9676f3 | 0.454219 | 4.324637 | false | false | false | false |
iocoder/graduation | hardware/pic/pic.vhd | 1 | 3,150 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pic is
Port (
CLK : in STD_LOGIC;
IRQ_in : in STD_LOGIC_VECTOR (7 downto 0);
IAK_out : out STD_LOGIC_VECTOR (7 downto 0);
IRQ_out : out STD_LOGIC := '0';
IAK_in : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1'
);
end pic;
architecture Behavioral of pic is
signal enable_back : std_logic := '0';
signal enable_forward : std_logic := '1';
signal int_device : std_logic_vector (31 downto 0);
begin
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
if (enable_back = enable_forward) then
if (IAK_in = '1') then
-- disable PIC
enable_back <= not enable_back;
-- select the interrupting device and handle IAK
if (IRQ_in(0) = '1') then
int_device <= x"00000000";
IAK_out <= "00000001";
elsif (IRQ_in(1) = '1') then
int_device <= x"00000001";
IAK_out <= "00000010";
elsif (IRQ_in(2) = '1') then
int_device <= x"00000002";
IAK_out <= "00000100";
elsif (IRQ_in(3) = '1') then
int_device <= x"00000003";
IAK_out <= "00001000";
elsif (IRQ_in(4) = '1') then
int_device <= x"00000004";
IAK_out <= "00010000";
elsif (IRQ_in(5) = '1') then
int_device <= x"00000005";
IAK_out <= "00100000";
elsif (IRQ_in(6) = '1') then
int_device <= x"00000006";
IAK_out <= "01000000";
else
int_device <= x"00000007";
IAK_out <= "10000000";
end if;
-- stop IRQ request
IRQ_out <= '0';
elsif (IRQ_in = x"00") then
-- no pending IRQ request
IRQ_out <= '0';
else
-- an IRQ is pending
IRQ_out <= '1';
end if;
else
-- stop IAK
IAK_out <= "00000000";
end if;
-- bus interface
if (CS = '1') then
if (RW = '1') then
if (Din(0) = '1') then
-- enable
enable_forward <= enable_back;
else
-- disable
enable_forward <= not enable_back;
end if;
else
Dout <= int_device;
end if;
else
Dout <= x"00000000";
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7363646aae96ac1efa5b862c36e93988 | 0.412381 | 4.048843 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_system.vhd | 3 | 35,113 | -------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MIRQ : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 31);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 255);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 3);
Sl_MWrErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 3);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 255);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_MPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_M_ABus : std_logic_vector(0 to 63);
signal plb_bus_M_BE : std_logic_vector(0 to 31);
signal plb_bus_M_MSize : std_logic_vector(0 to 3);
signal plb_bus_M_RNW : std_logic_vector(0 to 1);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 31);
signal plb_bus_M_UABus : std_logic_vector(0 to 63);
signal plb_bus_M_abort : std_logic_vector(0 to 1);
signal plb_bus_M_busLock : std_logic_vector(0 to 1);
signal plb_bus_M_lockErr : std_logic_vector(0 to 1);
signal plb_bus_M_priority : std_logic_vector(0 to 3);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 1);
signal plb_bus_M_request : std_logic_vector(0 to 1);
signal plb_bus_M_size : std_logic_vector(0 to 7);
signal plb_bus_M_type : std_logic_vector(0 to 5);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 1);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_SPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 3);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 3);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 3);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 3);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 255);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize(0 to 1),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(0 to 127),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(0 to 3),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority(0 to 1),
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE(0 to 15),
M_msize => plb_bus_M_MSize(0 to 1),
M_size => plb_bus_M_size(0 to 3),
M_type => plb_bus_M_type(0 to 2),
M_TAttribute => plb_bus_M_TAttribute(0 to 15),
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus(0 to 31),
M_ABus => plb_bus_M_ABus(0 to 31),
M_wrDBus => plb_bus_M_wrDBus(0 to 127),
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 1),
Sl_MRdErr => plb_bus_Sl_MRdErr(0 to 1),
Sl_MWrErr => plb_bus_Sl_MWrErr(0 to 1),
Sl_MIRQ => plb_bus_Sl_MIRQ(0 to 1)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request,
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock,
M_RNW => plb_bus_M_RNW,
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_abort => plb_bus_M_abort,
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst,
M_rdBurst => plb_bus_M_rdBurst,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMIRQ => net_gnd2,
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => plb_bus_SPLB_Rst,
MPLB_Rst => plb_bus_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW,
M_abort => plb_bus_M_abort,
M_busLock => plb_bus_M_busLock,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst,
M_request => plb_bus_M_request,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst,
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
SPLB_Clk => sys_clk,
SPLB_Rst => plb_bus_SPLB_Rst(1),
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(1),
PLB_wrPrim => plb_bus_PLB_wrPrim(1),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_MSize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_TAttribute => plb_bus_PLB_TAttribute,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(128 to 255),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_MBusy => plb_bus_Sl_MBusy(2 to 3),
Sl_MWrErr => plb_bus_Sl_MWrErr(2 to 3),
Sl_MRdErr => plb_bus_Sl_MRdErr(2 to 3),
Sl_MIRQ => plb_bus_Sl_MIRQ(2 to 3),
MPLB_Clk => sys_clk,
MPLB_Rst => plb_bus_MPLB_Rst(1),
M_request => plb_bus_M_request(1),
M_priority => plb_bus_M_priority(2 to 3),
M_busLock => plb_bus_M_busLock(1),
M_RNW => plb_bus_M_RNW(1),
M_BE => plb_bus_M_BE(16 to 31),
M_MSize => plb_bus_M_MSize(2 to 3),
M_size => plb_bus_M_size(4 to 7),
M_type => plb_bus_M_type(3 to 5),
M_TAttribute => plb_bus_M_TAttribute(16 to 31),
M_lockErr => plb_bus_M_lockErr(1),
M_abort => plb_bus_M_abort(1),
M_UABus => plb_bus_M_UABus(32 to 63),
M_ABus => plb_bus_M_ABus(32 to 63),
M_wrDBus => plb_bus_M_wrDBus(128 to 255),
M_wrBurst => plb_bus_M_wrBurst(1),
M_rdBurst => plb_bus_M_rdBurst(1),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(1),
PLB_MSSize => plb_bus_PLB_MSSize(2 to 3),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(1),
PLB_MTimeout => plb_bus_PLB_MTimeout(1),
PLB_MBusy => plb_bus_PLB_MBusy(1),
PLB_MRdErr => plb_bus_PLB_MRdErr(1),
PLB_MWrErr => plb_bus_PLB_MWrErr(1),
PLB_MIRQ => plb_bus_PLB_MIRQ(1),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(128 to 255),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(4 to 7),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(1),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(1),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(1),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
| bsd-3-clause | a3e9e4571cdbdcf63e9e5a3a57c33e7d | 0.606442 | 3.035619 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd | 2 | 22,003 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
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-- otherwise provided in a valid license issued to you by --
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
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-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
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-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.pselect_f;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity proc_common_v3_00_a.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity proc_common_v3_00_a.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| bsd-3-clause | af90b0176d9bc324d609508e08facf4b | 0.459301 | 4.450445 | false | false | false | false |
iocoder/graduation | hardware/mem/memif.vhd | 1 | 6,330 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : in STD_LOGIC; -- 0: read, 1: write
A : in STD_LOGIC_VECTOR (23 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1';
-- External Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1'; -- active low
WE : out STD_LOGIC := '1'; -- active low
MT_ADV : out STD_LOGIC := '0'; -- active low
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1'; -- active low
MT_LB : out STD_LOGIC := '1'; -- active low
MT_CE : out STD_LOGIC := '1'; -- active low
MT_CRE : out STD_LOGIC := '0'; -- active high
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1'; -- active low
ST_CE : out STD_LOGIC := '1' -- active low
);
end memif;
architecture Dataflow of memif is
signal LAST_CS : BOOLEAN;
signal READ : STD_LOGIC;
signal WRITE : STD_LOGIC;
signal A16a : STD_LOGIC_VECTOR (23 downto 0);
signal Din16a : STD_LOGIC_VECTOR (15 downto 0);
signal Dout16a : STD_LOGIC_VECTOR (15 downto 0);
signal LB16a : STD_LOGIC;
signal UB16a : STD_LOGIC;
signal EN16a : STD_LOGIC;
signal A16b : STD_LOGIC_VECTOR (23 downto 0);
signal Din16b : STD_LOGIC_VECTOR (15 downto 0);
signal Dout16b : STD_LOGIC_VECTOR (15 downto 0);
signal LB16b : STD_LOGIC;
signal UB16b : STD_LOGIC;
signal EN16b : STD_LOGIC;
signal A16 : STD_LOGIC_VECTOR (23 downto 0) := x"000000";
signal Din16 : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal Dout16 : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal LB16 : STD_LOGIC := '0';
signal UB16 : STD_LOGIC := '0';
signal EN16 : STD_LOGIC := '0';
signal counter : integer range 0 to 100 := 0;
begin
-- Read and Write signals:
READ <= (RAM_CS OR ROM_CS) AND EN16 AND (NOT RW);
WRITE <= (RAM_CS ) AND EN16 AND RW;
-- Address bus:
ADDR <= A16; -- NOTE: ADDRESS(0) is unconnected.
-- Data bus:
Dout16 <= DATA (15 downto 0) when READ='1' else "0000000000000000";
DATA <= Din16(15 downto 0) when WRITE='1' else "ZZZZZZZZZZZZZZZZ";
-- Bus direction:
OE <= NOT READ;
WE <= NOT WRITE;
-- Chip Enable:
MT_CE <= NOT (EN16 AND RAM_CS);
ST_CE <= NOT (EN16 AND ROM_CS);
-- Which byte
MT_LB <= NOT LB16;
MT_UB <= NOT Ub16;
-- Dout signal
Dout <= Dout16b & Dout16a when ((RAM_CS OR ROM_CS) AND (NOT RW))='1'
else x"00000000";
-- 32-BIT bus interfacing
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
if ((NOT LAST_CS) and (RAM_CS = '1' OR ROM_CS = '1')) then
-- startup of a new memory cycle
counter <= 0;
RDY <= '0';
if (DTYPE(0) = '1') then
-- BYTE
A16a <= A(23 downto 1) & "0";
Din16a <= Din(7 downto 0) & Din(7 downto 0);
LB16a <= NOT A(0);
UB16a <= A(0);
EN16a <= '1';
A16b <= x"000000";
Din16b <= x"0000";
LB16b <= '0';
UB16b <= '0';
EN16b <= '0';
elsif (DTYPE(1) = '1') then
-- HALF
A16a <= A(23 downto 1) & "0";
Din16a <= Din(15 downto 0);
LB16a <= '1';
UB16a <= '1';
EN16a <= '1';
A16b <= x"000000";
Din16b <= x"0000";
LB16b <= '0';
UB16b <= '0';
EN16b <= '0';
elsif (DTYPE(2) = '1') then
-- WORD
A16a <= A(23 downto 2) & "00";
Din16a <= Din(15 downto 0);
LB16a <= '1';
UB16a <= '1';
EN16a <= '1';
A16b <= A(23 downto 2) & "10";
Din16b <= Din(31 downto 16);
LB16b <= '1';
UB16b <= '1';
EN16b <= '1';
end if;
else
-- increase counter
if (counter < 7) then
-- in phase 1
A16 <= A16a;
Din16 <= Din16a;
LB16 <= LB16a;
UB16 <= UB16a;
EN16 <= EN16a;
if (DTYPE(0) = '1') then
if (LB16a = '1') then
Dout16a <= x"00" & Dout16(7 downto 0);
else
Dout16a <= x"00" & Dout16(15 downto 8);
end if;
else
Dout16a <= Dout16;
end if;
counter <= counter + 1;
elsif (counter = 7) then
-- before phase 2
A16 <= x"000000";
Din16 <= x"0000";
LB16 <= '0';
UB16 <= '0';
EN16 <= '0';
if (EN16b = '0') then
counter <= 14;
else
counter <= counter + 1;
end if;
elsif (counter < 14) then
-- in phase 2
A16 <= A16b;
Din16 <= Din16b;
LB16 <= LB16b;
UB16 <= UB16b;
EN16 <= EN16b;
Dout16b <= Dout16;
counter <= counter + 1;
else
-- done
A16 <= x"000000";
Din16 <= x"0000";
LB16 <= '0';
UB16 <= '0';
EN16 <= '0';
RDY <= '1';
end if;
end if;
LAST_CS <= (RAM_CS = '1' OR ROM_CS = '1');
end if;
end process;
end Dataflow;
| gpl-3.0 | f09ca2c9e1c787cf4fb40b27e53e2d78 | 0.426698 | 3.464696 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/plb_scheduler.vhd | 9 | 35,549 | ------------------------------------------------------------------------------
-- plb_scheduler.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_scheduler_v1_00_a;
use plb_scheduler_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_scheduler is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_scheduler;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_scheduler is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_scheduler_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
Soft_Stop => Soft_Stop ,
SWTM_DOB => SWTM_DOB ,
SWTM_ADDRB => SWTM_ADDRB ,
SWTM_DIB => SWTM_DIB ,
SWTM_ENB => SWTM_ENB ,
SWTM_WEB => SWTM_WEB ,
TM2SCH_current_cpu_tid => TM2SCH_current_cpu_tid ,
TM2SCH_opcode => TM2SCH_opcode ,
TM2SCH_data => TM2SCH_data ,
TM2SCH_request => TM2SCH_request ,
SCH2TM_busy => SCH2TM_busy ,
SCH2TM_data => SCH2TM_data ,
SCH2TM_next_cpu_tid => SCH2TM_next_cpu_tid ,
SCH2TM_next_tid_valid => SCH2TM_next_tid_valid ,
Preemption_Interrupt => Preemption_Interrupt ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
end IMP;
| bsd-3-clause | 8cd4efd425bd6188fcd854164d009d3e | 0.459675 | 4.208975 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_master_lite_v1_00_a/hdl/vhdl/axi_master_lite_cntlr.vhd | 2 | 44,094 | -------------------------------------------------------------------------------
-- axi_master_lite_cntlr.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_master_lite_cntlr.vhd
--
-- Description:
--
-- This VHDL file is the design implementation for the Read/Write Controller
-- that is part of the AXI Master Lite core.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_master_lite.vhd (v3_00_a)
-- |
-- |- axi_master_lite_cntlr.vhd
-- |
-- |- axi_master_lite_reset.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.3 $
-- Date: $12/01/2010$
--
-- History:
-- DET 12/01/2010 Initial Version
--
-- DET 12/14/2010 Initial
-- ~~~~~~
-- -- Per CR587090
-- - Removed the input port m_axi_rlast. It is not part of the AXI4-Lite
-- signal set.
-- ^^^^^^
--
-- DET 12/15/2010 Initial
-- ~~~~~~
-- -- Per CR587194
-- - Fixed the Bus2IP_Error assertion logic.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
Use proc_common_v3_00_a.proc_common_pkg.all;
Use proc_common_v3_00_a.family_support.all;
-------------------------------------------------------------------------------
entity axi_master_lite_cntlr is
generic (
-- AXI4 Parameters
C_M_AXI_LITE_ADDR_WIDTH : INTEGER range 32 to 32 := 32;
-- width of AXI4 Address Bus (in bits)
C_M_AXI_LITE_DATA_WIDTH : INTEGER range 32 to 32 := 32;
-- Width of the AXI4 Data Bus (in bits)
-- FPGA Family Parameter
C_FAMILY : String := "virtex6"
-- Select the target architecture type
-- see the family.vhd package in the proc_common
-- library
);
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
axi_aclk : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Reset Input (active high)
-----------------------------------------------------------------------
axi_reset : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Master Detected Error output
-----------------------------------------------------------------------
md_error : out std_logic ;-- Discrete Out
----------------------------------------------------------------------------
-- AXI4 Read Channels
----------------------------------------------------------------------------
-- AXI4 Read Address Channel -- AXI4
m_axi_arready : in std_logic ; -- AXI4
m_axi_arvalid : out std_logic ; -- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Read Data Channel -- AXI4
m_axi_rready : out std_logic ; -- AXI4
m_axi_rvalid : in std_logic ; -- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- AXI4 Write Channels
-----------------------------------------------------------------------------
-- AXI4 Write Address Channel
m_axi_awready : in std_logic ; -- AXI4
m_axi_awvalid : out std_logic ; -- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Write Data Channel -- AXI4
m_axi_wready : in std_logic ; -- AXI4
m_axi_wvalid : out std_logic ; -- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- AXI4
-- AXI4
-- AXI4 Write Response Channel -- AXI4
m_axi_bready : out std_logic ; -- AXI4
m_axi_bvalid : in std_logic ; -- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- IP Master Request/Qualifers
-----------------------------------------------------------------------------
ip2bus_mstrd_req : In std_logic; -- IPIC
ip2bus_mstwr_req : In std_logic; -- IPIC
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- IPIC
ip2bus_mst_be : in std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- IPIC
ip2bus_mst_lock : In std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IP Request Status Reply
-----------------------------------------------------------------------------
bus2ip_mst_cmdack : Out std_logic; -- IPIC
bus2ip_mst_cmplt : Out std_logic; -- IPIC
bus2ip_mst_error : Out std_logic; -- IPIC
bus2ip_mst_rearbitrate : Out std_logic; -- IPIC
bus2ip_mst_cmd_timeout : out std_logic; -- IPIC
-- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Read data
-----------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC
bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Write data
-----------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC
bus2ip_mstwr_dst_rdy_n : Out std_logic -- IPIC
);
end entity axi_master_lite_cntlr;
architecture implementation of axi_master_lite_cntlr is
-- Signal declarations ---------------------------------------
-- AXI4 Read Address Channel
signal sig_m_axi_arready : std_logic := '0';
signal sig_m_axi_arvalid : std_logic := '0';
signal sig_m_axi_araddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_m_axi_arprot : std_logic_vector(2 downto 0) := (others => '0') ;
-- AXI4 Read Data Channel
signal sig_m_axi_rready : std_logic := '0';
signal sig_m_axi_rvalid : std_logic := '0';
signal sig_m_axi_rdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_m_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
-- Write Address Channel
signal sig_m_axi_awready : std_logic := '0';
signal sig_m_axi_awvalid : std_logic := '0';
signal sig_m_axi_awaddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_m_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
-- Write Data Channel
signal sig_m_axi_wready : std_logic := '0';
signal sig_m_axi_wvalid : std_logic := '0';
signal sig_m_axi_wdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_m_axi_wstrb : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Write Response Channel
signal sig_m_axi_bready : std_logic := '0';
signal sig_m_axi_bvalid : std_logic := '0';
signal sig_m_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
-- IP Master Request Qualifers
signal sig_ip2bus_rd_req : std_logic := '0';
signal sig_ip2bus_wr_req : std_logic := '0';
signal sig_ip2bus_addr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_ip2bus_addr_reg : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_ip2bus_be : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ip2bus_lock : std_logic := '0';
-- IPIC Status Reply
signal sig_bus2ip_cmdack : std_logic := '0';
signal sig_bus2ip_rearbitrate : std_logic := '0';
signal sig_bus2ip_cmd_timeout : std_logic := '0';
signal sig_bus2ip_cmplt : std_logic := '0';
signal sig_bus2ip_error : std_logic := '0';
-- IPIC Data Interface
signal sig_bus2ip_mstrd_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_bus2ip_rd_src_rdy : std_logic := '0';
signal sig_ip2bus_mstwr_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_bus2ip_wr_dst_rdy : std_logic := '0';
-- AXI Error Response
signal sig_read_resp_error : std_logic := '0';
signal sig_read_error : std_logic := '0';
signal sig_write_resp_error : std_logic := '0';
signal sig_write_error : std_logic := '0';
-- Transfer completion
signal sig_rd_addrqual_taken : std_logic := '0';
signal sig_wr_addrqual_taken : std_logic := '0';
signal sig_rd_data_taken : std_logic := '0';
signal sig_wr_data_taken : std_logic := '0';
signal sig_wr_resp_taken : std_logic := '0';
-- Transfer Startup
signal sig_rd_start : std_logic := '0';
signal sig_wr_start : std_logic := '0';
signal sig_ld_addr : std_logic := '0';
-- Read Transfer sequence
signal sig_rd_req_reg : std_logic := '0';
signal sig_rd_in_prog : std_logic := '0';
signal sig_rd_addr_cmplt : std_logic := '0';
signal sig_rd_data_cmplt : std_logic := '0';
signal sig_rd_cmplt : std_logic := '0';
-- Write Transfer sequence
signal sig_wr_req_reg : std_logic := '0';
signal sig_wr_in_prog : std_logic := '0';
signal sig_wr_addr_cmplt : std_logic := '0';
signal sig_wr_data_cmplt : std_logic := '0';
signal sig_wr_resp_cmplt : std_logic := '0';
signal sig_wr_cmplt : std_logic := '0';
-- Command Completion
signal sig_bus2ip_cmplt_local : std_logic := '0';
-- Detected error
signal sig_md_error : std_logic := '0';
----------------------------------------------------------------
-- Register duplication attribute assignments to control fanout
-- on register clear signals
----------------------------------------------------------------
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_bus2ip_cmplt_local : signal is "TRUE";
Attribute KEEP of sig_bus2ip_cmplt : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt_local : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt : signal is "no";
begin --(architecture implementation)
-----------------------------------------------------------------------------
-- Port Assignments
-----------------------------------------------------------------------------
-- Read Address Channel port assignments
sig_m_axi_arready <= m_axi_arready ;
m_axi_arvalid <= sig_m_axi_arvalid ;
m_axi_araddr <= sig_m_axi_araddr ;
m_axi_arprot <= sig_m_axi_arprot ;
-- Read Data Channel port assignments
m_axi_rready <= sig_m_axi_rready ;
sig_m_axi_rvalid <= m_axi_rvalid ;
sig_m_axi_rdata <= m_axi_rdata ;
sig_m_axi_rresp <= m_axi_rresp ;
-- Write Address Channel port assignments
sig_m_axi_awready <= m_axi_awready ;
m_axi_awvalid <= sig_m_axi_awvalid ;
m_axi_awaddr <= sig_m_axi_awaddr ;
m_axi_awprot <= sig_m_axi_awprot ;
-- AXI4 Write Data Channel port assignments
sig_m_axi_wready <= m_axi_wready ;
m_axi_wvalid <= sig_m_axi_wvalid ;
m_axi_wdata <= sig_m_axi_wdata ;
m_axi_wstrb <= sig_m_axi_wstrb ;
-- AXI4 Write Response Channel port assignments
m_axi_bready <= sig_m_axi_bready ;
sig_m_axi_bvalid <= m_axi_bvalid ;
sig_m_axi_bresp <= m_axi_bresp ;
-- IPIC Command Qualifiers
sig_ip2bus_rd_req <= ip2bus_mstrd_req ; -- Input
sig_ip2bus_wr_req <= ip2bus_mstwr_req ; -- Input
sig_ip2bus_addr <= ip2bus_mst_addr ; -- Input
sig_ip2bus_be <= ip2bus_mst_be ; -- Input
sig_ip2bus_lock <= ip2bus_mst_lock ; -- Input
-- IPIC Status reply
bus2ip_mst_cmdack <= sig_bus2ip_cmdack ; -- output
bus2ip_mst_rearbitrate <= sig_bus2ip_rearbitrate ; -- output
bus2ip_mst_cmd_timeout <= sig_bus2ip_cmd_timeout ; -- output
bus2ip_mst_cmplt <= sig_bus2ip_cmplt ; -- output
bus2ip_mst_error <= sig_bus2ip_error ; -- output
-- IPIC Read Data IF
bus2ip_mstrd_d <= sig_bus2ip_mstrd_d ; -- output
bus2ip_mstrd_src_rdy_n <= not(sig_bus2ip_rd_src_rdy); -- output
-- IPIC write Data IF
sig_ip2bus_mstwr_d <= ip2bus_mstwr_d ; -- input
bus2ip_mstwr_dst_rdy_n <= not(sig_bus2ip_wr_dst_rdy); -- output
-- MD Error output
md_error <= sig_md_error ; -- output
-- IPIC Error status output
sig_bus2ip_error <= sig_read_error or -- Assert on either a read
sig_write_error ; -- or write error detection
-----------------------------------------------------------------------------
-- Combinitorial logic
-----------------------------------------------------------------------------
-- Drive the IPIC Rearbitrate and Timeout to zeros
sig_bus2ip_rearbitrate <= '0' ; -- not available in AXI4
sig_bus2ip_cmd_timeout <= '0' ; -- not available in AXI4
-- Drive the axi protection qualifiers to zeros
sig_m_axi_awprot <= (others => '0') ; -- always driven to zeros
sig_m_axi_arprot <= (others => '0') ; -- always driven to zeros
-- Share the address register for both read and write xfers
sig_m_axi_araddr <= sig_ip2bus_addr_reg ;
sig_m_axi_awaddr <= sig_ip2bus_addr_reg ;
-- Detect when the read address has been accepted on the axi bus
sig_rd_addrqual_taken <= sig_m_axi_arvalid and
sig_m_axi_arready ;
-- Detect when the write address has been accepted axi bus
sig_wr_addrqual_taken <= sig_m_axi_awvalid and
sig_m_axi_awready ;
-- Detect when the read data has been accepted axi bus
sig_rd_data_taken <= sig_m_axi_rvalid and
sig_m_axi_rready ;
-- Detect when the write data has been accepted axi bus
sig_wr_data_taken <= sig_m_axi_wvalid and
sig_m_axi_wready ;
-- Detect when the write response has been accepted axi bus
sig_wr_resp_taken <= sig_m_axi_bvalid and
sig_m_axi_bready ;
-- Detirmine if a read response error is being flagged
sig_read_resp_error <= '1'
when (sig_m_axi_rresp(0) = '1' or
sig_m_axi_rresp(1) = '1')
else '0';
-- Detirmine if a write response error is being flagged
sig_write_resp_error <= '1'
when (sig_m_axi_bresp(0) = '1' or
sig_m_axi_bresp(1) = '1')
else '0';
-- Detirmine if a read transfer sequence has completed
-- or is about to complete
sig_rd_cmplt <= sig_rd_in_prog and
(sig_rd_addr_cmplt or
sig_rd_addrqual_taken) and
(sig_rd_data_cmplt or
sig_rd_data_taken);
-- Detirmine if a write transfer sequence has completed
-- or is about to complete
sig_wr_cmplt <= sig_wr_in_prog and
(sig_wr_addr_cmplt or
sig_wr_addrqual_taken) and
(sig_wr_data_cmplt or
sig_wr_data_taken) and
(sig_wr_resp_cmplt or
sig_wr_resp_taken);
-- Generate the Command Address sample and hold signal
sig_ld_addr <= sig_rd_start or
sig_wr_start;
-- Detect rising edge of new read command
sig_rd_start <= sig_ip2bus_rd_req and
not(sig_rd_req_reg);
-- Detect rising edge of new write command
sig_wr_start <= sig_ip2bus_wr_req and
not(sig_wr_req_reg);
-----------------------------------------------------------------------------
-- Command Start detection
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDREQ_REG
--
-- Process Description:
-- Registers the IPIC read request input.
--
-------------------------------------------------------------
IMP_RDREQ_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_rd_req_reg <= '0' ;
else
sig_rd_req_reg <= sig_ip2bus_rd_req ;
end if;
end if;
end process IMP_RDREQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WRREQ_REG
--
-- Process Description:
-- Registers the IPIC write request input.
--
-------------------------------------------------------------
IMP_WRREQ_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_wr_req_reg <= '0' ;
else
sig_wr_req_reg <= sig_ip2bus_wr_req ;
end if;
end if;
end process IMP_WRREQ_REG;
-----------------------------------------------------------------------------
-- shared Address Register
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_REG
--
-- Process Description:
-- Registers the IPIC addres input whenever a new command
-- has been detected.
--
-------------------------------------------------------------
IMP_ADDR_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_ip2bus_addr_reg <= (others => '0') ;
elsif (sig_ld_addr = '1') then
sig_ip2bus_addr_reg <= sig_ip2bus_addr ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_ADDR_REG;
-----------------------------------------------------------------------------
-- Generate Write Transfer Registers and Control
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WRITE_IN_PROG_FLOP
--
-- Process Description:
-- Implements the read in progress flop.
--
-------------------------------------------------------------
IMP_WRITE_IN_PROG_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_wr_in_prog <= '0' ;
elsif (sig_wr_start = '1') then
sig_wr_in_prog <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WRITE_IN_PROG_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AWVALID_FLOP
--
-- Process Description:
-- Implements the write awvalid flop.
--
-------------------------------------------------------------
IMP_AWVALID_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_wr_addrqual_taken = '1') then
sig_m_axi_awvalid <= '0' ;
elsif (sig_wr_start = '1') then
sig_m_axi_awvalid <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_AWVALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WVALID_FLOP
--
-- Process Description:
-- Implements the write wvalid flop.
--
-------------------------------------------------------------
IMP_WVALID_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_wr_data_taken = '1') then
sig_m_axi_wvalid <= '0' ;
elsif (sig_wr_start = '1') then
sig_m_axi_wvalid <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WVALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDATA_REG
--
-- Process Description:
-- Implements the write data register.
--
-------------------------------------------------------------
IMP_WDATA_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_m_axi_wdata <= (others => '0') ;
sig_m_axi_wstrb <= (others => '0') ;
elsif (sig_wr_start = '1') then
sig_m_axi_wdata <= sig_ip2bus_mstwr_d ;
sig_m_axi_wstrb <= sig_ip2bus_be ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WDATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ERR_REG
--
-- Process Description:
-- Implements the read response error flag.
--
-------------------------------------------------------------
IMP_WR_ERR_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_write_error <= '0' ;
elsif (sig_wr_resp_taken = '1') then
sig_write_error <= sig_write_resp_error ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_DST_RDY_FLAG
--
-- Process Description:
-- Implements the IPIC write destination ready flag.
--
-------------------------------------------------------------
IMP_WR_DST_RDY_FLAG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_wr_dst_rdy = '1') then
sig_bus2ip_wr_dst_rdy <= '0' ;
--elsif (sig_wr_data_taken = '1') then
elsif (sig_wr_cmplt = '1') then
sig_bus2ip_wr_dst_rdy <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_DST_RDY_FLAG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_BREADY_FLOP
--
-- Process Description:
-- Implements the write response channel bready flop.
--
-------------------------------------------------------------
IMP_WR_BREADY_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_wr_resp_taken = '1') then
sig_m_axi_bready <= '0' ;
elsif (sig_wr_start = '1') then
sig_m_axi_bready <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_BREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_CMPLT_FLOP
--
-- Process Description:
-- Implements the write address complete flag.
--
-------------------------------------------------------------
IMP_WR_ADDR_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_wr_addr_cmplt <= '0' ;
elsif (sig_wr_addrqual_taken = '1') then
sig_wr_addr_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_ADDR_CMPLT_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_DATA_CMPLT_FLOP
--
-- Process Description:
-- Implements the write data complete flag.
--
-------------------------------------------------------------
IMP_WR_DATA_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_wr_data_cmplt <= '0' ;
elsif (sig_wr_data_taken = '1') then
sig_wr_data_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_DATA_CMPLT_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_RESP_CMPLT_FLOP
--
-- Process Description:
-- Implements the write data complete flag.
--
-------------------------------------------------------------
IMP_WR_RESP_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_wr_resp_cmplt <= '0' ;
elsif (sig_wr_resp_taken = '1') then
sig_wr_resp_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_RESP_CMPLT_FLOP;
-----------------------------------------------------------------------------
-- Generate Read Transfer Registers and Control
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_READ_IN_PROG_FLOP
--
-- Process Description:
-- Implements the read in progress flop.
--
-------------------------------------------------------------
IMP_READ_IN_PROG_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_rd_in_prog <= '0' ;
elsif (sig_rd_start = '1') then
sig_rd_in_prog <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_READ_IN_PROG_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RVALID_FLOP
--
-- Process Description:
-- Implements the write awvalid flop.
--
-------------------------------------------------------------
IMP_RVALID_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_rd_addrqual_taken = '1') then
sig_m_axi_arvalid <= '0' ;
elsif (sig_rd_start = '1') then
sig_m_axi_arvalid <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RVALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RREADY_FLOP
--
-- Process Description:
-- Implements the read rready flop.
--
-------------------------------------------------------------
IMP_RREADY_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_rd_data_taken = '1') then
sig_m_axi_rready <= '0' ;
elsif (sig_rd_start = '1') then
sig_m_axi_rready <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDATA_REG
--
-- Process Description:
-- Implements the read data register.
--
-------------------------------------------------------------
IMP_RDATA_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_bus2ip_mstrd_d <= (others => '0') ;
elsif (sig_rd_data_taken = '1') then
sig_bus2ip_mstrd_d <= sig_m_axi_rdata ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RDATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_SRC_RDY_FLAG
--
-- Process Description:
-- Implements the IPIC read source ready flag.
--
-------------------------------------------------------------
IMP_RD_SRC_RDY_FLAG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_rd_src_rdy = '1') then
sig_bus2ip_rd_src_rdy <= '0' ;
elsif (sig_rd_data_taken = '1') then
sig_bus2ip_rd_src_rdy <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RD_SRC_RDY_FLAG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_READ_ERR_REG
--
-- Process Description:
-- Implements the read response error flag.
--
-------------------------------------------------------------
IMP_READ_ERR_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_read_error <= '0' ;
elsif (sig_rd_data_taken = '1') then
sig_read_error <= sig_read_resp_error ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_READ_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_ADDR_CMPLT_FLOP
--
-- Process Description:
-- Implements the read address complete flag.
--
-------------------------------------------------------------
IMP_RD_ADDR_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_rd_addr_cmplt <= '0' ;
elsif (sig_rd_addrqual_taken = '1') then
sig_rd_addr_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RD_ADDR_CMPLT_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_DATA_CMPLT_FLOP
--
-- Process Description:
-- Implements the read data complete flag.
--
-------------------------------------------------------------
IMP_RD_DATA_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_rd_data_cmplt <= '0' ;
elsif (sig_rd_data_taken = '1') then
sig_rd_data_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_RD_DATA_CMPLT_FLOP;
-----------------------------------------------------------------------------
-- IPIC Command Status Generation logic
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMDACK_FLOP
--
-- Process Description:
-- Implements the IPIC Command Acknowledge status flag.
--
-------------------------------------------------------------
IMP_CMDACK_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmdack = '1') then
sig_bus2ip_cmdack <= '0' ;
elsif (sig_rd_addrqual_taken = '1' or
sig_wr_addrqual_taken = '1') then
sig_bus2ip_cmdack <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMDACK_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_CMPLT_LOCAL_FLOP
--
-- Process Description:
-- Implements the IPIC Command Acknowledge status flag.
--
-------------------------------------------------------------
IMP_CMD_CMPLT_LOCAL_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_bus2ip_cmplt_local <= '0' ;
elsif (sig_rd_cmplt = '1' or
sig_wr_cmplt = '1') then
sig_bus2ip_cmplt_local <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_CMPLT_LOCAL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_CMPLT_FLOP
--
-- Process Description:
-- Implements the IPIC Command Acknowledge status flag.
--
-------------------------------------------------------------
IMP_CMD_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_bus2ip_cmplt_local = '1') then
sig_bus2ip_cmplt <= '0' ;
elsif (sig_rd_cmplt = '1' or
sig_wr_cmplt = '1') then
sig_bus2ip_cmplt <= '1' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_CMPLT_FLOP;
-----------------------------------------------------------------------------
-- Master Detected error logic
-----------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_H_ERRORS
--
-- Process Description:
-- This process implements the sample and hold logic for
-- any detected errors. If an error is detected, then the
-- md_error output signal is driven high until the Master
-- is reset.
--
-------------------------------------------------------------
S_H_ERRORS : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_md_error <= '0';
elsif (sig_read_error = '1' or
sig_write_error = '1') then
sig_md_error <= '1';
else
null; -- hold last state
end if;
else
null;
end if;
end process S_H_ERRORS;
end implementation;
| bsd-3-clause | 14c7b9c2c8b19efc923ebb51147cefc2 | 0.412573 | 4.513204 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/util_intr_split_v1_00_a/hdl/vhdl/util_intr_split.vhd | 2 | 4,825 | -------------------------------------------------------------------------------
-- $Id: util_intr_split.vhd,v 1.1 2003/10/02 22:48:54 abq_ip Exp $
-------------------------------------------------------------------------------
-- util_intr_split.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_intr_split.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_intr_split.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/10/02 22:48:54 $
--
-- History:
-- goran 2003-05-19 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity util_intr_split is
generic (
C_SIZE_IN : integer := 2);
--C_LEFT_POS : integer := 0;
--C_SPLIT : integer := 1);
port (
Sig : in std_logic_vector(0 to C_SIZE_IN-1);
Out1 : out std_logic;
Out2 : out std_logic);
--Out1 : out std_logic_vector(C_LEFT_POS to C_SPLIT-1);
--Out2 : out std_logic_vector(C_SPLIT to C_SIZE_IN-1));
end entity util_intr_split;
architecture IMP of util_intr_split is
begin -- architecture IMP
Out1 <= Sig(0);
Out2 <= Sig(1);
--Out1 <= Sig(C_LEFT_POS to C_SPLIT-1);
--Out2 <= Sig(C_SPLIT to C_SIZE_IN-1);
end architecture IMP;
| bsd-3-clause | 6c155308560d08efcec5fff4886c0f49 | 0.391917 | 4.805777 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/priority_reg.vhd | 3 | 12,665 | -------------------------------------------------------------------------------
-- $Id: priority_reg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- priority_reg.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: priority_reg.vhd
-- Version: v1.02e
-- Description:
-- This file contains a priority register for each priority
-- level. A generic is passed in to specify the reset value
-- of the register. This register is either loaded with data
-- from the OPB or new data is shifted in based on the
-- priority of the master last granted the bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_VALUE -- Reset value for the register
-- C_NUM_MID_BITS -- number of bits required to encode master IDs
-- C_OPBDATA_WIDTH -- width of OPB data bus
--
-- Definition of Ports:
--
-- -- OPB Interface
-- input Priorreg_wrce -- Priority register write clock enable
-- input Bus2ip_data -- data to be loaded into priority register
--
-- -- Control Register bits
-- input Dpen -- Dynamic Priority Enable
--
-- -- Shift Signals
-- input Shift -- Shift enable
-- input Master_id_in -- Data to be shifted in
-- output Master_id_out -- Data for next priority register
-- output Priority -- Priority register output
--
-- -- Clock and Reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity priority_reg is
generic (
C_RESET_VALUE : std_logic_vector;
C_NUM_MID_BITS : integer := 2;
C_OPBDATA_WIDTH : integer := 32
);
port (
Priorreg_wrce : in std_logic;
Bus2ip_data : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Dpen : in std_logic;
Shift : in std_logic;
Master_id_in : in std_logic_vector(0 to C_NUM_MID_BITS-1);
Master_id_out : out std_logic_vector(0 to C_NUM_MID_BITS-1);
Priority : out std_logic_vector(0 to C_OPBDATA_WIDTH-1);
Clk : in std_logic;
Rst : in std_logic
);
end priority_reg;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of priority_reg is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- data is right justified in register data, calculate bit location to store
-- actual data
constant BIT_INDEX : integer := C_OPBDATA_WIDTH - C_NUM_MID_BITS;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- internal master id signal that will be assigned to output ports
signal master_id : std_logic_vector(0 to C_NUM_MID_BITS-1);
-- zero sig is used to pad the priority output with leading zeros
signal zero_sig : std_logic_vector(0 to BIT_INDEX-1);
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- PRIORITY_REG_PROCESS
-------------------------------------------------------------------------------
-- This process loads data from the OPB when there is a write request and this
-- register is enabled. If there is not a load from the OPB and dynamic
-- priority is enabled, the shift input from the SHIFT_LVLx logic will allow
-- a new Master ID to be loaded into the register.
-------------------------------------------------------------------------------
PRIORITY_REG_PROCESS:process (Clk, Rst, Priorreg_wrce, Dpen, Shift,
Bus2ip_data, Master_id_in, master_id)
begin -- process
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
master_id <= C_RESET_VALUE;
elsif Priorreg_wrce = '1' then
master_id <= Bus2ip_data(BIT_INDEX to C_OPBDATA_WIDTH-1);
elsif (Dpen = '1' and Shift = '1') then
master_id <= Master_id_in;
else
master_id <= master_id;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Output Generation
-------------------------------------------------------------------------------
zero_sig <= (others => '0');
Priority <= zero_sig & master_id;
Master_id_out <= master_id;
end implementation;
| bsd-3-clause | 09459cd6628b636bc4e896cf14c630fc | 0.417055 | 5.226991 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDEV2/IDE_top_level.vhd | 1 | 3,791 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:08:07 12/15/2015
-- Design Name:
-- Module Name: IDE_top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IDE_top_level is
Port ( W : in STD_LOGIC;
R : in STD_LOGIC;
Re : out STD_LOGIC;
CS : in STD_LOGIC;
CPU_data : inout STD_LOGIC_VECTOR (3 downto 0);
CS1FX : out STD_LOGIC;
CS3FX : out STD_LOGIC;
DA : out STD_LOGIC_VECTOR (2 downto 0);
HD_data : inout STD_LOGIC_VECTOR (7 downto 0);
DIOR : out STD_LOGIC;
DIOW : out STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
out_enables : OUT STD_LOGIC_VECTOR(2 downto 0);
wr_prev : OUT std_logic_vector (1 downto 0));
end IDE_top_level;
architecture Behavioral of IDE_top_level is
COMPONENT IDE_control_unit
PORT(
R : IN std_logic;
W : IN std_logic;
CS : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
Re : OUT std_logic;
enables : OUT std_logic_vector(2 downto 0);
data_select : OUT std_logic;
w_select : OUT std_logic;
data_enable : OUT std_logic;
wr_prev : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
component Reg is
Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
signal i_clk : STD_LOGIC;
signal i_enables : STD_LOGIC_VECTOR (2 downto 0);
signal i_data_s : STD_LOGIC;
signal i_w_select : STD_LOGIC;
signal i_data_en : STD_LOGIC;
signal i_enables_cs : STD_LOGIC_VECTOR (2 downto 0);
signal i_CMD_out : STD_LOGIC_VECTOR (3 downto 0);
signal i_D0_out : STD_LOGIC_VECTOR (3 downto 0);
signal i_D1_out : STD_LOGIC_VECTOR (3 downto 0);
signal i_CPU_data_out : STD_LOGIC_VECTOR (3 downto 0);
begin
CONTROL: IDE_control_unit PORT MAP(
R => R,
W => W,
Re => Re,
CS => CS,
enables => i_enables,
data_select => i_data_s,
clk => i_clk,
reset => not reset,
w_select => i_w_select,
wr_prev => wr_prev,
data_enable => i_data_en
);
CMD: Reg port map(
data_in => CPU_data,
data_out => i_CMD_out,
enable => i_enables_cs(0),
clk => i_clk,
rst => not reset
);
D0: Reg port map(
data_in => CPU_data,
data_out => i_D0_out,
enable => i_enables_cs(2),
clk => i_clk,
rst => not reset
);
D1: Reg port map(
data_in => CPU_data,
data_out => i_D1_out,
enable => i_enables_cs(1),
clk => i_clk,
rst => not reset
);
--Strobes
DIOR <= NOT i_data_en;
DIOW <= '1' when i_w_select = '1' else NOT W;
--Address
CS1FX <= NOT i_CMD_out(3);
CS3FX <= i_CMD_out(3);
DA <= i_CMD_out(2 downto 0);
--Data
HD_data <= i_D1_out & i_D0_out when i_data_en = '0' else "ZZZZZZZZ";
i_CPU_data_out <= HD_data(7 downto 4) when i_data_s = '0' else HD_data(3 downto 0);
CPU_data <= i_CPU_data_out when i_data_en = '1' else "ZZZZ";
i_enables_cs <= i_enables when CS = '0' else "000";
out_enables <= i_enables_cs;
i_clk <= clk;
end Behavioral;
| unlicense | 038881bb8ca327dd4baaed63053d7175 | 0.569771 | 2.936483 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/shiftL.vhd | 1 | 777 | library ieee;
use ieee.std_logic_1164.all;
ENTITY shiftL IS
generic (
width : integer := 8
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
Ci: In std_logic;
OP: IN std_logic_vector( 2 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0);
Co: out std_logic
);
END shiftL;
ARCHITECTURE behavior OF shiftL IS
begin
process( A, OP, Ci )
begin
S(width-1 downto 1) <= A(width-2 downto 0);
Co <= A(width-1);
case OP is
when "110" => --SLO
S(0) <= '0';
when "111" => --SL1
S(0) <= '1';
when "100" => --SLX
S(0) <= A(0);
when "000" => --SLA
S(0) <= Ci;
when "010" => --RL
S(0) <= A(width-1);
when others =>
S(0) <= '0';
end case;
end process;
end behavior;
| gpl-2.0 | c2e659474a99f7d7fb3b72cefac5b6e2 | 0.517375 | 2.474522 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/dma_sg.vhd | 2 | 8,083 | -------------------------------------------------------------------------------
-- $Id: dma_sg.vhd,v 1.4 2003/04/28 20:49:28 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg entity (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg.vhd
--
-- Description: Entity declaration for dma_sg.
-- This entity defines a DMA capability that is intended
-- for embodiement inside the IPIF (IP Interface).
--
-- Four types of DMA channels are available:
-- (1) Simple DMA
-- (2) Scatter gather DMA
-- (3) Scatter gather packet transmit
-- (4) Scatter gather packet receive
--
-- An arbitrary number of channels, each of any of the types,
-- may be included in an instantiation through appropriate
-- generic settings.
--
-- Packet transmit and receive channels may be outfitted with
-- optional interrupt-coalescing support.
--
-- The maximum length of DMA transfers is user selectable and
-- using the smallest feasible value may reduce FPGA resource
-- usage.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
-- -- Channels fixed at two for this version
-- -- to allow XST E.33 compatibility.
--
-- FLO 06/07/02 -- Added generic C_WFIFO_VACANCY_WIDTH.
--
-- FLO 01/30/03
-- ^^^^^^
-- Fixed Bus2IP_Data and DMA2Bus_Data at 32 bits, 0 to 31.
-- Fixed Bus2IP_BE 4 bits, 0 to 3.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.INTEGER_ARRAY_TYPE;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_ALLOW_BURST : boolean := true;
C_MA2SA_NUM_WIDTH : INTEGER := 4;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to C_DMA_CHAN_TYPE'length-1)
);
end dma_sg;
| bsd-3-clause | ac7005a7ff8bc0d239c386ec6b35e764 | 0.462205 | 4.051629 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsm2dsp.vhd | 1 | 1,769 | ---------------------------------------------------------------------------------------------------
--
-- Title : zcpsm2dsp
-- Design : baseband
-- Author : yanghb
-- Company : tsinghua
--
---------------------------------------------------------------------------------------------------
--
-- File : zcpsm2dsp.vhd
-- Generated : Tue Jan 4 16:04:14 2005
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : zcpsm to DSP interface transformer
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {zcpsm2dsp} architecture {behave}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity zcpsm2dsp is
port(
clk : in std_logic;
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0);
interrupt : out std_logic;
dsp_io : out std_logic;
dsp_rw : out std_logic;
dsp_a : out std_logic_vector(7 downto 0);
dsp_din : out std_logic_vector(7 downto 0);
dsp_dout : in std_logic_vector(7 downto 0);
dsp_int : in std_logic
);
end zcpsm2dsp;
--}} End of automatically maintained section
architecture behave of zcpsm2dsp is
begin
-- enter your statements here --
dsp_io <= clk;
dsp_rw <= not write_strobe;
dsp_a <= port_id;
dsp_din <= out_port;
in_port <= dsp_dout;
interrupt <= dsp_int;
end behave;
| gpl-2.0 | d4910881e01c07d324e88d744583cc2c | 0.471453 | 3.700837 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDEV2/IDE_control_unit.vhd | 1 | 2,757 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:27:07 12/15/2015
-- Design Name:
-- Module Name: IDE_control_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IDE_control_unit is
Port ( R : in STD_LOGIC;
W : in STD_LOGIC;
Re : out STD_LOGIC;
CS : in STD_LOGIC;
enables : out STD_LOGIC_VECTOR (2 downto 0);
data_select : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
w_select: out STD_LOGIC;
wr_prev: out STD_LOGIC_VECTOR (1 downto 0);
data_enable: out STD_LOGIC);
end IDE_control_unit;
architecture Behavioral of IDE_control_unit is
signal cycle_counter : std_logic_vector(2 downto 0) := "000";
signal prev_W : STD_LOGIC := '0';
signal prev_R : STD_LOGIC := '0';
signal i_ready : STD_LOGIC := '0';
begin
--Process to count and reset at required locations
process(clk, reset, R, W)
begin
if rising_edge(clk) and CS = '0' then
if prev_W = '1' and W = '0' then
cycle_counter <= cycle_counter + '1';
if cycle_counter = "100" then
cycle_counter <= "000";
end if;
elsif prev_R = '1' and R = '0' then
cycle_counter <= cycle_counter + '1';
if cycle_counter = "100" then
cycle_counter <= "000";
i_ready <= '0';
end if;
elsif prev_R = '0' and R = '1' then
if cycle_counter = "011" then
i_ready <= '1';
end if;
end if;
prev_W <= W;
prev_R <= R;
wr_prev <= prev_W & prev_R;
end if;
if reset = '1' then
cycle_counter <= "000";
end if;
end process;
--Combinational enable signals based on the table of signals on Google Drive
enables <= "001" when cycle_counter = "000" else
"010" when cycle_counter = "001" else
"100" when cycle_counter = "010" else
"000";
w_select <= '0' when cycle_counter = "011" else
'1';
data_select <= '0' when cycle_counter = "011" else
'1';
Re <= '1';
data_enable <= '1' when (cycle_counter = "011" AND i_ready = '1') OR
(cycle_counter = "100" AND i_ready = '1') else
'0';
end Behavioral;
| unlicense | f2a3ebe6a1f2e53a45d03652d7db7bf8 | 0.570185 | 3.239718 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/queue/Tx_queue.vhd | 1 | 3,609 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Tx_queue is
generic(
HEAD_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RAM_TYPE : string := "DIS_RAM"
);
port (
clk : in std_logic;
reset : in std_logic;
-- Tx Output
queue_empty : out std_logic;
head_raddr : in std_logic_vector(HEAD_AWIDTH - 1 downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end entity;
architecture arch_Tx_queue of Tx_queue is
component fifo_block
generic(
DWIDTH : INTEGER;
BLOCK_AWIDTH : INTEGER;
FIFO_AWIDTH : INTEGER;
RAM_TYPE : STRING);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component zcpsm2fifo
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_wr_block : out std_logic;
fifo_wren : out std_logic;
fifo_waddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_wdata : out std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_wren : std_logic;
signal fifo_waddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal fifo_wdata : std_logic_vector(7 downto 0);
signal fifo_wr_block : std_logic;
begin
u_queue : fifo_block
generic map(
DWIDTH => 8,
BLOCK_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => RAM_TYPE
)
port map(
clk => clk,
reset => reset,
clr => '0',
wr_block => fifo_wr_block,
wr_clk => zcpsm_clk,
wren => fifo_wren,
waddr => fifo_waddr,
wdata => zcpsm_out_port,
rd_block => head_rd_block,
rd_clk => clk,
raddr => head_raddr,
rdata => head_rdata,
empty => fifo_empty,
full => fifo_full
);
u_zcpsm_intf : zcpsm2fifo
generic map(
BLOCK_AWIDTH => HEAD_AWIDTH,
DWIDTH => 8
)
port map(
clk => clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
fifo_wr_block => fifo_wr_block,
fifo_wren => fifo_wren,
fifo_waddr => fifo_waddr,
fifo_wdata => fifo_wdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
queue_empty <= fifo_empty;
end arch_Tx_queue;
| gpl-2.0 | d74ef8cf2125d5abe24a76ba4960990b | 0.623441 | 2.665436 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/cond_init_1.vhd | 2 | 22,075 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_init_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * completedMutex
-- reg4 = * condvar
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of completedMutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
next_state <= STATE_6;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_6 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_8;
else
next_state <= FUNCTION_EXIT;
end if;
-- condvar = (hthread_cond_t *) malloc( sizeof( hthread_cond_t ) );
when STATE_8 =>
-- push 4B, the size of a hthread_cond_t
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call malloc
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- if ( condvar == NULL ) thread_exit_WITHERROR( NULL );
when STATE_10 =>
reg4_next <= intrfc2thrd_value;
case intrfc2thrd_value is
when x"00000000" =>
-- push null and call exit
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when others =>
next_state <= STATE_12;
end case;
when STATE_11 =>
-- Call exit with error
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT_ERROR;
thrd2intrfc_value <= Z32;
-- hthread_cond_init( condvar, NULL );
when STATE_12 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- call COND_INIT
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
next_state <= WAIT_STATE;
-- hthread_cond_signal( condvar );
when STATE_15 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call COND_SIGNAL
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_cond_destroy( condvar );
when STATE_17 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_cond_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- free( condvar );
when STATE_19 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call free
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_23 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_25 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 616b7d876090273d52f2c316348f274c | 0.557554 | 3.697036 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hwti_common_v1_00_a/hdl/vhdl/common.vhd | 2 | 8,533 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
package common is
constant HTHREAD_MTX_LOCK : std_logic_vector(0 to 7) := x"00";
constant HTHREAD_MTX_UNLOCK : std_logic_vector(0 to 7) := x"01";
constant HTHREAD_MTX_TRYLOCK : std_logic_vector(0 to 7) := x"02";
constant HTHREAD_MTX_OWNER : std_logic_vector(0 to 7) := x"03";
constant HTHREAD_MTX_KIND : std_logic_vector(0 to 7) := x"04";
constant HTHREAD_MTX_COUNT : std_logic_vector(0 to 7) := x"05";
constant HTHREAD_MTX_SETKIND : std_logic_vector(0 to 7) := x"06";
constant HTHREAD_MTX_FAST : std_logic_vector(0 to 1) := "00";
constant HTHREAD_MTX_RECURS : std_logic_vector(0 to 1) := "01";
constant HTHREAD_MTX_ERROR : std_logic_vector(0 to 1) := "10";
constant HTHREAD_CDV_OWNER : std_logic_vector(0 to 7) := x"10";
--constant HTHREAD_CDV_REQUEST : std_logic_vector(0 to 7) := x"12";
--constant HTHREAD_CDV_RELEASE : std_logic_vector(0 to 7) := x"11";
--constant HTHREAD_CDV_TRYLOCK : std_logic_vector(0 to 7) := x"13";
--constant HTHREAD_CDV_COUNT : std_logic_vector(0 to 7) := x"10";
constant HTHREAD_CDV_WAIT : std_logic_vector(0 to 7) := x"12";
--constant HTHREAD_CDV_POST : std_logic_vector(0 to 7) := x"13";
constant HTHREAD_CDV_SIGNAL : std_logic_vector(0 to 7) := x"11";
--constant HTHREAD_CDV_CWAIT : std_logic_vector(0 to 7) := x"12";
constant HTHREAD_CDV_BROAD : std_logic_vector(0 to 7) := x"13";
constant HTHREAD_THR_CLEAR : std_logic_vector(0 to 7) := x"20";
constant HTHREAD_THR_JOIN : std_logic_vector(0 to 7) := x"21";
constant HTHREAD_THR_DETACH : std_logic_vector(0 to 7) := x"22";
constant HTHREAD_THR_ADD : std_logic_vector(0 to 7) := x"24";
constant HTHREAD_THR_EXIT : std_logic_vector(0 to 7) := x"27";
--constant HTHREAD_THR_YIELD : std_logic_vector(0 to 7) := x"29";
--constant HTHREAD_THR_CREATEJ : std_logic_vector(0 to 7) := x"25";
--constant HTHREAD_THR_CREATED : std_logic_vector(0 to 7) := x"26";
constant HTHREAD_MEM_READ : std_logic_vector(0 to 7) := x"30";
constant HTHREAD_MEM_WRITE : std_logic_vector(0 to 7) := x"31";
constant STATUS_NOT_USED : std_logic_vector(0 to 7) := x"00";
constant STATUS_USED : std_logic_vector(0 to 7) := x"01";
constant STATUS_RUNNING : std_logic_vector(0 to 7) := x"02";
constant STATUS_BLOCKED : std_logic_vector(0 to 7) := x"04";
constant STATUS_EXITED : std_logic_vector(0 to 7) := x"08";
constant STATUS_ERROR : std_logic_vector(0 to 7) := x"20";
constant COMMAND_INIT : std_logic_vector(0 to 3) := x"0";
constant COMMAND_RUN : std_logic_vector(0 to 3) := x"1";
constant COMMAND_RESET : std_logic_vector(0 to 3) := x"2";
constant COMMAND_COLDBOOT : std_logic_vector(0 to 3) := x"4";
constant COMMAND_NOTUSED : std_logic_vector(0 to 3) := x"8";
subtype tfsl is std_logic_vector(0 to 63);
subtype tcmd is std_logic_vector(0 to 7);
subtype ttid is std_logic_vector(0 to 7);
subtype tmid is std_logic_vector(0 to 5);
subtype tcid is std_logic_vector(0 to 5);
subtype tknd is std_logic_vector(0 to 1);
subtype tbyt is std_logic_vector(0 to 23);
subtype targ is std_logic_vector(0 to 31);
subtype taddr is std_logic_vector(0 to 31);
function hwti_mtx_cmd( cmd : tcmd; mtx : tmid; knd : tknd ) return tfsl;
function hwti_mtx_lock( mtx : tmid ) return tfsl;
function hwti_mtx_unlock( mtx : tmid ) return tfsl;
function hwti_mtx_trylock( mtx : tmid ) return tfsl;
function hwti_mtx_owner( mtx : tmid ) return tfsl;
function hwti_mtx_kind( mtx : tmid ) return tfsl;
function hwti_mtx_setkind( mtx : tmid; knd : tknd ) return tfsl;
function hwti_mtx_count( mtx : tmid ) return tfsl;
function hwti_cdv_cmd( cmd : tcmd; cdv : tcid ) return tfsl;
function hwti_cdv_owner( cdv : tcid ) return tfsl;
function hwti_cdv_wait( cdv : tcid ) return tfsl;
function hwti_cdv_signal( cdv : tcid ) return tfsl;
function hwti_cdv_broadcast( cdv : tcid ) return tfsl;
function hwti_mem_cmd( cmd:tcmd; addr:taddr; bytes:tbyt ) return tfsl;
function hwti_mem_read( addr : taddr; bytes : tbyt ) return tfsl;
function hwti_mem_write( addr : taddr; bytes : tbyt ) return tfsl;
function hwti_thr_cmd( cmd:tcmd; arg:targ ) return tfsl;
function hwti_thr_join( tid:ttid ) return tfsl;
function hwti_thr_exit( arg:targ ) return tfsl;
function hwti_thr_clear( tid:ttid ) return tfsl;
function hwti_thr_detach return tfsl;
function hwti_thr_add( tid:ttid ) return tfsl;
procedure hwti_wake( signal result : in tfsl;
signal tid : out ttid;
signal arg : out targ );
end package;
package body common is
function hwti_mtx_cmd( cmd : tcmd; mtx : tmid; knd : tknd ) return tfsl is
begin
return cmd & x"0000" & knd & mtx & x"00000000";
end function;
function hwti_mtx_lock( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_LOCK, mtx, "00" );
end function;
function hwti_mtx_unlock( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_UNLOCK, mtx, "00" );
end function;
function hwti_mtx_trylock( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_TRYLOCK, mtx, "00" );
end function;
function hwti_mtx_owner( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_OWNER, mtx, "00" );
end function;
function hwti_mtx_kind( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_KIND, mtx, "00" );
end function;
function hwti_mtx_setkind( mtx : tmid; knd : tknd ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_SETKIND, mtx, knd );
end function;
function hwti_mtx_count( mtx : tmid ) return tfsl is
begin
return hwti_mtx_cmd( HTHREAD_MTX_COUNT, mtx, "00" );
end function;
function hwti_cdv_cmd( cmd : tcmd; cdv : tcid ) return tfsl is
begin
return cmd & x"0000" & "00" & cdv & x"00000000";
end function;
function hwti_cdv_owner( cdv : tcid ) return tfsl is
begin
return hwti_cdv_cmd( HTHREAD_CDV_OWNER, cdv );
end function;
function hwti_cdv_wait( cdv : tcid ) return tfsl is
begin
return hwti_cdv_cmd( HTHREAD_CDV_WAIT, cdv );
end function;
function hwti_cdv_signal( cdv : tcid ) return tfsl is
begin
return hwti_cdv_cmd( HTHREAD_CDV_SIGNAL, cdv );
end function;
function hwti_cdv_broadcast( cdv : tcid ) return tfsl is
begin
return hwti_cdv_cmd( HTHREAD_CDV_BROAD, cdv );
end function;
function hwti_mem_cmd( cmd:tcmd; addr:taddr; bytes:tbyt ) return tfsl is
begin
return cmd & bytes & addr;
end function;
function hwti_mem_read( addr : taddr; bytes : tbyt ) return tfsl is
begin
return hwti_mem_cmd( HTHREAD_MEM_READ, addr, bytes );
end function;
function hwti_mem_write( addr : taddr; bytes : tbyt ) return tfsl is
begin
return hwti_mem_cmd( HTHREAD_MEM_WRITE, addr, bytes );
end function;
function hwti_thr_cmd( cmd : tcmd; arg : targ ) return tfsl is
begin
return cmd & x"000000" & arg;
end function;
function hwti_thr_join( tid : ttid ) return tfsl is
begin
return hwti_thr_cmd( HTHREAD_THR_EXIT, x"000000" & tid );
end function;
function hwti_thr_exit( arg : targ ) return tfsl is
begin
return hwti_thr_cmd( HTHREAD_THR_EXIT, arg );
end function;
function hwti_thr_clear( tid:ttid ) return tfsl is
begin
return hwti_thr_cmd( HTHREAD_THR_CLEAR, x"000000" & tid );
end function;
function hwti_thr_detach return tfsl is
begin
return hwti_thr_cmd( HTHREAD_THR_DETACH, x"00000000" );
end function;
function hwti_thr_add( tid:ttid ) return tfsl is
begin
return hwti_thr_cmd( HTHREAD_THR_ADD, x"000000" & tid );
end function;
procedure hwti_wake( signal result : in tfsl;
signal tid : out ttid;
signal arg : out targ ) is
begin
tid <= result(24 to 31);
arg <= result(32 to 63);
end procedure;
end package body;
| bsd-3-clause | 8af7f0a4e194b0f748231c47e005bf87 | 0.626392 | 3.333203 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_hthreads_timer_v1_00_a/hdl/vhdl/plb_hthreads_timer.vhd | 9 | 24,036 | ------------------------------------------------------------------------------
-- plb_hthreads_timer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_hthreads_timer.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_hthreads_timer_v1_00_a;
use plb_hthreads_timer_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_hthreads_timer is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_hthreads_timer;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_hthreads_timer is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hthreads_timer_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause | 2508b068e183f32516f54c4575877ec2 | 0.452072 | 4.423261 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd | 2 | 16,056 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v3_00_a.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v3_00_a.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
| bsd-3-clause | 95e62515c98dd33165504a7067e826b1 | 0.449738 | 4.981694 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_crc_v1_00_a/hdl/vhdl/hw_acc_crc.vhd | 2 | 4,167 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_crc is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_crc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_crc is
component crc is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
uut : crc
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_dout,
array_dOUT0 => BRAM_A_din,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | 4e20b2ec3a0805d1b1dd65bf5f552c08 | 0.542597 | 3.14966 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_pctrl.vhd | 1 | 18,872 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF FiFo512Core32W32R_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:FiFo512Core32W32R_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 933ebd4743f9f9f80b331bb4dfde778a | 0.495973 | 3.297571 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_thread_manager_v1_00_a/hdl/vhdl/axi_thread_manager.vhd | 2 | 19,768 | ------------------------------------------------------------------------------
-- axi_thread_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_thread_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Jun 24 20:43:34 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_thread_manager_v1_00_a;
use axi_thread_manager_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_thread_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_RESET_TIMEOUT : natural := 4096;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"0000FFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_thread_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_thread_manager is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_thread_manager_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_RESET_TIMEOUT => C_RESET_TIMEOUT,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
| bsd-3-clause | 6a1a98d6e49e74c7b3e289b3981e900a | 0.458013 | 4.035109 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/vivado_archgen/pr/acc/hdl_wrapper.vhd | 2 | 4,974 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc is
component user_logic is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : vector_chan
port map (
Vector_A_addr0 => BRAM_A_addr,
Vector_A_dIN0 => BRAM_A_din,
Vector_A_dOUT0 => BRAM_A_dout,
Vector_A_rENA0 => BRAM_A_en,
Vector_A_wENA0 => BRAM_A_wen,
Vector_B_addr0 => BRAM_B_addr,
Vector_B_dIN0 => BRAM_B_din,
Vector_B_dOUT0 => BRAM_B_dout,
Vector_B_rENA0 => BRAM_B_en,
Vector_B_wENA0 => BRAM_B_wen,
Vector_C_addr0 => BRAM_C_addr,
Vector_C_dIN0 => BRAM_C_din,
Vector_C_dOUT0 => BRAM_C_dout,
Vector_C_rENA0 => BRAM_C_en,
Vector_C_wENA0 => BRAM_C_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause | 460892963c7bdeac43cf87d47f098900 | 0.577402 | 2.964243 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/xps_intc_v2_01_a/hdl/vhdl/xps_intc.vhd | 2 | 27,719 | -------------------------------------------------------------------------------
-- xps_intc - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xps_intc.vhd
-- Version: v2.01a
-- Description: Interrupt controller interfaced to plb v46 bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- xps_intc.vhd (wrapper for top level)
-- -- plbv46_slave_single
-- -plb_slave_attachment
-- -plb_address_decoder
-- -- intc_core
--
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 2/23/2007 First version
-- ^^^^^^^
-- Version xps_intc v1.00a functionality is based on opb_intc v1.00c wherein
-- the design is completed recoded for better readiabilty, save resources,
-- increase frequecny and remove the structural code. This provides interface
-- to plb_v46 bus.
-- ~~~~~~~
-- NSK 7/31/2007
-- ^^^^^^^
-- 1. Modified the generation of CE. Now generating 4 CEs to fix the problem
-- reported while accessign non existing address location with the updated
-- plbv46_slave_single design.
-- 2. Modified generation of ip2bus_rdack_int & ip2bus_wrack_int.
-- 3. Removed the bit (0) from the port mapping of intc_core. The signals
-- bus2ip_rdce and bus2ip_wrce are 8-bit.
-- 4. Removed unused ports Wr_ack & Rd_ack from port mapping of intc_core.
-- ~~~~~~~
-- NSK 9/13/2008 version v2.00a
-- ^^^^^^^
-- NSK 9/13/2008
-- ^^^^^^^
-- 1. Rolled to revision v2.00a.
-- 2. Removed the old EDK Changlog as per guideline.
-- 3. Changed the library proc_common from v2_00_a to v3_00_a.
-- 4. Changed the library plbv46_slave_single from v1_00_a to v1_01_a.
-- 5. Changed the library xps_intc from v1_00_a to v2_00_a.
-- 6. Fixed CR #442790 to support edge on Irq.
-- I. Added generic C_IRQ_IS_LEVEL
-- a. If set to 0 generates edge interrupt
-- b. If set to 1 generates level interrupt
-- II. Changed the definition of generic C_IRQ_ACTIVE
-- a. Defines the edge for output interrupt if C_IRQ_IS_LEVEL=0
-- "0" = FALLING EDGE
-- "1" = RISING EDGE
-- b. Defines the level for output interrupt if C_IRQ_IS_LEVEL=1
-- "0" = LOW LEVEL
-- "1" = HIGH LEVEL
-- III. Added generic C_IRQ_IS_LEVEL in generic map of instance INTC_CORE_I
-- for component "intc_core" from library "xps_intc_v2_00_a."
-- IV. Added "C_IRQ_IS_LEVEL" in Definition of Generics section in
-- comments.
-- ~~~~~~~
-- NSK 9/15/2008
-- ^^^^^^^
-- Removed unused parameter C_FAMILY from the instance of intc_core.
-- ~~~~~~~
-- NSK 9/23/2008
-- ^^^^^^^
-- Removed XRANGE PSFUtil attribute. As per new guidline this is part of
-- prime.mpd and not hdl.mpd.
-- ~~~~~~~
-- NSK 9/30/2008
-- ^^^^^^^
-- 1. Removed unused signals "wr_ack" & "rd_ack" from signal declaration.
-- 2. Updated for code review
-- A. Added C_INCLUDE_DPHASE_TIMER in the generic map of
-- plbv46_slave_single and tied to 1.
-- B. Reduce one clock delay in assertion of "Ack"
-- a. ip2bus_rdack is assigned to the registered output of
-- ip2bus_rdack_prev2.
-- b. ip2bus_wrack is assigned to the registered output of
-- ip2bus_wrack_prev2.
-- c. Removed unused signals ip2bus_rdack_prev1 & ip2bus_wrack_prev1.
-- ~~~~~~~
-- NSK 10/01/2008
-- ^^^^^^^
-- Updated the latest Copyright and removed XCS label.
-- ~~~~~~~
-- ~~~~~~~
-- BSB 01/31/2010
-- ^^^^^^^
-- New version v2.01.a created. attribute buffer type added on signal Intr
-- ~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v3_00_a;
-------------------------------------------------------------------------
-- Package proc_common_pkg is used because it contains the RESET_ACTIVE
-- constant used to assign reset as active high status.
-------------------------------------------------------------------------
use proc_common_v3_00_a.proc_common_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------
-- Package ipif_pkg is used because it contains the calc_num_ce,
-- INTEGER_ARRAY_TYPE & SLV64_ARRAY_TYPE.
-- 1. calc_num_ce is used to get the number of chip selects.
-- INTEGER_ARRAY_TYPE is used for type declaration on constants
-- 2. ARD_ID_ARRAY & ARD_NUM_CE_ARRAY.
-- type declaration on constants ARD_ID_ARRAY & ARD_NUM_CE_ARRAY.
-- 3. SLV64_ARRAY_TYPE is used for type declaration on constants
-- on constants ARD_ADDR_RANGE_ARRAY.
-------------------------------------------------------------------------
use proc_common_v3_00_a.ipif_pkg.calc_num_ce;
use proc_common_v3_00_a.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v3_00_a.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------
-- Library plbv46_slave_single_v1_01_a is used because it contains the
-- plbv46_slave_single which interraces intc_core to plb_v46.
-------------------------------------------------------------------------
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-------------------------------------------------------------------------
-- Library xps_intc_v2_01_a is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library xps_intc_v2_01_a;
use xps_intc_v2_01_a.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- System Parameter
-- C_FAMILY -- Target FPGA family
-- -- PLB Parameters
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_SPLB_AWIDTH -- PLBv46 address bus width
-- C_SPLB_DWIDTH -- PLBv46 data bus width
-- C_SPLB_P2P -- Selects point-to-point or shared plb topology
-- C_SPLB_NUM_MASTERS -- Number of PLB Masters
-- C_SPLB_MID_WIDTH -- PLB Master ID Bus Width
-- C_SPLB_NATIVE_DWIDTH -- Width of the slave data bus
-- C_SPLB_SUPPORT_BURSTS -- Burst support
-- -- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
--
-------------------------------------------------------------------------------
-- Definition of Ports:
-- -- Clocks and reset
-- SPLB_Clk -- PLB clock
-- SPLB_Rst -- PLB Reset
-- -- PLB Interface Signals
-- PLB_ABus -- PLB address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_masterID -- PLB current master indicator
-- PLB_RNW -- PLB read not write
-- PLB_BE -- PLB byte enables
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_wrDBus -- PLB write data bus
-- -- Unused PLB Interface Signals
-- PLB_UABus -- Slave address bits
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_abort -- PLB abort bus request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_MSize -- PLB master data bus size
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB pending write request
-- PLB_rdPendReq -- PLB pending read request
-- PLB_wrPendPri -- PLB pending write request priority
-- PLB_rdPendPri -- PLB pending read request priority
-- PLB_reqPri -- PLB request priority
-- PLB_TAttribute -- PLB transfer attribute
-- -- PLB Slave Interface Signals
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus sizer
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave rearbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_rdDBus -- Slave read bus
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- -- Unused PLB Slave Interface Signals
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MIRQ -- Slave interrupt indicator
-- -- Intc Interface Signals
-- Intr -- Input Interruput request
-- Irq -- Output Interruput request
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity xps_intc is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex5";
-- -- PLB Parameters
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_P2P : integer range 0 to 1 := 0;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 1;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 1;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_SUPPORT_BURSTS : integer := 0;
-- -- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1'
);
port
(
-- -- System Signals
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
-- -- PLB Interface Signals
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- -- Unused PLB Interface Signals
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
-- -- PLB Slave Interface Signals
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector (0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector (0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector (0 to C_SPLB_NUM_MASTERS-1);
-- -- Unused PLB Slave Interface Signals
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector (0 to C_SPLB_NUM_MASTERS-1);
-- -- Intc Interface Signals
Intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
Irq : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of SPLB_Clk : signal is "10000";
ATTRIBUTE MAX_FANOUT of SPLB_Rst : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of xps_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of xps_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of xps_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of xps_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of xps_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of xps_intc : entity is "TRUE";
ATTRIBUTE ADDR_TYPE : string;
ATTRIBUTE ADDR_TYPE of C_BASEADDR : constant is "REGISTER";
ATTRIBUTE ADDR_TYPE of C_HIGHADDR : constant is "REGISTER";
ATTRIBUTE ASSIGNMENT : string;
ATTRIBUTE ASSIGNMENT of C_BASEADDR : constant is "REQUIRE";
ATTRIBUTE ASSIGNMENT of C_HIGHADDR : constant is "REQUIRE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of SPLB_Clk : signal is "Clk";
ATTRIBUTE SIGIS of SPLB_Rst : signal is "Rst";
end xps_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of xps_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_SPLB_AWIDTH-1)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & C_BASEADDR,
ZERO_ADDR_PAD & (C_BASEADDR or X"0000001F")
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => 8);
constant BUS2CORE_CLK_RATIO : integer := 1;
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_address : std_logic_vector(2 downto 0);
signal read_data : std_logic_vector(C_SPLB_NATIVE_DWIDTH-1 downto 0);
signal write_data : std_logic_vector(C_SPLB_NATIVE_DWIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to ARD_ID_ARRAY'LENGTH-1);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_be : std_logic_vector(0 to (C_SPLB_NATIVE_DWIDTH/8)-1);
signal word_access : std_logic;
begin
register_address <= bus2ip_addr(C_SPLB_AWIDTH-5 to C_SPLB_AWIDTH-3);
-- Internal ack signals
ip2bus_rdack_int <= bus2ip_rdce(0) or bus2ip_rdce(1) or bus2ip_rdce(2) or
bus2ip_rdce(3) or bus2ip_rdce(4) or bus2ip_rdce(5) or
bus2ip_rdce(6) or bus2ip_rdce(7);
ip2bus_wrack_int <= bus2ip_wrce(0) or bus2ip_wrce(1) or bus2ip_wrce(2) or
bus2ip_wrce(3) or bus2ip_wrce(4) or bus2ip_wrce(5) or
bus2ip_wrce(6) or bus2ip_wrce(7);
-- Error signal generation
word_access <= bus2ip_be(0) and bus2ip_be(1) and bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-- Instantiating intc_core from xps_intc_v2_01_a library
INTC_CORE_I : entity xps_intc_v2_01_a.intc_core
generic map
(
C_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE
)
port map
(
-- Inputs
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Intr => Intr,
Reg_addr => register_address,
Valid_rd => bus2ip_rdce,
Valid_wr => bus2ip_wrce,
Wr_data => write_data,
-- Outputs
Rd_data => read_data,
Irq => Irq
);
--Instantiating plbv46_slave_single from plbv46_slave_single_v1_01_a library
PLBV46_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => BUS2CORE_CLK_RATIO,
C_INCLUDE_DPHASE_TIMER => 1,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
-- System signals
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
-- Bus Slave signals
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
-- Slave Response Signals
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => write_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end imp;
| bsd-3-clause | db6e3601704853b0b8fc0e29c73c5918 | 0.511815 | 4.001588 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hls_cores/vector_add/vectoradd_prj/solution1/impl/ip/hdl/vhdl/vectoradd.vhd | 2 | 22,295 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vectoradd is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
cmd_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
cmd_TVALID : IN STD_LOGIC;
cmd_TREADY : OUT STD_LOGIC;
resp_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
resp_TVALID : OUT STD_LOGIC;
resp_TREADY : IN STD_LOGIC;
a_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_EN_A : OUT STD_LOGIC;
a_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
a_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
a_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
a_Clk_A : OUT STD_LOGIC;
a_Rst_A : OUT STD_LOGIC;
b_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_EN_A : OUT STD_LOGIC;
b_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
b_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
b_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
b_Clk_A : OUT STD_LOGIC;
b_Rst_A : OUT STD_LOGIC;
result_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_EN_A : OUT STD_LOGIC;
result_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
result_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
result_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
result_Clk_A : OUT STD_LOGIC;
result_Rst_A : OUT STD_LOGIC );
end;
architecture behav of vectoradd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"vectoradd,hls_ip_2014_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx485tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.410000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal op_reg_209 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal end_reg_215 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_151_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_227 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_fu_156_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_231 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_166_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_1_reg_132_temp: signed (32-1 downto 0);
signal tmp_7_reg_238 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_fu_178_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_resp_TREADY : STD_LOGIC;
signal i_3_fu_172_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_reg_253 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_183_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal i_reg_141_temp: signed (32-1 downto 0);
signal tmp_3_reg_261 : STD_LOGIC_VECTOR (63 downto 0);
signal i_2_fu_189_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_reg_276 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_132 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_141 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ioackin_resp_TREADY : STD_LOGIC := '0';
signal a_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal b_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_195_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_202_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal result_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
signal ap_sig_bdd_91 : BOOLEAN;
signal ap_sig_bdd_102 : BOOLEAN;
signal ap_sig_bdd_129 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_resp_TREADY assign process. --
ap_reg_ioackin_resp_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_129) then
if (not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY)))) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = resp_TREADY)) then
ap_reg_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_132 assign process. --
i_1_reg_132_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_fu_151_p2 = ap_const_lv1_0) and not((tmp_1_fu_156_p2 = ap_const_lv1_0)))) then
i_1_reg_132 <= cmd_TDATA;
elsif ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
i_1_reg_132 <= i_3_reg_253;
end if;
end if;
end process;
-- i_reg_141 assign process. --
i_reg_141_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_fu_151_p2 = ap_const_lv1_0)))) then
i_reg_141 <= cmd_TDATA;
elsif ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
i_reg_141 <= i_2_reg_276;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm))) then
end_reg_215 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((tmp_reg_227 = ap_const_lv1_0)) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((ap_const_lv1_0 = tmp_2_fu_178_p2)))) then
i_2_reg_276 <= i_2_fu_189_p2;
tmp_3_reg_261 <= tmp_3_fu_183_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st5_fsm_4 = ap_CS_fsm) and (tmp_reg_227 = ap_const_lv1_0) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((tmp_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_6_fu_161_p2)))) then
i_3_reg_253 <= i_3_fu_172_p2;
tmp_7_reg_238 <= tmp_7_fu_166_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0)))) then
op_reg_209 <= cmd_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_fu_151_p2 = ap_const_lv1_0))) then
tmp_1_reg_231 <= tmp_1_fu_156_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
tmp_reg_227 <= tmp_fu_151_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (cmd_TVALID, ap_CS_fsm, tmp_reg_227, tmp_1_reg_231, tmp_2_fu_178_p2, tmp_6_fu_161_p2, ap_sig_ioackin_resp_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st2_fsm_1 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((cmd_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((tmp_reg_227 = ap_const_lv1_0)) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((ap_const_lv1_0 = tmp_2_fu_178_p2)))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
elsif (((tmp_reg_227 = ap_const_lv1_0) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((tmp_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_6_fu_161_p2)))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
a_Addr_A <= std_logic_vector(shift_left(unsigned(a_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- a_Addr_A_orig assign process. --
a_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_7_fu_166_p1, tmp_3_fu_183_p1, ap_sig_bdd_91, ap_sig_bdd_102)
begin
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
if (ap_sig_bdd_102) then
a_Addr_A_orig <= tmp_3_fu_183_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_91) then
a_Addr_A_orig <= tmp_7_fu_166_p1(32 - 1 downto 0);
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
a_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
a_Clk_A <= ap_clk;
a_Din_A <= ap_const_lv32_0;
-- a_EN_A assign process. --
a_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_227, tmp_1_reg_231, tmp_2_fu_178_p2, tmp_6_fu_161_p2, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and (tmp_reg_227 = ap_const_lv1_0) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((tmp_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_6_fu_161_p2))) or ((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((tmp_reg_227 = ap_const_lv1_0)) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((ap_const_lv1_0 = tmp_2_fu_178_p2))))) then
a_EN_A <= ap_const_logic_1;
else
a_EN_A <= ap_const_logic_0;
end if;
end process;
a_Rst_A <= ap_rst_n;
a_WEN_A <= ap_const_lv4_0;
-- ap_sig_bdd_102 assign process. --
ap_sig_bdd_102_assign_proc : process(tmp_reg_227, tmp_2_fu_178_p2)
begin
ap_sig_bdd_102 <= (not((tmp_reg_227 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_2_fu_178_p2)));
end process;
-- ap_sig_bdd_129 assign process. --
ap_sig_bdd_129_assign_proc : process(ap_CS_fsm, tmp_reg_227, tmp_1_reg_231, tmp_2_fu_178_p2, tmp_6_fu_161_p2)
begin
ap_sig_bdd_129 <= ((ap_ST_st5_fsm_4 = ap_CS_fsm) and (((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))));
end process;
-- ap_sig_bdd_91 assign process. --
ap_sig_bdd_91_assign_proc : process(tmp_reg_227, tmp_1_reg_231, tmp_6_fu_161_p2)
begin
ap_sig_bdd_91 <= ((tmp_reg_227 = ap_const_lv1_0) and not((tmp_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_6_fu_161_p2)));
end process;
-- ap_sig_ioackin_resp_TREADY assign process. --
ap_sig_ioackin_resp_TREADY_assign_proc : process(resp_TREADY, ap_reg_ioackin_resp_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_resp_TREADY)) then
ap_sig_ioackin_resp_TREADY <= resp_TREADY;
else
ap_sig_ioackin_resp_TREADY <= ap_const_logic_1;
end if;
end process;
b_Addr_A <= std_logic_vector(shift_left(unsigned(b_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- b_Addr_A_orig assign process. --
b_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_7_fu_166_p1, tmp_3_fu_183_p1, ap_sig_bdd_91, ap_sig_bdd_102)
begin
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
if (ap_sig_bdd_102) then
b_Addr_A_orig <= tmp_3_fu_183_p1(32 - 1 downto 0);
elsif (ap_sig_bdd_91) then
b_Addr_A_orig <= tmp_7_fu_166_p1(32 - 1 downto 0);
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
b_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
b_Clk_A <= ap_clk;
b_Din_A <= ap_const_lv32_0;
-- b_EN_A assign process. --
b_EN_A_assign_proc : process(ap_CS_fsm, tmp_reg_227, tmp_1_reg_231, tmp_2_fu_178_p2, tmp_6_fu_161_p2, ap_sig_ioackin_resp_TREADY)
begin
if ((((ap_ST_st5_fsm_4 = ap_CS_fsm) and (tmp_reg_227 = ap_const_lv1_0) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((tmp_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_6_fu_161_p2))) or ((ap_ST_st5_fsm_4 = ap_CS_fsm) and not((tmp_reg_227 = ap_const_lv1_0)) and not(((((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_sig_ioackin_resp_TREADY))) and not((ap_const_lv1_0 = tmp_2_fu_178_p2))))) then
b_EN_A <= ap_const_logic_1;
else
b_EN_A <= ap_const_logic_0;
end if;
end process;
b_Rst_A <= ap_rst_n;
b_WEN_A <= ap_const_lv4_0;
-- cmd_TREADY assign process. --
cmd_TREADY_assign_proc : process(cmd_TVALID, ap_CS_fsm)
begin
if ((((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((cmd_TVALID = ap_const_logic_0))) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm)) or (not((cmd_TVALID = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm)))) then
cmd_TREADY <= ap_const_logic_1;
else
cmd_TREADY <= ap_const_logic_0;
end if;
end process;
i_2_fu_189_p2 <= std_logic_vector(unsigned(i_reg_141) + unsigned(ap_const_lv32_1));
i_3_fu_172_p2 <= std_logic_vector(unsigned(i_1_reg_132) + unsigned(ap_const_lv32_1));
resp_TDATA <= ap_const_lv32_1;
-- resp_TVALID assign process. --
resp_TVALID_assign_proc : process(ap_CS_fsm, tmp_reg_227, tmp_1_reg_231, tmp_2_fu_178_p2, tmp_6_fu_161_p2, ap_reg_ioackin_resp_TREADY)
begin
if (((ap_ST_st5_fsm_4 = ap_CS_fsm) and (((tmp_reg_227 = ap_const_lv1_0) and (tmp_1_reg_231 = ap_const_lv1_0)) or (not((tmp_reg_227 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_2_fu_178_p2)) or ((tmp_reg_227 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_6_fu_161_p2))) and (ap_const_logic_0 = ap_reg_ioackin_resp_TREADY))) then
resp_TVALID <= ap_const_logic_1;
else
resp_TVALID <= ap_const_logic_0;
end if;
end process;
result_Addr_A <= std_logic_vector(shift_left(unsigned(result_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
-- result_Addr_A_orig assign process. --
result_Addr_A_orig_assign_proc : process(ap_CS_fsm, tmp_7_reg_238, tmp_3_reg_261)
begin
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_3_reg_261(32 - 1 downto 0);
elsif ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Addr_A_orig <= tmp_7_reg_238(32 - 1 downto 0);
else
result_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
result_Clk_A <= ap_clk;
-- result_Din_A assign process. --
result_Din_A_assign_proc : process(ap_CS_fsm, tmp_8_fu_195_p2, tmp_4_fu_202_p2)
begin
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_Din_A <= tmp_4_fu_202_p2;
elsif ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
result_Din_A <= tmp_8_fu_195_p2;
else
result_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- result_EN_A assign process. --
result_EN_A_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
result_EN_A <= ap_const_logic_1;
else
result_EN_A <= ap_const_logic_0;
end if;
end process;
result_Rst_A <= ap_rst_n;
-- result_WEN_A assign process. --
result_WEN_A_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
result_WEN_A <= ap_const_lv4_F;
else
result_WEN_A <= ap_const_lv4_0;
end if;
end process;
tmp_1_fu_156_p2 <= "1" when (op_reg_209 = ap_const_lv32_2) else "0";
tmp_2_fu_178_p2 <= "1" when (signed(i_reg_141) < signed(end_reg_215)) else "0";
i_reg_141_temp <= signed(i_reg_141);
tmp_3_fu_183_p1 <= std_logic_vector(resize(i_reg_141_temp,64));
tmp_4_fu_202_p2 <= std_logic_vector(unsigned(b_Dout_A) + unsigned(a_Dout_A));
tmp_6_fu_161_p2 <= "1" when (signed(i_1_reg_132) < signed(end_reg_215)) else "0";
i_1_reg_132_temp <= signed(i_1_reg_132);
tmp_7_fu_166_p1 <= std_logic_vector(resize(i_1_reg_132_temp,64));
tmp_8_fu_195_p2 <= std_logic_vector(unsigned(a_Dout_A) - unsigned(b_Dout_A));
tmp_fu_151_p2 <= "1" when (op_reg_209 = ap_const_lv32_1) else "0";
end behav;
| bsd-3-clause | 847832b08cae5b98d7f80082c6a35171 | 0.567571 | 2.674865 | false | false | false | false |
sorgelig/SAMCoupe_MIST | sid/sid_mixer.vhd | 6 | 3,710 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sid_mixer is
port (
clock : in std_logic;
reset : in std_logic;
valid_in : in std_logic := '0';
direct_out : in signed(17 downto 0);
high_pass : in signed(17 downto 0);
band_pass : in signed(17 downto 0);
low_pass : in signed(17 downto 0);
filter_hp : in std_logic;
filter_bp : in std_logic;
filter_lp : in std_logic;
volume : in unsigned(3 downto 0);
mixed_out : out signed(17 downto 0);
valid_out : out std_logic );
end sid_mixer;
architecture arith of sid_mixer is
signal mix_i : signed(17 downto 0);
signal mix_uns : unsigned(16 downto 0);
signal vol_uns : unsigned(16 downto 0);
signal vol_s : signed(16 downto 0);
signal state : integer range 0 to 7;
signal p_mul : unsigned(33 downto 0);
signal p_mul_s : signed(34 downto 0);
type t_volume_lut is array(natural range <>) of unsigned(15 downto 0);
constant c_volume_lut : t_volume_lut(0 to 15) := (
X"0000", X"0EEF", X"1DDE", X"2CCD", X"3BBC", X"4AAA", X"5999", X"6888",
X"7777", X"8666", X"9555", X"A444", X"B333", X"C221", X"D110", X"DFFF" );
begin
process(clock)
variable mix_total : signed(17 downto 0);
begin
if rising_edge(clock) then
valid_out <= '0';
state <= state + 1;
case state is
when 0 =>
if valid_in = '1' then
mix_i <= sum_limit(direct_out, to_signed(16384, 18));
else
state <= 0;
end if;
when 1 =>
if filter_hp='1' then
mix_i <= sum_limit(mix_i, high_pass);
end if;
when 2 =>
if filter_bp='1' then
mix_i <= sum_limit(mix_i, band_pass);
end if;
when 3 =>
if filter_lp='1' then
mix_i <= sum_limit(mix_i, low_pass);
end if;
when 4 =>
-- p_mul <= mix_uns * vol_uns;
p_mul_s <= mix_i * vol_s;
valid_out <= '1';
state <= 0;
when others =>
state <= 0;
end case;
-- mix_total := not(p_mul(32)) & signed(p_mul(31 downto 15));
-- mixed_out <= mix_total; -- + to_signed(16384, 18);
mixed_out <= p_mul_s(33 downto 16);
if reset='1' then
mix_i <= (others => '0');
state <= 0;
end if;
end if;
end process;
-- vol_uns <= "0" & volume & volume & volume & volume;
-- vol_uns <= '0' & c_volume_lut(to_integer(volume));
-- mix_uns <= not mix_i(17) & unsigned(mix_i(16 downto 1));
vol_s <= '0' & signed(c_volume_lut(to_integer(volume)));
end arith;
| gpl-2.0 | 04d11131d3db8f53eb07cf929716f243 | 0.440162 | 3.747475 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/sim/zynq_1_axi_quad_spi_0_0.vhd | 1 | 17,046 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_1;
USE axi_quad_spi_v3_1.axi_quad_spi;
ENTITY zynq_1_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END zynq_1_axi_quad_spi_0_0;
ARCHITECTURE zynq_1_axi_quad_spi_0_0_arch OF zynq_1_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
Async_Clk : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 full_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 full_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi4_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_FULL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
C_S_AXI4_BASEADDR => X"41E00000",
C_S_AXI4_HIGHADDR => X"41E00FFF",
C_FAMILY => "virtex7",
C_SUB_FAMILY => "virtex7",
C_INSTANCE => "axi_quad_spi_inst",
C_TYPE_OF_AXI4_INTERFACE => 1,
C_XIP_MODE => 0,
C_SPI_MEM_ADDR_BITS => 24,
C_FIFO_DEPTH => 256,
C_SCK_RATIO => 128,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 12,
Async_Clk => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => '0',
s_axi_aresetn => '0',
s_axi4_aclk => s_axi4_aclk,
s_axi4_aresetn => s_axi4_aresetn,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 7)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 7)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi4_awid => s_axi4_awid,
s_axi4_awaddr => s_axi4_awaddr,
s_axi4_awlen => s_axi4_awlen,
s_axi4_awsize => s_axi4_awsize,
s_axi4_awburst => s_axi4_awburst,
s_axi4_awlock => s_axi4_awlock,
s_axi4_awcache => s_axi4_awcache,
s_axi4_awprot => s_axi4_awprot,
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_awready => s_axi4_awready,
s_axi4_wdata => s_axi4_wdata,
s_axi4_wstrb => s_axi4_wstrb,
s_axi4_wlast => s_axi4_wlast,
s_axi4_wvalid => s_axi4_wvalid,
s_axi4_wready => s_axi4_wready,
s_axi4_bid => s_axi4_bid,
s_axi4_bresp => s_axi4_bresp,
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_bready => s_axi4_bready,
s_axi4_arid => s_axi4_arid,
s_axi4_araddr => s_axi4_araddr,
s_axi4_arlen => s_axi4_arlen,
s_axi4_arsize => s_axi4_arsize,
s_axi4_arburst => s_axi4_arburst,
s_axi4_arlock => s_axi4_arlock,
s_axi4_arcache => s_axi4_arcache,
s_axi4_arprot => s_axi4_arprot,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_arready => s_axi4_arready,
s_axi4_rid => s_axi4_rid,
s_axi4_rdata => s_axi4_rdata,
s_axi4_rresp => s_axi4_rresp,
s_axi4_rlast => s_axi4_rlast,
s_axi4_rvalid => s_axi4_rvalid,
s_axi4_rready => s_axi4_rready,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt
);
END zynq_1_axi_quad_spi_0_0_arch;
| mit | 9c42134b2594df486e32de5e9de85693 | 0.663205 | 2.978508 | false | false | false | false |
gregani/la16fw | test_fifo.vhd | 1 | 4,496 | --
-- This file is part of the lafw16 project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_fifo is
end test_fifo;
architecture behavior of test_fifo is
-- Component Declaration for the Unit Under Test (UUT)
component fifo
port(
reset : in std_logic;
clk_read : in std_logic;
clk_write : in std_logic;
data_in : in std_logic_vector(15 downto 0);
enable_write : in std_logic;
enable_read : in std_logic;
data_out : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
--Inputs
signal reset : std_logic := '0';
signal clk_read : std_logic := '0';
signal clk_write : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal enable_write : std_logic := '0';
signal enable_read : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(15 downto 0);
signal full : std_logic;
signal empty : std_logic;
signal last_empty : std_logic := '1';
-- Clock period definitions
constant clk_read_period : time := 20.83 ns;
constant clk_write_period : time := 100 ns;
signal write_count : unsigned(15 downto 0) := (0=>'1',others=>'0');
signal read_count : unsigned(15 downto 0) := (0=>'1',others=>'0');
signal do_read : std_logic := '0';
signal read_toggle : std_logic := '0';
begin
-- Instantiate the Unit Under Test (UUT)
uut: fifo
port map(
reset => reset,
clk_read => clk_read,
clk_write => clk_write,
data_in => data_in,
enable_write => enable_write,
enable_read => enable_read,
data_out => data_out,
full => full,
empty => empty
);
-- Clock process definitions
clk_read_process :process
begin
read_toggle <= not read_toggle;
--read_toggle <= '1';
clk_read <= '0';
wait for clk_read_period/2;
clk_read <= '1';
if (enable_read = '1') and (empty = '0') then
read_count <= read_count + 1;
assert data_out = std_logic_vector(read_count)
report "wrong data"
severity failure;
-- severity warning;
end if;
wait for clk_read_period/2;
enable_read <= read_toggle and do_read;
end process;
clk_write_process :process
begin
clk_write <= '0';
wait for clk_write_period/2;
clk_write <= '1';
if (enable_write = '1') and (full = '0') then
write_count <= write_count + 1;
end if;
wait for clk_write_period/2;
end process;
data_in <= std_logic_vector(write_count);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_read_period*10;
-- fill fifo
wait until full = '0';
wait until rising_edge(clk_write);
wait for clk_write_period/4;
enable_write <= '1';
wait until full = '1';
enable_write <= '0';
wait for 5 us;
-- read fifo
--wait until empty = '0';
wait until rising_edge(clk_read);
wait for clk_read_period/4;
do_read <= '1';
wait for 5*clk_read_period;
do_read <= '0';
wait for 5*clk_read_period;
do_read <= '1';
-- wait for clk_read_period;
-- wait until empty = '1';
-- do_read <= '0';
-- wait for 1 us;
wait;
end process;
end;
| gpl-2.0 | 86ba9194df6edb134e39e456f290e981 | 0.565169 | 3.712634 | false | false | false | false |
sorgelig/SAMCoupe_MIST | t80/T80_ALU.vhd | 2 | 12,080 | --------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
-- 0240 : Added GB operations
-- 0242 : Cleanup
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
if IR(2 downto 0) = "110" or XY_State /= "00" then
F_Out(Flag_X) <= WZ(11);
F_Out(Flag_Y) <= WZ(13);
else
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
| gpl-2.0 | bf84176313b283ab2fcac376bd0f7ead | 0.555298 | 2.629517 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/netgen/synthesis/CPU_synthesis.vhd | 1 | 25,151 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: CPU_synthesis.vhd
-- /___/ /\ Timestamp: Sat Nov 30 23:59:56 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm CPU -w -dir netgen/synthesis -ofmt vhdl -sim CPU.ngc CPU_synthesis.vhd
-- Device : xc3s1200e-4-fg320
-- Input file : CPU.ngc
-- Output file : D:\study\2013fall\ComputerOrganization\lastproject\makecomputer\src\CPU\netgen\synthesis\CPU_synthesis.vhd
-- # of Entities : 1
-- Design Name : CPU
-- Xilinx : D:\mydownload\ISExilinx\14.6\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity CPU is
port (
clk : in STD_LOGIC := 'X';
Ram1WE : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
Ram1EN : out STD_LOGIC;
Ram1OE : out STD_LOGIC;
Ram1Data : inout STD_LOGIC_VECTOR ( 15 downto 0 );
Ram1Addr : out STD_LOGIC_VECTOR ( 17 downto 0 )
);
end CPU;
architecture Structure of CPU is
signal ALU_1_Mmux_Output_45 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_10_rt_2 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_11_rt_4 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_12_rt_6 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_13_rt_8 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_14_rt_10 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_3_rt_13 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_4_rt_15 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_5_rt_17 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_6_rt_19 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_7_rt_21 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_8_rt_23 : STD_LOGIC;
signal Add_PC_Madd_Output_cy_9_rt_25 : STD_LOGIC;
signal Add_PC_Madd_Output_xor_15_rt_27 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_EN_28 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_EN_mux0000 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_flag_FSM_FFd1_31 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_flag_FSM_FFd2_32 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_flag_FSM_FFd3_33 : STD_LOGIC;
signal InstructionMem_1_Inst_RAM_ramaddr_and0000 : STD_LOGIC;
signal Ram1Addr_0_OBUF_81 : STD_LOGIC;
signal clk0 : STD_LOGIC;
signal clk_BUFGP_103 : STD_LOGIC;
signal divClk_1_Mcount_num : STD_LOGIC;
signal divClk_1_Mcount_num1 : STD_LOGIC;
signal divClk_1_temp_108 : STD_LOGIC;
signal divClk_1_temp_and0000 : STD_LOGIC;
signal divClk_1_temp_not0001 : STD_LOGIC;
signal rst_IBUF_126 : STD_LOGIC;
signal Add_PC_Madd_Output_cy : STD_LOGIC_VECTOR ( 14 downto 2 );
signal Add_PC_Madd_Output_lut : STD_LOGIC_VECTOR ( 2 downto 2 );
signal InstructionMem_1_Inst_RAM_ramaddr : STD_LOGIC_VECTOR ( 15 downto 2 );
signal PCReg_1_Output : STD_LOGIC_VECTOR ( 15 downto 2 );
signal divClk_1_num : STD_LOGIC_VECTOR ( 1 downto 0 );
signal pc_add4 : STD_LOGIC_VECTOR ( 15 downto 2 );
begin
XST_GND : GND
port map (
G => Ram1Addr_0_OBUF_81
);
XST_VCC : VCC
port map (
P => ALU_1_Mmux_Output_45
);
divClk_1_temp : FDE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_103,
CE => divClk_1_temp_and0000,
D => divClk_1_temp_not0001,
Q => divClk_1_temp_108
);
divClk_1_num_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_103,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => divClk_1_Mcount_num,
Q => divClk_1_num(0)
);
divClk_1_num_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_103,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => divClk_1_Mcount_num1,
Q => divClk_1_num(1)
);
Add_PC_Madd_Output_cy_2_Q : MUXCY
port map (
CI => Ram1Addr_0_OBUF_81,
DI => ALU_1_Mmux_Output_45,
S => Add_PC_Madd_Output_lut(2),
O => Add_PC_Madd_Output_cy(2)
);
Add_PC_Madd_Output_xor_2_Q : XORCY
port map (
CI => Ram1Addr_0_OBUF_81,
LI => Add_PC_Madd_Output_lut(2),
O => pc_add4(2)
);
Add_PC_Madd_Output_cy_3_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(2),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_3_rt_13,
O => Add_PC_Madd_Output_cy(3)
);
Add_PC_Madd_Output_xor_3_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(2),
LI => Add_PC_Madd_Output_cy_3_rt_13,
O => pc_add4(3)
);
Add_PC_Madd_Output_cy_4_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(3),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_4_rt_15,
O => Add_PC_Madd_Output_cy(4)
);
Add_PC_Madd_Output_xor_4_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(3),
LI => Add_PC_Madd_Output_cy_4_rt_15,
O => pc_add4(4)
);
Add_PC_Madd_Output_cy_5_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(4),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_5_rt_17,
O => Add_PC_Madd_Output_cy(5)
);
Add_PC_Madd_Output_xor_5_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(4),
LI => Add_PC_Madd_Output_cy_5_rt_17,
O => pc_add4(5)
);
Add_PC_Madd_Output_cy_6_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(5),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_6_rt_19,
O => Add_PC_Madd_Output_cy(6)
);
Add_PC_Madd_Output_xor_6_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(5),
LI => Add_PC_Madd_Output_cy_6_rt_19,
O => pc_add4(6)
);
Add_PC_Madd_Output_cy_7_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(6),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_7_rt_21,
O => Add_PC_Madd_Output_cy(7)
);
Add_PC_Madd_Output_xor_7_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(6),
LI => Add_PC_Madd_Output_cy_7_rt_21,
O => pc_add4(7)
);
Add_PC_Madd_Output_cy_8_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(7),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_8_rt_23,
O => Add_PC_Madd_Output_cy(8)
);
Add_PC_Madd_Output_xor_8_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(7),
LI => Add_PC_Madd_Output_cy_8_rt_23,
O => pc_add4(8)
);
Add_PC_Madd_Output_cy_9_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(8),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_9_rt_25,
O => Add_PC_Madd_Output_cy(9)
);
Add_PC_Madd_Output_xor_9_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(8),
LI => Add_PC_Madd_Output_cy_9_rt_25,
O => pc_add4(9)
);
Add_PC_Madd_Output_cy_10_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(9),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_10_rt_2,
O => Add_PC_Madd_Output_cy(10)
);
Add_PC_Madd_Output_xor_10_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(9),
LI => Add_PC_Madd_Output_cy_10_rt_2,
O => pc_add4(10)
);
Add_PC_Madd_Output_cy_11_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(10),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_11_rt_4,
O => Add_PC_Madd_Output_cy(11)
);
Add_PC_Madd_Output_xor_11_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(10),
LI => Add_PC_Madd_Output_cy_11_rt_4,
O => pc_add4(11)
);
Add_PC_Madd_Output_cy_12_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(11),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_12_rt_6,
O => Add_PC_Madd_Output_cy(12)
);
Add_PC_Madd_Output_xor_12_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(11),
LI => Add_PC_Madd_Output_cy_12_rt_6,
O => pc_add4(12)
);
Add_PC_Madd_Output_cy_13_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(12),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_13_rt_8,
O => Add_PC_Madd_Output_cy(13)
);
Add_PC_Madd_Output_xor_13_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(12),
LI => Add_PC_Madd_Output_cy_13_rt_8,
O => pc_add4(13)
);
Add_PC_Madd_Output_cy_14_Q : MUXCY
port map (
CI => Add_PC_Madd_Output_cy(13),
DI => Ram1Addr_0_OBUF_81,
S => Add_PC_Madd_Output_cy_14_rt_10,
O => Add_PC_Madd_Output_cy(14)
);
Add_PC_Madd_Output_xor_14_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(13),
LI => Add_PC_Madd_Output_cy_14_rt_10,
O => pc_add4(14)
);
Add_PC_Madd_Output_xor_15_Q : XORCY
port map (
CI => Add_PC_Madd_Output_cy(14),
LI => Add_PC_Madd_Output_xor_15_rt_27,
O => pc_add4(15)
);
PCReg_1_Output_15 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(15),
Q => PCReg_1_Output(15)
);
PCReg_1_Output_14 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(14),
Q => PCReg_1_Output(14)
);
PCReg_1_Output_13 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(13),
Q => PCReg_1_Output(13)
);
PCReg_1_Output_12 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(12),
Q => PCReg_1_Output(12)
);
PCReg_1_Output_11 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(11),
Q => PCReg_1_Output(11)
);
PCReg_1_Output_10 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(10),
Q => PCReg_1_Output(10)
);
PCReg_1_Output_9 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(9),
Q => PCReg_1_Output(9)
);
PCReg_1_Output_8 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(8),
Q => PCReg_1_Output(8)
);
PCReg_1_Output_7 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(7),
Q => PCReg_1_Output(7)
);
PCReg_1_Output_6 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(6),
Q => PCReg_1_Output(6)
);
PCReg_1_Output_5 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(5),
Q => PCReg_1_Output(5)
);
PCReg_1_Output_4 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(4),
Q => PCReg_1_Output(4)
);
PCReg_1_Output_3 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(3),
Q => PCReg_1_Output(3)
);
PCReg_1_Output_2 : FDCE
port map (
C => clk0,
CE => ALU_1_Mmux_Output_45,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => pc_add4(2),
Q => PCReg_1_Output(2)
);
InstructionMem_1_Inst_RAM_flag_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_103,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => InstructionMem_1_Inst_RAM_flag_FSM_FFd2_32,
Q => InstructionMem_1_Inst_RAM_flag_FSM_FFd1_31
);
InstructionMem_1_Inst_RAM_flag_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_103,
CLR => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
D => InstructionMem_1_Inst_RAM_flag_FSM_FFd3_33,
Q => InstructionMem_1_Inst_RAM_flag_FSM_FFd2_32
);
InstructionMem_1_Inst_RAM_flag_FSM_FFd3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk_BUFGP_103,
D => InstructionMem_1_Inst_RAM_flag_FSM_FFd1_31,
PRE => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
Q => InstructionMem_1_Inst_RAM_flag_FSM_FFd3_33
);
InstructionMem_1_Inst_RAM_ramaddr_15 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(15),
Q => InstructionMem_1_Inst_RAM_ramaddr(15)
);
InstructionMem_1_Inst_RAM_ramaddr_14 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(14),
Q => InstructionMem_1_Inst_RAM_ramaddr(14)
);
InstructionMem_1_Inst_RAM_ramaddr_13 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(13),
Q => InstructionMem_1_Inst_RAM_ramaddr(13)
);
InstructionMem_1_Inst_RAM_ramaddr_12 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(12),
Q => InstructionMem_1_Inst_RAM_ramaddr(12)
);
InstructionMem_1_Inst_RAM_ramaddr_11 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(11),
Q => InstructionMem_1_Inst_RAM_ramaddr(11)
);
InstructionMem_1_Inst_RAM_ramaddr_10 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(10),
Q => InstructionMem_1_Inst_RAM_ramaddr(10)
);
InstructionMem_1_Inst_RAM_ramaddr_9 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(9),
Q => InstructionMem_1_Inst_RAM_ramaddr(9)
);
InstructionMem_1_Inst_RAM_ramaddr_8 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(8),
Q => InstructionMem_1_Inst_RAM_ramaddr(8)
);
InstructionMem_1_Inst_RAM_ramaddr_7 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(7),
Q => InstructionMem_1_Inst_RAM_ramaddr(7)
);
InstructionMem_1_Inst_RAM_ramaddr_6 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(6),
Q => InstructionMem_1_Inst_RAM_ramaddr(6)
);
InstructionMem_1_Inst_RAM_ramaddr_5 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(5),
Q => InstructionMem_1_Inst_RAM_ramaddr(5)
);
InstructionMem_1_Inst_RAM_ramaddr_4 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(4),
Q => InstructionMem_1_Inst_RAM_ramaddr(4)
);
InstructionMem_1_Inst_RAM_ramaddr_3 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(3),
Q => InstructionMem_1_Inst_RAM_ramaddr(3)
);
InstructionMem_1_Inst_RAM_ramaddr_2 : FDE
port map (
C => clk_BUFGP_103,
CE => InstructionMem_1_Inst_RAM_ramaddr_and0000,
D => PCReg_1_Output(2),
Q => InstructionMem_1_Inst_RAM_ramaddr(2)
);
InstructionMem_1_Inst_RAM_EN : FDP
port map (
C => clk_BUFGP_103,
D => InstructionMem_1_Inst_RAM_EN_mux0000,
PRE => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv,
Q => InstructionMem_1_Inst_RAM_EN_28
);
divClk_1_clk01 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rst_IBUF_126,
I1 => divClk_1_temp_108,
O => clk0
);
divClk_1_Mcount_num_xor_1_11 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => divClk_1_num(0),
I1 => divClk_1_num(1),
O => divClk_1_Mcount_num1
);
divClk_1_Mcount_num_xor_0_11 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => divClk_1_num(0),
I1 => divClk_1_num(1),
O => divClk_1_Mcount_num
);
InstructionMem_1_Inst_RAM_EN_mux00001 : LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => InstructionMem_1_Inst_RAM_EN_28,
I1 => InstructionMem_1_Inst_RAM_flag_FSM_FFd3_33,
I2 => InstructionMem_1_Inst_RAM_flag_FSM_FFd1_31,
O => InstructionMem_1_Inst_RAM_EN_mux0000
);
InstructionMem_1_Inst_RAM_ramaddr_and00001 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rst_IBUF_126,
I1 => InstructionMem_1_Inst_RAM_flag_FSM_FFd3_33,
O => InstructionMem_1_Inst_RAM_ramaddr_and0000
);
divClk_1_temp_and00001 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => rst_IBUF_126,
I1 => divClk_1_num(0),
I2 => divClk_1_num(1),
O => divClk_1_temp_and0000
);
rst_IBUF : IBUF
port map (
I => rst,
O => rst_IBUF_126
);
Ram1Data_15_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(15)
);
Ram1Data_14_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(14)
);
Ram1Data_13_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(13)
);
Ram1Data_12_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(12)
);
Ram1Data_11_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(11)
);
Ram1Data_10_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(10)
);
Ram1Data_9_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(9)
);
Ram1Data_8_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(8)
);
Ram1Data_7_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(7)
);
Ram1Data_6_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(6)
);
Ram1Data_5_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(5)
);
Ram1Data_4_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(4)
);
Ram1Data_3_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(3)
);
Ram1Data_2_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(2)
);
Ram1Data_1_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(1)
);
Ram1Data_0_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Data(0)
);
Ram1WE_OBUF : OBUF
port map (
I => ALU_1_Mmux_Output_45,
O => Ram1WE
);
Ram1EN_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_EN_28,
O => Ram1EN
);
Ram1OE_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_EN_28,
O => Ram1OE
);
Ram1Addr_17_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Addr(17)
);
Ram1Addr_16_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Addr(16)
);
Ram1Addr_15_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(15),
O => Ram1Addr(15)
);
Ram1Addr_14_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(14),
O => Ram1Addr(14)
);
Ram1Addr_13_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(13),
O => Ram1Addr(13)
);
Ram1Addr_12_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(12),
O => Ram1Addr(12)
);
Ram1Addr_11_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(11),
O => Ram1Addr(11)
);
Ram1Addr_10_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(10),
O => Ram1Addr(10)
);
Ram1Addr_9_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(9),
O => Ram1Addr(9)
);
Ram1Addr_8_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(8),
O => Ram1Addr(8)
);
Ram1Addr_7_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(7),
O => Ram1Addr(7)
);
Ram1Addr_6_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(6),
O => Ram1Addr(6)
);
Ram1Addr_5_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(5),
O => Ram1Addr(5)
);
Ram1Addr_4_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(4),
O => Ram1Addr(4)
);
Ram1Addr_3_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(3),
O => Ram1Addr(3)
);
Ram1Addr_2_OBUF : OBUF
port map (
I => InstructionMem_1_Inst_RAM_ramaddr(2),
O => Ram1Addr(2)
);
Ram1Addr_1_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Addr(1)
);
Ram1Addr_0_OBUF : OBUF
port map (
I => Ram1Addr_0_OBUF_81,
O => Ram1Addr(0)
);
Add_PC_Madd_Output_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(3),
O => Add_PC_Madd_Output_cy_3_rt_13
);
Add_PC_Madd_Output_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(4),
O => Add_PC_Madd_Output_cy_4_rt_15
);
Add_PC_Madd_Output_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(5),
O => Add_PC_Madd_Output_cy_5_rt_17
);
Add_PC_Madd_Output_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(6),
O => Add_PC_Madd_Output_cy_6_rt_19
);
Add_PC_Madd_Output_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(7),
O => Add_PC_Madd_Output_cy_7_rt_21
);
Add_PC_Madd_Output_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(8),
O => Add_PC_Madd_Output_cy_8_rt_23
);
Add_PC_Madd_Output_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(9),
O => Add_PC_Madd_Output_cy_9_rt_25
);
Add_PC_Madd_Output_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(10),
O => Add_PC_Madd_Output_cy_10_rt_2
);
Add_PC_Madd_Output_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(11),
O => Add_PC_Madd_Output_cy_11_rt_4
);
Add_PC_Madd_Output_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(12),
O => Add_PC_Madd_Output_cy_12_rt_6
);
Add_PC_Madd_Output_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(13),
O => Add_PC_Madd_Output_cy_13_rt_8
);
Add_PC_Madd_Output_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(14),
O => Add_PC_Madd_Output_cy_14_rt_10
);
Add_PC_Madd_Output_xor_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCReg_1_Output(15),
O => Add_PC_Madd_Output_xor_15_rt_27
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_103
);
Add_PC_Madd_Output_lut_2_INV_0 : INV
port map (
I => PCReg_1_Output(2),
O => Add_PC_Madd_Output_lut(2)
);
rst_inv1_INV_0 : INV
port map (
I => rst_IBUF_126,
O => InstructionMem_1_Inst_RAM_flag_FSM_Acst_FSM_inv
);
divClk_1_temp_not00011_INV_0 : INV
port map (
I => divClk_1_temp_108,
O => divClk_1_temp_not0001
);
end Structure;
| mit | bacc0dcfde79532667127e10681f0cdb | 0.549561 | 2.830407 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/RAM.vhd | 1 | 2,386 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:16:34 11/30/2013
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ramaddr : out STD_LOGIC_VECTOR (17 downto 0);
ramdata : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC;
WE : out STD_LOGIC;
EN : out STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
data : in STD_LOGIC_VECTOR (15 downto 0);
dataout: out STD_LOGIC_VECTOR (15 downto 0);
r: in std_logic); --Ϊ1¼´Îª¶Á£¬·ñÔòΪд
end RAM;
architecture Behavioral of RAM is
signal flag: std_logic_vector(1 downto 0):= "00";
begin
process(clk, rst)
begin
if rst = '0' then
OE <= '1';
WE <= '1';
EN <= '1';
flag <= "00";
ramdata <= Int16_Zero;
elsif (clk'event and clk = '1') then
if r = '0' then
case flag is
when "00" =>
EN <= '0';
OE <= '1';
WE <= '1';
ramaddr <= "00" & addr;
ramdata <= data;
flag <= "01";
when "01" =>
WE <= '0';
flag <= "10";
when "10" =>
WE <= '1';
EN <= '1';
flag <= "11";
when others =>
flag <= "00";
end case;
else
case flag is
when "00" =>
EN <= '0';
OE <= '0';
WE <= '1';
ramaddr <= "00" & addr;
ramdata <= "ZZZZZZZZZZZZZZZZ";
flag <= "01";
when "01" =>
dataout <= ramdata;
flag <= "10";
when "10" =>
OE <= '1';
EN <= '1';
flag <= "11";
when others =>
flag <= "00";
end case;
end if;
end if;
end process;
end Behavioral;
| mit | b55c02f1010269599e28f4f63e40d856 | 0.489522 | 3.202685 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dc_ss.vhd | 9 | 8,726 | `protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
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| gpl-3.0 | 7bf422b4c92b1dbfa71b9c01c5ecb2ea | 0.917603 | 1.924994 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/KeySignaltoChar.vhd | 1 | 3,096 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou. ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_logic_1164.all;
USe IEEE.Std_logic_unsigned.all;
use IEEE.Std_logic_arith.all;
ENTITY KeySignaltoChar IS
PORT
(
key: in std_logic_vector(7 downto 0);
char: out std_logic_vector(7 downto 0)
);
END KeySignaltoChar ;
ARCHITECTURE behave OF KeySignaltoChar IS
begin
process(key)
begin
case key is
when "01000101"=>
char <= "00010000"; -- 0
when "00010110"=>
char <= "00010001"; -- 1
when "00011110"=>
char <= "00010010"; -- 2
when "00100110"=>
char <= "00010011"; -- 3
when "00100101"=>
char <= "00010100"; -- 4
when "00101110"=>
char <= "00010101"; -- 5
when "00110110"=>
char <= "00010110"; -- 6
when "00111101"=>
char <= "00010111"; -- 7
when "00111110"=>
char <= "00011000"; -- 8
when "01000110"=>
char <= "00011001"; -- 9
when "00011100"=>
char <= "00100001"; -- A
when "00110010"=>
char <= "00100010"; -- B
when "00100001"=>
char <= "00100011"; -- C
when "00100011"=>
char <= "00100100"; -- D
when "00100100"=>
char <= "00100101"; -- E
when "00101011"=>
char <= "00100110"; -- F
when "00110100"=>
char <= "00100111"; -- G
when "00110011"=>
char <= "00101000"; -- H
when "01000011"=>
char <= "00101001"; -- I
when "00111011"=>
char <= "00101010"; -- J
when "01000010"=>
char <= "00101011"; -- K
when "01001011"=>
char <= "00101100"; -- L
when "00111010"=>
char <= "00101101"; -- M
when "00110001"=>
char <= "00101110"; -- N
when "01000100"=>
char <= "00101111"; -- O
when "01001101"=>
char <= "00110000"; -- P
when "00010101"=>
char <= "00110001"; -- Q
when "00101101"=>
char <= "00110010"; -- R
when "00011011"=>
char <= "00110011"; -- S
when "00101100"=>
char <= "00110100"; -- T
when "00111100"=>
char <= "00110101"; -- U
when "00101010"=>
char <= "00110110"; -- V
when "00011101"=>
char <= "00110111"; -- W
when "00100010"=>
char <= "00111000"; -- X
when "00110101"=>
char <= "00111001"; -- Y
when "00011010"=>
char <= "00111010"; -- Z
when "00101001"=>
char <= "00000000"; -- space
when "01000001"=>
char <= "00001100"; -- ,
when "01010100" =>
char <= "00111011"; -- [
when "01011011" =>
char <= "00111101"; -- ]
when "01010101" =>
char <= "00011101"; -- =
when "01010010" =>
char <= "00000111"; -- '
when "01001001" =>
char <= "00001110"; -- .
when "01001100" =>
char <= "00011011"; -- ;
when "01011010"=>
char <= "11111100"; -- enter
when "11110000"=>
char <= "11110000"; -- F0
when others =>
char <= "11111111";
end case;
end process;
end behave;
| mit | cfca38d065cea910ae5f45543759338b | 0.529393 | 3.279661 | false | false | false | false |
6769/VHDL | Lab_6/TheFinalCodeVersion/Addsub.vhd | 2 | 692 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Addsub_Unit is
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end entity Addsub_Unit;
architecture Behavior of Addsub_Unit is
begin
process(select_add_sub,a,b)
begin
case select_add_sub is
when '0'=>
result<=a+b;
when '1'=>
result<=a-b;
when others=>
result<=(others=>'Z');
end case;
end process;
end architecture Behavior; | gpl-2.0 | fb0b1e4efb2b10d668f985314847ea7b | 0.536127 | 3.700535 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/interrupt_control_v3_0/hdl/src/vhdl/interrupt_control.vhd | 6 | 57,024 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_0
-- ~~~~~~
-- - Modified to used proc_common_v4_0 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
Use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| mit | 2262af845efe25b767ec9963ef99ae1b | 0.466137 | 4.552087 | false | false | false | false |
meaepeppe/FIR_ISA | VHDL/clk_gen.vhd | 1 | 703 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_gen is
port (
END_SIM : in std_logic;
CLK : out std_logic;
RST_n : out std_logic);
end clk_gen;
architecture beh of clk_gen is
constant Ts : time := 6 ns;
signal CLK_i : std_logic;
begin -- beh
process
begin -- process
if (CLK_i = 'U') then
CLK_i <= '0';
else
CLK_i <= not(CLK_i);
end if;
wait for Ts/2;
end process;
CLK <= CLK_i and not(END_SIM);
process
begin -- process
RST_n <= '0';
wait for 3*Ts/2;
RST_n <= '1';
wait;
end process;
end beh;
| gpl-3.0 | c7b8afc1737473cf2aa0d9290ee3d885 | 0.534851 | 2.978814 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/axi_qspi_xip_if.vhd | 1 | 341,829 | -------------------------------------------------------------------------------
-- $Id: axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.async_fifo_fg;-- 1/8/2013
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_1.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
elsif(Rx_FIFO_rd_ack = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
S_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '1') then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
s_axi_rvalid_i <= Rx_FIFO_rd_ack; -- '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= Rx_FIFO_rd_ack;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (LOGIC_CHANGE = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI2AXI4: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
TO_XIPSR_axi_rx_empty <= '1';
elsif(axi4_tr_over = '1')then
TO_XIPSR_axi_rx_empty <= '1';
elsif(new_tr_at_axi4 = '1')then
TO_XIPSR_axi_rx_empty <= '0';
end if;
end if;
end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity proc_common_v4_0.async_fifo_fg
generic map(
-- 3/30/2013 starts
--C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
--C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => S_AXI4_ARESET ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_1.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '0') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d1='1') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
------------------------------------------------------------------------------- | mit | 12843bf567711d0589a4e00870099636 | 0.372991 | 4.279603 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd | 5 | 33,313 | -------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
library proc_common_v4_0;
use proc_common_v4_0.ipif_pkg.calc_num_ce;
use proc_common_v4_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v4_0.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v2_0;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_0;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_0.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
| mit | a32c5eef00de38091080ffdcf7a584c6 | 0.471438 | 3.879921 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_mode_control_logic.vhd | 1 | 143,649 | --
---- qspi_mode_control_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_control_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - This module is heart of C_SPI_MODE 1 and 2. this will generate the clock
-- - transmit data and control the _T signals.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.proc_common_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_mode_control_logic is
generic(
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SUB_FAMILY : string
);
port(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------
DTR_FIFO_Data_Exists : in std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Data_To_Rx_FIFO_1 : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
SPIXfer_done_Rx_Wr_en: out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
--SR_6_Rx_Full : in std_logic;
--Last_count : in std_logic;
---------------------- from control register
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
---------------------- from look up table
Data_Dir : in std_logic;
Data_Mode_1 : in std_logic;
Data_Mode_0 : in std_logic;
Data_Phase : in std_logic;
----------------------
Quad_Phase : in std_logic;
--Dummy_Bits : in std_logic_vector(3 downto 0);
----------------------
Addr_Mode_1 : in std_logic;
Addr_Mode_0 : in std_logic;
Addr_Bit : in std_logic;
Addr_Phase : in std_logic;
----------------------
CMD_Mode_1 : in std_logic;
CMD_Mode_0 : in std_logic;
CMD_Error : in std_logic;
CMD_decoded : in std_logic;
----------------------
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
IO0_I : in std_logic;
IO0_O : out std_logic; -- MOSI
IO0_T : out std_logic;
IO1_I : in std_logic; -- MISO
IO1_O : out std_logic;
IO1_T : out std_logic;
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
Control_bit_7_8 : in std_logic_vector(0 to 1); --(7 to 8)
pr_state_idle : out std_logic;
Rx_FIFO_Full : in std_logic ;
DRR_Overrun_reg : out std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic
);
end entity qspi_mode_control_logic;
----------------------------------
architecture imp of qspi_mode_control_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-- function declaration
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
return 2;
end if;
end spcl_log2;
-- type declaration
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
ADDR_SEND,TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,TEMP_DATA_SEND,
DATA_RECEIVE,TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ps: STATE_TYPE;
signal qspi_cntrl_ns: STATE_TYPE;
-----------------------------------------
-- signal declaration
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
signal Count_1 : std_logic_vector(COUNT_WIDTH downto 0);
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal Serial_Din_0 : std_logic;
signal Serial_Din_1 : std_logic;
signal Serial_Din_2 : std_logic;
signal Serial_Din_3 : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal serial_dout_int : std_logic;
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal master_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal MODF_strobe_int : std_logic;
signal Load_tx_data_to_shift_reg_int : std_logic;
signal mode_0 : std_logic;
signal mode_1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SCK_O_1 : std_logic;-- :='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal pr_state_cmd_ph : std_logic;
signal pr_state_addr_ph : std_logic;
signal pr_state_dummy_ph : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal dummy_cnt : std_logic_vector(3 downto 0);
signal stop_clock : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal dummy : std_logic;
signal no_slave_selected : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Data_To_Rx_FIFO_2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--attribute IOB : string;
--attribute IOB of QSPI_SCK_T : label is "true";
--attribute IOB of QSPI_SS_T : label is "true";
--attribute IOB of QSPI_IO0_T : label is "true";-- MOSI_T
--attribute IOB of QSPI_IO1_T : label is "true";-- MISO_T
--attribute IOB of QSPI_SPISEL : label is "true";-- SPISEL
signal Mst_Trans_inhibit_d1 : std_logic;
signal Mst_Trans_inhibit_pulse : std_logic;
signal stop_clock_reg : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse_11: std_logic;
signal DRR_Overrun_reg_int : std_logic;
signal Rx_FIFO_Full_reg : std_logic;
-----
begin
-----
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(Rx_FIFO_Full = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--------------------------------------
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not SPISEL_sync) and spisel_d1;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- __________|--|_____ -- SPISEL_pulse_op
SPISEL_pulse_op <= not SPISEL_sync; -- spisel_pulse;
SPISEL_d1_reg <= spisel_d1;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,
CPHA,
SPIXfer_done_int,
transfer_start_pulse,
Mst_Trans_inhibit_pulse) is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') then -- Tranfer not in progress
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
--------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF
)is
-----
begin
-----
if(Soft_Reset_op = RESET_ACTIVE) then
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
(--(Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
)
)
)then
Load_tx_data_to_shift_reg_int <= '1'; --Set flag
else
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
------------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1' -- core is in Data Receive State and DRR is not full
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') -- or
--(SPIXfer_done_int_pulse_d1 = '1')-- or
--(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- glitch at the end of
-- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
--------------------------------
--TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- (
-- (
-- SPI_En = '0' or -- enable not asserted or
-- (SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
-- SR_3_MODF = '1' or -- mode fault error
-- Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
-- stop_clock = '1' -- core is in Data Receive State and DRR is not full
-- )
-- )
-- )then
--
-- transfer_start <= '0';
-- else
---- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
---- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1')-- or
-- --(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
-- transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
-- end if;
-- end if;
--end process TRANSFER_START_PROCESS;
-------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
transfer_start_pulse_11 <= transfer_start_d2 and (not transfer_start_d3);
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_1 <= (others => '0');
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
--elsif(SPIXfer_done_int_pulse = '1') then
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011;
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
RECEIVE_DATA_STROBE_PROCESS_1: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_2 <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
Data_To_Rx_FIFO_2 <= Data_To_Rx_FIFO_1;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_1;
--receive_Data_int <= Data_To_Rx_FIFO_2;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
-- SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_d1; -- SPIXfer_done_int_pulse_d1;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
-- SPIXfer_done_rd_tx_en <= SPIXfer_done_int;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if((Soft_Reset_op = RESET_ACTIVE) or
-- (transfer_start_d1 = '0') or
-- --(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
-- (Mst_N_Slv = '0')
-- )then
--
-- Count <= (others => '0');
-- elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
-- end if;
-- end if;
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPIXfer_done_int = '1') or
(transfer_start = '0')
--(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
--(Mst_N_Slv = '0')
)then
Count <= (others => '0');
elsif (Count(COUNT_WIDTH) = '0') and ((CPOL and CPHA) = '0') then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
--sck_o_int <= (not sck_o_int) xor Count(COUNT_WIDTH);
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then --SPIXfer_done_int_pulse_d2
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d1='1') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
----------------------------------
RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
------------------------------------------------------
-----
end generate RATIO_OF_2_GENERATE;
---------------------------------
--------==================================================================-----
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
------------------------------
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(CPHA = '0' and CPOL = '0') then
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(0) and Count(1);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);--- and
--(and_reduce(Ratio_Count));-- dual mode
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
else
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(1) and
Count(0);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of IO0_I_REG : label is "true";
-----
begin
-----
-------------------------------------------------------------------------------
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => IO0_I --MOSI_I
);
-----------------------
-- IO1_I_REG_IOB: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-------------
IO1_I_REG_IOB: if (C_SUB_FAMILY = "virtex7"
or
C_SUB_FAMILY = "kintex7"
or
C_SUB_FAMILY = "artix7"
-- or -- 1/23/2013
-- C_SUB_FAMILY = "spartan6" -- 1/23/2013
)
-- or
-- (
-- C_USE_STARTUP = 0
-- and
-- C_SUB_FAMILY = "virtex6"
-- )
generate
-----
--attribute IOB : string;
--attribute IOB of IO1_I_REG : label is "true";
-----
begin
-----
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => IO1_I -- MISO_I
);
end generate IO1_I_REG_IOB;
---------------------------
-- -- IO1_I_REG_NO_IOB: If C_USE_STARTUP is used and family is virtex6, then
-- -- IO1_I is registered only, but it is not pushed in IOB.
-- -- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- IO1_I_REG_NO_IOB: if ( C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- )generate
-- -----
-- begin
-- -----
-- IO1_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => IO1_I -- MISO_I
-- );
-- end generate IO1_I_REG_NO_IOB;
-- ------------------------------
NO_IO_x_I_SYNC_MODE_1_GEN: if C_SPI_MODE = 1 generate
-----
begin
-----
io2_i_sync <= '0';
io3_i_sync <= '0';
end generate NO_IO_x_I_SYNC_MODE_1_GEN;
---------------------------------------
IO_x_I_SYNC_MODE_2_GEN: if C_SPI_MODE = 2 generate
----------------
--attribute IOB : string;
--attribute IOB of IO2_I_REG : label is "true";
--attribute IOB of IO3_I_REG : label is "true";
-----
begin
-----
-----------------------
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => Bus2IP_Clk,
D => IO2_I
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => Bus2IP_Clk,
D => IO3_I
);
-----------------------
end generate IO_x_I_SYNC_MODE_2_GEN;
------------------------------------
Serial_Din_0 <= mosi_i_sync;
Serial_Din_1 <= miso_i_sync;
Serial_Din_2 <= io2_i_sync ;
Serial_Din_3 <= io3_i_sync ;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
OTHER_RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process OTHER_RATIO_COUNT_PROCESS;
--------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
--(SPIXfer_done_int = '1') or
(transfer_start = '0')
) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS;
--------------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)or
(SPIXfer_done_int = '1') or
(transfer_start = '0') then
Count <= (others => '0');
--elsif (transfer_start = '0') then
-- Count <= (others => '0');
elsif (Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
OTHER_RATIO_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process OTHER_RATIO_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
OTHER_RATIO_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process OTHER_RATIO_DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
OTHER_RATIO_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and
(transfer_start = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
--(pr_state_data_receive = '1')
) then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
Serial_Din_1;-- MISO_I
elsif((mode_1 = '0' and mode_0 = '1') -- for Dual transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
Serial_Din_1 &-- MSB first
Serial_Din_0;
elsif((mode_1 = '1' and mode_0 = '0') -- for Quad transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
Serial_Din_3 & -- MSB first
Serial_Din_2 &
Serial_Din_1 &
Serial_Din_0;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process OTHER_RATIO_CAPT_RX_FE_MODE_00_11;
---------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din_1;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & Serial_Din_1
& Serial_Din_0;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & Serial_Din_3
& Serial_Din_2
& Serial_Din_1
& Serial_Din_0;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din_1;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & Serial_Din_1
& Serial_Din_0;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & Serial_Din_3
& Serial_Din_2
& Serial_Din_1
& Serial_Din_0;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
-------------------------------------------------------
end generate OTHER_RATIO_GENERATE;
----------------------------------
--------------------------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
--------------------------------
QSPI_DUAL_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 1 and
(
C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1
)
)generate
--------------------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => --if((SPIXfer_done_int_pulse='1')
-- )then
-- if (no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
-- else
-- stop_clock <= SR_5_Tx_Empty;
-- if(SR_5_Tx_Empty='1')then
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
-- else
-- qspi_cntrl_ns <= ADDR_SEND;
-- end if;
-- end if;
--else
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
--end if;
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
--if(no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
--else
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 2 and
(C_SPI_MEMORY = 1 or
C_SPI_MEMORY = 0
)
)
generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Error ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate QSPI_QUAD_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_DUAL_MODE_NM_MEM_GEN: if C_SPI_MODE = 1 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
-----
begin
-----
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= not (Mst_N_Slv); -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0'))then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
slave_mode <= not (Mst_N_Slv);-- dont allow SPI clock to go out when core is in slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv, -- in master mode
sck_o_int, -- value driven on sck_int
CPOL, -- CPOL mode thr SPICR
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH)
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')--and
--(pr_state_non_idle = '1')
)then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0') -- SM is in IDLE state or core in slave mode
)then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
---------------------
end architecture imp;
---------------------
| mit | 82bafbcec4de39d545ef14890feadc70 | 0.353953 | 4.759426 | false | false | false | false |
1995parham/FPGA-Homework | HW-4/src/p4/p4-1.vhd | 1 | 701 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 06-05-2016
-- Module Name: p4-1.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity logic1 is
port (A, B, C : in std_logic;
F : out std_logic);
end logic1;
architecture behavioral of logic1 is
begin
process(A,B,C) begin
if A = '1' then
F<= '1';
elsif B = '1' and C = '1' then
F <= '0';
-- providing else clause in order to
-- preventing from transparent latch
-- creation.
else
F <= 'X';
end if;
end process;
end behavioral;
| gpl-3.0 | 1db825524f05933a9e3f5201eea9c73f | 0.480742 | 3.505 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/dist_mem_gen_v8_0_synth.vhd | 1 | 30,145 | `protect begin_protected
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`protect end_protected
| mit | edb1c95fe6e1c89867eafeff09573278 | 0.944435 | 1.859655 | false | false | false | false |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/imports/new/wrapper.vhd | 1 | 19,020 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity wrapper is
generic (
DATAWIDTH : integer := 32
);
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end wrapper;
architecture rtl of wrapper is
component BD_PR_3 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
m_axis_data_0_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_0_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_0_tlast : inout STD_LOGIC;
m_axis_data_0_tready : inout STD_LOGIC;
m_axis_data_0_tvalid : inout STD_LOGIC;
s_axis_data_0_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_0_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_0_tlast : inout STD_LOGIC;
s_axis_data_0_tready : inout STD_LOGIC;
s_axis_data_0_tvalid : inout STD_LOGIC;
m_axis_data_1_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_1_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_1_tlast : inout STD_LOGIC;
m_axis_data_1_tready : inout STD_LOGIC;
m_axis_data_1_tvalid : inout STD_LOGIC;
s_axis_data_1_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_1_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_1_tlast : inout STD_LOGIC;
s_axis_data_1_tready : inout STD_LOGIC;
s_axis_data_1_tvalid : inout STD_LOGIC;
m_axis_data_2_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
m_axis_data_2_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
m_axis_data_2_tlast : inout STD_LOGIC;
m_axis_data_2_tready : inout STD_LOGIC;
m_axis_data_2_tvalid : inout STD_LOGIC;
s_axis_data_2_tdata : inout STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
s_axis_data_2_tkeep : inout STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
s_axis_data_2_tlast : inout STD_LOGIC;
s_axis_data_2_tready : inout STD_LOGIC;
s_axis_data_2_tvalid : inout STD_LOGIC;
AXIS_CLK : buffer STD_LOGIC
);
end component;
component pr_axis_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
static_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
static_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_m_axis_data_tready : out std_logic;
static_m_axis_data_tlast : in std_logic;
static_m_axis_data_tvalid : in std_logic;
pr_m_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
pr_m_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_m_axis_data_tready : out std_logic;
pr_m_axis_data_tlast : in std_logic;
pr_m_axis_data_tvalid : in std_logic;
static_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
static_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
static_s_axis_data_tready : in std_logic;
static_s_axis_data_tlast : out std_logic;
static_s_axis_data_tvalid : out std_logic;
pr_s_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
pr_s_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
pr_s_axis_data_tready : in std_logic;
pr_s_axis_data_tlast : out std_logic;
pr_s_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
component pr_axis is
generic (
DATAWIDTH : integer := DATAWIDTH
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
signal static_m_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_0_tlast : STD_LOGIC;
signal static_m_axis_data_0_tready : STD_LOGIC;
signal static_m_axis_data_0_tvalid : STD_LOGIC;
signal static_s_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_0_tlast : STD_LOGIC;
signal static_s_axis_data_0_tready : STD_LOGIC;
signal static_s_axis_data_0_tvalid : STD_LOGIC;
signal pr_m_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_0_tlast : STD_LOGIC;
signal pr_m_axis_data_0_tready : STD_LOGIC;
signal pr_m_axis_data_0_tvalid : STD_LOGIC;
signal pr_s_axis_data_0_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_0_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_0_tlast : STD_LOGIC;
signal pr_s_axis_data_0_tready : STD_LOGIC;
signal pr_s_axis_data_0_tvalid : STD_LOGIC;
signal static_m_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_1_tlast : STD_LOGIC;
signal static_m_axis_data_1_tready : STD_LOGIC;
signal static_m_axis_data_1_tvalid : STD_LOGIC;
signal static_s_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_1_tlast : STD_LOGIC;
signal static_s_axis_data_1_tready : STD_LOGIC;
signal static_s_axis_data_1_tvalid : STD_LOGIC;
signal pr_m_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_1_tlast : STD_LOGIC;
signal pr_m_axis_data_1_tready : STD_LOGIC;
signal pr_m_axis_data_1_tvalid : STD_LOGIC;
signal pr_s_axis_data_1_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_1_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_1_tlast : STD_LOGIC;
signal pr_s_axis_data_1_tready : STD_LOGIC;
signal pr_s_axis_data_1_tvalid : STD_LOGIC;
signal static_m_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_m_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_m_axis_data_2_tlast : STD_LOGIC;
signal static_m_axis_data_2_tready : STD_LOGIC;
signal static_m_axis_data_2_tvalid : STD_LOGIC;
signal static_s_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal static_s_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal static_s_axis_data_2_tlast : STD_LOGIC;
signal static_s_axis_data_2_tready : STD_LOGIC;
signal static_s_axis_data_2_tvalid : STD_LOGIC;
signal pr_m_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_m_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_m_axis_data_2_tlast : STD_LOGIC;
signal pr_m_axis_data_2_tready : STD_LOGIC;
signal pr_m_axis_data_2_tvalid : STD_LOGIC;
signal pr_s_axis_data_2_tdata : STD_LOGIC_VECTOR ( DATAWIDTH - 1 downto 0 );
signal pr_s_axis_data_2_tkeep : STD_LOGIC_VECTOR ( DATAWIDTH/8 - 1 downto 0 );
signal pr_s_axis_data_2_tlast : STD_LOGIC;
signal pr_s_axis_data_2_tready : STD_LOGIC;
signal pr_s_axis_data_2_tvalid : STD_LOGIC;
signal clk : STD_LOGIC;
begin
block_design: component BD_PR_3
port map(
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
m_axis_data_0_tdata => static_m_axis_data_0_tdata,
m_axis_data_0_tkeep => static_m_axis_data_0_tkeep,
m_axis_data_0_tlast => static_m_axis_data_0_tlast,
m_axis_data_0_tready => static_m_axis_data_0_tready,
m_axis_data_0_tvalid => static_m_axis_data_0_tvalid,
s_axis_data_0_tdata => static_s_axis_data_0_tdata,
s_axis_data_0_tkeep => static_s_axis_data_0_tkeep,
s_axis_data_0_tlast => static_s_axis_data_0_tlast,
s_axis_data_0_tready => static_s_axis_data_0_tready,
s_axis_data_0_tvalid => static_s_axis_data_0_tvalid,
m_axis_data_1_tdata => static_m_axis_data_1_tdata,
m_axis_data_1_tkeep => static_m_axis_data_1_tkeep,
m_axis_data_1_tlast => static_m_axis_data_1_tlast,
m_axis_data_1_tready => static_m_axis_data_1_tready,
m_axis_data_1_tvalid => static_m_axis_data_1_tvalid,
s_axis_data_1_tdata => static_s_axis_data_1_tdata,
s_axis_data_1_tkeep => static_s_axis_data_1_tkeep,
s_axis_data_1_tlast => static_s_axis_data_1_tlast,
s_axis_data_1_tready => static_s_axis_data_1_tready,
s_axis_data_1_tvalid => static_s_axis_data_1_tvalid,
m_axis_data_2_tdata => static_m_axis_data_2_tdata,
m_axis_data_2_tkeep => static_m_axis_data_2_tkeep,
m_axis_data_2_tlast => static_m_axis_data_2_tlast,
m_axis_data_2_tready => static_m_axis_data_2_tready,
m_axis_data_2_tvalid => static_m_axis_data_2_tvalid,
s_axis_data_2_tdata => static_s_axis_data_2_tdata,
s_axis_data_2_tkeep => static_s_axis_data_2_tkeep,
s_axis_data_2_tlast => static_s_axis_data_2_tlast,
s_axis_data_2_tready => static_s_axis_data_2_tready,
s_axis_data_2_tvalid => static_s_axis_data_2_tvalid,
AXIS_CLK => clk
);
pr_0_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_0_tdata,
static_m_axis_data_tkeep => static_m_axis_data_0_tkeep,
static_m_axis_data_tready => static_m_axis_data_0_tready,
static_m_axis_data_tlast => static_m_axis_data_0_tlast,
static_m_axis_data_tvalid => static_m_axis_data_0_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_0_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_0_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_0_tready,
pr_m_axis_data_tlast => pr_m_axis_data_0_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_0_tvalid,
static_s_axis_data_tdata => static_s_axis_data_0_tdata,
static_s_axis_data_tkeep => static_s_axis_data_0_tkeep,
static_s_axis_data_tready => static_s_axis_data_0_tready,
static_s_axis_data_tlast => static_s_axis_data_0_tlast,
static_s_axis_data_tvalid => static_s_axis_data_0_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_0_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_0_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_0_tready,
pr_s_axis_data_tlast => pr_s_axis_data_0_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_0_tvalid,
clk => clk
);
pr_1_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_1_tdata,
static_m_axis_data_tkeep => static_m_axis_data_1_tkeep,
static_m_axis_data_tready => static_m_axis_data_1_tready,
static_m_axis_data_tlast => static_m_axis_data_1_tlast,
static_m_axis_data_tvalid => static_m_axis_data_1_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_1_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_1_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_1_tready,
pr_m_axis_data_tlast => pr_m_axis_data_1_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_1_tvalid,
static_s_axis_data_tdata => static_s_axis_data_1_tdata,
static_s_axis_data_tkeep => static_s_axis_data_1_tkeep,
static_s_axis_data_tready => static_s_axis_data_1_tready,
static_s_axis_data_tlast => static_s_axis_data_1_tlast,
static_s_axis_data_tvalid => static_s_axis_data_1_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_1_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_1_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_1_tready,
pr_s_axis_data_tlast => pr_s_axis_data_1_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_1_tvalid,
clk => clk
);
pr_2_buffer: component pr_axis_buffer
port map (
static_m_axis_data_tdata => static_m_axis_data_2_tdata,
static_m_axis_data_tkeep => static_m_axis_data_2_tkeep,
static_m_axis_data_tready => static_m_axis_data_2_tready,
static_m_axis_data_tlast => static_m_axis_data_2_tlast,
static_m_axis_data_tvalid => static_m_axis_data_2_tvalid,
pr_m_axis_data_tdata => pr_m_axis_data_2_tdata,
pr_m_axis_data_tkeep => pr_m_axis_data_2_tkeep,
pr_m_axis_data_tready => pr_m_axis_data_2_tready,
pr_m_axis_data_tlast => pr_m_axis_data_2_tlast,
pr_m_axis_data_tvalid => pr_m_axis_data_2_tvalid,
static_s_axis_data_tdata => static_s_axis_data_2_tdata,
static_s_axis_data_tkeep => static_s_axis_data_2_tkeep,
static_s_axis_data_tready => static_s_axis_data_2_tready,
static_s_axis_data_tlast => static_s_axis_data_2_tlast,
static_s_axis_data_tvalid => static_s_axis_data_2_tvalid,
pr_s_axis_data_tdata => pr_s_axis_data_2_tdata,
pr_s_axis_data_tkeep => pr_s_axis_data_2_tkeep,
pr_s_axis_data_tready => pr_s_axis_data_2_tready,
pr_s_axis_data_tlast => pr_s_axis_data_2_tlast,
pr_s_axis_data_tvalid => pr_s_axis_data_2_tvalid,
clk => clk
);
pr_0 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_0_tdata,
s_axis_data_tkeep => pr_s_axis_data_0_tkeep,
s_axis_data_tready => pr_s_axis_data_0_tready,
s_axis_data_tlast => pr_s_axis_data_0_tlast,
s_axis_data_tvalid => pr_s_axis_data_0_tvalid,
m_axis_data_tdata => pr_m_axis_data_0_tdata,
m_axis_data_tkeep => pr_m_axis_data_0_tkeep,
m_axis_data_tready => pr_m_axis_data_0_tready,
m_axis_data_tlast => pr_m_axis_data_0_tlast,
m_axis_data_tvalid => pr_m_axis_data_0_tvalid,
clk => clk
);
pr_1 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_1_tdata,
s_axis_data_tkeep => pr_s_axis_data_1_tkeep,
s_axis_data_tready => pr_s_axis_data_1_tready,
s_axis_data_tlast => pr_s_axis_data_1_tlast,
s_axis_data_tvalid => pr_s_axis_data_1_tvalid,
m_axis_data_tdata => pr_m_axis_data_1_tdata,
m_axis_data_tkeep => pr_m_axis_data_1_tkeep,
m_axis_data_tready => pr_m_axis_data_1_tready,
m_axis_data_tlast => pr_m_axis_data_1_tlast,
m_axis_data_tvalid => pr_m_axis_data_1_tvalid,
clk => clk
);
pr_2 : component pr_axis
port map (
s_axis_data_tdata => pr_s_axis_data_2_tdata,
s_axis_data_tkeep => pr_s_axis_data_2_tkeep,
s_axis_data_tready => pr_s_axis_data_2_tready,
s_axis_data_tlast => pr_s_axis_data_2_tlast,
s_axis_data_tvalid => pr_s_axis_data_2_tvalid,
m_axis_data_tdata => pr_m_axis_data_2_tdata,
m_axis_data_tkeep => pr_m_axis_data_2_tkeep,
m_axis_data_tready => pr_m_axis_data_2_tready,
m_axis_data_tlast => pr_m_axis_data_2_tlast,
m_axis_data_tvalid => pr_m_axis_data_2_tvalid,
clk => clk
);
end architecture rtl; | mit | c41819b869afa5516e36cadfbbd74a1c | 0.596688 | 2.972804 | false | false | false | false |
1995parham/FPGA-Homework | HW-3/src/p12/p12.vhd | 1 | 2,774 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-04-2016
-- Module Name: p12.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity drawstring is
port (p1, p2 : in std_logic;
clk, reset : in std_logic;
led : out std_logic_vector (9 downto 1));
end entity;
architecture rtl of drawstring is
type state is (led1, led2, led3, led4, led5, led6, led7, led8, led9);
signal current_state, next_state : state := led5;
begin
process (clk, reset)
begin
if reset = '1' then
current_state <= led5;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process (current_state, p1, p2)
begin
case current_state is
when led1 =>
if p1'event and p1 = '1' then
next_state <= led2;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led2 =>
if p1'event and p1 = '1' then
next_state <= led3;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led3 =>
if p1'event and p1 = '1' then
next_state <= led4;
elsif p2'event and p2 = '1' then
next_state <= led2;
end if;
when led4 =>
if p1'event and p1 = '1' then
next_state <= led5;
elsif p2'event and p2 = '1' then
next_state <= led3;
end if;
when led5 =>
if p1'event and p1 = '1' then
next_state <= led6;
elsif p2'event and p2 = '1' then
next_state <= led4;
end if;
when led6 =>
if p1'event and p1 = '1' then
next_state <= led7;
elsif p2'event and p2 = '1' then
next_state <= led5;
end if;
when led7 =>
if p1'event and p1 = '1' then
next_state <= led8;
elsif p2'event and p2 = '1' then
next_state <= led6;
end if;
when led8 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led7;
end if;
when led9 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led8;
end if;
end case;
end process;
process (current_state)
begin
case current_state is
when led1 => led <= (1 => '1', others => '0');
when led2 => led <= (2 => '1', others => '0');
when led3 => led <= (3 => '1', others => '0');
when led4 => led <= (4 => '1', others => '0');
when led5 => led <= (5 => '1', others => '0');
when led6 => led <= (6 => '1', others => '0');
when led7 => led <= (7 => '1', others => '0');
when led8 => led <= (8 => '1', others => '0');
when led9 => led <= (9 => '1', others => '0');
end case;
end process;
end architecture;
| gpl-3.0 | 1d391488d8cd22f6073f83b69e4c5e2f | 0.525595 | 2.776777 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_defaults.vhd | 9 | 30,146 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | ba11a0c72a21a2650b887c93d3cd8e60 | 0.943409 | 1.848427 | false | false | false | false |
6769/VHDL | Lab_6/TheFinalCodeVersion/dec3to8.vhd | 2 | 673 | library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
when "001" => Y <= "01000000";
when "010" => Y <= "00100000";
when "011" => Y <= "00010000";
when "100" => Y <= "00001000";
when "101" => Y <= "00000100";
when "110" => Y <= "00000010";
when "111" => Y <= "00000001";
when others=> null;
end case;
else
Y <= "00000000";
end if;
end process;
end Behavior; | gpl-2.0 | 20b5ff87887afa993c9eea8325b13a11 | 0.558692 | 2.769547 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_mode_0_module.vhd | 1 | 91,071 | --
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - First version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.proc_common_pkg.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
--attribute IOB : string;
--attribute IOB of SPI_TRISTATE_CONTROL_II : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_III : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_IV : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_V : label is "true";
--attribute IOB of OTHER_RATIO_GENERATE : label is "true";
--attribute IOB of SCK_I_REG : label is "true";
--attribute IOB of SPISEL_REG : label is "true";
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
--SPIXfer_done_int <= Count(COUNT_WIDTH-1) and
-- Count(COUNT_WIDTH-2) and
-- Count(COUNT_WIDTH-3) and
-- not Count(COUNT_WIDTH-4);
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if(Loop_mode = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
else
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of MOSI_I_REG : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
OTHER_RATIO_MISO_I_REG_IOB_GEN: if(C_SUB_FAMILY = "virtex7"
or
C_SUB_FAMILY = "kintex7"
or
C_SUB_FAMILY = "artix7"
--or
--C_SUB_FAMILY = "spartan6"
)
-- or
-- (
-- C_USE_STARTUP = 0
-- and
-- C_SUB_FAMILY = "virtex6"
-- )
generate
-- attribute IOB : string;
--attribute IOB of MISO_I_REG : label is "true";
-----
begin
-----
MISO_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => MISO_I
);
end generate OTHER_RATIO_MISO_I_REG_IOB_GEN;
-----------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: If C_USE_STARTUP is used and family is virtex6, then
-- IO1_I is registered only, but it is not pushed in IOB.
-- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: if(C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- ) generate
-------
--begin
-------
--MISO_I_REG: component FD
--generic map
-- (
-- INIT => '0'
-- )
--port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
--end generate OTHER_RATIO_MISO_I_REG_NO_IOB_GEN;
-----------------------------------------------------------------
MOSI_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => MOSI_I
);
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- if (sck_rising_edge = '1') then
if (sck_d1 = '1') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
if ((sck_d1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
if ((sck_fe1 = '0') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
| mit | a6b2a967575bfd166f532d9f1553677e | 0.430488 | 4.176419 | false | false | false | false |
1995parham/FPGA-Homework | HW-4/src/p7/p7.vhd | 1 | 810 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: p7.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity p7 is
end entity;
architecture rtl of p7 is
component ring_counter
generic (N : integer := 4);
port (clk, start : in std_logic;
Q : out std_logic_vector(N - 1 downto 0));
end component;
for all:ring_counter use entity work.ring_counter;
signal clk : std_logic := '0';
signal start : std_logic := '1';
signal Q : std_logic_vector(3 downto 0);
begin
clk <= not clk after 50 ns;
start <= '0' after 75 ns;
m:ring_counter port map (clk, start, Q);
end architecture;
| gpl-3.0 | b6b5d07e306320ffae8f89122e877ecd | 0.530864 | 3.584071 | false | false | false | false |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/uart.vhd | 3 | 10,307 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_write, data_in)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and busy_write_sig = '0' then
-- if enable_write = '1' then
-- index := conv_integer(data_in(6 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
-- --The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
-- synthesis_on
--synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_read, data_save_reg)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and enable_read = '1' then
-- if data_save_reg(8) = '1' then
-- index := conv_integer(data_save_reg(7 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
----The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
----synthesis_on
end; --architecture logic
| gpl-3.0 | c2ae30f91c02de0c44ff886bdcfbb024 | 0.55244 | 3.510559 | false | false | false | false |
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers.vhd | 3 | 59,747 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop Finite State Machine (FSM)
--
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in,
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig,
health_info => health_info_sig,
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info => err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info => err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info => err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info => err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info => err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info => err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info => err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info => err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info => err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info => err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change
);
fault_info <= fault_info_sig;
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- Anything below here is pure combinational.
-- Control part (Logic for checking how we should give credit to previous node, whether it is real or fake credit)
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
-- Data-path related part (party calculation)
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
-- Data-path related part (parity checking)
process(valid_in, RX, xor_all)begin
fault_info_sig <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_info_sig <= '1';
end if;
end process;
-- Mixture of data-path related and control part
process(RX, faulty_packet_out, fault_info_sig, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, RX, valid_in)begin
-- this is the default value of the memory!
-- Writing to the corresponding location where write pointer is pointing to (in the FIFO slots)
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
-- Some default values (some sort of initialization, also used for avoiding latch(es) ??)
fault_info_sig <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_info_sig = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_info_sig = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_info_sig = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_info_sig = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
-- Control part of FIFO (reading the corresponding location based on where read pointer is pointing to in FIFO slots)
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
-- Control part of FIFO
-- read enable signal computation logic (based on grants from arbiters (allocator) and empty signal)
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
-- Control part of FIFO (write pointer update logic (rotate left one-bit))
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
-- Control part of FIFO (read pointer update logic (rotate left one-bit))
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
-- Control part of FIFO (more or less, although because of fault_out, it is also a bit related to the data-path part)
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_info_sig) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_info_sig = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
-- Control part of FIFO (Empty and Full signals computation logic)
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 7f9776b15b82501bff18861eb344f8af | 0.521382 | 3.609873 | false | false | false | false |
sorgelig/SAMCoupe_MIST | sid/adsr_multi.vhd | 1 | 7,734 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sid_debug_pkg.all;
-- LUT: 195, FF:68
entity adsr_multi is
generic (
g_num_voices : integer := 8 );
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
gate : in std_logic;
attack : in std_logic_vector(3 downto 0);
decay : in std_logic_vector(3 downto 0);
sustain : in std_logic_vector(3 downto 0);
release : in std_logic_vector(3 downto 0);
env_state: out std_logic_vector(1 downto 0); -- for testing only
env_out : out unsigned(7 downto 0) );
end adsr_multi;
-- 158 1 62 .. FF
-- 45 2 35 .. 61
-- 26 4 1C .. 34
-- 13 8 0D .. 1B
-- 6 16 07 .. 0C
-- 7 30 00 .. 06
architecture gideon of adsr_multi is
type presc_array_t is array(natural range <>) of unsigned(15 downto 0);
constant prescalers : presc_array_t(0 to 15) := (
X"0008", X"001F", X"003E", X"005E",
X"0094", X"00DB", X"010A", X"0138",
X"0187", X"03D0", X"07A1", X"0C35",
X"0F42", X"2DC7", X"4C4B", X"7A12" );
signal enveloppe : unsigned(7 downto 0) := (others => '0');
signal state : unsigned(1 downto 0) := (others => '0');
constant st_release : unsigned(1 downto 0) := "00";
constant st_attack : unsigned(1 downto 0) := "01";
constant st_decay : unsigned(1 downto 0) := "11";
type state_array_t is array(natural range <>) of unsigned(29 downto 0);
signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0'));
begin
env_out <= enveloppe;
env_state <= std_logic_vector(state);
-- FF-5E 01
-- 5D-37 02
-- 36-1B 04
-- 1A-0F 08
-- 0E-07 10
-- 06-01 1E
process(clock)
function logarithmic(lev: unsigned(7 downto 0)) return unsigned is
variable res : unsigned(4 downto 0);
begin
if lev = X"00" then
res := "00000"; -- prescaler off
elsif lev < X"07" then
res := "11101"; -- 1E-1
elsif lev < X"0F" then
res := "01111"; -- 10-1
elsif lev < X"1B" then
res := "00111"; -- 08-1
elsif lev < X"37" then
res := "00011"; -- 04-1
elsif lev < X"5E" then
res := "00001"; -- 02-1
else
res := "00000"; -- 01-1
end if;
return res;
end function logarithmic;
variable presc_select : integer range 0 to 15;
variable cur_state : unsigned(1 downto 0);
variable cur_env : unsigned(7 downto 0);
variable cur_pre15 : unsigned(14 downto 0);
variable cur_pre5 : unsigned(4 downto 0);
variable next_state : unsigned(1 downto 0);
variable next_env : unsigned(7 downto 0);
variable next_pre15 : unsigned(14 downto 0);
variable next_pre5 : unsigned(4 downto 0);
variable presc_val : unsigned(14 downto 0);
variable log_div : unsigned(4 downto 0);
variable do_count_15 : std_logic;
variable do_count_5 : std_logic;
begin
if rising_edge(clock) then
cur_state := state_array(0)(1 downto 0);
cur_env := state_array(0)(9 downto 2);
cur_pre15 := state_array(0)(24 downto 10);
cur_pre5 := state_array(0)(29 downto 25);
voice_o <= voice_i;
enable_o <= enable_i;
next_state := cur_state;
next_env := cur_env;
next_pre15 := cur_pre15;
next_pre5 := cur_pre5;
-- PRESCALER LOGIC, output: do_count --
-- 15 bit prescaler select --
case cur_state is
when st_attack =>
presc_select := to_integer(unsigned(attack));
when st_decay =>
presc_select := to_integer(unsigned(decay));
when others => -- includes release and idle
presc_select := to_integer(unsigned(release));
end case;
presc_val := prescalers(presc_select)(14 downto 0);
-- 15 bit prescaler counter --
do_count_15 := '0';
if cur_pre15 = presc_val then
next_pre15 := (others => '0');
do_count_15 := '1';
else
next_pre15 := cur_pre15 + 1;
end if;
-- 5 bit prescaler --
log_div := logarithmic(cur_env);
do_count_5 := '0';
if do_count_15='1' then
if (cur_state = st_attack) or cur_pre5 = log_div then
next_pre5 := "00000";
do_count_5 := '1';
else
next_pre5 := cur_pre5 + 1;
end if;
end if;
-- END PRESCALER LOGIC --
case cur_state is
when st_attack =>
if gate = '0' then
next_state := st_release;
elsif cur_env = X"FF" then
next_state := st_decay;
end if;
if do_count_15='1' then
next_env := cur_env + 1;
-- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!!
-- next_state := st_decay;
-- end if;
end if;
when st_decay =>
if gate = '0' then
next_state := st_release;
end if;
if do_count_15='1' and do_count_5='1' and
std_logic_vector(cur_env) /= (sustain & sustain) and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when st_release =>
if gate = '1' then
next_state := st_attack;
end if;
if do_count_15='1' and do_count_5='1' and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when others =>
next_state := st_release;
end case;
if enable_i='1' then
state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1);
state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state;
enveloppe <= next_env;
state <= next_state;
end if;
if reset='1' then
state <= "00";
enveloppe <= (others => '0');
enable_o <= '0';
end if;
end if;
end process;
end gideon;
| gpl-2.0 | 909f04d726840cb68d26d94b4e2db104 | 0.444272 | 3.921907 | false | false | false | false |
gregani/la16fw | syncflag.vhd | 1 | 2,883 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity syncflag is
generic(
n : integer := 3
);
port(
clk_input : in std_logic;
clk_output : in std_logic;
input : in std_logic;
output : out std_logic
);
end syncflag;
-- http://forums.xilinx.com/t5/Implementation/Attributes-in-Asynchronous-Input-Synchronization-issue-warnings/td-p/122912
--
-- TIG="TRUE" - Specifies a timing ignore for the asynchronous input
-- IOB="FALSE" = Specifies to not place the register into the IOB allowing
-- both synchronization registers to exist in the same slice
-- allowing for the shortest propagation time between them
-- ASYNC_REG="TRUE" - Specifies registers will be receiving asynchronous data
-- input to allow for better timing simulation
-- characteristics
-- SHIFT_EXTRACT="NO" - Specifies to the synthesis tool to not infer an SRL
-- HBLKNM="sync_reg" - Specifies to pack both registers into the same slice
architecture behavioral of syncflag is
signal sync : unsigned(n-1 downto 0) := (others=>'0');
signal flag_toggle : std_logic := '0';
signal sync_in : std_logic := '0';
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of sync_in : signal is "TRUE";
--attribute ASYNC_REG of sync_in : signal is "TRUE";
--attribute SHIFT_EXTRACT of sync : signal is "NO";
--attribute HBLKNM of sync : signal is "sync_reg";
begin
process (clk_input)
begin
if rising_edge(clk_input) then
flag_toggle <= flag_toggle xor input;
sync_in <= flag_toggle;
end if;
end process;
process (clk_output)
begin
if rising_edge(clk_output) then
sync <= sync(sync'high-1 downto 0) & sync_in;
end if;
end process;
output <= sync(sync'high) xor sync(sync'high-1);
end behavioral;
| gpl-2.0 | 8e49d4a68f5926760203bbfb62697eb8 | 0.662504 | 4.004167 | false | false | false | false |
6769/VHDL | Lab_1_partB/Segment7Decoder.vhd | 1 | 1,072 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; | gpl-2.0 | f2c9de45ab9e578a9240ea3d6498c35c | 0.630597 | 3.190476 | false | false | false | false |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@p@b_@f060_@i@p/_primary.vhd | 3 | 9,453 | library verilog;
use verilog.vl_types.all;
entity MSS_APB_F060_IP is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR : out vl_logic_vector(19 downto 0);
MSSPWDATA : out vl_logic_vector(31 downto 0);
MSSPWRITE : out vl_logic;
MSSPSEL : out vl_logic;
MSSPENABLE : out vl_logic;
MSSPRDATA : in vl_logic_vector(31 downto 0);
MSSPREADY : in vl_logic;
MSSPSLVERR : in vl_logic;
FABPADDR : in vl_logic_vector(31 downto 0);
FABPWDATA : in vl_logic_vector(31 downto 0);
FABPWRITE : in vl_logic;
FABPSEL : in vl_logic;
FABPENABLE : in vl_logic;
FABPRDATA : out vl_logic_vector(31 downto 0);
FABPREADY : out vl_logic;
FABPSLVERR : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
ADC12 : in vl_logic;
ADC13 : in vl_logic;
ADC14 : in vl_logic;
ADC15 : in vl_logic;
ADC16 : in vl_logic;
ADC17 : in vl_logic;
ADC18 : in vl_logic;
ADC19 : in vl_logic;
ADC20 : in vl_logic;
ADC21 : in vl_logic;
ADC22 : in vl_logic;
ADC23 : in vl_logic;
ADC24 : in vl_logic;
ADC25 : in vl_logic;
SDD0 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
TM0 : in vl_logic;
CM0 : in vl_logic;
GNDTM0 : in vl_logic;
VAREF0 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_APB_F060_IP;
| gpl-3.0 | a2291f516a1c33f529d37789ea4868ec | 0.404422 | 3.659698 | false | false | false | false |
1995parham/FPGA-Homework | BCD/bcd-8-multiplier.vhd | 1 | 1,136 | library ieee;
use ieee.std_logic_1164.all;
entity bcd_eight_multiplier is
port (a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (3 downto 0);
v: out std_logic_vector (35 downto 0));
end entity;
architecture structeral of bcd_eight_multiplier is
component bcd_multiplier is
port (a, b : in std_logic_vector (3 downto 0);
r : out std_logic_vector (7 downto 0));
end component;
component bcd_adder is
port (a : in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
res: out std_logic_vector (3 downto 0);
cout: out std_logic_vector (3 downto 0));
end component;
signal sum : std_logic_vector (31 downto 0);
signal c : std_logic_vector (35 downto 0);
begin
c (3 downto 0) <= "0000";
v (35 downto 32) <= c (35 downto 32);
M: for I in 0 to 7 generate
ms: bcd_multiplier port map (a => a(I * 4 + 3 downto I * 4), b => b, r(7 downto 4) => c(I * 4 + 7 downto I * 4 + 4), r(3 downto 0) => sum(I * 4 + 3 downto I * 4));
as: bcd_adder port map ("0000" & sum(I * 4 + 3 downto I * 4), c(I * 4 + 3 downto I * 4), v(I * 4 + 3 downto I * 4), open);
end generate M;
end architecture;
| gpl-3.0 | 70baeb997cbeb1e03b0c02240c6c7520 | 0.634683 | 2.784314 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/dpram/dpram.vhd | 1 | 40,715 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28400)
`protect data_block
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8gthHwI8PqI+X7JbEUjXEHcZGoL85QnHj1dYwpKY2XiOIR5EilCkxdmr9bd7K+/XxVDgwXWImfaa
mYq/B5vAxfm/RodjowNf3VmWc1pocpintHuc9q4FmPIAtjEajxU2uNb04fMhtDS6ssLXZnA2PZbX
WX9jmL/xzMrrRRpGd+qgNF8HudSDuOGMRL7R3jUhj+pyYwvPA/epdAA+XTEyltOQHHbZ02msllRy
2nySnfl05ePoGD/ZCEM=
`protect end_protected
| mit | 2627420d10a7d7eeedc23f502cc2b0c5 | 0.948839 | 1.845063 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/top/rtl/top.vhd | 4 | 8,204 | --
-- Copyright (c) 2011 OrphanedGland ([email protected])
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Top level file for bitcoin FPGA miner
--
-- The number of parallel SHA256 pairs is set via the NUM_CORES constant
--
-- Two different types of SHA256 cores can be selected by setting
-- the constant SHA256_SEL
-- SHA256_SEL = 0 => Pre-calculation of H+K+W used
-- SHA256_SEL = 1 => Quasi-pipelining used
--
-- This is largely a port of fpgaminer's fpgaminer_top.v (cb24cc3)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
port (
OSC_CLK : in std_logic
);
end entity top;
architecture top_rtl of top is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component altsource_probe is
generic (
enable_metastability : string := "NO";
instance_id : string := "UNUSED";
lpm_hint : string := "altsource_probe";
lpm_type : string := "altsource_probe";
probe_width : natural := 1;
sld_auto_instance_index : string := "YES";
sld_instance_index : natural := 0;
source_initial_value : string := "0";
source_width : natural := 1
);
port (
probe : in std_logic_vector(PROBE_WIDTH-1 downto 0) := (others => '0');
source : out std_logic_vector(SOURCE_WIDTH-1 downto 0);
source_clk : in std_logic := '0';
source_ena : in std_logic := '1'
);
end component altsource_probe;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
-- in-system debugging I/O
data_source: altsource_probe
generic map (
instance_id => "DAT2",
probe_width => 0,
source_width => 256
)
port map (
source => data_in
);
h_source: altsource_probe
generic map (
instance_id => "STAT",
probe_width => 0,
source_width => 256
)
port map (
source => h_in
);
gnon_probe: altsource_probe
generic map (
instance_id => "GNON",
probe_width => 32,
source_width => 0
)
port map (
probe => q_golden_nonce
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= (others => '0');
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= to_unsigned(i,q_nonce(i)'length);
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_rtl;
| gpl-3.0 | 3c041d3ac5d227117422a18e2b390dfa | 0.48842 | 3.912256 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/MemoryTop.vhd | 1 | 9,297 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:03:31 11/21/2013
-- Design Name:
-- Module Name: MemoryTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.std_logic_unsigned.all;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoryTop is
Port(
-- cpu connect
-- addr1 is instruction
address1 : in STD_LOGIC_VECTOR (15 downto 0);
output1 : out STD_LOGIC_VECTOR (15 downto 0);
-- addr2 is common memory
address2 : in STD_LOGIC_VECTOR (15 downto 0);
output2 : out STD_LOGIC_VECTOR (15 downto 0);
-- clocks
-- 50MHz in
clock : in STD_LOGIC;
-- 12.5MHz standard CPU clock out
cpuclock : out STD_LOGIC;
-- only for address 2
dataInput : in STD_LOGIC_VECTOR (15 downto 0); --only for address2
MemWrite : in STD_LOGIC;
MemRead : in STD_LOGIC;
-- connection with memory
memoryAddress : out STD_LOGIC_VECTOR (17 downto 0);
extendDatabus : inout STD_LOGIC_VECTOR(15 downto 0);
memoryEN : out STD_LOGIC;
memoryOE : out STD_LOGIC;
memoryRW : out STD_LOGIC;
-- line with flash
flash_byte : out std_logic;
flash_vpen : out std_logic;
flash_ce : out std_logic;
flash_oe : out std_logic;
flash_we : out std_logic;
flash_rp : out std_logic;
flash_addr : out std_logic_vector(22 downto 1);
flash_data : inout std_logic_vector(15 downto 0);
-- connection with serial port
serial_wrn : out STD_LOGIC;
serial_rdn : out STD_LOGIC;
serial_dataready : in STD_LOGIC;
serial_tsre : in STD_LOGIC;
serial_tbre : in STD_LOGIC;
-- basi cdatabus: ram1, serial port
basicdatabus : inout STD_LOGIC_VECTOR(7 downto 0);
-- to make ram1 disable not disturb databus (set to 1)
ram1_en : out STD_LOGIC;
reset : in STD_LOGIC;
--connection with keyboard
Keyboard_Data : in std_logic_vector(7 downto 0);
Keyboard_Dataready : in std_logic;
Keyboard_wrn : out std_logic;
--connection with vga
VGA_addr : out std_logic_vector(10 downto 0);
VGA_write : out std_LOGIC_vector(0 downto 0);
VGA_char : out std_logic_vector(7 downto 0)
);
end MemoryTop;
architecture Behavioral of MemoryTop is
-------------------------------------
-- CM
-- condition machine
type state_type is (
-- boot CM
BOOT, BOOT_FLASH, BOOT_RAM1, BOOT_RAM2, BOOT_READY,
-- work cpu CM
READ1, IDEL1, RW1, IDEL2
);
signal state : state_type := Boot;
-------------------------------------
-- flash
-- flash port
component FlashIO
port(
-- ×ÖģʽÏÂΪ22-1£¬×Ö½ÚģʽΪ22-0
addr: in std_logic_vector(22 downto 1);
datain: in std_logic_vector(15 downto 0);
dataout: out std_logic_vector(15 downto 0);
clk: in std_logic;
reset: in std_logic;
-- hard port
flash_byte : out std_logic;
flash_vpen : out std_logic;
flash_ce : out std_logic;
flash_oe : out std_logic;
flash_we : out std_logic;
flash_rp : out std_logic;
flash_addr : out std_logic_vector(22 downto 1);
flash_data : inout std_logic_vector(15 downto 0);
ctl_read : in std_logic;
ctl_write : in std_logic;
ctl_erase : in std_logic
);
end component;
signal ctl_read, ctl_write, ctl_erase : std_logic;
signal flash_addr_input : std_logic_vector(22 downto 1);
signal flash_data_input : std_logic_vector(15 downto 0);
signal flash_data_output : std_logic_vector(15 downto 0);
-- use for sleep to wait for data actually
signal flash_addr_count: std_logic_vector(7 downto 0);
signal flashpc : std_logic_vector(15 downto 0) := x"FFFF";
signal flash_hold_data : STD_LOGIC_VECTOR(15 downto 0);
-------------------------------------
-- Memory Control
-- store output1
signal buffer1: STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
-- store output2
signal buffer2: STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal bus_flag : STD_LOGIC;
signal BF01 : STD_LOGIC_VECTOR (15 downto 0);
signal BF03 : STD_LOGIC_VECTOR (15 downto 0);
signal readin, holder, addressTemp : STD_LOGIC_VECTOR (15 downto 0);
-------------------------------------
-- Serial port
signal serial_flag : STD_LOGIC;
signal serialHolder : STD_LOGIC_VECTOR (7 downto 0);
begin
-------------------------------------
-- kayboard
Keyboard_wrn <=
MemRead when (address2=x"BF02" and (state=IDEL2)) else '0';
BF03(0) <= Keyboard_Dataready;
BF03(15 downto 1) <= "000000000000000";
-------------------------------------
-- memory control
output1 <= buffer1;
output2 <= buffer2;
memoryEN <= '0';
memoryRW <=
'1' when (address2 = x"BF00" and state = RW1)
else NOT MemWrite when state = RW1
else '0' when (state = BOOT_RAM2)
else '1';
extendDatabus <= holder when bus_flag = '0' else "ZZZZZZZZZZZZZZZZ";
memoryAddress <= "00" & addressTemp;
with state select
addressTemp <=
address2 when IDEL2 | RW1,
address1 when IDEL1 | READ1,
FLASHPC when BOOT_FLASH | BOOT_RAM1 | BOOT_RAM2,
"0000000000000000" when others;
with state select
memoryOE <=
NOT MemRead when RW1,
'1' when BOOT_FLASH | BOOT_RAM1 | BOOT_RAM2,
'0' when others;
with state select
bus_flag <=
NOT MemWrite when RW1 | IDEL1,
'0' when BOOT_RAM1 | BOOT_RAM2,
'1' when others;
-- special addresss
BF01(0) <= serial_tsre and serial_tbre;
BF01(1) <= serial_dataready;
BF01(15 downto 2) <= "00000000000000";
-------------------------------------
-- serial port part
ram1_en <= '1'; --disable ram1
with state select
serial_flag <=
NOT MemWrite when RW1 | IDEL1 | IDEL2,
'1' when others;
basicDatabus <=
serialHolder when serial_flag = '0' else "ZZZZZZZZ";
-- serial port signal
serial_wrn <=
NOT MemWrite when (address2 = x"BF00" and state = RW1) else '1';
serial_rdn <=
NOT MemRead when (address2 = x"BF00" and ((state = IDEL1) or (state = RW1) or (state = IDEL2))) else '1';
serialHolder <= dataInput (7 downto 0);
-------------------------------------
-- flash part
flash: FlashIO port map(
addr=> flash_addr_input,
datain=> flash_data_input,
dataout=> flash_data_output,
clk=> clock,
reset=> reset,
-- hard port
flash_byte => flash_byte,
flash_vpen => flash_vpen,
flash_ce => flash_ce,
flash_oe => flash_oe,
flash_we => flash_we,
flash_rp => flash_rp,
flash_addr => flash_addr,
flash_data => flash_data,
-- signal to vhdl entity
ctl_read => ctl_read,
ctl_write => ctl_write,
ctl_erase => ctl_erase
);
-- design: will never write or erase flash
ctl_write <= '1';
ctl_erase <= '1';
-- when boot-flash then drop down ctl_read to read data from flash
with state select
ctl_read <=
'0' when BOOT_FLASH,
'1' when others;
-- when booting, data is from flash
with state select
holder <=
flash_hold_data when BOOT_FLASH | BOOT_RAM1 | BOOT_RAM2,
datainput when others;
-- 50 MHz -> 12.5MHz
with state select
cpuclock <=
'1' when IDEL1 | READ1,
'0' when others;
-------------------------------------
-- VGA
VGA_addr <= address2(10 downto 0);
VGA_char <= dataInput(7 downto 0);
VGA_write <=
"1" when ((MemWrite='1') and (state=RW1) and (address2(15 downto 12)=x"F"))else "0"; -- 1111 XXXX XXXX XXXX, > F
-------------------------------------
-- main machine part
process(clock, reset)
begin
if reset='0' then
state <= Boot; --TODO
buffer1 <= extendDatabus;
elsif clock'event and clock='1' then
case state is
-- BOOT from flash loops
when BOOT =>
flash_addr_count <= "00000000";
state <= BOOT_FLASH;
when BOOT_FLASH =>
case flash_addr_count is
when "00000000" =>
flash_addr_input <= flashpc + 1;
flashpc <= flashpc + 1;
flash_addr_count <= flash_addr_count + 1;
when "11111111" =>
flash_hold_data <= flash_data_output;
flash_addr_count <= "00000000";
state <= BOOT_RAM1;
when others =>
flash_addr_count <= flash_addr_count + 1;
end case;
when BOOT_RAM1 =>
state <= BOOT_RAM2;
when BOOT_RAM2 =>
if flashpc < x"0FFF" then
state <= BOOT_FLASH;
else
state <= BOOT_READY;
end if;
when BOOT_READY =>
state <= READ1;
-- normal CPU work loop
when READ1 =>
state <= IDEL1;
buffer1 <= extendDatabus;
when IDEL1 =>
state <= RW1;
when RW1 =>
state <= IDEL2;
case address2 is
when x"BF01" =>
buffer2 <= BF01;
when x"BF00" =>
buffer2 <= "00000000" & basicDatabus;
when x"BF02" =>
buffer2 <= "00000000" & Keyboard_Data;
-- buffer2 <= (others => '0');
when x"BF03" =>
buffer2 <= BF03;
when others =>
buffer2 <= extendDatabus;
end case;
when others =>
state <= READ1;
end case;
end if;
end process;
end Behavioral;
| mit | a858b5777bd1f23dbdc315a052d35975 | 0.608476 | 3.165475 | false | false | false | false |
gregani/la16fw | sample.vhd | 1 | 8,682 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
----------------------------------------------------------------------------------
--
-- samples the logic inputs and converts the data into blocks of 16 samples per
-- enabled channel
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sample is
port(
sample_clk : in std_logic; -- sample clock, 100 or 160MHz
sample_run : in std_logic; -- set to '1' to sample, '0' to reset
sample_rate_divisor : in std_logic_vector(7 downto 0); -- sample rate = clock / (div + 1)
logic_data : in std_logic_vector(15 downto 0); -- input pins
channel_select : in std_logic_vector(15 downto 0); -- channel select bits, async (must only be changed while sample_tick is inactive)
fifo_data : out std_logic_vector(15 downto 0) := (others=>'0'); -- data to fifo
fifo_reset : out std_logic := '0'; -- reset/clear fifo (sync'd to sample clock)
fifo_write : out std_logic; -- tell fifo to write data on next clock
fifo_full : in std_logic;
fifo_almost_full : in std_logic
);
end sample;
architecture behavioral of sample is
function sl2int(x : std_logic) return integer is
begin
if (x = '1') then return 1; else return 0; end if;
end;
subtype vector16_t is std_logic_vector(15 downto 0);
type vector16_arr_t is array (natural range <>) of vector16_t;
signal sample_run_get : std_logic; -- sample_run signal accross clock domains
signal sample_tick_count : unsigned(7 downto 0); -- used to divide sample clock
signal sample_tick : std_logic; -- flag when sample_tick_count reached zero
signal sample_count : unsigned(4 downto 0); -- count samples
signal logic_data_reg : std_logic_vector(15 downto 0); -- "register" input
signal input_write_reg : std_logic; -- used to switch between the two input shift regs
signal last_input_write_reg : std_logic;
signal input_shift_in : std_logic_vector(0 to 1); -- enable shift into input shiftreg
signal input_shift_out : std_logic_vector(0 to 1); -- enable shift out of input shiftreg
signal input_shiftreg_data : vector16_arr_t(0 to 1);
signal input_shiftreg_data_valid : std_logic;
signal write_to_fifo : std_logic := '0';
signal fifo_write_int : std_logic := '0';
signal fifo_write_sequence : vector16_t;
signal fifo_write_count : unsigned(3 downto 0);
signal fifo_ready : std_logic := '0';
attribute TIG : string;
attribute TIG of sample_rate_divisor : signal is "TRUE";
attribute TIG of channel_select : signal is "TRUE";
signal DEBUG : boolean := false;--true;
signal count : unsigned(31 downto 0);
signal wait_write : std_logic := '0';
begin
-- sync sample_run signal to sample_clk
signal_inst : entity work.syncsignal
port map(
clk_output => sample_clk,
input => sample_run,
output => sample_run_get
);
-- input shiftregs
gen : for i in 0 to 1 generate
begin
input_shiftreg_inst : entity work.input_shiftreg
port map (
clk => sample_clk,
shift_in => input_shift_in(i),
data_in => logic_data_reg,
shift_out => input_shift_out(i),
data_out => input_shiftreg_data(i)
);
end generate gen;
-- sample input data and write it to fifo
fifo_write <= fifo_write_int;
input_write_reg <= sample_count(4);
process (sample_clk)
begin
if rising_edge(sample_clk) then
-- divide sample clock
if (sample_run_get = '1') and (fifo_ready = '1') then
if (sample_tick_count = 0) then
sample_tick_count <= unsigned(sample_rate_divisor);
else
sample_tick_count <= sample_tick_count - 1;
end if;
else
sample_tick_count <= unsigned(sample_rate_divisor);
end if;
sample_tick <= '0';
if (sample_tick_count = 0) then
sample_tick <= '1';
end if;
-- write data from input shiftreg to fifo
last_input_write_reg <= input_write_reg;
input_shift_out <= (others=>'0');
fifo_write_int <= '0';
if (write_to_fifo = '1') then
input_shift_out(sl2int(not last_input_write_reg)) <= '1';
fifo_data <= input_shiftreg_data(sl2int(not last_input_write_reg));
fifo_write_int <= fifo_write_sequence(0);
fifo_write_sequence <= fifo_write_sequence(0) & fifo_write_sequence(15 downto 1);
fifo_write_count <= fifo_write_count + 1;
if (fifo_write_count = 15) then
write_to_fifo <= '0';
end if;
end if;
-- read input
logic_data_reg <= logic_data;
input_shift_in <= (others=>'0');
if (sample_run_get = '1') and (fifo_ready = '1') and (sample_tick = '1') then
-- shift data into currently active input shiftreg
input_shift_in(sl2int(input_write_reg)) <= '1';
-- shift enabled channels from other input shiftreg to fifo
--input_shift_out(sl2int(not input_write_reg)) <= '1';
-- count sample to know when to switch between input shiftreg etc.
sample_count <= sample_count + 1;
if (sample_count = 16) then
-- 16th sample so the first input shiftreg is full next clock edge
input_shiftreg_data_valid <= '1';
end if;
if (sample_count = 16) or ((input_shiftreg_data_valid = '1') and (sample_count = 0)) then
write_to_fifo <= '1';
input_shift_out(sl2int(not input_write_reg)) <= '1';
end if;
end if;
--debug
if DEBUG then
fifo_write_int <= '0';
wait_write <= '0';
if (sample_run_get = '1') and (fifo_ready = '1') and
( (fifo_almost_full = '0') or ((fifo_write_int = '0') and (fifo_full = '0')) ) and
(wait_write = '0') then--and (count /= 176*1024) then
fifo_data <= std_logic_vector(count(15 downto 0) + 1);
--fifo_data <= std_logic_vector(count(25 downto 10) + 1);
fifo_write_int <= '1';
--wait_write <= '1';
count <= count + 1;
end if;
end if;
-- check for overflow
if (fifo_ready = '1') and (fifo_full = '1') then
-- FIXME: set some status bit?
end if;
-- reset
fifo_reset <= '0';
if (fifo_ready = '0') and (fifo_full = '0') then
fifo_ready <= '1';
end if;
if (sample_run_get = '0') then
sample_count <= (others=>'0');
last_input_write_reg <= '0';
input_shiftreg_data_valid <= '0';
write_to_fifo <= '0';
fifo_write_sequence <= channel_select;
fifo_write_count <= (others=>'0');
fifo_ready <= '0';
fifo_data <= (others=>'0');
fifo_reset <= '1';
count <= (others=>'0');
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 25470e97e20fe905add41e1cf0a17469 | 0.524994 | 4.097216 | false | false | false | false |
6769/VHDL | Lab_5/Modelsim/View.vhd | 1 | 1,718 | library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
entity View is
port(
Rb, Reset, CLK: in bit;
Win, Lose:out bit;
hex0,hex1:out unsigned(7 downto 0)
);
end entity View;
architecture Combination of View is
component clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end component;
component DiceGame_controller_text
port(Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end component;
component Segment7Decoder is
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end component;
component Roll_Sum is
port(Rb,CLK,Reset:in bit;
hex0,hex1:out integer range 6 downto 1;
Sum:out integer range 12 downto 2
);
end component;
signal mid_Roll,mid_Carry,mid_Lose,mid_Win,mid_CLK:bit;
signal mid_Sum:integer range 12 downto 2;
signal mid_hex0,mid_hex1:integer range 6 downto 1;
signal mid_hex0_unsigned,mid_hex1_unsigned:unsigned(3 downto 0);
begin
label_clock:clock_signal_per_second port map(CLK,mid_CLK);
label_control:DiceGame_controller_text port map(Rb,Reset,mid_CLK,mid_Sum,mid_Roll,mid_Win,mid_Lose);
label_Roll_sum:Roll_Sum port map(mid_Roll,mid_CLK,Reset,mid_hex0,mid_hex1,mid_Sum);
Dispaly_hex0:Segment7Decoder port map(mid_hex0_unsigned,hex0(7 downto 1));
Dispaly_hex1:Segment7Decoder port map(mid_hex1_unsigned,hex1(7 downto 1));
mid_hex0_unsigned<=to_unsigned(mid_hex0,4);
mid_hex1_unsigned<=to_unsigned(mid_hex1,4);
hex0(0)<='1';--shutdown Dot..
hex1(0)<='1';
Win<=mid_Win;
Lose<=mid_Lose;
end architecture Combination ;
| gpl-2.0 | f4355f3f826f0427ce122f577c470d40 | 0.689756 | 3.008757 | false | false | false | false |
gregani/la16fw | mainmodule.vhd | 1 | 13,937 | --
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
----------------------------------------------------------------------------------
--
-- connect all stuff together
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mainmodule is
generic(
-- spi addresses
ADDRESS_FPGA_VERSION : integer := 0;
ADDRESS_STATUS_CONTROL : integer := 1;
ADDRESS_CHANNEL_SELECT_LO : integer := 2;
ADDRESS_CHANNEL_SELECT_HI : integer := 3;
ADDRESS_SAMPLE_RATE_DIVISOR : integer := 4;
ADDRESS_LED_BRIGHTNESS : integer := 5;
ADDRESS_SAMPLE_CLOCK_CONTROL : integer := 10;
FPGA_VERSION : integer := 16;
-- other constants
tick_1M_div : integer := 48 -- divider to get 1MHz from 48MHz clk
);
port(
-- always used
clk_in : in std_logic; --external clock input
led : out std_logic;
spi_ss_n : in std_logic;
spi_sclk : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic;
-- parallel data bus to fx2 chip
fifo_clk : in std_logic; -- 48MHz clock for the fifo bus
fifo_empty : out std_logic; -- flag the fx2 whether the fifo is empty (fx2 RDY0 pin)
fifo_read_n : in std_logic; -- low while the fx2 reads data, high otherwise
fifo_data : out std_logic_vector(15 downto 0);
-- logic inputs
logic_data : in std_logic_vector(15 downto 0)
-- logic_data : out std_logic_vector(15 downto 0)
);
end mainmodule;
architecture behavioral of mainmodule is
-- reset
signal reset : std_logic := '1';
signal reset_count : unsigned(4 downto 0) := (others=>'1');
signal reset_dcm : std_logic;
-- clock
signal clk : std_logic; -- 48MHz clock signal from the selected DCM
signal clk_a, clk_b : std_logic;
signal clk_c, clk_d : std_logic;
signal clk_100M : std_logic; -- 100MHz clock from dcm1
signal clk_100M_locked : std_logic;
signal clk_160M : std_logic; -- 160MHz clock from dcm2
signal clk_160M_locked : std_logic;
signal clk_user : std_logic; -- user clock
signal clk_user_2x : std_logic; -- 2x user clock from dcm3
signal clk_user_2x_locked : std_logic;
signal clk_user_4x : std_logic; -- 4x user clock from dcm4
signal clk_user_4x_locked : std_logic;
signal tick_1M : std_logic := '0';
signal tick_1M_count : unsigned(5 downto 0) := (others=>'0');
-- internal data bus FIXME: spi
signal spi_enable_write : std_logic;
signal spi_enable_read : std_logic;
signal spi_addr : std_logic_vector(6 downto 0);
signal spi_data_out : std_logic_vector(7 downto 0);
signal spi_data_in : std_logic_vector(7 downto 0);
-- status/control
signal led_brightness : std_logic_vector(7 downto 0);
signal led_invert : std_logic;
signal sample_run : std_logic := '0'; -- set to '1' to sample data
signal status_bit6 : std_logic;
signal sample_rate_divisor : std_logic_vector(7 downto 0); -- sample rate is base clock / (rate_divisor + 1)
signal sample_clk_sel : unsigned(1 downto 0); -- 0: clk_100M, 1: clk_160M, 2: user 2x, 3: user 4x
signal sample_clk : std_logic; -- sample clock, 100 or 160MHz
signal selected_channels : std_logic_vector(15 downto 0);
-- fifo to buffer logic data (from the core generator)
signal fifo_reset : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_data_in : std_logic_vector(15 downto 0);
signal fifo_data_out : std_logic_vector(15 downto 0);
signal fifo_enable_read : std_logic;
signal fifo_enable_write : std_logic;
signal fifo_full : std_logic;
signal fifo_almost_full : std_logic;
-- debug
signal debug : std_logic_vector(15 downto 0);
begin
-- debug
--logic_data <= debug;
debug(0) <= sample_run;
--debug(2) <= fifo_almost_empty;
--debug(2) <= not fifo_read_n;
debug(2) <= '1' when (unsigned(fifo_data_out) = 165) else '0';
-- clock units: generates 100MHz and 160MHz from 48MHz input
clock_100M_inst : entity work.clock
generic map(
CLK_FAST_DIV => 12,
CLK_FAST_MUL => 25,
STARTUP_WAIT => true
)
port map(
clk_in => clk_in,
reset => reset_dcm,
clk => clk_a,
clk_fb => clk_a,
clk_fast => clk_100M,
locked => clk_100M_locked
);
clock_160M_inst : entity work.clock
generic map(
CLK_FAST_DIV => 3,
CLK_FAST_MUL => 10,
STARTUP_WAIT => true
)
port map(
clk_in => clk_in,
reset => reset_dcm,
clk => clk_b,
clk_fb => clk_b,
clk_fast => clk_160M,
locked => clk_160M_locked
);
-- clock_user1_inst : entity work.clock
-- generic map(
-- CLK_FAST_DIV => 1,
-- CLK_FAST_MUL => 2
-- )
-- port map(
-- clk_in => clk_user,
-- reset => reset_dcm,
-- clk => clk_c,
-- clk_fb => clk_c,
-- clk_fast => clk_user_2x,
-- locked => clk_user_2x_locked
-- );
-- clock_user2_inst : entity work.clock
-- generic map(
-- CLK_FAST_DIV => 1,
-- CLK_FAST_MUL => 4
-- )
-- port map(
-- clk_in => clk_user,
-- reset => reset_dcm,
-- clk => clk_d,
-- clk_fb => clk_d,
-- clk_fast => clk_user_4x,
-- locked => clk_user_4x_locked
-- );
clk_user <= logic_data(15);
clockmux_inst : entity work.clockmux
generic map(
n_log2 => 2
)
port map(
clk_ctl => clk,
clk_sel => std_logic_vector(sample_clk_sel),
clk_in(0) => clk_100M,
clk_in(1) => clk_160M,
clk_in(2) => '0',--clk_user_2x,
clk_in(3) => '0',--clk_user_4x,
clk_out => sample_clk
);
clk <= clk_in; --FIXME: which clock to use for logic?
-- FIXME: use a BUFGMUX or custom circuit to avoid glitches
--sample_clk <= clk_100M when (sample_clk_sel = '0') else clk_160M;
-- led unit: creates pwm signal for the led from 1MHz tick
led_inst : entity work.led
port map(
clk => clk,
reset => reset,
tick_1M => tick_1M,
brightness => led_brightness,
invert => led_invert,
led => led
);
-- spi unit: provides the control interface to the fx2 chip
spi_inst : entity work.spi
port map(
clk => clk,
reset => reset,
enable_write => spi_enable_write,
enable_read => spi_enable_read,
addr => spi_addr,
data_out => spi_data_out,
data_in => spi_data_in,
ss_n => spi_ss_n,
sclk => spi_sclk,
mosi => spi_mosi,
miso => spi_miso
);
-- fifo unit
-- used for buffering the data between logic input and fx2
-- output is connected to the fx2
-- input is connected to the sample unit
fifo_inst : entity work.fifo
port map(
reset => fifo_reset,
clk_write => sample_clk,
clk_read => fifo_clk,
data_in => fifo_data_in,
enable_write => fifo_enable_write,
enable_read => fifo_enable_read,
data_out => fifo_data_out,
full => fifo_full,
almost_full => fifo_almost_full,
almost_empty => fifo_almost_empty
);
-- for some reason the fx2 reads one word too much if empty is used
fifo_empty <= fifo_almost_empty or (not sample_run);
fifo_data <= fifo_data_out;
fifo_enable_read <= (not fifo_read_n);
-- sample logic inputs
sample_inst : entity work.sample
port map(
sample_clk => sample_clk,
sample_run => sample_run,
sample_rate_divisor => sample_rate_divisor,
channel_select => selected_channels,
logic_data => logic_data,
--logic_data => (others=>'0'),
fifo_data => fifo_data_in,
fifo_reset => fifo_reset,
fifo_write => fifo_enable_write,
fifo_full => fifo_full,
fifo_almost_full => fifo_almost_full
);
-- create internal reset signal from 48MHz input clock
process(clk_in)
begin
if rising_edge(clk_in) then
if (reset_count = 0) then
reset <= '0';
else
reset <= '1';
end if;
if (reset_count /= 0) and
(((clk_100M_locked = '1') and (clk_160M_locked = '1')) or
(reset_count /= 5)) then
reset_count <= reset_count - 1;
end if;
end if;
end process;
-- make sure dcm clock starts/runs while reset is still '1'
reset_dcm <= '1' when (reset_count > 2**reset_count'length-5) else '0';
-- create 1MHz tick from 48MHz clock
process(clk)
begin
if rising_edge(clk) then
-- create 1MHz tick
if (tick_1M_count = 0) then
tick_1M <= '1';
tick_1M_count <= to_unsigned(tick_1M_div - 1, tick_1M_count'length);
else
tick_1M <= '0';
tick_1M_count <= tick_1M_count - 1;
end if;
end if;
end process;
-- handle reset and spi
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
sample_clk_sel <= (others=>'0');
spi_data_in <= (others=>'0');
-- init status/control
led_brightness <= (others=>'0');
led_invert <= '0';
sample_run <= '0';
status_bit6 <= '0';
selected_channels <= (others=>'1');
sample_rate_divisor <= (others=>'0');
else
-- handle spi
spi_data_in <= (others=>'0');
if (spi_enable_read = '1') then
if (unsigned(spi_addr) = ADDRESS_FPGA_VERSION) then
spi_data_in <= std_logic_vector(to_unsigned(FPGA_VERSION, spi_data_in'length));
elsif (unsigned(spi_addr) = ADDRESS_STATUS_CONTROL) then
spi_data_in <= "0" & status_bit6 & "00100" & sample_run;
elsif (unsigned(spi_addr) = ADDRESS_CHANNEL_SELECT_LO) then
spi_data_in <= selected_channels(7 downto 0);
elsif (unsigned(spi_addr) = ADDRESS_CHANNEL_SELECT_HI) then
spi_data_in <= selected_channels(15 downto 8);
elsif (unsigned(spi_addr) = ADDRESS_SAMPLE_RATE_DIVISOR) then
spi_data_in <= sample_rate_divisor;
elsif (unsigned(spi_addr) = ADDRESS_LED_BRIGHTNESS) then
spi_data_in <= led_brightness;
elsif (unsigned(spi_addr) = ADDRESS_SAMPLE_CLOCK_CONTROL) then
spi_data_in <= "0000000" & sample_clk_sel(0);
end if;
end if;
if (spi_enable_write = '1') then
if (unsigned(spi_addr) = ADDRESS_STATUS_CONTROL) then
sample_run <= spi_data_out(0);
status_bit6 <= spi_data_out(6);
led_invert <= spi_data_out(0);
elsif (unsigned(spi_addr) = ADDRESS_CHANNEL_SELECT_LO) then
selected_channels(7 downto 0) <= spi_data_out;
elsif (unsigned(spi_addr) = ADDRESS_CHANNEL_SELECT_HI) then
selected_channels(15 downto 8) <= spi_data_out;
elsif (unsigned(spi_addr) = ADDRESS_SAMPLE_RATE_DIVISOR) then
sample_rate_divisor <= spi_data_out;
elsif (unsigned(spi_addr) = ADDRESS_LED_BRIGHTNESS) then
led_brightness <= spi_data_out;
elsif (unsigned(spi_addr) = ADDRESS_SAMPLE_CLOCK_CONTROL) then
sample_clk_sel(0) <= spi_data_out(0);
elsif (unsigned(spi_addr) = 123) then--foo
sample_clk_sel(1) <= spi_data_out(0);--bogus
end if;
end if;
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | f95a6cbb260b12d18b972a9d2bb432d9 | 0.505489 | 3.852128 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/family_support.vhd | 12 | 329,235 | --------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package family_support is
type families_type is
(
nofamily
, kintex8
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex8
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix8
, artix7
, aartix7
, artix7l
, qartix7
, qartix7l
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 865;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
-- Primitives added for OLYMPUS support
constant u_BUFGCE_DIV : primitives_type := u_ZHOLD_DELAY +1;
constant u_BUFCE_ROW : primitives_type := u_BUFGCE_DIV +1;
constant u_BUFCE_LEAF : primitives_type := u_BUFCE_ROW +1;
constant u_MMCME3_ADV : primitives_type := u_BUFCE_LEAF +1;
constant u_MMCME3_BASE : primitives_type := u_MMCME3_ADV +1;
constant u_DNA_PORTE3 : primitives_type := u_MMCME3_BASE +1;
constant u_FRAME_ECCE3 : primitives_type := u_DNA_PORTE3 +1;
constant u_ICAPE3 : primitives_type := u_FRAME_ECCE3 +1;
constant u_JTAG_SIME3 : primitives_type := u_ICAPE3 +1;
constant u_MCAP : primitives_type := u_JTAG_SIME3 +1;
constant u_SIM_CONFIGE3 : primitives_type := u_MCAP +1;
constant u_SYSMONE1 : primitives_type := u_SIM_CONFIGE3 +1;
constant u_CARRY8 : primitives_type := u_SYSMONE1 +1;
constant u_DSP48E2 : primitives_type := u_CARRY8 +1;
constant u_DSP_A_B_DATA : primitives_type := u_DSP48E2 +1;
constant u_DSP_ALU : primitives_type := u_DSP_A_B_DATA +1;
constant u_DSP_C_DATA : primitives_type := u_DSP_ALU +1;
constant u_DSP_M_DATA : primitives_type := u_DSP_C_DATA +1;
constant u_DSP_MULTIPLIER : primitives_type := u_DSP_M_DATA +1;
constant u_DSP_OUTPUT : primitives_type := u_DSP_MULTIPLIER +1;
constant u_DSP_PREADD : primitives_type := u_DSP_OUTPUT +1;
constant u_DSP_PREADD_DATA : primitives_type := u_DSP_PREADD +1;
constant u_FIFO18E2 : primitives_type := u_DSP_PREADD_DATA +1;
constant u_FIFO36E2 : primitives_type := u_FIFO18E2 +1;
constant u_RAMB18E2 : primitives_type := u_FIFO36E2 +1;
constant u_RAMB36E2 : primitives_type := u_RAMB18E2 +1;
constant u_RAM256X1D : primitives_type := u_RAMB36E2 +1;
constant u_RAM512X1S : primitives_type := u_RAM256X1D +1;
constant u_RAM32M16 : primitives_type := u_RAM512X1S +1;
constant u_RAM64M8 : primitives_type := u_RAM32M16 +1;
constant u_SYNC_UNIT : primitives_type := u_RAM64M8 +1;
constant u_BUFG_GT : primitives_type := u_SYNC_UNIT +1;
constant u_GTHE3_CHANNEL : primitives_type := u_BUFG_GT +1;
constant u_GTHE3_COMMON : primitives_type := u_GTHE3_CHANNEL +1;
constant u_GTPE3_CHANNEL : primitives_type := u_GTHE3_COMMON +1;
constant u_GTPE3_COMMON : primitives_type := u_GTPE3_CHANNEL +1;
constant u_GTY : primitives_type := u_GTPE3_COMMON +1;
constant u_GTZE2_OCTAL : primitives_type := u_GTY +1;
constant u_IBUFDS_GTE3 : primitives_type := u_GTZE2_OCTAL +1;
constant u_OBUFDS_GTE3 : primitives_type := u_IBUFDS_GTE3 +1;
constant u_PCIE_3_1 : primitives_type := u_OBUFDS_GTE3 +1;
constant u_IDELAYE3 : primitives_type := u_PCIE_3_1 +1;
constant u_ISERDESE3 : primitives_type := u_IDELAYE3 +1;
constant u_ODELAYE3 : primitives_type := u_ISERDESE3 +1;
constant u_OSERDESE3 : primitives_type := u_ODELAYE3 +1;
constant u_TXPLL : primitives_type := u_OSERDESE3 +1;
constant u_BITSLICE_CONTROL : primitives_type := u_TXPLL +1;
constant u_RX_BITSLICE : primitives_type := u_BITSLICE_CONTROL +1;
constant u_TX_BITSLICE : primitives_type := u_RX_BITSLICE +1;
constant u_IBUFCTRL : primitives_type := u_TX_BITSLICE +1;
constant u_DIFFINBUF : primitives_type := u_IBUFCTRL +1;
constant u_ADDMACC_MACRO : primitives_type := u_DIFFINBUF +1;
constant u_ADDSUB_MACRO : primitives_type := u_ADDMACC_MACRO +1;
constant u_BRAM_SDP_MACRO : primitives_type := u_ADDSUB_MACRO +1;
constant u_BRAM_SINGLE_MACRO : primitives_type := u_BRAM_SDP_MACRO +1;
constant u_BRAM_TDP_MACRO : primitives_type := u_BRAM_SINGLE_MACRO +1;
constant u_COUNTER_LOAD_MACRO : primitives_type := u_BRAM_TDP_MACRO +1;
constant u_COUNTER_TC_MACRO : primitives_type := u_COUNTER_LOAD_MACRO +1;
constant u_EQ_COMPARE_MACRO : primitives_type := u_COUNTER_TC_MACRO +1;
constant u_FIFO_DUALCLOCK_MACRO : primitives_type := u_EQ_COMPARE_MACRO +1;
constant u_FIFO_SYNC_MACRO : primitives_type := u_FIFO_DUALCLOCK_MACRO +1;
constant u_MACC_MACRO : primitives_type := u_FIFO_SYNC_MACRO +1;
constant u_MULT_MACRO : primitives_type := u_MACC_MACRO +1;
constant u_PLLE3_ADV : primitives_type := u_MULT_MACRO +1;
constant u_PLLE3_BASE : primitives_type := u_PLLE3_ADV +1;
constant u_ODDRE1 : primitives_type := u_PLLE3_BASE +1;
constant u_IDDRE1 : primitives_type := u_ODDRE1 +1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package family_support;
package body family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artix8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex8 => return "virtex8" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex8 => return "kintex8" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix8 => return "artix8" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when qartix7l => return "qartix7l" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- Virtex7 Root family
if (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7l" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- Kintex8 Root family
Elsif (equalIgnoringCase(family_in, "kintex8" )) Then return "kintex8" ;
-- Virtex8 Root family
Elsif (equalIgnoringCase(family_in, "virtex8" )) Then return "virtex8" ;
-- artix8 Root family
Elsif (equalIgnoringCase(family_in, "artix8" )) Then return "artix8" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body family_support;
| mit | fa5e7723b37a56357a0fa798212a8773 | 0.320134 | 3.089426 | false | false | false | false |
fpgaddicted/car_taillights_animation-engine | alarm_anim.vhd | 1 | 1,659 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco (fpgaddicted)
--
-- Create Date: 18:58:26 04/27/2017
-- Design Name:
-- Module Name: alarm_anim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.2 - Bug fix
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alarm_anim is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
led_out : out STD_LOGIC_VECTOR (2 downto 0));
end alarm_anim;
architecture animation_engine of alarm_anim is
type state is (s0,s1);
signal s : state;
begin
process(clk,reset,s,en)
variable i: integer:=0;
begin
if rising_edge(clk) then
if (reset = '1') or (en = '0') then
s <= s0;
led_out <= "000";
else
case s is
when s0=>
i:=i+1;
led_out <="000";
if(i=12500000) then
i:=0;
s <= s1;
end if;
when s1=>
i:=i+1;
led_out <="111";
if(i=12500000) then
i:=0;
s <= s0;
end if;
end case;
end if;
end if;
end process;
end animation_engine;
| gpl-3.0 | bf710bcd94d3d737ff19512f84a5be6c | 0.52381 | 3.344758 | false | false | false | false |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/synth/zynq_1_axi_gpio_0_0.vhd | 3 | 9,974 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY zynq_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_axi_gpio_0_0;
ARCHITECTURE zynq_1_axi_gpio_0_0_arch OF zynq_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_1_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_1_axi_gpio_0_0_arch : ARCHITECTURE IS "zynq_1_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_1_axi_gpio_0_0_arch: ARCHITECTURE IS "zynq_1_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=32,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 32,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_1_axi_gpio_0_0_arch;
| mit | e898c89340e654bc9d638b0d9e0e1703 | 0.685783 | 3.149353 | false | false | false | false |
zzhou007/161lab | lab6/CAM_Array.vhd | 1 | 1,387 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Array is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 4 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end CAM_Array;
architecture Behavioral of CAM_Array is
component CAM_Row is
Generic (CAM_WIDTH : integer := 8) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
row_match : out STD_LOGIC);
end component ;
begin
GEN_REG:
for i in 0 to (CAM_DEPTH-1) generate
cam_array : cam_row
generic map
(
CAM_WIDTH => CAM_WIDTH
)
port map
(
clk => clk,
rst => rst,
we => we_decoded_row_address(i),
search_word => search_word,
dont_care_mask => dont_care_mask,
row_match => decoded_match_address(i)
);
end generate GEN_REG;
end Behavioral;
| gpl-2.0 | c1c032a5c43f5bef3659127d6e10a8df | 0.591204 | 3.075388 | false | false | false | false |
quicky2000/top_mandelbrot_1b | mandel_loop.vhd | 1 | 3,829 | --
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mandel_loop is
Port ( clk : in std_logic;
rst : std_logic;
x : in STD_LOGIC_VECTOR (15 downto 0);
y : in STD_LOGIC_VECTOR (15 downto 0);
nb_iter_max : in STD_LOGIC_VECTOR (5 downto 0);
ok : out STD_LOGIC;
ready : out std_logic);
end mandel_loop;
architecture Behavioral of mandel_loop is
signal x_n_plus_1 : std_logic_vector(15 downto 0) := (others => '0'); -- x * x
signal y_n_plus_1 : std_logic_vector(15 downto 0) := (others => '0'); -- y * y
signal x_n : std_logic_vector(15 downto 0) := (others => '0'); -- x * x
signal y_n : std_logic_vector(15 downto 0) := (others => '0'); -- y * y
signal x_square_in : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal y_square_in : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal x_square_out : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal y_square_out : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
begin
x_x_mult : entity work.mult_16_8
port map (
a => x_square_in,
b => x_square_in,
p => x_square_out);
y_y_mult : entity work.mult_16_8
port map (
a => y_square_in,
b => y_square_in,
p => y_square_out);
inst_mandel_iter : entity work.mandel_iter
port map (
x_n => x_n,
y_n => y_n,
x_square_in => x_square_out,
y_square_in => y_square_out,
a => x,
b => y,
x_n_plus_1 => x_n_plus_1,
y_n_plus_1 => y_n_plus_1);
compute_process : process (clk, rst)
variable l_nb_iter : natural range 0 to 127:= 0; -- current iteration
begin -- process compute_process
if rising_edge(clk) then -- rising clock edge
if rst = '1' then -- asynchronous reset (active low)
ok <= '0';
l_nb_iter := 0;
x_square_in <= x;
y_square_in <= y;
x_n <= x;
y_n <= y;
ready <= '0';
ok <= '0';
else
-- if l_nb_iter /= 0 then
x_square_in <= x_n_plus_1;
y_square_in <= y_n_plus_1;
x_n <= x_n_plus_1;
y_n <= y_n_plus_1;
-- else
-- x_square_in <= x;
-- y_square_in <= y;
-- end if;
if unsigned(x_square_out) + unsigned(y_square_out) > 16#400# then
ready <= '1';
ok <= '0';
else
if l_nb_iter /= unsigned(nb_iter_max) then
l_nb_iter := l_nb_iter +1;
ready <= '0';
ok <= '0';
else
ready <= '1';
ok <= '1';
end if;
end if;
end if ;
end if;
end process compute_process;
end Behavioral;
| gpl-3.0 | 06bec67707b4c4e2fc8316d5e39b735a | 0.56046 | 3.223064 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/fifo_mem.vhd | 2 | 5,775 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_mem.vhd when simulating
-- the core, fifo_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_mem IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END fifo_mem;
ARCHITECTURE fifo_mem_a OF fifo_mem IS
-- synthesis translate_off
COMPONENT wrapped_fifo_mem
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "fifo_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_mem
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END fifo_mem_a;
| mit | 019ce6e4e0c25e05a040762d9ba48415 | 0.532641 | 3.915254 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_fifo_ifmodule.vhd | 1 | 19,704 | -------------------------------------------------------------------------------
-- $Id: qspi_fifo_ifmodule.vhd
-------------------------------------------------------------------------------
-- qspi_fifo_ifmodule.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_fifo_ifmodule.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (QSPI) Module for interfacing
-- with a 32-bit axi Bus. FIFO Interface module
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - First version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.RESET_ACTIVE;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_RcFIFO_RdCE -- Bus2IP receive FIFO read CE
-- Bus2IP_TxFIFO_WrCE -- Bus2IP transmit FIFO write CE
-- Rd_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- Wr_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- IP2Bus_RX_FIFO_Data -- Data to send on the bus
-- Transmit_ip2bus_error -- Transmit FIFO error signal
-- Receive_ip2bus_error -- Receive FIFO error signal
-- FIFO INTERFACE
-- Data_From_TxFIFO -- Data from transmit FIFO
-- Tx_FIFO_Data_WithZero -- Components to put zeros on input
-- to Shift Register when FIFO is empty
-- Data_From_Rc_FIFO -- Receive FIFO data output
-- Rc_FIFO_Empty -- Receive FIFO empty
-- Rc_FIFO_Full -- Receive FIFO full
-- Rc_FIFO_Full_strobe -- 1 cycle wide receive FIFO full strobe
-- Tx_FIFO_Empty -- Transmit FIFO empty
-- Tx_FIFO_Empty_strobe -- 1 cycle wide transmit FIFO full strobe
-- Tx_FIFO_Full -- Transmit FIFO full
-- Tx_FIFO_Occpncy_MSB -- Transmit FIFO occupancy register
-- MSB bit
-- Tx_FIFO_less_half -- Transmit FIFO less than half empty
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SPIXfer_done -- SPI transfer done flag
-- DTR_Underrun_strobe -- DTR Underrun Strobe bit
-- DTR_underrun -- DTR underrun generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_fifo_ifmodule is
generic
(
C_NUM_TRANSFER_BITS : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_RcFIFO_RdCE : in std_logic;
Bus2IP_TxFIFO_WrCE : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
-- FIFO ports
Data_From_TxFIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Data_From_Rc_FIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Tx_FIFO_Data_WithZero: out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
IP2Bus_RX_FIFO_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
---------------------
Rc_FIFO_Full : in std_logic;
Rc_FIFO_Full_strobe : out std_logic;
---------------------
Tx_FIFO_Empty : in std_logic;
Tx_FIFO_Empty_strobe : out std_logic;
---------------------
Rc_FIFO_Empty : in std_logic;
Receive_ip2bus_error : out std_logic;
Tx_FIFO_Full : in std_logic;
Transmit_ip2bus_error: out std_logic;
---------------------
Tx_FIFO_Occpncy_MSB : in std_logic;
Tx_FIFO_less_half : out std_logic;
---------------------
DTR_underrun : in std_logic;
DTR_Underrun_strobe : out std_logic;
---------------------
SPIXfer_done : in std_logic;
rready : in std_logic
--DRR_Overrun_reg : out std_logic
---------------------
);
end qspi_fifo_ifmodule;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_fifo_ifmodule is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
-- signal drr_Overrun_i : std_logic;
signal rc_FIFO_Full_d1 : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal tx_FIFO_Empty_d1 : std_logic;
signal tx_FIFO_Occpncy_MSB_d1 : std_logic;
signal dtr_underrun_d1 : std_logic;
signal RST_TxFIFO_ptr_int : std_logic;
signal DRR_Overrun_reg_int : std_logic;
---------------------------------------------
begin
-----
-- Combinatorial operations
-------------------------------------------------------------------------------
-- DRR_Overrun_reg <= DRR_Overrun_reg_int;
-------------------------------------------------------------------------------
-- SPI_RECEIVE_FIFO_RD_GENERATE : Read of SPI receive FIFO
----------------------------------
SPI_RECEIVE_FIFO_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
-----
begin
-----
IP2Bus_RX_FIFO_Data(i) <= Data_From_Rc_FIFO(i) and
(
(Rd_ce_reduce_ack_gen or rready) and
Bus2IP_RcFIFO_RdCE
);
end generate SPI_RECEIVE_FIFO_RD_GENERATE;
-------------------------------------------------------------------------------
-- PUT_ZEROS_IN_SR_GENERATE : Put zeros on input to SR when FIFO is empty.
-- Requested by software designers
------------------------------
PUT_ZEROS_IN_SR_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
Tx_FIFO_Data_WithZero(i) <= Data_From_TxFIFO(i) and (not Tx_FIFO_Empty);
end generate PUT_ZEROS_IN_SR_GENERATE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS : Strobe error when receive FIFO is empty.
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
RX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Receive_ip2bus_error <= '0';
else
Receive_ip2bus_error <= Rc_FIFO_Empty and Bus2IP_RcFIFO_RdCE;
end if;
end if;
end process RX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- TX_ERROR_ACK_REG_PROCESS : Strobe error when transmit FIFO is full
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
TX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Transmit_ip2bus_error <= '0';
else
Transmit_ip2bus_error <= Tx_FIFO_Full and Bus2IP_TxFIFO_WrCE;
end if;
end if;
end process TX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- **********************************************************
-- Below logic will generate the inputs to the Interrupt bits
-- **********************************************************
-------------------------------------------------------------------------------
-- I_DRR_OVERRUN_REG_PROCESS:DRR overrun strobe-1 cycle strobe will be generated
-----------------------------
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rc_FIFO_Full and
SPIXfer_done;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
-------------------------------------------------------------------------------
-- RX_FIFO_STROBE_REG_PROCESS : Strobe when receive FIFO is full
----------------------------------
RX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
rc_FIFO_Full_d1 <= '0';
else
rc_FIFO_Full_d1 <= Rc_FIFO_Full;
end if;
end if;
end process RX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Rc_FIFO_Full_strobe <= (not rc_FIFO_Full_d1) and Rc_FIFO_Full;
-- TX_FIFO_STROBE_REG_PROCESS : Strobe when transmit FIFO is empty
----------------------------------
TX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Empty_d1 <= '1';
else
tx_FIFO_Empty_d1 <= Tx_FIFO_Empty;
end if;
end if;
end process TX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Tx_FIFO_Empty_strobe <= (not tx_FIFO_Empty_d1) and Tx_FIFO_Empty;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
DTR_Underrun_strobe <= DTR_underrun and (not dtr_underrun_d1);
-------------------------------------------------------------------------------
-- TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P : Strobe for when transmit FIFO is
-- less than half full
-------------------------------------------
TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Occpncy_MSB_d1 <= '0';
else
tx_FIFO_Occpncy_MSB_d1 <= Tx_FIFO_Occpncy_MSB;
end if;
end if;
end process TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P;
--------------------------------------------------
Tx_FIFO_less_half <= tx_FIFO_Occpncy_MSB_d1 and (not Tx_FIFO_Occpncy_MSB);
--------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
| mit | 3d6e6d14faa445de157ef195085cab2a | 0.430014 | 4.66036 | false | false | false | false |
frankvanbever/MIPS_processor | testbenches/Imem_tb.vhd | 1 | 2,366 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:48 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/Imem_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: imem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Imem_tb IS
END Imem_tb;
ARCHITECTURE behavior OF Imem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT imem
PORT(
pc : IN std_logic_vector(31 downto 0);
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal pc : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
signal clk : std_logic;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: imem PORT MAP (
pc => pc,
Instruction => Instruction
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
pc <= X"00000000";
wait for clk_period;
pc <= X"00000004";
wait for clk_period;
pc <= X"00000008";
wait for clk_period;
pc <= X"0000000C";
wait for clk_period;
pc <= X"00000010";
wait for clk_period;
wait;
end process;
END;
| mit | 9d710d6f38d29e72aa3404e77ae8e4f1 | 0.605241 | 3.85342 | false | true | false | false |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_wrapper.vhd | 3 | 6,136 | ---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component TS1N40LPB4096X32M4S is
--generic (cdeFileInit : string);
port (
PD : in std_logic; --Power down mode
CLK : in std_logic; --CLK input
CEB : in std_logic; --Chip enable, active low for SRAM operation; active high for fuse data setting
WEB : in std_logic; --Write enable, active low
CEBM : in std_logic; --Chip enable for BIST, active low for SRAM operation; active high for fuse data setting
WEBM : in std_logic; --Write enable for BIST, active low
AWT : in std_logic; --Asynchronous write through
A: in std_logic_vector(11 downto 0); --Address input
D: in std_logic_vector(31 downto 0); --Data input
BWEB: in std_logic_vector(31 downto 0); --Bit write enable, active low
AM: in std_logic_vector(9 downto 0); --Address input for BIST
DM: in std_logic_vector(31 downto 0); --Data input for BIST
BWEBM: in std_logic_vector(31 downto 0); --Bit write enable, active low
BIST: in std_logic; --BIST enable
RTSEL:in std_logic_vector(1 downto 0); --Read margin setting pins
WTSEL:in std_logic_vector(1 downto 0); --Write margin setting pins
Q: out std_logic_vector(31 downto 0) --Data output
);
end component;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
signal write_enable: std_logic;
signal write_BWEB: std_logic_vector(31 downto 0);
signal not_clock: std_logic;
signal delayed_data_out, Q: std_logic_vector(31 downto 0);
begin
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
end case;
end process;
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
-- the following process is not actually tested!
process(Mem_write_byte_enable)
begin
write_BWEB <= (others => '1');
if Mem_write_byte_enable(0) = '1' then
write_BWEB(7 downto 0) <= "00000000";
end if;
if Mem_write_byte_enable(1) = '1' then
write_BWEB(15 downto 8) <= "00000000";
end if;
if Mem_write_byte_enable(2) = '1' then
write_BWEB(23 downto 16) <= "00000000";
end if;
if Mem_write_byte_enable(3) = '1' then
write_BWEB(31 downto 24) <= "00000000";
end if;
end process;
-- Plasma wants the data in the next clock cycle!
process(Mem_clk, Mem_reset)begin
if Mem_reset = '1' then
delayed_data_out <= (others=> '0');
elsif rising_edge(Mem_clk) then
delayed_data_out <= Q;
end if;
end process;
RAM_unit: TS1N40LPB4096X32M4S
generic map (cdeFileInit => stim_file)
port map(
PD => '0',
CLK => not_clock, -- this is the part that we changed. there was some serious timing issues with setup and hold times!
CEB => '0',
WEB => write_enable,
CEBM => '0',
WEBM => '1',
AWT => '0',
A => Mem_address(13 downto 2),
D => Mem_data_write,
BWEB => write_BWEB,
AM => (others =>'0'),
DM => (others =>'0'),
BWEBM => (others =>'1'),
BIST => '0',
RTSEL => "01", -- they said and i qoute: "Please use this setting"
WTSEL => "01", -- they said and i qoute: "Please use this setting"
Q => Q
);
Mem_data_read <= delayed_data_out;
end; --architecture logic
| gpl-3.0 | a35a94d526885ab1dd508c0875efaac0 | 0.55264 | 3.669856 | false | false | false | false |
sunoc/vhdl-lz4-variation | z_old/sha1/reducer.vhd | 1 | 32,840 | -----------------------------------------------------------------------------------
--! @file reducer.vhd
--! @brief REDUCER MODULE :
--! 異なるデータ幅のパスを継ぐためのアダプタ
--! @version 1.0.0
--! @date 2012/8/11
--! @author Ichiro Kawazome <[email protected]>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief REDUCER :
--! 異なるデータ幅のパスを継ぐためのアダプタ.
--! * REDUCER とは配管用語で径違い継ぎ手、つまり直径違う配管(パイプ)を接続
--! するために用いる管継手のことです.
--! * 論理回路の世界でも、ビット幅の異なるデータパスどうしを継ぐことが多い
--! のでこのような汎用のアダプタを作って REDUCER という名前をつけました.
--! * ちょっと汎用的に作りすぎたせいか、多少回路が冗長です.
--! 特にI_WIDTHが大きいとかなり大きな回路になってしまいます.
--! 例えば32bit入力64bit出力の場合、
--! WORD_BITS=8 、ENBL_BITS=1、I_WIDTH=4、O_WIDTH=8 とするよりも、
--! WORD_BITS=32、ENBL_BITS=4、I_WIDTH=1、O_WIDTH=2 としたほうが
--! 回路はコンパクトになります.
--! * O_WIDTH>I_WIDTHの場合、最初のワードデータを出力する際のオフセットを
--! 設定できます. 詳細はOFFSETの項を参照.
-----------------------------------------------------------------------------------
entity REDUCER is
generic (
WORD_BITS : --! @brief WORD BITS :
--! １ワードのデータのビット数を指定する.
integer := 8;
ENBL_BITS : --! @brief ENABLE BITS :
--! ワードデータのうち有効なデータであることを示す信号の
--! ビット数を指定する.
integer := 1;
I_WIDTH : --! @brief INPUT WORD WIDTH :
--! 入力側のデータのワード数を指定する.
integer := 4;
O_WIDTH : --! @brief OUTPUT WORD WIDTH :
--! 出力側のデータのワード数を指定する.
integer := 4;
QUEUE_SIZE : --! @brief QUEUE SIZE :
--! キューの大きさをワード数で指定する.
--! * 少なくともキューの大きさは、I_WIDTH+O_WIDTH-1以上で
--! なければならない.
--! * ただしQUEUE_SIZE=0を指定した場合は、キューの深さは
--! 自動的にI_WIDTH+O_WIDTH に設定される.
integer := 0;
VALID_MIN : --! @brief BUFFER VALID MINIMUM NUMBER :
--! VALID信号の配列の最小値を指定する.
integer := 0;
VALID_MAX : --! @brief BUFFER VALID MAXIMUM NUMBER :
--! VALID信号の配列の最大値を指定する.
integer := 0;
I_JUSTIFIED : --! @brief INPUT WORD JUSTIFIED :
--! 入力側の有効なデータが常にLOW側に詰められていることを
--! 示すフラグ.
--! * 常にLOW側に詰められている場合は、シフタが必要なくなる
--! ため回路が簡単になる.
integer := 0;
FLUSH_ENABLE: --! @brief FLUSH ENABLE :
--! FLUSH/I_FLUSHによるフラッシュ処理を有効にするかどうかを
--! 指定する.
--! * FLUSHとDONEとの違いは、DONEは最後のデータの出力時に
--! キューの状態をすべてクリアするのに対して、
--! FLUSHは最後のデータの出力時にENBLだけをクリアしてVALは
--! クリアしない.
--! そのため次の入力データは、最後のデータの次のワード位置
--! から格納される.
--! * フラッシュ処理を行わない場合は、0を指定すると回路が若干
--! 簡単になる.
integer := 1
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 各種制御信号
-------------------------------------------------------------------------------
START : --! @brief START :
--! 開始信号.
--! * この信号はOFFSETを内部に設定してキューを初期化する.
--! * 最初にデータ入力と同時にアサートしても構わない.
in std_logic;
OFFSET : --! @brief OFFSET :
--! 最初のワードの出力位置を指定する.
--! * START信号がアサートされた時のみ有効.
--! * O_WIDTH>I_WIDTHの場合、最初のワードデータを出力する際の
--! オフセットを設定できる.
--! * 例えばWORD_BITS=8、I_WIDTH=1(1バイト入力)、O_WIDTH=4(4バイト出力)の場合、
--! OFFSET="0000"に設定すると、最初に入力したバイトデータは
--! 1バイト目から出力される.
--! OFFSET="0001"に設定すると、最初に入力したバイトデータは
--! 2バイト目から出力される.
--! OFFSET="0011"に設定すると、最初に入力したバイトデータは
--! 3バイト目から出力される.
--! OFFSET="0111"に設定すると、最初に入力したバイトデータは
--! 4バイト目から出力される.
in std_logic_vector(O_WIDTH-1 downto 0);
DONE : --! @brief DONE :
--! 終了信号.
--! * この信号をアサートすることで、キューに残っているデータ
--! を掃き出す.
--! その際、最後のワードと同時にO_DONE信号がアサートされる.
--! * FLUSH信号との違いは、FLUSH_ENABLEの項を参照.
in std_logic;
FLUSH : --! @brief FLUSH :
--! フラッシュ信号.
--! * この信号をアサートすることで、キューに残っているデータ
--! を掃き出す.
--! その際、最後のワードと同時にO_FLUSH信号がアサートされる.
--! * DONE信号との違いは、FLUSH_ENABLEの項を参照.
in std_logic;
BUSY : --! @brief BUSY :
--! ビジー信号.
--! * 最初にデータが入力されたときにアサートされる.
--! * 最後のデータが出力し終えたらネゲートされる.
out std_logic;
VALID : --! @brief QUEUE VALID FLAG :
--! キュー有効信号.
--! * 対応するインデックスのキューに有効なワードが入って
--! いるかどうかを示すフラグ.
out std_logic_vector(VALID_MAX downto VALID_MIN);
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
I_DATA : --! @brief INPUT WORD DATA :
--! ワードデータ入力.
in std_logic_vector(I_WIDTH*WORD_BITS-1 downto 0);
I_ENBL : --! @brief INPUT WORD ENABLE :
--! ワードイネーブル信号入力.
in std_logic_vector(I_WIDTH*ENBL_BITS-1 downto 0);
I_DONE : --! @brief INPUT WORD DONE :
--! 最終ワード信号入力.
--! * 最後の力ワードデータ入であることを示すフラグ.
--! * 基本的にはDONE信号と同じ働きをするが、I_DONE信号は
--! 最後のワードデータを入力する際に同時にアサートする.
--! * I_FLUSH信号との違いはFLUSH_ENABLEの項を参照.
in std_logic;
I_FLUSH : --! @brief INPUT WORD FLUSH :
--! 最終ワード信号入力.
--! * 最後のワードデータ入力であることを示すフラグ.
--! * 基本的にはFLUSH信号と同じ働きをするが、I_FLUSH信号は
--! 最後のワードデータを入力する際に同時にアサートする.
--! * I_DONE信号との違いはFLUSH_ENABLEの項を参照.
in std_logic;
I_VAL : --! @brief INPUT WORD VALID :
--! 入力ワード有効信号.
--! * I_DATA/I_ENBL/I_DONE/I_FLUSHが有効であることを示す.
--! * I_VAL='1'and I_RDY='1'でワードデータがキューに取り込まれる.
in std_logic;
I_RDY : --! @brief INPUT WORD READY :
--! 入力レディ信号.
--! * キューが次のワードデータを入力出来ることを示す.
--! * I_VAL='1'and I_RDY='1'でワードデータがキューに取り込まれる.
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT WORD DATA :
--! ワードデータ出力.
out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
O_ENBL : --! @brief OUTPUT WORD ENABLE :
--! ワードイネーブル信号出力.
out std_logic_vector(O_WIDTH*ENBL_BITS-1 downto 0);
O_DONE : --! @brief OUTPUT WORD DONE :
--! 最終ワード信号出力.
--! * 最後のワードデータ出力であることを示すフラグ.
--! * O_FLUSH信号との違いはFLUSH_ENABLEの項を参照.
out std_logic;
O_FLUSH : --! @brief OUTPUT WORD FLUSH :
--! 最終ワード信号出力.
--! * 最後のワードデータ出力であることを示すフラグ.
--! * O_DONE信号との違いはFLUSH_ENABLEの項を参照.
out std_logic;
O_VAL : --! @brief OUTPUT WORD VALID :
--! 出力ワード有効信号.
--! * O_DATA/O_ENBL/O_DONE/O_FLUSHが有効であることを示す.
--! * O_VAL='1'and O_RDY='1'でワードデータがキューから取り除かれる.
out std_logic;
O_RDY : --! @brief OUTPUT WORD READY :
--! 出力レディ信号.
--! * キューから次のワードを取り除く準備が出来ていることを示す.
--! * O_VAL='1'and O_RDY='1'でワードデータがキューから取り除かれる.
in std_logic
);
end REDUCER;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture RTL of REDUCER is
-------------------------------------------------------------------------------
--! @brief ワード単位でデータ/データイネーブル信号/ワード有効フラグをまとめておく
-------------------------------------------------------------------------------
type WORD_TYPE is record
DATA : std_logic_vector(WORD_BITS-1 downto 0);
ENBL : std_logic_vector(ENBL_BITS-1 downto 0);
VAL : boolean;
end record;
-------------------------------------------------------------------------------
--! @brief WORD TYPE の初期化時の値.
-------------------------------------------------------------------------------
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
ENBL => (others => '0'),
VAL => FALSE);
-------------------------------------------------------------------------------
--! @brief WORD TYPE の配列の定義.
-------------------------------------------------------------------------------
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
-------------------------------------------------------------------------------
--! @brief キューの最後にワードを追加するプロシージャ.
-------------------------------------------------------------------------------
procedure APPEND(
variable QUEUE : inout WORD_VECTOR;
WORDS : in WORD_VECTOR
) is
alias vec : WORD_VECTOR(0 to WORDS'length-1) is WORDS;
type bv is array (INTEGER range <>) of boolean;
variable val : bv(QUEUE'low to QUEUE'high);
variable hit : boolean;
begin
for i in val'range loop -- 先に val を作っておいた方が論理合成の結果
val(i) := QUEUE(i).VAL; -- が良かった
end loop; --
for i in val'range loop
if (val(i) = FALSE) then
QUEUE(i) := WORD_NULL;
for pos in vec'range loop
if (i-pos-1 < val'low) then
hit := TRUE;
else
hit := val(i-pos-1);
end if;
if (hit) then
QUEUE(i) := vec(pos);
exit;
end if;
end loop;
end if;
end loop;
end APPEND;
-------------------------------------------------------------------------------
--! @brief キューのサイズを計算する関数.
-------------------------------------------------------------------------------
function QUEUE_DEPTH return integer is begin
if (QUEUE_SIZE > 0) then
if (QUEUE_SIZE >= O_WIDTH+I_WIDTH-1) then
return QUEUE_SIZE;
else
assert (QUEUE_SIZE >= I_WIDTH+O_WIDTH-1)
report "require QUEUE_SIZE >= I_WIDTH+O_WIDTH-1" severity WARNING;
return I_WIDTH+O_WIDTH;
end if;
else
return I_WIDTH+O_WIDTH;
end if;
end function;
-------------------------------------------------------------------------------
--! @brief 現在のキューの状態.
-------------------------------------------------------------------------------
signal curr_queue : WORD_VECTOR(0 to QUEUE_DEPTH-1);
-------------------------------------------------------------------------------
--! @brief 1ワード分のイネーブル信号がオール0であることを示す定数.
-------------------------------------------------------------------------------
constant ENBL_NULL : std_logic_vector(ENBL_BITS-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
--! @brief FLUSH 出力フラグ.
-------------------------------------------------------------------------------
signal flush_output : std_logic;
-------------------------------------------------------------------------------
--! @brief FLUSH 保留フラグ.
-------------------------------------------------------------------------------
signal flush_pending : std_logic;
-------------------------------------------------------------------------------
--! @brief DONE 出力フラグ.
-------------------------------------------------------------------------------
signal done_output : std_logic;
-------------------------------------------------------------------------------
--! @brief DONE 保留フラグ.
-------------------------------------------------------------------------------
signal done_pending : std_logic;
-------------------------------------------------------------------------------
--! @brief O_VAL信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal o_valid : std_logic;
-------------------------------------------------------------------------------
--! @brief I_RDY信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal i_ready : std_logic;
-------------------------------------------------------------------------------
--! @brief BUSY信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal curr_busy : std_logic;
begin
-------------------------------------------------------------------------------
-- メインプロセス
-------------------------------------------------------------------------------
process (CLK, RST)
variable in_word : WORD_VECTOR(0 to I_WIDTH-1);
variable next_queue : WORD_VECTOR(curr_queue'range);
variable next_flush_output : std_logic;
variable next_flush_pending: std_logic;
variable next_flush_fall : std_logic;
variable next_done_output : std_logic;
variable next_done_pending : std_logic;
variable next_done_fall : std_logic;
variable pending_flag : boolean;
begin
if (RST = '1') then
curr_queue <= (others => WORD_NULL);
flush_output <= '0';
flush_pending <= '0';
done_output <= '0';
done_pending <= '0';
i_ready <= '0';
o_valid <= '0';
curr_busy <= '0';
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
curr_queue <= (others => WORD_NULL);
flush_output <= '0';
flush_pending <= '0';
done_output <= '0';
done_pending <= '0';
i_ready <= '0';
o_valid <= '0';
curr_busy <= '0';
else
-------------------------------------------------------------------
-- 次のクロックでのキューの状態を示す変数に現在のキューの状態をセット
-------------------------------------------------------------------
next_queue := curr_queue;
-------------------------------------------------------------------
-- データ出力時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (o_valid = '1' and O_RDY = '1') then
if (FLUSH_ENABLE > 0 ) and
(flush_output = '1') and
(O_WIDTH > 1 ) and
(curr_queue(O_WIDTH-1).VAL = FALSE) then
for i in next_queue'range loop
if (i < O_WIDTH-1) then
next_queue(i).VAL := curr_queue(i).VAL;
else
next_queue(i).VAL := FALSE;
end if;
next_queue(i).DATA := (others => '0');
next_queue(i).ENBL := (others => '0');
end loop;
else
for i in next_queue'range loop
if (i+O_WIDTH > next_queue'high) then
next_queue(i) := WORD_NULL;
else
next_queue(i) := curr_queue(i+O_WIDTH);
end if;
end loop;
end if;
end if;
-------------------------------------------------------------------
-- キュー初期化時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (START = '1') then
for i in next_queue'range loop
if (i < O_WIDTH-1) then
next_queue(i).VAL := (OFFSET(i) = '1');
else
next_queue(i).VAL := FALSE;
end if;
next_queue(i).DATA := (others => '0');
next_queue(i).ENBL := (others => '0');
end loop;
end if;
-------------------------------------------------------------------
-- データ入力時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (I_VAL = '1' and i_ready = '1') then
for i in in_word'range loop
in_word(i).DATA := I_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS);
in_word(i).ENBL := I_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS);
in_word(i).VAL := (I_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS) /= ENBL_NULL);
end loop;
if (I_JUSTIFIED > 0) or
(in_word'length = 1) then
APPEND(next_queue, in_word);
else
for i in in_word'range loop
if (in_word(i).VAL) then
APPEND(next_queue, in_word(i to in_word'high));
exit;
end if;
end loop;
end if;
end if;
-------------------------------------------------------------------
-- 次のクロックでのキューの状態をレジスタに保持
-------------------------------------------------------------------
curr_queue <= next_queue;
-------------------------------------------------------------------
-- 次のクロックでのキューの状態でO_WIDTHの位置にデータが入って
-- いるか否かをチェック.
-------------------------------------------------------------------
if (next_queue'high >= O_WIDTH) then
pending_flag := (next_queue(O_WIDTH).VAL);
else
pending_flag := FALSE;
end if;
-------------------------------------------------------------------
-- FLUSH制御
-------------------------------------------------------------------
if (FLUSH_ENABLE = 0) then
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '0';
elsif (flush_output = '1') then
if (o_valid = '1' and O_RDY = '1') then
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '1';
else
next_flush_output := '1';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
elsif (flush_pending = '1') or
(FLUSH = '1') or
(I_VAL = '1' and i_ready = '1' and I_FLUSH = '1') then
if (pending_flag) then
next_flush_output := '0';
next_flush_pending := '1';
next_flush_fall := '0';
else
next_flush_output := '1';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
else
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
flush_output <= next_flush_output;
flush_pending <= next_flush_pending;
-------------------------------------------------------------------
-- DONE制御
-------------------------------------------------------------------
if (done_output = '1') then
if (o_valid = '1' and O_RDY = '1') then
next_done_output := '0';
next_done_pending := '0';
next_done_fall := '1';
else
next_done_output := '1';
next_done_pending := '0';
next_done_fall := '0';
end if;
elsif (done_pending = '1') or
(DONE = '1') or
(I_VAL = '1' and i_ready = '1' and I_DONE = '1') then
if (pending_flag) then
next_done_output := '0';
next_done_pending := '1';
next_done_fall := '0';
else
next_done_output := '1';
next_done_pending := '0';
next_done_fall := '0';
end if;
else
next_done_output := '0';
next_done_pending := '0';
next_done_fall := '0';
end if;
done_output <= next_done_output;
done_pending <= next_done_pending;
-------------------------------------------------------------------
-- 出力有効信号の生成
-------------------------------------------------------------------
if (next_done_output = '1') or
(next_flush_output = '1') or
(next_queue(O_WIDTH-1).VAL = TRUE) then
o_valid <= '1';
else
o_valid <= '0';
end if;
-------------------------------------------------------------------
-- 入力可能信号の生成
-------------------------------------------------------------------
if (next_done_output = '0' and next_done_pending = '0') and
(next_flush_output = '0' and next_flush_pending = '0') and
(next_queue(next_queue'length-I_WIDTH).VAL = FALSE) then
i_ready <= '1';
else
i_ready <= '0';
end if;
-------------------------------------------------------------------
-- 現在処理中であることを示すフラグ
-- 最初に入力があった時点で'1'になり、O_DONEまたはO_FLUSHが出力完了
-- した時点で'0'になる。
-------------------------------------------------------------------
if (curr_busy = '1') then
if (next_flush_fall = '1') or
(next_done_fall = '1') then
curr_busy <= '0';
else
curr_busy <= '1';
end if;
else
if (I_VAL = '1' and i_ready = '1') then
curr_busy <= '1';
else
curr_busy <= '0';
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- 各種出力信号の生成
-------------------------------------------------------------------------------
O_FLUSH <= flush_output when(FLUSH_ENABLE > 0) else '0';
O_DONE <= done_output;
O_VAL <= o_valid;
I_RDY <= i_ready;
BUSY <= curr_busy;
process (curr_queue) begin
for i in 0 to O_WIDTH-1 loop
O_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS) <= curr_queue(i).DATA;
O_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS) <= curr_queue(i).ENBL;
end loop;
for i in VALID'range loop
if (curr_queue'low <= i and i <= curr_queue'high) then
if (curr_queue(i).VAL) then
VALID(i) <= '1';
else
VALID(i) <= '0';
end if;
else
VALID(i) <= '0';
end if;
end loop;
end process;
end RTL;
| gpl-3.0 | 3dd43c1ef662490f809caae450c9dbb4 | 0.333228 | 4.411027 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/cross_clk_sync_fifo_0.vhd | 1 | 85,497 | -------------------------------------------------------------------------------
-- $Id: cross_clk_sync_fifo_0.vhd
-------------------------------------------------------------------------------
-- cross_clk_sync_fifo_0.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cross_clk_sync_fifo_0.vhd
-- Version: v3.1
-- Description: This is the CDC logic when FIFO = 0.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_0 is
generic (
C_NUM_TRANSFER_BITS : integer;
C_NUM_SS_BITS : integer--;
--C_AXI_SPI_CLK_EQ_DIFF : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_axi : in std_logic;
Tx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_d1_reg_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spisel_pulse_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_pulse_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spiXfer_done_cdc_from_spi : in std_logic; -- = spiXfer_done_cdc_from_spi_clk, -- in
spiXfer_done_cdc_to_axi : out std_logic; -- = spiXfer_done_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
modf_strobe_cdc_from_spi : in std_logic; -- = modf_strobe_cdc_from_spi_clk, -- in
modf_strobe_cdc_to_axi : out std_logic; -- = modf_strobe_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
Slave_MODF_strobe_cdc_from_spi : in std_logic; -- = slave_MODF_strobe_cdc_from_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi : out std_logic; -- = slave_MODF_strobe_cdc_to_axi_clk ,-- out
--------------------------:-------------------------------
receive_Data_cdc_from_spi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_Data_cdc_from_spi_clk, -- in
receive_Data_cdc_to_axi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_data_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic;
--------------------------:-------------------------------
dtr_underrun_cdc_from_spi : in std_logic; -- = dtr_underrun_cdc_from_spi_clk, -- in
dtr_underrun_cdc_to_axi : out std_logic; -- = dtr_underrun_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
transmit_Data_cdc_from_axi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_from_axi_clk, -- in
transmit_Data_cdc_to_spi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_to_spi_clk -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1))
----------------------------
);
end entity cross_clk_sync_fifo_0;
architecture imp of cross_clk_sync_fifo_0 is
--------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d4 : std_logic;
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal declaration
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
-- signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d3 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d4 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of SPISEL_D1_REG_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1 : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
-- SPI_AXI_EQUAL_GEN: AXI and SPI domain clocks are same
---------------------
--SPI_AXI_EQUAL_GEN: if C_AXI_SPI_CLK_EQ_DIFF = 0 generate
-----
--begin
-----
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE =0) generate
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI: process(Bus2IP_Clk) is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1')then
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= '1';
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= '1';
else
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d1;
end if;
end if;
end process TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI;
-----------------------------------------
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
-------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_3: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
-------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_SYNC_SPI_2_AXI_2: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_SPI_2_AXI_1: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_2: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_3: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
---------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
---------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
---------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P: process(Bus2IP_Clk) is
-------------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
receive_Data_cdc_from_spi_d1 <= receive_Data_cdc_from_spi;
receive_Data_cdc_from_spi_d2 <= receive_Data_cdc_from_spi_d1;
end if;
end process RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P;
-------------------------------------------
receive_Data_cdc_to_axi <= receive_Data_cdc_from_spi_d2;
-----------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-----------------------------------------------
TR_DATA_SYNC_AX2SP_GEN: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TR_DATA_SYNC_AX2SP_1: label is "TRUE";
-----
begin
-----
TR_DATA_SYNC_AX2SP_1: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TR_DATA_SYNC_AX2SP_2: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TR_DATA_SYNC_AX2SP_GEN;
transmit_Data_cdc_to_spi <= transmit_Data_cdc_from_axi_d2;
-----------------------------------------------
SPICR_0_LOOP_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1 : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1 : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
end generate LOGIC_GENERATION_FDR ;
--============================================================================================================
LOGIC_GENERATION_CDC : if (LOGIC_CHANGE =1) generate
--============================================================================================================
-- Tx_FIFO_Empty_cdc_from_axi <= Tx_FIFO_Empty_cdc_from_axi;
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_cdc_to_spi;
-- Tx_FIFO_Empty_SPISR_cdc_from_spi <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
-- Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_cdc_to_axi;
-- spisel_d1_reg_cdc_from_spi <= spisel_d1_reg_cdc_from_spi;
-- spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_cdc_to_axi;
-- spisel_pulse_cdc_from_spi <= spisel_pulse_cdc_from_spi;
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_cdc_to_axi;
-- spiXfer_done_cdc_from_spi <= spiXfer_done_cdc_from_spi;
-- spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_cdc_to_axi;
-- modf_strobe_cdc_from_spi <= modf_strobe_cdc_from_spi;
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_cdc_to_axi;
-- Slave_MODF_strobe_cdc_from_spi <= Slave_MODF_strobe_cdc_from_spi;
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_cdc_to_axi;
-- receive_Data_cdc_from_spi <= receive_Data_cdc_from_spi;
-- receive_Data_cdc_to_axi <= receive_Data_cdc_cdc_to_axi;
-- drr_Overrun_int_cdc_from_spi <= drr_Overrun_int_cdc_from_spi;
-- drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_cdc_to_axi;
-- dtr_underrun_cdc_from_spi <= dtr_underrun_cdc_from_spi;
-- dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_cdc_to_axi;
-- transmit_Data_cdc_from_axi <= transmit_Data_cdc_from_axi;
-- transmit_Data_cdc_to_spi <= transmit_Data_cdc_cdc_to_spi;
-- SPICR_0_LOOP_cdc_from_axi <= SPICR_0_LOOP_cdc_from_axi;
-- SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_cdc_to_spi;
-- SPICR_1_SPE_cdc_from_axi <= SPICR_1_SPE_cdc_from_axi;
-- SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_cdc_to_spi;
-- SPICR_2_MST_N_SLV_cdc_from_axi <= SPICR_2_MST_N_SLV_cdc_from_axi;
-- SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_cdc_to_spi;
-- SPICR_3_CPOL_cdc_from_axi <= SPICR_3_CPOL_cdc_from_axi;
-- SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_cdc_to_spi;
-- SPICR_4_CPHA_cdc_from_axi <= SPICR_4_CPHA_cdc_from_axi;
-- SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_cdc_to_spi;
-- SPICR_5_TXFIFO_cdc_from_axi <= SPICR_5_TXFIFO_cdc_from_axi;
-- SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_cdc_to_spi;
-- SPICR_6_RXFIFO_RST_cdc_from_axi <= SPICR_6_RXFIFO_RST_cdc_from_axi;
-- SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_cdc_to_spi;
-- SPICR_7_SS_cdc_from_axi <= SPICR_7_SS_cdc_from_axi;
-- SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_cdc_to_spi;
-- SPICR_8_TR_INHIBIT_cdc_from_axi <= SPICR_8_TR_INHIBIT_cdc_from_axi;
-- SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_cdc_to_spi;
-- SPICR_9_LSB_cdc_from_axi <= SPICR_9_LSB_cdc_from_axi;
-- SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_cdc_to_spi;
-- SPICR_bits_7_8_cdc_from_axi <= SPICR_bits_7_8_cdc_from_axi;
-- SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_cdc_to_spi;
-- SR_3_modf_cdc_from_axi <= SR_3_modf_cdc_from_axi;
-- SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_cdc_to_spi;
-- SPISSR_cdc_from_axi <= SPISSR_cdc_from_axi;
-- SPISSR_cdc_to_spi <= SPISSR_cdc_cdc_to_spi;
--============================================================================================================
-- all the signals pass through FF with reset before CDC_SYNC module to initialise the value of the signal
-- at its reset state. As many signals coming from bram have initial value of XX.
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI_CDC : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0') ,
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
----------------------------------------------------------------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_axi_int_2,--Tx_FIFO_Empty_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => Tx_FIFO_Empty_cdc_from_axi_d2--Tx_FIFO_Empty_cdc_to_spi
);
TX_FIFO_EMPTY_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
Tx_FIFO_Empty_cdc_from_axi_d3 <= Tx_FIFO_Empty_cdc_from_axi_d2;
end if;
end process TX_FIFO_EMPTY_STRETCH_1_CDC;
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
----------------------------------------------------------------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
-----------------------------------------------------------------------------------------------------------
SPISEL_PULSE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
--spisel_pulse_cdc_from_spi_d1 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
--spisel_pulse_cdc_from_spi_d1 <= spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1_CDC;
SPISEL_PULSE_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_pulse_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_pulse_cdc_from_spi_d2
);
SPISEL_PULSE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
spisel_pulse_cdc_from_spi_d3 <= spisel_pulse_cdc_from_spi_d2;
end if;
end process SPISEL_PULSE_STRETCH_1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
--------------------------------------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d2 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 ,-- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2--spiXfer_done_cdc_to_axi
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3;
--------------------------------------------------------------------------------------------------------------
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
--modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2--modf_strobe_cdc_to_axi
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2 ;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3;
----------------------------------------------------------------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
-- Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
-- Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3;
-----------------------------------------------------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => receive_Data_cdc_from_spi,
scndry_aclk => Bus2IP_Clk,
prmry_in => '0',
scndry_resetn => Soft_Reset_op,
scndry_vect_out => receive_Data_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_4: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d3,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d4 xor drr_Overrun_int_cdc_from_spi_d3;
-------------------------------------------------------------------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
------------------------------------------------------------------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
----------------------------------------------------------------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
TR_DATA_SYNC_AX2SP_GEN_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => transmit_Data_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => transmit_Data_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SR_3_MODF_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
SPISSR_SYNC_GEN_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_SS_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => SPISSR_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => SPISSR_cdc_to_spi
);
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
SPICR_BITS_7_8_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
-----------------------------------------
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
| mit | 81fae2aa300b6cf1026fd55879df64dc | 0.429419 | 3.748717 | false | false | false | false |
sunoc/vhdl-lz4-variation | lz4_assembly.vhdl | 1 | 2,891 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lz4_pkg.all;
entity lz4_assembly is
port (
clk_i : in std_logic;
reset_i : in std_logic;
litLength_i : in std_logic_vector(9 downto 0);
offset_i : in std_logic_vector(9 downto 0);
matchLength_i : in std_logic_vector(9 downto 0);
internalStream_i : in std_logic;
-- main output
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end lz4_assembly;
architecture behavior of lz4_assembly is
signal toStream_s : std_logic_vector(3 downto 0) := "0000";
begin
-- ==============================
-- literal length token part
process (clk_i, reset_i)
variable litLength_p : integer range 0 to 10 := 9;
variable fourBits : integer range 0 to 4 := 0;
begin
-- tsarts to stream out right after a match
if matchLength_i /= "UUUUUUUUUU" and toStream_s = "0000" then
if rising_edge(clk_i) or falling_edge(clk_i) then
-- the 4 first bits for the lit length
if litLength_p > 0 and fourBits < 4 then
if to_integer(unsigned(litLength_i)) > 15 then
outputStream_o <= '1';
litLength_p := litLength_p - 1;
fourBits := fourBits + 1;
else
end if;
else
toStream_s <= "0001";
end if;
end if;
end if;
end process;
-- ==============================
-- match length part of the token
process (clk_i, reset_i)
variable matchLength_p : integer range 0 to 10 := 9;
variable matchLength_s : std_logic_vector(9 downto 0);
variable fourBits : integer range 0 to 4 := 0;
begin
-- tsarts to stream out right after a match
if matchLength_i /= "UUUUUUUUUU" and toStream_s = "0001" then
if rising_edge(clk_i) or falling_edge(clk_i) then
-- 4 next bits are for the match length (minus the minmatch)
if matchLength_p > 0 and fourBits < 4 then
if to_integer(unsigned(matchLength_i)) - 4 > 255 then
elsif to_integer(unsigned(matchLength_i)) - 4 > 15 then
outputStream_o <= '1';
matchLength_p := matchLength_p - 1;
fourBits := fourBits + 1;
else
matchLength_s := std_logic_vector(to_unsigned(to_integer(unsigned(matchLength_i)) - 4, 10));
outputStream_o <= matchLength_s(3 - fourBits);
--outputStream_o <= matchLength_s(matchLength_p);
matchLength_p := matchLength_p - 1;
fourBits := fourBits + 1;
end if;
end if;
end if;
end if;
end process;
-- tell that there is an output stream
--outputFlag_o <= '1';
end;
| gpl-3.0 | 5e491601b0228f5fc6281399a4758762 | 0.541681 | 3.901484 | false | false | false | false |
zzhou007/161lab | lab02/bin_alu.vhd | 1 | 2,436 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity bin_alu is
generic(NUMBITS : natural := 32);
Port ( Atemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
Btemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
A : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
B : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
result : out STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
carryout : out STD_LOGIC;
overflow : out STD_LOGIC;
zero : out STD_LOGIC);
end bin_alu;
architecture Behavioral of bin_alu is
--temp signal for alu
signal stuff: std_logic_vector(NUMBITS downto 0);
begin
process (A, B, opcode, stuff, Atemp, Btemp)
begin
--UNSIGNED ADD
if opcode = "1000" then
stuff <= std_logic_vector( unsigned('0' & A ) + unsigned( '0' & B));
result <= stuff(NUMBITS-1 downto 0);
--carryout <= '1';
carryout <= stuff(NUMBITS);
overflow <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED ADD
elsif opcode = "1100" then
stuff <= std_logic_vector( signed('0' & A) + signed('0' & B) );
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--UNSIGNED SUB
elsif opcode = "1001" then
stuff <= std_logic_vector( ('0' & unsigned(A) ) + ( '0' & ((not unsigned(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (Atemp < Btemp) then
overflow <= '1';
end if;
if stuff(NUMBITS - 1) = '0' then
carryout <= '1';
else
carryout <= '0';
end if;
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED SUB
elsif opcode = "1101" then
stuff <= std_logic_vector( ('0' & signed(A) ) + ( '0' & ((not signed(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (A(NUMBITS-1) = '0') and (B(NUMBITS-1) = '1') and (stuff(NUMBITS-2) = '1') then
overflow <= '1';
elsif (A(NUMBITS-1) = '1') and (B(NUMBITS-1) = '0') and (stuff(NUMBITS-2) = '0') then
overflow <= '1';
else
overflow <= '0';
end if;
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 0f1b5610e164f3f6816b92586f051c33 | 0.575944 | 2.893112 | false | false | false | false |
zzhou007/161lab | newlab5/teebee.vhd | 1 | 2,266 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cs161_processor
PORT(
clk : IN std_logic;
rst : IN std_logic;
prog_count : OUT std_logic_vector(31 downto 0);
instr_opcode : OUT std_logic_vector(5 downto 0);
reg1_addr : OUT std_logic_vector(4 downto 0);
reg1_data : OUT std_logic_vector(31 downto 0);
reg2_addr : OUT std_logic_vector(4 downto 0);
reg2_data : OUT std_logic_vector(31 downto 0);
write_reg_addr : OUT std_logic_vector(4 downto 0);
write_reg_data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal prog_count : std_logic_vector(31 downto 0);
signal instr_opcode : std_logic_vector(5 downto 0);
signal reg1_addr : std_logic_vector(4 downto 0);
signal reg1_data : std_logic_vector(31 downto 0);
signal reg2_addr : std_logic_vector(4 downto 0);
signal reg2_data : std_logic_vector(31 downto 0);
signal write_reg_addr : std_logic_vector(4 downto 0);
signal write_reg_data : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cs161_processor PORT MAP (
clk => clk,
rst => rst,
prog_count => prog_count,
instr_opcode => instr_opcode,
reg1_addr => reg1_addr,
reg1_data => reg1_data,
reg2_addr => reg2_addr,
reg2_data => reg2_data,
write_reg_addr => write_reg_addr,
write_reg_data => write_reg_data
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 100ns;
rst <= '0';
wait for 10000ns;
wait;
end process;
END;
| gpl-2.0 | c41ff660c97c6a2e96ea36376cd03a88 | 0.60812 | 3.449011 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/InstructionMemory.vhd | 1 | 1,810 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:11:34 11/21/2013
-- Design Name:
-- Module Name: InstructionMem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionMem is
Port(
clk : in std_logic;
rst : in std_logic;
Address : in Int16;
Data : out Int16;
ramdata : INOUT std_logic_vector(15 downto 0);
ramaddr : OUT std_logic_vector(17 downto 0);
OE : OUT std_logic;
WE : OUT std_logic;
EN : OUT std_logic
);
end InstructionMem;
architecture Behavioral of InstructionMem is
signal flag: std_logic:= '0';
begin
process(rst, clk)
begin
if rst = '0' then
flag <= '0';
ramdata <= Int16_Z;
OE <= '1';
WE <= '1';
EN <= '1';
Data <= Int16_Zero;
ramaddr <= "00" & Int16_Zero;
elsif falling_edge(clk) then
case flag is
when '0' =>
EN <= '0';
OE <= '0';
WE <= '1';
ramaddr <= "00" & Address;
ramdata <= Int16_Z;
flag <= '1';
when '1' =>
data <= ramdata;
flag <= '0';
when others => flag <= '0';
end case;
end if;
end process;
end Behavioral;
| mit | 9479e30ff85ae3419c7036acc36a8de4 | 0.537569 | 3.395872 | false | false | false | false |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop.vhd | 3 | 16,426 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if (read_en ='1' or fake_credit = '1') then
credit_in <= '1';
end if;
if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
| gpl-3.0 | 12303d6735cb61642872f6ace76f3f12 | 0.40929 | 3.660798 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd | 2 | 10,130 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | dfed5820cfcc5362536546c3fa6d2fb8 | 0.493485 | 3.781262 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/TReg.vhd | 1 | 1,282 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: tuk.
--
-- Create Date: 19:03:31 11/21/2013
-- Design Name:
-- Module Name: TReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TReg is
Port(
Input : in STD_LOGIC_VECTOR (15 downto 0);
TType : in STD_LOGIC;
TWrite : in STD_LOGIC;
T : out STD_LOGIC
);
end TReg;
architecture Behavioral of TReg is
begin
process(Input, TType, TWrite)
begin
if Twrite = '1' then
T <= '0';
if (TType = '0') then
if Input(15) = '1' then
T <= '1';
end if;
elsif (Input /= Int16_Zero) then
T <= '1';
end if;
end if;
end process;
end Behavioral;
| mit | 9532f5f4d79973b46916862fa9474d8e | 0.567083 | 3.464865 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/miner.vhd | 4 | 2,591 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:17:26 05/29/2011
-- Design Name:
-- Module Name: miner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity miner is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (95 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
nonce : in STD_LOGIC_VECTOR (31 downto 0);
hit : out STD_LOGIC);
end miner;
architecture Behavioral of miner is
COMPONENT sha256_pipeline
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : IN std_logic_vector(255 downto 0);
input : IN std_logic_vector(511 downto 0);
hash : OUT std_logic_vector(255 downto 0)
);
END COMPONENT;
constant innerprefix : std_logic_vector(383 downto 0) := x"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000";
constant outerprefix : std_logic_vector(255 downto 0) := x"0000010000000000000000000000000000000000000000000000000080000000";
constant outerstate : std_logic_vector(255 downto 0) := x"5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667";
signal innerdata : std_logic_vector(511 downto 0);
signal outerdata : std_logic_vector(511 downto 0);
signal innerhash : std_logic_vector(255 downto 0);
signal outerhash : std_logic_vector(255 downto 0);
begin
innerdata <= innerprefix & nonce & data;
outerdata <= outerprefix & innerhash;
hit <= '1' when outerhash(255 downto 224) = x"00000000" and step = "000000" else '0';
inner: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => state,
input => innerdata,
hash => innerhash
);
outer: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => outerstate,
input => outerdata,
hash => outerhash
);
end Behavioral;
| gpl-3.0 | fb37b42f5d0be10a10c08e1bf69ef272 | 0.631416 | 3.598611 | false | false | false | false |
fpgaddicted/car_taillights_animation-engine | brake_anim.vhd | 1 | 1,642 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco (fpgaddicted)
--
-- Create Date: 19:15:33 04/27/2017
-- Design Name:
-- Module Name: brake_anim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.2 Bug fix
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity brake_anim is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
led_out : out STD_LOGIC_VECTOR (1 downto 0));
end brake_anim;
architecture animation_engine of brake_anim is
type state is (s0,s1);
signal s : state;
begin
process(clk,reset,s,en)
variable i: integer:=0;
begin
if rising_edge(clk) then
if (reset = '1') or (en = '0') then
s <= s0;
led_out <= "00";
else
case s is
when s0=>
i:=i+1;
led_out <="00";
if(i=2000000) then
i:=0;
s <= s1;
end if;
when s1=>
i:=i+1;
led_out <="11";
if(i=2000000) then
i:=0;
s <= s0;
end if;
end case;
end if;
end if;
end process;
end animation_engine;
| gpl-3.0 | 43c031b1129cd25a3e47574c08aff1d8 | 0.526188 | 3.323887 | false | false | false | false |
6769/VHDL | Lab_2_part2/clock/clock_second.vhd | 1 | 594 | --Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk50Mhz:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk50Mhz'event and clk50Mhz='1';
if counter_for_osc_signal < 50*1000*1000 then
counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
end if;
end process;
second<='1' when counter_for_osc_signal>25*1000*1000
else '0' ;
end architecture Distribution;
| gpl-2.0 | bb5772c0351927f4d144ad812ae3e1d5 | 0.739057 | 3.046154 | false | false | false | false |
6769/VHDL | Lab_4/Part1/clock_second.vhd | 1 | 783 | --Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal < 25--*1000*1000
then
counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second<=not second;
--here is the problem that second signal will result unflatten square wave,if using the commented mathod.
end if;
end process;
-- second<='1' when counter_for_osc_signal> 25*1000*1000 --High_percent_of_counter
-- else '0' ;
-- timing analysis here ...
end architecture Distribution;
| gpl-2.0 | 444f1e7853ce91357e317f9cbc297428 | 0.719029 | 3.2625 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/axi_quad_spi.vhd | 1 | 74,101 | -------------------------------------------------------------------------------
-- $Id: axi_quad_spi.vhd
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- xip_cross_clk_sync.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 11/12/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Upgraded AXI4 Lite based core performance.
-- 2. Added AXI4 full interface support and added functionality
-- 3. Added XIP mode functionality and corresponding logic files
-- 4. Separated AXI and SPI clock so that the SPI functionality can operate at
-- independent frequency.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
library axi_lite_ipif_v2_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
-------------------------------------------------------------------------------
entity axi_quad_spi is
generic(
-- Async_Clk parameter is added only for Vivado, it is not used in the design, this is
-- NON HDL parameter
Async_Clk : integer := 0;
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_quad_spi_inst";
-------------------------
C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode
C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used
C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ;
-------------------------
-- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL
C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000"
-------------------------
);
port(
-- external async clock for SPI interface logic
ext_spi_clk : in std_logic;
-- axi4 lite interface clk and reset signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi4 full interface clk and reset signals
s_axi4_aclk : in std_logic;
s_axi4_aresetn : in std_logic;
-------------------------------
-------------------------------
--*axi4 lite port interface* --
-------------------------------
-------------------------------
-- axi write address channel signals
---------------
s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
---------------
-- axi write data channel signals
---------------
s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
---------------
-- axi write response channel signals
---------------
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-------------------------------
-------------------------------
--*axi4 full port interface* --
-------------------------------
------------------------------------
-- axi write address Channel Signals
------------------------------------
s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_awlen : in std_logic_vector(7 downto 0);
s_axi4_awsize : in std_logic_vector(2 downto 0);
s_axi4_awburst : in std_logic_vector(1 downto 0);
s_axi4_awlock : in std_logic; -- not supported in design
s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_awvalid : in std_logic;
s_axi4_awready : out std_logic;
---------------------------------------
-- axi4 full write Data Channel Signals
---------------------------------------
s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0);
s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
s_axi4_wlast : in std_logic;
s_axi4_wvalid : in std_logic;
s_axi4_wready : out std_logic;
-------------------------------------------
-- axi4 full write Response Channel Signals
-------------------------------------------
s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_bresp : out std_logic_vector(1 downto 0);
s_axi4_bvalid : out std_logic;
s_axi4_bready : in std_logic;
-----------------------------------
-- axi read address Channel Signals
-----------------------------------
s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_arlen : in std_logic_vector(7 downto 0);
s_axi4_arsize : in std_logic_vector(2 downto 0);
s_axi4_arburst : in std_logic_vector(1 downto 0);
s_axi4_arlock : in std_logic; -- not supported in design
s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_arvalid : in std_logic;
s_axi4_arready : out std_logic;
--------------------------------
-- axi read data Channel Signals
--------------------------------
s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0);
s_axi4_rresp : out std_logic_vector(1 downto 0);
s_axi4_rlast : out std_logic;
s_axi4_rvalid : out std_logic;
s_axi4_rready : in std_logic;
--------------------------------
-------------------------------
--*SPI port interface * --
-------------------------------
io0_i : in std_logic; -- MOSI signal in standard SPI
io0_o : out std_logic;
io0_t : out std_logic;
-------------------------------
io1_i : in std_logic; -- MISO signal in standard SPI
io1_o : out std_logic;
io1_t : out std_logic;
-----------------
-- quad mode pins
-----------------
io2_i : in std_logic;
io2_o : out std_logic;
io2_t : out std_logic;
---------------
io3_i : in std_logic;
io3_o : out std_logic;
io3_t : out std_logic;
---------------------------------
-- common pins
----------------
spisel : in std_logic;
-----
sck_i : in std_logic;
sck_o : out std_logic;
sck_t : out std_logic;
-----
ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
ss_t : out std_logic;
----------------------
-- INTERRUPT INTERFACE
----------------------
ip2intc_irpt : out std_logic
---------------------------------
);
-------------------------------
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000";
attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000";
attribute INITIALVAL : string;
attribute INITIALVAL of SPISEL : signal is "VCC";
-------------------------------
end entity axi_quad_spi;
--------------------------------------------------------------------------------
architecture imp of axi_quad_spi is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- constant added for webtalk information
---------------------------------------------------------------------------------
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{"
-- & "C_FAMILY = " & C_FAMILY
-- & ",C_SUB_FAMILY = " & C_SUB_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH)
-- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH)
-- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH)
-- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH)
-- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH)
-- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO)
-- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS)
-- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS)
-- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP)
-- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE)
-- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY)
-- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE)
-- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------
-------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------
-- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth.
--
function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is
-----
begin
-----
if(C_FIFO_DEPTH = 0)then
return 0;
else
return 1;
end if;
end function get_fifo_presence;
function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is
-----
begin
-----
if(C_FIFO_EXIST = 1)then
return C_FIFO_DEPTH;
else
return 64; -- to ensure that log2 functions does not become invalid
end if;
end function get_fifo_depth;
------------------------------
function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is
-----
variable j : integer := 0;
variable k : integer := 0;
-----
begin
-----
if (C_FIFO_DEPTH = 0) then
return 4;
else
for i in 0 to 11 loop
if(2**i >= C_FIFO_DEPTH) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
end if;
-------
end function get_fifo_occupancy_count;
------------------------------
-- Constant declarations
------------------------------
--------------------- ******************* ------------------------------------
-- Core Parameters
--------------------- ******************* ------------------------------------
--
constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH);
constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH);
-- width of control register
constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS
-- width of status register
constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS
-- count the counter width for calculating FIFO occupancy
constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED);
-- width of spi shift register
constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed
constant C_NUM_SPI_REGS : integer := 8;-- this is fixed
constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13
--------------------- ******************* ------------------------------------
-- AXI lite parameters
--------------------- ******************* ------------------------------------
constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 20;
-- interupt mode
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):=
(
others => INTR_REG_EVENT
-- when C_SPI_MODE = 0
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0
-- OR
-- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode
----------------------- OR ---------------------------
-- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode
-- OR
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
-- when C_SPI_MODE = 1 or 2
-- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
);
constant ZEROES : std_logic_vector(31 downto 0):= X"00000000";
-- this constant is defined as the start of SPI register addresses.
constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060";
-- Address range array
constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--ZEROES & C_BASEADDR,
--ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--interrupt address higher range
-- soft reset register base & high addr
--ZEROES & (C_BASEADDR or X"00000040"),
--ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018")
ZEROES & C_IP_REG_ADDR_OFFSET,
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- AXI4 Address range array
constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--*ZEROES & C_S_AXI4_BASEADDR,
--*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--soft reset register high addr
-- soft reset register base & high addr
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"),
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- No. of CE's required per address range
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 16 , -- 16 CEs required for interrupt
--1 => 1, -- 1 CE required for soft reset
1 => 8, -- 8 CE required for Addressing Holes in soft reset
2 => C_NUM_SPI_REGS
);
-- no. of Chip Enable Signals
constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- no. of Chip Select Signals
constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2);
-----------------------------
----------------------- ******************* ------------------------------------
---- XIP Mode parameters
----------------------- ******************* ------------------------------------
-- No. of XIP SPI registers
constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed
-- width of XIP control register
constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS
-- width of XIP status register
constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS
-- Address range array
constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004")
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004")
);
-- No. of CE's required per address range
constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface
);
-- no. of Chip Enable Signals
constant C_NUM_XIP_CE_SIGNALS : integer :=
calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY);
function assign_addr_bits (addr_bits_info : integer) return string is
variable addr_width_24 : integer:= 24;
variable addr_width_32 : integer:= 32;
begin
if addr_bits_info = 24 then -- old logic for 24 bit addressing
return X"00FFFFFF";--addr_width_24;
else
return X"FFFFFFFF";--addr_width_32;
end if;
end function assign_addr_bits;
constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF";
-- XIP Full Interface Address range array
constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_S_AXI4_BASEADDR),
--*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET)
ZEROES & X"00000000",
ZEROES & C_XIP_ADDR_OFFSET
);
-- No. of CE's required per address range
constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface
);
---------------------------------------------------------------------------------
constant C_XIP_FIFO_DEPTH : integer := 264;
-------------------------------------------------------------------------------
-- signal declaration
signal bus2ip_clk : std_logic;
signal bus2ip_be_int : std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0);
signal ip2bus_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0 )
:= (others => '0');
signal ip2bus_wrack_int : std_logic := '0';
signal ip2bus_rdack_int : std_logic := '0';
signal ip2bus_error_int : std_logic := '0';
signal bus2ip_reset_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
-- XIP signals
signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal burst_tr_int : std_logic;
signal rready_int : std_logic;
signal bus2ip_reset_ipif4_inverted : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
---------------
-- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design
---------------
QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate
---------------
begin
-----
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
(
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int);
end if;
end process REG_RST_FRM_IPIF;
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_1.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => ext_spi_clk, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => '0',
WVALID => '0',
---------------------------------------------------
--SPI Ports
IO0_I => io0_i,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt
-----
);
burst_tr_int <= '0';
end generate QSPI_LEGACY_MD_GEN;
------------------------------------------------------------------------------
QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate
---------------
begin
-----
-- AXI_QUAD_SPI_I: core instance
QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_1.axi_qspi_enhanced_mode
generic map(
-- General Parameters
C_FAMILY => C_FAMILY , -- : string := "virtex7";
C_SUB_FAMILY => C_SUB_FAMILY , -- : string := "virtex7";
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
--C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode
C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; --
C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000"
-------------------------
C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
-------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL ,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added
)
port map(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
-----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address channel signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready, -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready, -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out
----------------------------------------------------------
-- Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int, -- in
----------------------------------------------------------
burst_tr => burst_tr_int, -- in
rready => rready_int
);
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_1.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => rready_int,
WVALID => S_AXI4_WVALID,
--SPI Ports
IO0_I => io0_i,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt
-----
);
end generate QSPI_ENHANCED_MD_GEN;
--------------------------------------------------------------------------------
-----------------
-- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface
-- used in the design
---------------
XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate
---------------
constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h
constant XIPSR : natural := 1;
--
signal bus2ip_reset_int : std_logic;
signal bus2ip_clk_int : std_logic;
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_error_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
signal IP2Bus_XIPCR_WrAck : std_logic;
signal IP2Bus_XIPCR_RdAck : std_logic;
signal XIPCR_1_CPOL_int : std_logic;
signal XIPCR_0_CPHA_int : std_logic;
signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
signal TO_XIPSR_AXI_TR_ERR_int : std_logic;
signal TO_XIPSR_mst_modf_err_int : std_logic;
signal TO_XIPSR_axi_rx_full_int : std_logic;
signal TO_XIPSR_axi_rx_empty_int : std_logic;
signal xipsr_cpha_cpol_err_int :std_logic;
signal xipsr_cmd_err_int :std_logic;
signal ip2bus_xipsr_wrack :std_logic;
signal ip2bus_xipsr_rdack :std_logic;
signal xipsr_axi_tr_err_int :std_logic;
signal xipsr_axi_tr_done_int :std_logic;
signal ip2bus_xipsr_rdack_int :std_logic;
signal ip2bus_xipsr_wrack_int :std_logic;
signal MISO_I_int :std_logic;
signal SCK_O_int :std_logic;
signal TO_XIPSR_trans_error_int :std_logic;
signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic;
signal ip2bus_wrack_core_reg_d1 :std_logic;
signal ip2bus_wrack_core_reg :std_logic;
signal ip2bus_rdack_core_reg_d1 :std_logic;
signal ip2bus_rdack_core_reg_d2 :std_logic;
signal ip2Bus_RdAck_core_reg_d3 :std_logic;
signal Rst_to_spi_int :std_logic;
begin
-----
---- AXI4 Lite interface instance and interface with the port list
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
( -- AXI4 Lite interface
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk_int , -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => open, -- bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
--------------------------------------------------------------------------
ip2bus_error_int <= '0'; -- there is no error in this mode
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN);
end if;
end process REG_RST_FRM_IPIF;
--------------------------------------------------------------------------
XIP_CR_I : entity axi_quad_spi_v3_1.xip_cntrl_reg
generic map
(
C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SPI_MODE => C_SPI_MODE
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------
ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck,
ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck,
------------------------
--XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector;
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
------------------------
IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic;
------------------------
TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic
);
--------------------------------------------------------------------------
REG_WR_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR);
ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR)) and
(not ip2Bus_WrAck_core_reg_d1);
end if;
end if;
end process REG_WR_ACK_P;
-------------------------
ip2bus_wrack_int <= ip2Bus_WrAck_core_reg;
-------------------------
REG_RD_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg_d2 <= '0';
ip2Bus_RdAck_core_reg_d3 <= '0';
else
ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR);
ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR)) and
(not ip2Bus_RdAck_core_reg_d1);
ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2;
end if;
end if;
end process REG_RD_ACK_P;
-------------------------
ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3;
-------------------------
REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2bus_data_int <= (others => '0');
elsif(ip2Bus_RdAck_core_reg_d2 = '1') then
ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or
("000000000000000000000000000" & IP2Bus_XIPSR_Data_int);
end if;
end if;
end process REG_IP2BUS_DATA_P;
-------------------------
--------------------------------------------------------------------------
XIP_SR_I : entity axi_quad_spi_v3_1.xip_status_reg
generic map
(
C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic;
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic;
XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic;
XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic;
XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic;
------------------------
Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR),
Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR),
-------------------
IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int ,
ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3
);
---------------------------------------------------------------------------
--REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN);
end if;
end process REG_RST4_FRM_IPIF;
-------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_1.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------------------------------------------
AXI_QSPI_XIP_I : entity axi_quad_spi_v3_1.axi_qspi_xip_if
generic map
(
C_FAMILY => C_FAMILY ,
C_SUB_FAMILY => C_SUB_FAMILY ,
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
--C_XIP_MODE => C_XIP_MODE ,
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
--C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
-------------------------
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH ,
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH ,
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR ,
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR ,
-------------------------
--C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH ,
--C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH ,
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY
)
port map
(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int,
----------------------------------
S_AXI_ACLK => s_axi_aclk , -- : in std_logic;
S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic;
----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic;
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel Signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready , -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready , -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic
-------------------------------
TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic
TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int,
TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int ,
TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int,
-------------------------------
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
--*SPI port interface * --
-------------------------------
IO0_I => io0_i, -- : in std_logic; -- MOSI signal in standard SPI
IO0_O => io0_o, -- : out std_logic;
IO0_T => io0_t, -- : out std_logic;
-------------------------------
IO1_I => MISO_I_int, -- : in std_logic; -- MISO signal in standard SPI
IO1_O => io1_o, -- : out std_logic;
IO1_T => io1_t, -- : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I => io2_i, -- : in std_logic;
IO2_O => io2_o, -- : out std_logic;
IO2_T => io2_t, -- : out std_logic;
---------------
IO3_I => io3_i, -- : in std_logic;
IO3_O => io3_o, -- : out std_logic;
IO3_T => io3_t, -- : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL => spisel, -- : in std_logic;
-----
SCK_I => sck_i , -- : in std_logic;
SCK_O_reg => SCK_O_int , -- : out std_logic;
SCK_T => sck_t , -- : out std_logic;
-----
SS_I => ss_i , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O => ss_o , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T => ss_t -- : out std_logic;
----------------------
);
-- no interrupt from this mode of core
IP2INTC_Irpt <= '0';
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
end generate XIP_MODE_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
| mit | d900f09edf4eafb4151b8df635afe193 | 0.432545 | 3.873752 | false | false | false | false |
6769/VHDL | Lab_1_partB/Input_Display.vhd | 1 | 2,150 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--finally synthesis all component;
entity Input_Display is
port(adder1,adder2:in bit_vector(7 downto 0);
adder1_hex_display,adder2_hex_display:out bit_vector(15 downto 0);
sum:out bit_vector(23 downto 0)
);
end entity Input_Display;
architecture combination of Input_Display is
--bcd4-adder;
component Bcd2digitAdder
port (adder1,adder2:in bit_vector(7 downto 0);
result:out bit_vector(7 downto 0);
finalCarry:out bit);
end component;
--7segment decoder;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
signal result_in_bcd:bit_vector(7 downto 0);
signal HighBit:bit;
signal tower:bit_vector(3 downto 0):="0000";
signal point_value:bit:='1';
begin
tower(0)<= HighBit;
Bcdadder:Bcd2digitAdder port map(adder1,adder2,result_in_bcd,HighBit);
--display Adder1;
--lower 4
Dis7Segment_adder1_lower:Segment7Decoder port map(adder1(3 downto 0),adder1_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder1_higer:Segment7Decoder port map(adder1(7 downto 4),adder1_hex_display(15 downto 9));
--point in bit 8,0
--display Adder2 ;
--lower 4
Dis7Segment_adder2_lower:Segment7Decoder port map(adder2(3 downto 0),adder2_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder2_higer:Segment7Decoder port map(adder2(7 downto 4),adder2_hex_display(15 downto 9));
--display result_in_bcd
Dis7Segment_result_lower:Segment7Decoder port map(result_in_bcd(3 downto 0),sum( 7 downto 1));
Dis7Segment_result_higer:Segment7Decoder port map(result_in_bcd(7 downto 4),sum(15 downto 9));
Dis7Segment_result_tower:Segment7Decoder port map(tower ,sum(23 downto 17));
--point in bit 16,8,0;
--reset All of Point in segment ;
adder1_hex_display(0)<=point_value;
adder1_hex_display(8)<=point_value;
adder2_hex_display(0)<=point_value;
adder2_hex_display(8)<=point_value;
sum(0)<=point_value;
sum(8)<=point_value;
sum(16)<=point_value;
end architecture combination; | gpl-2.0 | dce915d403c219ad32fe55ee97210040 | 0.731163 | 2.921196 | false | false | false | false |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/dist_mem_utils.vhd | 1 | 9,999 | `protect begin_protected
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`protect end_protected
| mit | 22a02cfb0cba5ffb1f50650f3358c904 | 0.925893 | 1.927332 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer | src/VGA/VGA_play.vhd | 2 | 6,134 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 17:12:10 11/26/2013
-- Design Name:
-- Module Name: VGA_play - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_play is
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- following are debug ports
--hclk: in std_logic; -- hand-clock, for debug
--wctrlin: in std_logic_vector(0 downto 0);
--KEY16_INPUT : in std_logic_vector(15 downto 0);
--LED_output : out std_logic_vector(15 downto 0);
--mout : out std_logic_vector(0 downto 0)
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end VGA_play;
architecture Behavioral of VGA_play is
signal clk: std_logic; -- div 50M to 25M
signal vector_x : std_logic_vector(9 downto 0); --X 10b 640
signal vector_y : std_logic_vector(8 downto 0); --Y 9b 480
signal r0 : std_logic_vector(2 downto 0);
signal g0 : std_logic_vector(2 downto 0);
signal b0 : std_logic_vector(2 downto 0);
signal hs1 : std_logic;
signal vs1 : std_logic;
component char_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
end component;
component fifo_mem
PORT (
-- a for write
clka : IN STD_LOGIC;
-- enable, 1 is write signal
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- b for read
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal char: std_logic_vector(7 downto 0) := "00000000";
signal pr: STD_LOGIC_VECTOR(0 DOWNTO 0);
signal char_addr: std_logic_vector(14 downto 0);
signal caddr: std_logic_vector(10 downto 0);
begin
-- waddr <= "0000000" & KEY16_INPUT(11 downto 8);
-- wdata <= KEY16_INPUT(7 downto 0);
-- debug code
-- LED_output <= "0000" & KEY16_INPUT(11 downto 8) & KEY16_INPUT(7 downto 0);
-- mout <= wctrl(0 downto 0);
-- process(hclk)
-- begin
-- if(hclk'event and hclk = '1') then
-- wctrl(0 downto 0) <= not wctrl(0 downto 0);
-- end if;
-- end process;
-- store char
ram: char_mem port map(clka => clk, addra => char_addr, douta => pr);
-- display cache
cache: fifo_mem port map(
-- a for write
clka => clk,
-- enable, 1 is write signal
wea => wctrl,
addra => waddr,
dina => wdata,
-- b for read
clkb => clk,
addrb => caddr,
doutb => char
);
-- cache addr 5 + 6 = 11
caddr <= vector_y(8 downto 4) & vector_x(9 downto 4);
-- char acess addr 7 + 4 + 4 = 15
-- last 2 control the display(x, y)
-- first char control which char
char_addr <= char(6 downto 0) & vector_y(3 downto 0) & vector_x(3 downto 0);
-- -- this is only for debug
-- process(reset, hclk)
-- begin
-- if reset = '0' then
-- char <= (others => '0');
-- elsif hclk'event and hclk = '1' then
-- char <= char + 1;
-- end if;
-- end process;
-- 25 MHz Sync
clkout <= clk;
-- 50 MHz -> 25 MHz
process(CLK_0)
begin
if(CLK_0'event and CLK_0 = '1') then
clk <= not clk;
end if;
end process;
process(clk, reset) -- ÐÐÇø¼äÏñËØÊý (800)
begin
if reset = '0' then
vector_x <= (others => '0');
elsif clk'event and clk = '1' then
if vector_x = 799 then
vector_x <= (others => '0');
else
vector_x <= vector_x + 1;
end if;
end if;
end process;
process(clk, reset) -- ³¡Çø¼äÐÐÊý (525)
begin
if reset = '0' then
vector_y <= (others => '0');
elsif clk'event and clk = '1' then
if vector_x = 799 then
if vector_y = 524 then
vector_y <= (others => '0');
else
vector_y <= vector_y + 1;
end if;
end if;
end if;
end process;
process(clk, reset) -- ÐÐͬ²½Ðźţ¨640+ÏûÒþÇø£º16¿Õ+96µÍ+48¿Õ£©
begin
if reset='0' then
hs1 <= '1';
elsif clk'event and clk='1' then
if vector_x >= 656 and vector_x < 752 then
hs1 <= '0';
else
hs1 <= '1';
end if;
end if;
end process;
process(clk, reset) -- ³¡Í¬²½Ðźţ¨480+ÏûÒþÇø£º10¿Õ+2µÍ+33¿Õ£©
begin
if reset = '0' then
vs1 <= '1';
elsif clk'event and clk = '1' then
if vector_y >= 490 and vector_y < 492 then
vs1 <= '0';
else
vs1 <= '1';
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '0' then
hs <= '0';
vs <= '0';
elsif clk'event and clk = '1' then
hs <= hs1;
vs <= vs1;
end if;
end process;
process(reset, clk, vector_x, vector_y) -- X, Y ×ø±ê¿ØÖÆ
begin
if reset = '0' then
r0 <= "000";
g0 <= "000";
b0 <= "000";
elsif clk'event and clk = '1' then
if vector_x > 639 or vector_y > 479 then
r0 <= "000";
g0 <= "000";
b0 <= "000";
else
-- play-ground
-- play-ground
if pr(0) = '1' then
r0 <= "111";
g0 <= "000";
b0 <= "000";
else
r0 <= "000";
g0 <= "001";
b0 <= "001";
end if;
-- play-ground
-- play-ground
end if;
end if;
end process;
process(hs1, vs1, r0, g0, b0) -- ×îµÍµÄÉ«²ÊÊä³ö
begin
if hs1 = '1' and vs1 = '1' then
R <= r0;
G <= g0;
B <= b0;
else
R <= (others => '0');
G <= (others => '0');
B <= (others => '0');
end if;
end process;
end Behavioral;
| mit | 423844420f4895e47627e6c54aadc2ae | 0.589664 | 2.705779 | false | false | false | false |
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