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|---|---|---|---|---|---|---|---|---|---|---|---|---|
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/cart_slot_pkg.vhd | 3 | 2,562 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(3 downto 0);
cartridge_kill : std_logic;
kernal_enable : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
eth_enable : std_logic;
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => X"0",
cartridge_kill => '0',
kernal_enable => '0',
reu_enable => '0',
reu_size => "111",
eth_enable => '0',
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1' );
end cart_slot_pkg;
| gpl-3.0 | 4cfed926c9250f27d06e2e5fe4739ea0 | 0.532006 | 3.113001 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper.vhd | 5 | 4,244 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.copper_pkg.all;
entity copper is
generic (
g_copper_size : natural := 12 );
port (
clock : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
phi2_tick : in std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp );
end entity;
architecture gideon of copper is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_gate : std_logic := '0';
signal copper_addr : unsigned(g_copper_size-1 downto 0);
signal copper_rdata : std_logic_vector(7 downto 0);
signal copper_wdata : std_logic_vector(7 downto 0);
signal copper_we : std_logic;
signal copper_en : std_logic;
signal control : t_copper_control;
signal status : t_copper_status;
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
i_regs: entity work.copper_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => g_copper_size,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(g_copper_size-1 downto 0),
a_rdata => ram_rdata,
a_wdata => io_req_ram.data,
a_en => '1',
a_we => io_req_ram.write,
b_clock => clock,
b_address => copper_addr,
b_rdata => copper_rdata,
b_wdata => copper_wdata,
b_en => copper_en,
b_we => copper_we );
process(clock)
begin
if rising_edge(clock) then
io_resp_ram.ack <= io_req_ram.read or io_req_ram.write;
ram_gate <= io_req_ram.read;
end if;
end process;
io_resp_ram.data <= ram_rdata when ram_gate='1' else X"00";
i_fsm: entity work.copper_engine
generic map (
g_copper_size => g_copper_size )
port map (
clock => clock,
reset => reset,
irq_n => irq_n,
phi2_tick => phi2_tick,
ram_address => copper_addr,
ram_rdata => copper_rdata,
ram_wdata => copper_wdata,
ram_en => copper_en,
ram_we => copper_we,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
slot_req => slot_req,
slot_resp => slot_resp,
dma_req => dma_req,
dma_resp => dma_resp,
control => control,
status => status );
end gideon;
| gpl-3.0 | 7b70e350dceba214a47c4895cb4b4394 | 0.474552 | 3.453214 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/cs8900a/vhdl_source/cs8900a_bus.vhd | 3 | 7,543 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
| gpl-3.0 | cb6373589b342cafa51544a673fb2986 | 0.456715 | 3.838677 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op980_14.vhdl | 1 | 6,801 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 97d0221800ea6ca3f8042edad44f29f8 | 0.573445 | 3.084354 | false | false | false | false |
chrismasters/fpga-notes | vga_test/ipcore_dir/vga_clk/simulation/vga_clk_tb.vhd | 1 | 6,124 | -- file: vga_clk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity vga_clk_tb is
end vga_clk_tb;
architecture test of vga_clk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component vga_clk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : vga_clk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | 4d7d20646f39a9b71866902966d9e790 | 0.637655 | 4.276536 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_15sk1_0.vhdl | 1 | 6,646 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 3.145e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 3.145e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 3.74e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.25e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 4.61e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.25e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 4.61e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 6.94e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.06e-05,
W => Wcm_1,
Wcm_1init => 7.1e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.06e-05,
W => Wcmout_1,
Wcmout_1init => 3.185e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 6.94e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 9.7e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 9.7e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 9.7e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 9.7e-06
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 9.7e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 9.7e-06
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | defcb9116dd814c80853747619b08552 | 0.582907 | 2.918753 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/reu_pkg.vhd | 4 | 1,402 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
| gpl-3.0 | 1f4ceb7156707f8d150eef017fe1daac | 0.567047 | 2.804 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op984_5.vhdl | 1 | 4,600 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 76399405534c6a52d96c38f3bf3dab4c | 0.582391 | 3.214535 | false | false | false | false |
chrismasters/fpga-notes | sdramcontroller/sdramcontroller_testbench.vhd | 1 | 3,498 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT sdramcontroller
PORT(
clk : IN std_logic;
addr : IN std_logic_vector(15 downto 0);
cmd : IN std_logic_vector(1 downto 0);
dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
ready : OUT std_logic;
chipCS : OUT std_logic;
chipWE : OUT std_logic;
chipCAS : OUT std_logic;
chipRAS : OUT std_logic;
chipDQML : OUT std_logic;
chipDQMH : OUT std_logic;
chipBA : OUT std_logic_vector(1 downto 0);
chipADDR : OUT std_logic_vector(11 downto 0);
chipDATA : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mt48lc4m16a2
PORT(
Addr : IN std_logic_vector(11 downto 0);
Ba : IN std_logic_vector(1 downto 0);
Clk : IN std_logic;
Cke : IN std_logic;
Cs_n : IN std_logic;
Ras_n : IN std_logic;
Cas_n : IN std_logic;
We_n : IN std_logic;
Dqm : IN std_logic_vector(1 downto 0);
Dq : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL clkinv : std_logic;
SIGNAL addr : std_logic_vector(15 downto 0) := (others => '0');
SIGNAL cmd : std_logic_vector(1 downto 0) := "00";
SIGNAL dataIn : std_logic_vector(7 downto 0) := (others => 'Z');
SIGNAL dataOut : std_logic_vector(7 downto 0) := (others => 'Z');
SIGNAL ready : std_logic;
SIGNAL chipCS : std_logic;
SIGNAL chipWE : std_logic;
SIGNAL chipCAS : std_logic;
SIGNAL chipRAS : std_logic;
SIGNAL chipDQML : std_logic;
SIGNAL chipDQMH : std_logic;
SIGNAL dqm : std_logic_vector(1 downto 0);
SIGNAL chipBA : std_logic_vector(1 downto 0);
SIGNAL chipADDR : std_logic_vector(11 downto 0);
SIGNAL chipDATA : std_logic_vector(15 downto 0) := (others => 'Z');
constant clk_period : time := 7.518ns;
BEGIN
dqm <= chipDQMH & chipDQML;
clkinv <= not clk;
uut: sdramcontroller PORT MAP(
clk => clk,
addr => addr,
dataIn => dataIn,
dataOut => dataOut,
cmd => cmd,
ready => ready,
chipCS => chipCS,
chipWE => chipWE,
chipCAS => chipCAS,
chipRAS => chipRAS,
chipDQML => chipDQML,
chipDQMH => chipDQMH,
chipBA => chipBA,
chipADDR => chipADDR,
chipDATA => chipDATA
);
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process clk_process;
Inst_mt48lc4m16a2: mt48lc4m16a2 PORT MAP(
Dq => chipDATA,
Addr => chipADDR,
Ba => chipBA,
Clk => clkinv,
Cke => '1',
Cs_n => chipCS,
Ras_n => chipRAS,
Cas_n => chipCAS,
We_n => chipWE,
Dqm => dqm
);
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
wait for 1000 ns;
--assert ready = '1' report "end of init sequence and controller not ready" severity failure;
addr <= "0000000000011110";
dataIn <= "11110101";
cmd <= "11";
wait for 20ns;
cmd <= "00";
wait for 30ns;
assert chipData = "0000000011110101" report "chipData out didn't contain right data" severity failure;
--chipDATA <= "0000000001010101";
addr <= "0000000000011110";
cmd <= "01";
wait for 20ns;
cmd <= "00";
wait for 60ns;
assert ready = '1' report "end of read sequence and controller not ready" severity failure;
assert dataOut = "11110101" report "data out didn't contain right data" severity failure;
--chipDATA <= (others => 'Z');
wait; -- will wait forever
END PROCESS tb;
END;
| mit | da9fdb1cac8c93ea4f3d2ea8c1e30dbd | 0.651229 | 2.937028 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_8bit_ok.vhd | 5 | 28,212 | ------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_i : in unsigned(c_opcode_width-1 downto 0);
c_valid_i : in std_logic;
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_o : out unsigned(c_opcode_width-1 downto 0);
c_en_o : out std_logic;
c_we_o : out std_logic );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
-- constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal dec_valid : std_logic;
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= '1';
b_en_o <= '1';
c_en_o <= '1' when state = st_fetch else c_en_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
byte_cnt_d <= byte_cnt;
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
dec_valid <= not c_mux_d and c_valid_i;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
if dec_valid = '1' then
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_en_r <= '1';
-- c_mux_r <= '1';
-- byte_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
end if; -- decode valid
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
if c_valid_i = '1' then
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
end if;
if byte_cnt = "00" then
c_mux_r <= '0';
c_en_r <= '0';
end if;
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_en_r <= '0';
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
first <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: zpu_8bit
| gpl-3.0 | 8ca2b35562406296ac142fb4dc223363 | 0.31834 | 4.730382 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op0.vhdl | 1 | 8,912 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.05e-06,
W => Wdiff_0,
Wdiff_0init => 6.4e-06,
scope => private
)
port map(
D => net1,
G => in1,
S => net3
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.05e-06,
W => Wdiff_0,
Wdiff_0init => 6.4e-06,
scope => private
)
port map(
D => net2,
G => in2,
S => net3
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => W_0,
W_0init => 2.08e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.05e-06,
W => Wdiff_0,
Wdiff_0init => 6.4e-06,
scope => private
)
port map(
D => net4,
G => in1,
S => net3
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.05e-06,
W => Wdiff_0,
Wdiff_0init => 6.4e-06,
scope => private
)
port map(
D => net4,
G => in2,
S => net3
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.3e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.3e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.3e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net1,
G => net4,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.3e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net2,
G => net4,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 5e-07,
W => Wsrc_1,
Wsrc_1init => 7.42e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 9.5e-07,
W => Wsrc_1,
Wsrc_1init => 7.42e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => out2,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => Wcursrc_2,
Wcursrc_2init => 6.67e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => Wcursrc_2,
Wcursrc_2init => 6.67e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net5,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net8,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net7,
N => net5
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => W_1,
W_1init => 7.705e-05
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.17e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 7.705e-05,
scope => private
)
port map(
D => net8,
G => vref,
S => net6
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.17e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 7.705e-05,
scope => private
)
port map(
D => net7,
G => net5,
S => net6
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.05e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 4.25e-06,
scope => private
)
port map(
D => net7,
G => net7,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.05e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 4.25e-06,
scope => private
)
port map(
D => net8,
G => net7,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7e-07,
W => Wcmbias_0,
Wcmbias_0init => 5.5e-07,
scope => private
)
port map(
D => out1,
G => net8,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7e-07,
W => Wcmbias_0,
Wcmbias_0init => 5.5e-07,
scope => private
)
port map(
D => out2,
G => net8,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => (pfak)*(WBias),
WBiasinit => 7.52e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.3e-06,
W => (pfak)*(WBias),
WBiasinit => 7.52e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.52e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.52e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.52e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.52e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 52d19791a9f828a60b89b765ad58c47c | 0.57013 | 2.840025 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/mt48lc16m16a2.vhd | 5 | 81,238 | --------------------------------------------------------------------------------
-- File Name: mt48lc16m16a2.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2005-2010. Free Model Foundry; http://www.freemodelfoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 M.Marinkovic 05 Jan 11 Initial release
-- V1.1 D.Popovic 07 Mar 19 correction of burst full page,
-- burst_lenght,
-- V1.2 S.Petrovic 10 Jan 27 corrected memory addressing in
-- part of column address
-- Thanks to Michael Pagen for finding
-- this bug.
-- V1.3 S.Petrovic 10 Apr 24 Corrected refresh period,
-- tdevice_REF, and max value of
-- refresh counter, Ref_Cnt.
-- Increment of the refresh counter is
-- in idle state, when ref
-- command occurs, instead of in
-- auto_refresh state.
-- Added condition for warnings
-- related to the DQML/H values when
-- precharge command truncates write
-- operation.
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: RAM
-- Technology: LVTTL
-- Part: mt48lc16m16a2, V54C3256, HYB 39S256800DT
--
-- Description: 4M x 16 x 4Banks SDRAM
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
USE STD.textio.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mt48lc16m16a2 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_BA0 : VitalDelayType01 := VitalZeroDelay01;
tipd_BA1 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQMH : VitalDelayType01 := VitalZeroDelay01;
tipd_DQML : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01;
tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01;
tipd_CLK : VitalDelayType01 := VitalZeroDelay01;
tipd_CKE : VitalDelayType01 := VitalZeroDelay01;
tipd_A0 : VitalDelayType01 := VitalZeroDelay01;
tipd_A1 : VitalDelayType01 := VitalZeroDelay01;
tipd_A2 : VitalDelayType01 := VitalZeroDelay01;
tipd_A3 : VitalDelayType01 := VitalZeroDelay01;
tipd_A4 : VitalDelayType01 := VitalZeroDelay01;
tipd_A5 : VitalDelayType01 := VitalZeroDelay01;
tipd_A6 : VitalDelayType01 := VitalZeroDelay01;
tipd_A7 : VitalDelayType01 := VitalZeroDelay01;
tipd_A8 : VitalDelayType01 := VitalZeroDelay01;
tipd_A9 : VitalDelayType01 := VitalZeroDelay01;
tipd_A10 : VitalDelayType01 := VitalZeroDelay01;
tipd_A11 : VitalDelayType01 := VitalZeroDelay01;
tipd_A12 : VitalDelayType01 := VitalZeroDelay01;
tipd_WENeg : VitalDelayType01 := VitalZeroDelay01;
tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_CLK_DQ2 : VitalDelayType01Z := UnitDelay01Z;
tpd_CLK_DQ3 : VitalDelayType01Z := UnitDelay01Z;
-- tpw values: pulse widths
tpw_CLK_posedge : VitalDelayType := UnitDelay;
tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- tsetup values: setup times
tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- thold values: hold times
thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- tperiod_min: minimum clock period = 1/max freq
tperiod_CLK_posedge : VitalDelayType := UnitDelay;
-- tdevice values: values for internal delays
tdevice_REF : VitalDelayType := 7_810 ns;
tdevice_TRC : VitalDelayType := 66 ns;
tdevice_TRCD : VitalDelayType := 20 ns;
tdevice_TRP : VitalDelayType := 20 ns;
tdevice_TRCAR : VitalDelayType := 66 ns;
tdevice_TWR : VitalDelayType := 15 ns;
tdevice_TRAS : VitalDelayType01 := (44 ns, 120_000 ns);
-- tpowerup: Power up initialization time. Data sheets say 100 us.
-- May be shortened during simulation debug.
tpowerup : TIME := 100 us;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
SeverityMode : SEVERITY_LEVEL := WARNING;
-- memory file to be loaded
mem_file_name : STRING := "mt48lc16m16a2.mem";
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
BA0 : IN std_logic := 'U';
BA1 : IN std_logic := 'U';
DQMH : IN std_logic := 'U';
DQML : IN std_logic := 'U';
DQ0 : INOUT std_logic := 'U';
DQ1 : INOUT std_logic := 'U';
DQ2 : INOUT std_logic := 'U';
DQ3 : INOUT std_logic := 'U';
DQ4 : INOUT std_logic := 'U';
DQ5 : INOUT std_logic := 'U';
DQ6 : INOUT std_logic := 'U';
DQ7 : INOUT std_logic := 'U';
DQ8 : INOUT std_logic := 'U';
DQ9 : INOUT std_logic := 'U';
DQ10 : INOUT std_logic := 'U';
DQ11 : INOUT std_logic := 'U';
DQ12 : INOUT std_logic := 'U';
DQ13 : INOUT std_logic := 'U';
DQ14 : INOUT std_logic := 'U';
DQ15 : INOUT std_logic := 'U';
CLK : IN std_logic := 'U';
CKE : IN std_logic := 'U';
A0 : IN std_logic := 'U';
A1 : IN std_logic := 'U';
A2 : IN std_logic := 'U';
A3 : IN std_logic := 'U';
A4 : IN std_logic := 'U';
A5 : IN std_logic := 'U';
A6 : IN std_logic := 'U';
A7 : IN std_logic := 'U';
A8 : IN std_logic := 'U';
A9 : IN std_logic := 'U';
A10 : IN std_logic := 'U';
A11 : IN std_logic := 'U';
A12 : IN std_logic := 'U';
WENeg : IN std_logic := 'U';
RASNeg : IN std_logic := 'U';
CSNeg : IN std_logic := 'U';
CASNeg : IN std_logic := 'U'
);
ATTRIBUTE VITAL_LEVEL0 of mt48lc16m16a2 : ENTITY IS TRUE;
END mt48lc16m16a2;
--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mt48lc16m16a2 IS
ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT partID : STRING := "mt48lc16m16a2";
CONSTANT hi_bank : NATURAL := 3;
CONSTANT depth : NATURAL := 4194304; -- 16#400000#
SIGNAL CKEreg : X01 := 'X';
SIGNAL PoweredUp : boolean := false;
SIGNAL BA0_ipd : std_ulogic := 'X';
SIGNAL BA1_ipd : std_ulogic := 'X';
SIGNAL DQML_ipd : std_ulogic := 'X';
SIGNAL DQMH_ipd : std_ulogic := 'X';
SIGNAL DQ0_ipd : std_ulogic := 'X';
SIGNAL DQ1_ipd : std_ulogic := 'X';
SIGNAL DQ2_ipd : std_ulogic := 'X';
SIGNAL DQ3_ipd : std_ulogic := 'X';
SIGNAL DQ4_ipd : std_ulogic := 'X';
SIGNAL DQ5_ipd : std_ulogic := 'X';
SIGNAL DQ6_ipd : std_ulogic := 'X';
SIGNAL DQ7_ipd : std_ulogic := 'X';
SIGNAL DQ8_ipd : std_ulogic := 'X';
SIGNAL DQ9_ipd : std_ulogic := 'X';
SIGNAL DQ10_ipd : std_ulogic := 'X';
SIGNAL DQ11_ipd : std_ulogic := 'X';
SIGNAL DQ12_ipd : std_ulogic := 'X';
SIGNAL DQ13_ipd : std_ulogic := 'X';
SIGNAL DQ14_ipd : std_ulogic := 'X';
SIGNAL DQ15_ipd : std_ulogic := 'X';
SIGNAL CLK_ipd : std_ulogic := 'X';
SIGNAL CKE_ipd : std_ulogic := 'X';
SIGNAL A0_ipd : std_ulogic := 'X';
SIGNAL A1_ipd : std_ulogic := 'X';
SIGNAL A2_ipd : std_ulogic := 'X';
SIGNAL A3_ipd : std_ulogic := 'X';
SIGNAL A4_ipd : std_ulogic := 'X';
SIGNAL A5_ipd : std_ulogic := 'X';
SIGNAL A6_ipd : std_ulogic := 'X';
SIGNAL A7_ipd : std_ulogic := 'X';
SIGNAL A8_ipd : std_ulogic := 'X';
SIGNAL A9_ipd : std_ulogic := 'X';
SIGNAL A10_ipd : std_ulogic := 'X';
SIGNAL A11_ipd : std_ulogic := 'X';
SIGNAL A12_ipd : std_ulogic := 'X';
SIGNAL WENeg_ipd : std_ulogic := 'X';
SIGNAL RASNeg_ipd : std_ulogic := 'X';
SIGNAL CSNeg_ipd : std_ulogic := 'X';
SIGNAL CASNeg_ipd : std_ulogic := 'X';
SIGNAL BA0_nwv : std_ulogic := 'X';
SIGNAL BA1_nwv : std_ulogic := 'X';
SIGNAL DQML_nwv : std_ulogic := 'X';
SIGNAL DQMH_nwv : std_ulogic := 'X';
SIGNAL DQ0_nwv : std_ulogic := 'X';
SIGNAL DQ1_nwv : std_ulogic := 'X';
SIGNAL DQ2_nwv : std_ulogic := 'X';
SIGNAL DQ3_nwv : std_ulogic := 'X';
SIGNAL DQ4_nwv : std_ulogic := 'X';
SIGNAL DQ5_nwv : std_ulogic := 'X';
SIGNAL DQ6_nwv : std_ulogic := 'X';
SIGNAL DQ7_nwv : std_ulogic := 'X';
SIGNAL DQ8_nwv : std_ulogic := 'X';
SIGNAL DQ9_nwv : std_ulogic := 'X';
SIGNAL DQ10_nwv : std_ulogic := 'X';
SIGNAL DQ11_nwv : std_ulogic := 'X';
SIGNAL DQ12_nwv : std_ulogic := 'X';
SIGNAL DQ13_nwv : std_ulogic := 'X';
SIGNAL DQ14_nwv : std_ulogic := 'X';
SIGNAL DQ15_nwv : std_ulogic := 'X';
SIGNAL A0_nwv : std_ulogic := 'X';
SIGNAL A1_nwv : std_ulogic := 'X';
SIGNAL A2_nwv : std_ulogic := 'X';
SIGNAL A3_nwv : std_ulogic := 'X';
SIGNAL A4_nwv : std_ulogic := 'X';
SIGNAL A5_nwv : std_ulogic := 'X';
SIGNAL A6_nwv : std_ulogic := 'X';
SIGNAL A7_nwv : std_ulogic := 'X';
SIGNAL A8_nwv : std_ulogic := 'X';
SIGNAL A9_nwv : std_ulogic := 'X';
SIGNAL A10_nwv : std_ulogic := 'X';
SIGNAL A11_nwv : std_ulogic := 'X';
SIGNAL A12_nwv : std_ulogic := 'X';
SIGNAL CLK_nwv : std_ulogic := 'X';
SIGNAL CKE_nwv : std_ulogic := 'X';
SIGNAL WENeg_nwv : std_ulogic := 'X';
SIGNAL RASNeg_nwv : std_ulogic := 'X';
SIGNAL CSNeg_nwv : std_ulogic := 'X';
SIGNAL CASNeg_nwv : std_ulogic := 'X';
SIGNAL rct_in : std_ulogic := '0';
SIGNAL rct_out : std_ulogic := '0';
SIGNAL rcdt_in : std_ulogic_vector(3 downto 0) := (others => '0');
SIGNAL rcdt_out : std_ulogic_vector(3 downto 0) := (others => '0');
SIGNAL pre_in : std_ulogic := '0';
SIGNAL pre_out : std_ulogic := '0';
SIGNAL refreshed_in : std_ulogic := '0';
SIGNAL refreshed_out : std_ulogic := '0';
SIGNAL rcar_out : std_ulogic := '0';
SIGNAL rcar_in : std_ulogic := '0';
SIGNAL wrt_in : std_ulogic := '0';
SIGNAL wrt_out : std_ulogic := '0';
SIGNAL ras_in : std_ulogic_vector(3 downto 0) := (others => '0');
SIGNAL ras_out : std_ulogic_vector(3 downto 0) := (others => '0');
BEGIN
----------------------------------------------------------------------------
-- Internal Delays
----------------------------------------------------------------------------
-- Artificial VITAL primitives to incorporate internal delays
REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));
TRC : VitalBuf (rct_out, rct_in, (tdevice_TRC, UnitDelay));
TRCD : VitalBuf (rcdt_out(0), rcdt_in(0), (UnitDelay, tdevice_TRCD));
TRCD1 : VitalBuf (rcdt_out(1), rcdt_in(1), (UnitDelay, tdevice_TRCD));
TRCD2 : VitalBuf (rcdt_out(2), rcdt_in(2), (UnitDelay, tdevice_TRCD));
TRCD3 : VitalBuf (rcdt_out(3), rcdt_in(3), (UnitDelay, tdevice_TRCD));
TRP : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay));
TRCAR : VitalBuf (rcar_out, rcar_in, (tdevice_TRCAR, UnitDelay));
TWR : VitalBuf (wrt_out, wrt_in, (UnitDelay, tdevice_TWR));
TRAS : VitalBuf (ras_out(0), ras_in(0), tdevice_TRAS);
TRAS1 : VitalBuf (ras_out(1), ras_in(1), tdevice_TRAS);
TRAS2 : VitalBuf (ras_out(2), ras_in(2), tdevice_TRAS);
TRAS3 : VitalBuf (ras_out(3), ras_in(3), tdevice_TRAS);
----------------------------------------------------------------------------
-- Wire Delays
----------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0);
w_2 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1);
w_3 : VitalWireDelay (DQML_ipd, DQML, tipd_DQML);
w_4 : VitalWireDelay (DQMH_ipd, DQMH, tipd_DQMH);
w_5 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
w_6 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
w_7 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
w_8 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
w_9 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
w_10 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
w_11 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
w_12 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
w_13 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8);
w_14 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9);
w_15 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10);
w_16 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11);
w_17 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12);
w_18 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13);
w_19 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14);
w_20 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15);
w_21 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
w_22 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE);
w_23 : VitalWireDelay (A0_ipd, A0, tipd_A0);
w_24 : VitalWireDelay (A1_ipd, A1, tipd_A1);
w_25 : VitalWireDelay (A2_ipd, A2, tipd_A2);
w_26 : VitalWireDelay (A3_ipd, A3, tipd_A3);
w_27 : VitalWireDelay (A4_ipd, A4, tipd_A4);
w_28 : VitalWireDelay (A5_ipd, A5, tipd_A5);
w_29 : VitalWireDelay (A6_ipd, A6, tipd_A6);
w_30 : VitalWireDelay (A7_ipd, A7, tipd_A7);
w_31 : VitalWireDelay (A8_ipd, A8, tipd_A8);
w_32 : VitalWireDelay (A9_ipd, A9, tipd_A9);
w_33 : VitalWireDelay (A10_ipd, A10, tipd_A10);
w_34 : VitalWireDelay (A11_ipd, A11, tipd_A11);
w_35 : VitalWireDelay (A12_ipd, A12, tipd_A12);
w_36 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
w_37 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
w_38 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
w_39 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);
END BLOCK;
WENeg_nwv <= To_UX01(WENeg_ipd);
RASNeg_nwv <= To_UX01(RASNeg_ipd);
CSNeg_nwv <= To_UX01(CSNeg_ipd);
CASNeg_nwv <= To_UX01(CASNeg_ipd);
CLK_nwv <= To_UX01(CLK_ipd);
CKE_nwv <= To_UX01(CKE_ipd);
BA0_nwv <= To_UX01(BA0_ipd);
BA1_nwv <= To_UX01(BA1_ipd);
DQML_nwv <= To_UX01(DQML_ipd);
DQMH_nwv <= To_UX01(DQMH_ipd);
DQ0_nwv <= To_UX01(DQ0_ipd);
DQ1_nwv <= To_UX01(DQ1_ipd);
DQ2_nwv <= To_UX01(DQ2_ipd);
DQ3_nwv <= To_UX01(DQ3_ipd);
DQ4_nwv <= To_UX01(DQ4_ipd);
DQ5_nwv <= To_UX01(DQ5_ipd);
DQ6_nwv <= To_UX01(DQ6_ipd);
DQ7_nwv <= To_UX01(DQ7_ipd);
DQ8_nwv <= To_UX01(DQ8_ipd);
DQ9_nwv <= To_UX01(DQ9_ipd);
DQ10_nwv <= To_UX01(DQ10_ipd);
DQ11_nwv <= To_UX01(DQ11_ipd);
DQ12_nwv <= To_UX01(DQ12_ipd);
DQ13_nwv <= To_UX01(DQ13_ipd);
DQ14_nwv <= To_UX01(DQ14_ipd);
DQ15_nwv <= To_UX01(DQ15_ipd);
A0_nwv <= To_UX01(A0_ipd);
A1_nwv <= To_UX01(A1_ipd);
A2_nwv <= To_UX01(A2_ipd);
A3_nwv <= To_UX01(A3_ipd);
A4_nwv <= To_UX01(A4_ipd);
A5_nwv <= To_UX01(A5_ipd);
A6_nwv <= To_UX01(A6_ipd);
A7_nwv <= To_UX01(A7_ipd);
A8_nwv <= To_UX01(A8_ipd);
A9_nwv <= To_UX01(A9_ipd);
A10_nwv <= To_UX01(A10_ipd);
A11_nwv <= To_UX01(A11_ipd);
A12_nwv <= To_UX01(A12_ipd);
----------------------------------------------------------------------------
-- Main Behavior Block
----------------------------------------------------------------------------
Main : BLOCK
PORT (
BAIn : IN std_logic_vector(1 downto 0);
DQMLIn : IN std_ulogic := 'X';
DQMHIn : IN std_ulogic := 'X';
DataIn : IN std_logic_vector(15 downto 0);
DataOut : OUT std_logic_vector(15 downto 0)
:= (others => 'Z');
CLKIn : IN std_ulogic := 'X';
CKEIn : IN std_ulogic := 'X';
AddressIn : IN std_logic_vector(12 downto 0);
WENegIn : IN std_ulogic := 'X';
RASNegIn : IN std_ulogic := 'X';
CSNegIn : IN std_ulogic := 'X';
CASNegIn : IN std_ulogic := 'X'
);
PORT MAP (
BAIn(0) => BA0_nwv,
BAIn(1) => BA1_nwv,
DQMHIn => DQMH_nwv,
DQMLIn => DQML_nwv,
DataOut(0) => DQ0,
DataOut(1) => DQ1,
DataOut(2) => DQ2,
DataOut(3) => DQ3,
DataOut(4) => DQ4,
DataOut(5) => DQ5,
DataOut(6) => DQ6,
DataOut(7) => DQ7,
DataOut(8) => DQ8,
DataOut(9) => DQ9,
DataOut(10) => DQ10,
DataOut(11) => DQ11,
DataOut(12) => DQ12,
DataOut(13) => DQ13,
DataOut(14) => DQ14,
DataOut(15) => DQ15,
DataIn(0) => DQ0_nwv,
DataIn(1) => DQ1_nwv,
DataIn(2) => DQ2_nwv,
DataIn(3) => DQ3_nwv,
DataIn(4) => DQ4_nwv,
DataIn(5) => DQ5_nwv,
DataIn(6) => DQ6_nwv,
DataIn(7) => DQ7_nwv,
DataIn(8) => DQ8_nwv,
DataIn(9) => DQ9_nwv,
DataIn(10) => DQ10_nwv,
DataIn(11) => DQ11_nwv,
DataIn(12) => DQ12_nwv,
DataIn(13) => DQ13_nwv,
DataIn(14) => DQ14_nwv,
DataIn(15) => DQ15_nwv,
CLKIn => CLK_nwv,
CKEIn => CKE_nwv,
AddressIn(0) => A0_nwv,
AddressIn(1) => A1_nwv,
AddressIn(2) => A2_nwv,
AddressIn(3) => A3_nwv,
AddressIn(4) => A4_nwv,
AddressIn(5) => A5_nwv,
AddressIn(6) => A6_nwv,
AddressIn(7) => A7_nwv,
AddressIn(8) => A8_nwv,
AddressIn(9) => A9_nwv,
AddressIn(10) => A10_nwv,
AddressIn(11) => A11_nwv,
AddressIn(12) => A12_nwv,
WENegIn => WENeg_nwv,
RASNegIn => RASNeg_nwv,
CSNegIn => CSNeg_nwv,
CASNegIn => CASNeg_nwv
);
-- Type definition for state machine
TYPE mem_state IS (pwron,
precharge,
idle,
mode_set,
self_refresh,
self_refresh_rec,
auto_refresh,
pwrdwn,
bank_act,
bank_act_pwrdwn,
write,
write_suspend,
read,
read_suspend,
write_auto_pre,
read_auto_pre
);
TYPE statebanktype IS array (hi_bank downto 0) of mem_state;
SIGNAL statebank : statebanktype;
SIGNAL CAS_Lat : NATURAL RANGE 0 to 3 := 0;
SIGNAL D_zd : std_logic_vector(15 DOWNTO 0);
BEGIN
PoweredUp <= true after tpowerup;
----------------------------------------------------------------------------
-- Main Behavior Process
----------------------------------------------------------------------------
Behavior : PROCESS (BAIn, DQMLIn, DQMHIn, DataIn, CLKIn,
CKEIn, AddressIn, WENegIn, RASNegIn, CSNegIn,
CASNegIn, PoweredUp)
-- Type definition for commands
TYPE command_type is (desl,
nop,
bst,
read,
writ,
act,
pre,
mrs,
ref
);
-- Timing Check Variables
VARIABLE Tviol_BA_CLK : X01 := '0';
VARIABLE TD_BA_CLK : VitalTimingDataType;
VARIABLE Tviol_DQML_CLK : X01 := '0';
VARIABLE TD_DQML_CLK : VitalTimingDataType;
VARIABLE Tviol_DQMH_CLK : X01 := '0';
VARIABLE TD_DQMH_CLK : VitalTimingDataType;
VARIABLE Tviol_D0_CLK : X01 := '0';
VARIABLE TD_D0_CLK : VitalTimingDataType;
VARIABLE Tviol_CKE_CLK : X01 := '0';
VARIABLE TD_CKE_CLK : VitalTimingDataType;
VARIABLE Tviol_Address_CLK : X01 := '0';
VARIABLE TD_Address_CLK : VitalTimingDataType;
VARIABLE Tviol_WENeg_CLK : X01 := '0';
VARIABLE TD_WENeg_CLK : VitalTimingDataType;
VARIABLE Tviol_RASNeg_CLK : X01 := '0';
VARIABLE TD_RASNeg_CLK : VitalTimingDataType;
VARIABLE Tviol_CSNeg_CLK : X01 := '0';
VARIABLE TD_CSNeg_CLK : VitalTimingDataType;
VARIABLE Tviol_CASNeg_CLK : X01 := '0';
VARIABLE TD_CASNeg_CLK : VitalTimingDataType;
VARIABLE Pviol_CLK : X01 := '0';
VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit;
-- Memory array declaration
TYPE MemStore IS ARRAY (0 to 2*depth-1) OF INTEGER
RANGE -2 TO 255;
TYPE MemBlock IS ARRAY (0 to 3) OF MemStore;
TYPE Burst_type IS (sequential, interleave);
TYPE Write_Burst_type IS (programmed, single);
TYPE sequence IS ARRAY (0 to 7) OF NATURAL RANGE 0 to 7;
TYPE seqtab IS ARRAY (0 to 7) OF sequence;
TYPE MemLoc IS ARRAY (0 to 3) OF std_logic_vector(22 DOWNTO 0);
TYPE burst_counter IS ARRAY (0 to 3) OF NATURAL RANGE 0 to 513;
TYPE StartAddr_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 7;
TYPE Burst_Inc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 511;
TYPE BaseLoc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 2*depth-1;
SUBTYPE OutWord IS std_logic_vector(15 DOWNTO 0);
CONSTANT seq0 : sequence := (0 & 1 & 2 & 3 & 4 & 5 & 6 & 7);
CONSTANT seq1 : sequence := (1 & 0 & 3 & 2 & 5 & 4 & 7 & 6);
CONSTANT seq2 : sequence := (2 & 3 & 0 & 1 & 6 & 7 & 4 & 5);
CONSTANT seq3 : sequence := (3 & 2 & 1 & 0 & 7 & 6 & 5 & 4);
CONSTANT seq4 : sequence := (4 & 5 & 6 & 7 & 0 & 1 & 2 & 3);
CONSTANT seq5 : sequence := (5 & 4 & 7 & 6 & 1 & 0 & 3 & 2);
CONSTANT seq6 : sequence := (6 & 7 & 4 & 5 & 2 & 3 & 0 & 1);
CONSTANT seq7 : sequence := (7 & 6 & 5 & 4 & 3 & 2 & 1 & 0);
CONSTANT intab : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5,
seq6, seq7);
FILE mem_file : text IS mem_file_name;
VARIABLE MemData : MemBlock;
VARIABLE file_bank : NATURAL := 0;
VARIABLE ind : NATURAL := 0;
VARIABLE buf : line;
VARIABLE MemAddr : MemLoc;
VARIABLE Location : NATURAL RANGE 0 TO 2*depth-1 := 0;
VARIABLE Location_tmp1 : NATURAL := 0;
VARIABLE Location_tmp2 : NATURAL := 0;
VARIABLE Location_tmp : std_logic_vector(15 DOWNTO 0);
VARIABLE BaseLoc : BaseLoc_type;
VARIABLE Burst_Inc : Burst_Inc_type;
VARIABLE StartAddr : StartAddr_type;
VARIABLE Burst_Length : NATURAL RANGE 0 TO 512 := 0;
VARIABLE Burst_Bits : NATURAL RANGE 0 TO 7 := 0;
VARIABLE Burst : Burst_Type;
VARIABLE WB : Write_Burst_Type;
VARIABLE Burst_Cnt : burst_counter;
VARIABLE command : command_type;
VARIABLE written : boolean := false;
VARIABLE chip_en : boolean := false;
VARIABLE cur_bank : natural range 0 to hi_bank;
VARIABLE ModeReg : std_logic_vector(12 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE Ref_Cnt : NATURAL RANGE 0 TO 8192 := 0;
VARIABLE next_ref : TIME;
VARIABLE BankString : STRING(8 DOWNTO 1) := " Bank-X ";
-- Functionality Results Variables
VARIABLE Violation : X01 := '0';
VARIABLE DataDriveOut : std_logic_vector(15 DOWNTO 0)
:= (OTHERS => 'Z');
VARIABLE DataDrive : OutWord;
VARIABLE DataDrive1 : OutWord;
VARIABLE DataDrive2 : OutWord;
VARIABLE DataDrive3 : OutWord;
VARIABLE DQML_reg0 : UX01;
VARIABLE DQML_reg1 : UX01;
VARIABLE DQML_reg2 : UX01;
VARIABLE DQMH_reg0 : UX01;
VARIABLE DQMH_reg1 : UX01;
VARIABLE DQMH_reg2 : UX01;
VARIABLE check_DQML_init : BOOLEAN := FALSE;
VARIABLE check_DQMH_init : BOOLEAN := FALSE;
VARIABLE command_nop_init: BOOLEAN := FALSE;
VARIABLE report_err : BOOLEAN := FALSE;
VARIABLE line : NATURAL := 0;
VARIABLE last_clk : TIME := 0 ns;
VARIABLE clk_per : TIME := 0 ns;
BEGIN
--------------------------------------------------------------------
-- Timing Check Section
--------------------------------------------------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => BAIn,
TestSignalName => "BA",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_BA_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_BA_CLK );
VitalSetupHoldCheck (
TestSignal => DQMLIn,
TestSignalName => "DQML",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_DQML_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_DQML_CLK );
VitalSetupHoldCheck (
TestSignal => DQMHIn,
TestSignalName => "DQMH",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_DQMH_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_DQMH_CLK );
VitalSetupHoldCheck (
TestSignal => DataIn,
TestSignalName => "Data",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_D0_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D0_CLK );
VitalSetupHoldCheck (
TestSignal => CKEIn,
TestSignalName => "CKE",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_CKE_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_CKE_CLK );
VitalSetupHoldCheck (
TestSignal => AddressIn,
TestSignalName => "Address",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_Address_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_Address_CLK );
VitalSetupHoldCheck (
TestSignal => WENegIn,
TestSignalName => "WENeg",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WENeg_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_WENeg_CLK );
VitalSetupHoldCheck (
TestSignal => RASNegIn,
TestSignalName => "RASNeg",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_RASNeg_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RASNeg_CLK );
VitalSetupHoldCheck (
TestSignal => CSNegIn,
TestSignalName => "CSNeg",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_CSNeg_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_CSNeg_CLK );
VitalSetupHoldCheck (
TestSignal => CASNegIn,
TestSignalName => "CASNeg",
RefSignal => CLKIn,
RefSignalName => "CLK",
SetupHigh => tsetup_DQ0_CLK,
SetupLow => tsetup_DQ0_CLK,
HoldHigh => thold_DQ0_CLK,
HoldLow => thold_DQ0_CLK,
CheckEnabled => chip_en,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_CASNeg_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_CASNeg_CLK );
VitalPeriodPulseCheck (
TestSignal => CLKIn,
TestSignalName => "CLK",
Period => tperiod_CLK_posedge,
PulseWidthLow => tpw_CLK_negedge,
PulseWidthHigh => tpw_CLK_posedge,
PeriodData => PD_CLK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_CLK,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE );
Violation := Pviol_CLK OR Tviol_BA_CLK OR Tviol_DQMH_CLK OR
Tviol_DQML_CLK OR Tviol_D0_CLK OR Tviol_CKE_CLK OR
Tviol_Address_CLK OR Tviol_WENeg_CLK OR
Tviol_RASNeg_CLK OR Tviol_CSNeg_CLK OR
Tviol_CASNeg_CLK;
ASSERT Violation = '0'
REPORT InstancePath & partID & ": simulation may be" &
" inaccurate due to timing violations"
SEVERITY SeverityMode;
END IF; -- Timing Check Section
--------------------------------------------------------------------
-- Functional Section
--------------------------------------------------------------------
IF (rising_edge(CLKIn)) THEN
CKEreg <= CKE_nwv;
IF (NOW > Next_Ref AND PoweredUp AND Ref_Cnt > 0) THEN
Ref_Cnt := Ref_Cnt - 1;
Next_Ref := NOW + tdevice_REF;
END IF;
IF CKEreg = '1' THEN
IF CSNegIn = '0' THEN
chip_en := true;
ELSE
chip_en := false;
END IF;
END IF;
END IF;
IF (rising_edge(CLKIn) AND CKEreg = '1' AND to_X01(CSNegIn) = '0') THEN
ASSERT (not(Is_X(DQMLIn)))
REPORT InstancePath & partID & ": Unusable value for DQML"
SEVERITY SeverityMode;
ASSERT (not(Is_X(DQMHIn)))
REPORT InstancePath & partID & ": Unusable value for DQMH"
SEVERITY SeverityMode;
ASSERT (not(Is_X(WENegIn)))
REPORT InstancePath & partID & ": Unusable value for WENeg"
SEVERITY SeverityMode;
ASSERT (not(Is_X(RASNegIn)))
REPORT InstancePath & partID & ": Unusable value for RASNeg"
SEVERITY SeverityMode;
ASSERT (not(Is_X(CASNegIn)))
REPORT InstancePath & partID & ": Unusable value for CASNeg"
SEVERITY SeverityMode;
-- Command Decode
IF ((RASNegIn = '1') AND (CASNegIn = '1') AND (WENegIn = '1')) THEN
command := nop;
ELSIF ((RASNegIn = '0') AND (CASNegIn = '1') AND (WENegIn = '1')) THEN
command := act;
ELSIF ((RASNegIn = '1') AND (CASNegIn = '0') AND (WENegIn = '1')) THEN
command := read;
ELSIF ((RASNegIn = '1') AND (CASNegIn = '0') AND (WENegIn = '0')) THEN
command := writ;
ELSIF ((RASNegIn = '1') AND (CASNegIn = '1') AND (WENegIn = '0')) THEN
command := bst;
ELSIF ((RASNegIn = '0') AND (CASNegIn = '1') AND (WENegIn = '0')) THEN
command := pre;
ELSIF ((RASNegIn = '0') AND (CASNegIn = '0') AND (WENegIn = '1')) THEN
command := ref;
ELSIF ((RASNegIn = '0') AND (CASNegIn = '0') AND (WENegIn = '0')) THEN
command := mrs;
END IF;
-- PowerUp Check
IF (NOT(PoweredUp) AND command /= nop) THEN
ASSERT false
REPORT InstancePath & partID & ": Incorrect power up. Command"
& " issued before power up complete."
SEVERITY SeverityMode;
END IF;
-- Bank Decode
CASE BAIn IS
WHEN "00" => cur_bank := 0; BankString := " Bank-0 ";
WHEN "01" => cur_bank := 1; BankString := " Bank-1 ";
WHEN "10" => cur_bank := 2; BankString := " Bank-2 ";
WHEN "11" => cur_bank := 3; BankString := " Bank-3 ";
WHEN others =>
ASSERT false
REPORT InstancePath & partID & ": Could not decode bank"
& " selection - results may be incorrect."
SEVERITY SeverityMode;
END CASE;
END IF;
-- The Big State Machine
IF (rising_edge(CLKIn) AND CKEreg = '1') THEN
ASSERT (not(Is_X(CSNegIn)))
REPORT InstancePath & partID & ": Unusable value for CSNeg"
SEVERITY SeverityMode;
IF (CSNegIn = '1') THEN
command := nop;
END IF;
-- DQM pipeline
DQML_reg2 := DQML_reg1;
DQML_reg1 := DQML_reg0;
DQML_reg0 := DQMLIn;
DQMH_reg2 := DQMH_reg1;
DQMH_reg1 := DQMH_reg0;
DQMH_reg0 := DQMHIn;
-- by default data drive is Z, might get over written in one
-- of the passes below
DataDrive := (OTHERS => 'Z');
banks : FOR bank IN 0 TO hi_bank LOOP
CASE statebank(bank) IS
WHEN pwron =>
IF NOT check_DQML_init THEN
ASSERT (DQMLIn = '1')
REPORT InstancePath & partID & BankString
&": DQML must be held high"
& " during initialization."
SEVERITY SeverityMode;
check_DQML_init := TRUE;
END IF;
IF NOT check_DQMH_init THEN
ASSERT (DQMHIn = '1')
REPORT InstancePath & partID & BankString
&": DQMH must be held high"
& " during initialization."
SEVERITY SeverityMode;
check_DQMH_init := TRUE;
END IF;
IF (PoweredUp = false) THEN
IF NOT command_nop_init THEN
ASSERT (command = nop)
REPORT InstancePath & partID & BankString
&": Only NOPs allowed"
& " during power up."
SEVERITY SeverityMode;
command_nop_init := TRUE;
END IF;
DataDrive := "ZZZZZZZZZZZZZZZZ";
ELSIF (command = pre) AND ((cur_bank = bank) OR
(AddressIn(10) = '1')) THEN
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
END IF;
WHEN precharge =>
IF cur_bank = bank THEN
-- It is only an error if this bank is selected
ASSERT (command = nop OR command = pre)
REPORT InstancePath & partID & BankString
&": Illegal command received"
& " during precharge."
SEVERITY SeverityMode;
END IF;
WHEN idle =>
IF (command = nop OR command = bst OR command = pre) OR
(cur_bank /= bank) THEN
null;
ELSIF (command = mrs) THEN
IF (statebank = idle & idle & idle & idle) THEN
ModeReg := AddressIn;
statebank <= mode_set & mode_set & mode_set & mode_set;
END IF;
ELSIF (command = ref) THEN
IF (statebank = idle & idle & idle & idle) THEN
IF (CKEIn = '1') THEN
IF (Ref_Cnt < 8192) THEN
Ref_Cnt := Ref_Cnt + 1;
END IF;
statebank(bank) <= auto_refresh, idle
AFTER tdevice_TRCAR;
ELSE
statebank(bank) <= self_refresh;
END IF;
END IF;
ELSIF (command = act) THEN
statebank(bank) <= bank_act;
ras_in(bank) <= '1', '0' AFTER 70 ns;
rct_in <= '1', '0' AFTER 1 ns;
rcdt_in(bank) <= '1', '0' AFTER 1 ns;
MemAddr(bank)(22 downto 10) := AddressIn; -- latch row addr
ELSE -- IF cur_bank = bank THEN
ASSERT false
REPORT InstancePath & partID & ": Illegal command"
& " received in idle state."
SEVERITY SeverityMode;
END IF;
WHEN mode_set =>
statebank <= idle & idle & idle & idle;
ASSERT (ModeReg(7) = '0' AND ModeReg(8) ='0')
REPORT InstancePath & partID & BankString
&": Illegal operating mode set."
SEVERITY SeverityMode;
ASSERT command = nop
REPORT InstancePath & partID & BankString
& ": Illegal command received during mode_set."
SEVERITY SeverityMode;
-- read burst length
IF (ModeReg(2 downto 0) = "000") THEN
Burst_Length := 1;
Burst_Bits := 0;
ELSIF (ModeReg(2 downto 0) = "001") THEN
Burst_Length := 2;
Burst_Bits := 1;
ELSIF (ModeReg(2 downto 0) = "010") THEN
Burst_Length := 4;
Burst_Bits := 2;
ELSIF (ModeReg(2 downto 0) = "011") THEN
Burst_Length := 8;
Burst_Bits := 3;
ELSIF (ModeReg(2 downto 0) = "111") THEN
Burst_Length := 512;
Burst_Bits := 7;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString
&": Invalid burst length specified."
SEVERITY SeverityMode;
END IF;
-- read burst type
IF (ModeReg(3) = '0') THEN
Burst := sequential;
ELSIF (ModeReg(3) = '1') THEN
Burst := interleave;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString
&": Invalid burst type specified."
SEVERITY SeverityMode;
END IF;
-- read CAS latency
IF (ModeReg(6 downto 4) = "010") THEN
CAS_Lat <= 2;
ELSIF (ModeReg(6 downto 4) = "011") THEN
CAS_Lat <= 3;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString &
": CAS Latency set incorrecty "
SEVERITY SeverityMode;
END IF;
-- read write burst mode
IF (ModeReg(9) = '0') THEN
WB := programmed;
ELSIF (ModeReg(9) = '1') THEN
WB := single;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString &
": Invalid burst type specified."
SEVERITY SeverityMode;
END IF;
WHEN auto_refresh =>
ASSERT command = nop
REPORT InstancePath & partID & BankString &
": Illegal command received during auto_refresh."
SEVERITY SeverityMode;
WHEN bank_act =>
IF (command = pre)AND((cur_bank = bank)OR(AddressIn(10) = '1'))
THEN
ASSERT ras_out(bank) = '1'
REPORT InstancePath & partID & BankString &
": precharge command"
& " does not meet tRAS time."
SEVERITY SeverityMode;
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
ELSIF (command = nop OR command = bst)OR(cur_bank /= bank) THEN
null;
ELSIF (command = read) THEN
ASSERT rcdt_out(bank) = '0'
REPORT InstancePath & partID & BankString &
": read command received too soon after active."
SEVERITY SeverityMode;
ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1'))
REPORT InstancePath & partID & BankString &
": AddressIn(10) = X"
& " during read command. Next state unknown."
SEVERITY SeverityMode;
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
DataDrive(7 downto 0) := (others => 'U');
IF MemData(Bank)(Location) > -2 THEN
DataDrive(7 downto 0) := (others => 'X');
END IF;
IF MemData(Bank)(Location) > -1 THEN
DataDrive(7 downto 0) :=
to_slv(MemData(Bank)(Location),8);
END IF;
DataDrive(15 downto 8) := (others => 'U');
IF MemData(Bank)(Location+1) > -2 THEN
DataDrive(15 downto 8) := (others => 'X');
END IF;
IF MemData(Bank)(Location+1) > -1 THEN
DataDrive(15 downto 8) :=
to_slv(MemData(Bank)(Location+1),8);
END IF;
Burst_Cnt(bank) := 1;
IF (AddressIn(10) = '0') THEN
statebank(bank) <= read;
ELSIF (AddressIn(10) = '1') THEN
statebank(bank) <= read_auto_pre;
END IF;
ELSIF (command = writ) THEN
ASSERT rcdt_out(bank) = '0'
REPORT InstancePath & partID & BankString &
": write command"
& " received too soon after active."
SEVERITY SeverityMode;
ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1'))
REPORT InstancePath & partID & BankString &
": AddressIn(10) = X"
& " during write command. Next state unknown."
SEVERITY SeverityMode;
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
IF (DQML_nwv = '0') THEN
MemData(Bank)(Location) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location) := to_nat(DataIn(7 downto 0));
END IF;
END IF;
IF (DQMH_nwv = '0') THEN
MemData(Bank)(Location+1) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location+1) :=
to_nat(DataIn(15 downto 8));
END IF;
END IF;
Burst_Cnt(bank) := 1;
wrt_in <= '1';
IF (AddressIn(10) = '0') THEN
statebank(bank) <= write;
ELSIF (AddressIn(10) = '1') THEN
statebank(bank) <= write_auto_pre;
END IF;
written := true;
ELSIF (cur_bank = bank) OR (command = mrs) THEN
ASSERT false
REPORT InstancePath & partID & BankString &
": Illegal command "
& "received in active state."
SEVERITY SeverityMode;
END IF;
WHEN write =>
IF (command = bst) THEN
statebank(bank) <= bank_act;
Burst_Cnt(bank) := 0;
ELSIF (command = read) THEN
IF (bank = cur_bank) THEN
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
DataDrive(7 downto 0) := (others => 'U');
IF MemData(Bank)(Location) > -2 THEN
DataDrive(7 downto 0) := (others => 'X');
END IF;
IF MemData(Bank)(Location) > -1 THEN
DataDrive(7 downto 0):=
to_slv(MemData(Bank)(Location),8);
END IF;
DataDrive(15 downto 8) := (others => 'U');
IF MemData(Bank)(Location+1) > -2 THEN
DataDrive(15 downto 8) := (others => 'X');
END IF;
IF MemData(Bank)(Location+1) > -1 THEN
DataDrive(15 downto 8):=
to_slv(MemData(Bank)(Location+1),8);
END IF;
Burst_Cnt(bank) := 1;
IF (AddressIn(10) = '0') THEN
statebank(bank) <= read;
ELSIF (AddressIn(10) = '1') THEN
statebank(bank) <= read_auto_pre;
END IF;
ELSE
statebank(bank) <= bank_act;
END IF;
ELSIF (command = writ) THEN
IF cur_bank = bank THEN
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
IF (DQML_nwv = '0') THEN
MemData(Bank)(Location) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location) :=
to_nat(DataIn(7 downto 0));
END IF;
END IF;
IF (DQMH_nwv = '0') THEN
MemData(Bank)(Location+1) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location+1) :=
to_nat(DataIn(15 downto 8));
END IF;
END IF;
Burst_Cnt(bank) := 1;
wrt_in <= '1';
IF (AddressIn(10) = '1') THEN
statebank(bank) <= write_auto_pre;
END IF;
ELSE
statebank(bank) <= bank_act;
END IF;
ELSIF (command = pre) AND ((cur_bank = bank) OR
(AddressIn(10) = '1')) THEN
ASSERT ras_out(bank) = '1'
REPORT InstancePath & partID & BankString &
": precharge command"
& " does not meet tRAS time."
SEVERITY SeverityMode;
IF ( clk_per < 15 ns) THEN
ASSERT (DQML_nwv = '1')
REPORT InstancePath & partID & BankString &
": DQML should be"
& " held high, data is lost."
SEVERITY SeverityMode;
ASSERT (DQMH_nwv = '1')
REPORT InstancePath & partID & BankString &
": DQMH should be"
& " held high, data is lost."
SEVERITY SeverityMode;
END IF;
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
ELSIF (command = nop) OR (cur_bank /= bank) THEN
IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN
statebank(bank) <= bank_act;
Burst_Cnt(bank) := 0;
ras_in(bank) <= '1';
ELSE
IF (Burst = sequential) THEN
Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
Burst_Length;
ELSE
Burst_Inc(bank) := intab(StartAddr(bank))
(Burst_Cnt(bank));
END IF;
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
IF (DQML_nwv = '0') THEN
MemData(Bank)(Location) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location) :=
to_nat(DataIn(7 downto 0));
END IF;
END IF;
IF (DQMH_nwv = '0') THEN
MemData(Bank)(Location+1) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location+1) :=
to_nat(DataIn(15 downto 8));
END IF;
END IF;
Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
wrt_in <= '1';
END IF;
ELSIF cur_bank = bank THEN
ASSERT false
REPORT InstancePath & partID & ": Illegal command"
& " received in write state."
SEVERITY SeverityMode;
END IF;
WHEN read =>
IF (command = bst) THEN
statebank(bank) <= bank_act;
Burst_Cnt(bank) := 0;
ELSIF (command = read) THEN
IF cur_bank = bank THEN
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
DataDrive(7 downto 0) := (others => 'U');
IF MemData(Bank)(Location) > -2 THEN
DataDrive(7 downto 0) := (others => 'X');
END IF;
IF MemData(Bank)(Location) > -1 THEN
DataDrive(7 downto 0) :=
to_slv(MemData(Bank)(Location),8);
END IF;
DataDrive(15 downto 8) := (others => 'U');
IF MemData(Bank)(Location+1) > -2 THEN
DataDrive(15 downto 8) := (others => 'X');
END IF;
IF MemData(Bank)(Location+1) > -1 THEN
DataDrive(15 downto 8) :=
to_slv(MemData(Bank)(Location+1),8);
END IF;
Burst_Cnt(bank) := 1;
IF (AddressIn(10) = '0') THEN
statebank(bank) <= read;
ELSIF (AddressIn(10) = '1') THEN
statebank(bank) <= read_auto_pre;
END IF;
ELSE
statebank(bank) <= bank_act;
END IF;
ELSIF (command = writ) THEN
IF cur_bank = bank THEN
ASSERT rcdt_out(bank) = '0'
REPORT InstancePath & partID & BankString &
": write command"
& " received too soon after active."
SEVERITY SeverityMode;
ASSERT ((AddressIn(10) = '0') OR (AddressIn(10) = '1'))
REPORT InstancePath & partID & BankString &
": AddressIn(10) = X"
& " during write command. Next state unknown."
SEVERITY SeverityMode;
MemAddr(bank)(9 downto 0) := (others => '0');
-- clr old addr
MemAddr(bank)(9 downto Burst_Bits+1) :=
AddressIn(8 downto Burst_Bits); --latch col addr
IF (Burst_Bits > 0) THEN
Burst_Inc(bank) :=
to_nat(AddressIn(Burst_Bits-1 downto 0));
END IF;
StartAddr(bank) := Burst_Inc(bank) mod 8;
BaseLoc(bank) := to_nat(MemAddr(bank));
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
IF (DQML_nwv = '0') THEN
MemData(Bank)(Location) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location) :=
to_nat(DataIn(7 downto 0));
END IF;
END IF;
IF (DQMH_nwv = '0') THEN
MemData(Bank)(Location+1) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location+1) :=
to_nat(DataIn(15 downto 8));
END IF;
END IF;
Burst_Cnt(bank) := 1;
wrt_in <= '1';
IF (AddressIn(10) = '0') THEN
statebank(bank) <= write;
ELSIF (AddressIn(10) = '1') THEN
statebank(bank) <= write_auto_pre;
END IF;
ELSE
statebank(bank) <= bank_act;
END IF;
ELSIF (command = pre) AND ((cur_bank = bank) OR
(AddressIn(10) = '1')) THEN
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
ASSERT ras_out(bank) = '1'
REPORT InstancePath & partID & BankString &
": precharge command"
& " does not meet tRAS time."
SEVERITY SeverityMode;
ELSIF (command = nop) OR (cur_bank /= bank) THEN
IF (Burst_Cnt(bank) = Burst_Length) THEN
statebank(bank) <= bank_act;
Burst_Cnt(bank) := 0;
ras_in(bank) <= '1';
ELSE
IF (Burst = sequential) THEN
Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
Burst_Length;
ELSE
Burst_Inc(bank) := intab(StartAddr(bank))
(Burst_Cnt(bank));
END IF;
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
DataDrive(7 downto 0) := (others => 'U');
IF MemData(Bank)(Location) > -2 THEN
DataDrive(7 downto 0) := (others => 'X');
END IF;
IF MemData(Bank)(Location) > -1 THEN
DataDrive(7 downto 0) :=
to_slv(MemData(Bank)(Location),8);
END IF;
DataDrive(15 downto 8) := (others => 'U');
IF MemData(Bank)(Location+1) > -2 THEN
DataDrive(15 downto 8) := (others => 'X');
END IF;
IF MemData(Bank)(Location+1) > -1 THEN
DataDrive(15 downto 8) :=
to_slv(MemData(Bank)(Location+1),8);
END IF;
Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
END IF;
ELSIF cur_bank = bank THEN
ASSERT false
REPORT InstancePath & partID & BankString &
": Illegal command"
& " received in read state."
SEVERITY SeverityMode;
END IF;
WHEN write_auto_pre =>
IF (command = nop) OR (cur_bank /= bank) THEN
IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
Burst_Cnt(bank) := 0;
ras_in(bank) <= '1';
ELSE
IF (Burst = sequential) THEN
Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
Burst_Length;
ELSE
Burst_Inc(bank) := intab(StartAddr(bank))
(Burst_Cnt(bank));
END IF;
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
IF (DQML_nwv = '0') THEN
MemData(Bank)(Location) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location) :=
to_nat(DataIn(7 downto 0));
END IF;
END IF;
IF (DQMH_nwv = '0') THEN
MemData(Bank)(Location+1) := -1;
IF Violation = '0' THEN
MemData(Bank)(Location+1) :=
to_nat(DataIn(15 downto 8));
END IF;
END IF;
Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
wrt_in <= '1';
END IF;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString &
": Illegal command"
& " received in write state."
SEVERITY SeverityMode;
END IF;
WHEN read_auto_pre =>
IF (command = nop) OR (cur_bank /= bank) THEN
IF (Burst_Cnt(bank) = Burst_Length) THEN
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
Burst_Cnt(bank) := 0;
ras_in(bank) <= '1';
ELSE
IF (Burst = sequential) THEN
Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
Burst_Length;
ELSE
Burst_Inc(bank) := intab(StartAddr(bank))
(Burst_Cnt(bank));
END IF;
Location := BaseLoc(bank) + 2*Burst_Inc(bank);
DataDrive(7 downto 0) := (others => 'U');
IF MemData(Bank)(Location) > -2 THEN
DataDrive(7 downto 0) := (others => 'X');
END IF;
IF MemData(Bank)(Location) > -1 THEN
DataDrive(7 downto 0) :=
to_slv(MemData(Bank)(Location),8);
END IF;
DataDrive(15 downto 8) := (others => 'U');
IF MemData(Bank)(Location+1) > -2 THEN
DataDrive(15 downto 8) := (others => 'X');
END IF;
IF MemData(Bank)(Location+1) > -1 THEN
DataDrive(15 downto 8) :=
to_slv(MemData(Bank)(Location+1),8);
END IF;
Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
END IF;
ELSIF (command = read) AND (cur_bank /= bank) THEN
statebank(bank) <= precharge, idle AFTER tdevice_TRP;
ELSE
ASSERT false
REPORT InstancePath & partID & BankString &
": Illegal command"
& " received in read state."
SEVERITY SeverityMode;
END IF;
WHEN others => null;
END CASE;
END LOOP banks;
-- Check Refresh Status
IF (written = true) THEN
ASSERT Ref_Cnt > 0
REPORT InstancePath & partID &
": memory not refreshed (by ref_cnt)"
SEVERITY SeverityMode;
END IF;
END IF;
-- Latency adjustments and DQM read masking
IF (rising_edge(CLKIn)) THEN
IF (rising_edge(CLKIn) AND CKEreg = '1') THEN
DataDrive3 := DataDrive2;
DataDrive2 := DataDrive1;
DataDrive1 := DataDrive;
END IF;
IF (DQML_reg1 = '0') THEN
IF (CAS_Lat = 3) THEN
DataDriveOut(7 downto 0) := DataDrive3(7 downto 0);
ELSE
DataDriveOut(7 downto 0) := DataDrive2(7 downto 0);
END IF;
ELSE
DataDriveOut(7 downto 0) := (others => 'Z');
END IF;
IF (DQMH_reg1 = '0') THEN
IF (CAS_Lat = 3) THEN
DataDriveOut(15 downto 8) := DataDrive3(15 downto 8);
ELSE
DataDriveOut(15 downto 8) := DataDrive2(15 downto 8);
END IF;
ELSE
DataDriveOut(15 downto 8) := (others => 'Z');
END IF;
END IF;
-- The Powering-down State Machine
IF (rising_edge(CLKIn) AND CKEreg = '1' AND CKEIn = '0') THEN
ASSERT (not(Is_X(CSNegIn)))
REPORT InstancePath & partID & ": Unusable value for CSNeg"
SEVERITY SeverityMode;
IF (CSNegIn = '1') THEN
command := nop;
END IF;
CASE statebank(cur_bank) IS
WHEN idle =>
IF (command = nop) THEN
statebank <= pwrdwn & pwrdwn & pwrdwn & pwrdwn;
ELSIF (command = ref) THEN
statebank <= self_refresh & self_refresh & self_refresh
& self_refresh;
END IF;
WHEN write =>
statebank(cur_bank) <= write_suspend;
WHEN read =>
statebank(cur_bank) <= read_suspend;
WHEN bank_act =>
IF (command = writ) THEN
statebank(cur_bank) <= write_suspend;
ELSIF (command = read) THEN
statebank(cur_bank) <= read_suspend;
ELSE
statebank(cur_bank) <= bank_act_pwrdwn;
END IF;
WHEN others => null;
END CASE;
END IF;
-- The Powering-up State Machine
IF (rising_edge(CLKIn) AND CKEreg = '0' AND CKEIn = '1') THEN
ASSERT (not(Is_X(CSNegIn)))
REPORT InstancePath & partID & ": Unusable value for CSNeg"
SEVERITY SeverityMode;
IF (CSNegIn = '1') THEN
command := nop;
END IF;
CASE statebank(cur_bank) IS
WHEN write_suspend =>
statebank(cur_bank) <= write;
WHEN read_suspend =>
statebank(cur_bank) <= read;
WHEN self_refresh =>
statebank <= idle & idle & idle & idle after tdevice_TRP;
Ref_Cnt := 8192;
ASSERT command = nop
REPORT InstancePath & partID & ": Illegal command received"
& " during self_refresh."
SEVERITY SeverityMode;
WHEN pwrdwn =>
statebank <= idle & idle & idle & idle;
WHEN bank_act_pwrdwn =>
statebank(cur_bank) <= bank_act;
WHEN others => null;
END CASE;
END IF;
-- Clock period
IF (rising_edge(CLKIn) AND CKEIn = '1') THEN
clk_per := now - last_clk;
last_clk := now;
END IF;
--------------------------------------------------------------------
-- File Read Section
--------------------------------------------------------------------
-------------------------------------------------------------------------------
-----mt48lc16m16a2 memory preload file format------
-----------------------------------
-------------------------------------------------------------------------------
-- / - comment
-- @abbbbbbb - <a> stands for memory file bank(from 0 to 3)
-- - <bbbbbbb> stands for adddress within file bank (from 0 to 2*depth-1)
-- dd - <dd> is byte to be written at MemData(a)(bbbbbbb++)
-- (bbbbbbb is incremented at every load)
-- only first 1-9 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
-------------------------------------------------------------------------------
IF PoweredUp'EVENT and PoweredUp and (mem_file_name /= "none") THEN
ind := 0;
WHILE (not ENDFILE (mem_file)) LOOP
READLINE (mem_file, buf);
line := line +1;
IF buf(1) = '#' THEN
NEXT;
ELSIF buf(1) = '@' THEN
file_bank := h(buf(2 to 2));
ind := h(buf(4 to 9));
ELSE
IF (file_bank) <= 3 AND ind<= (2*depth-1) THEN
MemData(file_bank)(ind) := h(buf(1 to 2));
ind := ind + 1;
ELSE
IF report_err = FALSE THEN
ASSERT FALSE
REPORT "Memory file: " & mem_file_name &
" Address range error at line: "&to_int_Str(line)
SEVERITY error;
report_err := TRUE;
END IF;
END IF;
END IF;
END LOOP;
END IF;
--------------------------------------------------------------------
-- Output Section
--------------------------------------------------------------------
D_zd <= DataDriveOut;
END PROCESS;
------------------------------------------------------------------------
-- Path Delay Process
------------------------------------------------------------------------
DataOutBlk : FOR i IN 15 DOWNTO 0 GENERATE
DataOut_Delay : PROCESS (D_zd(i))
VARIABLE D_GlitchData:VitalGlitchDataArrayType(15 Downto 0);
BEGIN
VitalPathDelay01Z (
OutSignal => DataOut(i),
OutSignalName => "Data",
OutTemp => D_zd(i),
Mode => OnEvent,
GlitchData => D_GlitchData(i),
Paths => (
1 => (InputChangeTime => CLKIn'LAST_EVENT,
PathDelay => tpd_CLK_DQ2,
PathCondition => CAS_Lat = 2),
2 => (InputChangeTime => CLKIn'LAST_EVENT,
PathDelay => tpd_CLK_DQ3,
PathCondition => CAS_Lat = 3)
)
);
END PROCESS;
END GENERATE;
END BLOCK;
END vhdl_behavioral;
| gpl-3.0 | 2a00f11cf8c1e41131a21e4f3e9af403 | 0.405537 | 4.717106 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/video_fpga/vhdl_source/s3e_clockgen.vhd | 5 | 4,287 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3e_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_shifted : out std_logic;
pix_clock : out std_logic; -- * 7/25 (14 MHz)
pix_clock_en: out std_logic;
pix_reset : out std_logic );
end s3e_clockgen;
architecture Gideon of s3e_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sysrst_cnt : integer range 0 to 63;
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal pix_clock_pre : std_logic;
signal pix_clock_ii : std_logic;
signal pix_clock_i : std_logic;
signal pixrst_cnt : integer range 0 to 63;
signal pix_reset_i : std_logic := '1';
signal pix_reset_p : std_logic := '1';
signal pixdiv : integer range 0 to 7;
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_270_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 2,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK270 => clk_270_pre,
CLKFX => pix_clock_pre,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_pix: BUFG port map (I => pix_clock_pre, O => pix_clock_ii);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_shft: BUFG port map (I => clk_270_pre, O => sys_shifted);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
pix_clock <= pix_clock_ii;
pix_clock_i <= pix_clock_ii;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
process(pix_clock_i, dcm1_locked)
begin
if rising_edge(pix_clock_i) then
if pixdiv = 0 then
pixdiv <= 4;
pix_clock_en <= '1';
else
pixdiv <= pixdiv - 1;
pix_clock_en <= '0';
end if;
if pixrst_cnt = 63 then
pix_reset_i <= '0';
else
pixrst_cnt <= pixrst_cnt + 1;
end if;
pix_reset_p <= pix_reset_i;
end if;
if dcm1_locked='0' then
pixrst_cnt <= 0;
pix_reset_i <= '1';
pix_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
pix_reset <= pix_reset_p;
end Gideon;
| gpl-3.0 | a4150040094f3a1a264d042783cbbfe0 | 0.483788 | 3.277523 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_sim/ulpi_phy_bfm.vhd | 10 | 10,740 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end ulpi_phy_bfm;
architecture gideon of ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : integer := 0;
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_nxt_d : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
type t_data8 is array(natural range <>) of std_logic_vector(7 downto 0);
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
signal irq_status : std_logic_vector(7 downto 0) := X"00";
signal func_select : std_logic_vector(7 downto 0) := X"00";
signal intf_control : std_logic_vector(7 downto 0) := X"00";
signal otg_control : std_logic_vector(7 downto 0) := X"00";
signal scratch : std_logic_vector(7 downto 0) := X"00";
signal power : std_logic := '0';
signal power_level : std_logic_vector(1 downto 0) := "00";
signal pid : std_logic_vector(3 downto 0) := X"F";
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
function to_std(a : boolean) return std_logic is
begin
if (a) then
return '1';
else
return '0';
end if;
end function;
begin
crc_sync <= '1' when (state = idle) else '0';
irq_status(3) <= to_std(status_in(3 downto 2) = "01");
irq_status(2) <= status_in(3);
irq_status(1) <= to_std(status_in(3 downto 2) = "11");
status_in(3 downto 2) <= power_level;
process(power)
begin
if power'event then
if power = '1' then
power_level <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
elsif power = '0' then
power_level <= transport "11",
"10" after 3 us,
"01" after 6 us,
"00" after 10 us;
else
power_level <= "00";
end if;
end if;
end process;
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
variable a : integer;
begin
a := to_integer(unsigned(addr));
case a is
when 4 =>
func_select <= data;
if data(4 downto 0) = "10000" then -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
elsif data(4 downto 3) ="00" then -- normal operation
status_in(1 downto 0) <= data(1 downto 0); -- for the time being
end if;
when 7 =>
intf_control <= data;
when 8 =>
intf_control <= intf_control or data;
when 9 =>
intf_control <= intf_control and not data;
when 10 =>
otg_control <= data;
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
power <= '1';
else -- power off
report "Power Off";
power <= '0';
end if;
when 22 =>
scratch <= data;
when 23 =>
scratch <= scratch or data;
when 24 =>
scratch <= scratch and not data;
when others =>
null;
end case;
end procedure;
variable receive_buffer : t_data8(0 to 127);
variable transmit_buffer : t_data8(0 to 127);
variable receive_length : integer := 0;
variable transmit_length : integer := 0;
procedure determine_response is
begin
if receive_buffer(0) = X"43" then -- data0 packet
transmit_buffer(0) := X"D2";
transmit_length := 1;
do_send <= '1';
end if;
end procedure;
impure function read_ulpi_register(addr: std_logic_vector(5 downto 0)) return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
variable a : integer;
begin
a := to_integer(unsigned(addr));
ret := X"00";
case a is
when 19 | 20 =>
ret := irq_status;
when 0 =>
ret := X"24";
when 1|2 =>
ret := X"04";
when 4|5|6 =>
ret := func_select;
when 7|8|9 =>
ret := intf_control;
when 10|11|12 =>
ret := otg_control;
when 22|23|24 =>
ret := scratch;
when others =>
null;
end case;
return ret;
end function;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
counter <= 0;
byte_count := transmit_length;
elsif ulpi_dir_i = '0' then
pid <= ULPI_DATA(3 downto 0);
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
receive_length := 0;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
address := ULPI_DATA(5 downto 0);
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= transmit_buffer(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
report "Received packet with length = " & integer'image(receive_length);
determine_response;
else
if (ulpi_nxt_i = '1') and (pid /= X"0") then
receive_buffer(receive_length) := ULPI_DATA;
receive_length := receive_length + 1;
end if;
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= read_ulpi_register(address);
state <= idle;
when others =>
state <= idle;
end case;
ulpi_nxt_d <= ulpi_nxt_i;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => ulpi_nxt_d,
data_in => ULPI_DATA,
crc => data_crc );
end gideon;
| gpl-3.0 | 82cc2a3268b69199bb444cc4a248a8b6 | 0.410428 | 4.439851 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/simple_sram.vhd | 5 | 5,597 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
| gpl-3.0 | 9966c11eddbb6f8470006e46d9fc97d2 | 0.471324 | 3.454938 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/io_bus_bfm.vhd | 5 | 1,888 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
| gpl-3.0 | 846f070fb3b21c26d7491db3b4000cf2 | 0.457097 | 4.122271 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_implied_hi.vhd | 5 | 2,448 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tb_implied_hi is
end tb_implied_hi;
architecture tb of tb_implied_hi is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal z_in : std_logic := 'Z';
signal d_in : std_logic := 'Z';
signal v_in : std_logic := 'Z';
signal reg_a : std_logic_vector(7 downto 0) := X"11";
signal reg_x : std_logic_vector(7 downto 0) := X"01";
signal reg_y : std_logic_vector(7 downto 0) := X"FF";
signal reg_s : std_logic_vector(7 downto 0) := X"44";
signal n_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal v_out : std_logic;
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal opcode : string(1 to 3);
type t_implied_opcode is array(0 to 15) of string(1 to 3);
constant implied_opcodes : t_implied_opcode := (
"DEY", "TAY", "INY", "INX",
"TXA", "TAX", "DEX", "NOP",
"TYA", "CLV", "CLD", "SED",
"TXS", "TSX", "---", "---" );
begin
mut: entity work.implied_hi
port map (
inst => inst,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => reg_a,
reg_x => reg_x,
reg_y => reg_y,
reg_s => reg_s,
n_out => n_out,
z_out => z_out,
d_out => d_out,
v_out => v_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => data_out );
test: process
variable inst_thumb : std_logic_vector(3 downto 0);
begin
for i in 0 to 15 loop
inst_thumb := conv_std_logic_vector(i, 4);
inst <= '1' & inst_thumb(1 downto 0) & inst_thumb(3) & "10" & inst_thumb(2) & '0';
opcode <= implied_opcodes(i);
wait for 1 us;
end loop;
wait;
end process;
end tb;
| gpl-3.0 | 35f7420eb8539869a5ba3613ec85ed3d | 0.443627 | 3.250996 | false | false | false | false |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_source/ext_mem_test_v5.vhd | 2 | 2,731 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v5 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_req_32;
resp : in t_mem_resp_32;
run : out std_logic;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_v5 is
signal req_i : t_mem_req_32;
signal expected_data : std_logic_vector(31 downto 0);
signal okay_i : std_logic;
signal run_i : std_logic;
function xor_reduce(s : std_logic_vector) return std_logic is
variable o : std_logic := '1';
begin
for i in s'range loop
o := o xor s(i);
end loop;
return o;
end function;
begin
req <= req_i;
okay <= okay_i;
run <= run_i;
p_test: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
req_i <= c_mem_req_32_init;
req_i.read_writen <= '0'; -- write
req_i.request <= '1';
req_i.size <= '1';
req_i.data <= X"12345678";
req_i.byte_en <= "1000";
req_i.tag <= X"34";
okay_i <= '1';
run_i <= '0';
else
if resp.rack='1' then
if req_i.read_writen = '1' then
if signed(req_i.address) = -4 then
req_i.data <= not req_i.data;
run_i <= not run_i;
end if;
req_i.address <= req_i.address + 4;
else
expected_data <= req_i.data;
end if;
req_i.read_writen <= not req_i.read_writen;
end if;
if resp.dack_tag = X"34" then
if resp.data /= expected_data then
okay_i <= not okay_i;
end if;
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 1e703870fe3af5a5b84179e76051cbfc | 0.393995 | 4.195084 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/dma_bus_arbiter_pri.vhd | 5 | 2,562 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to g_ports-1);
resps : out t_dma_resp_array(0 to g_ports-1);
req : out t_dma_req;
resp : in t_dma_resp );
end entity;
architecture rtl of dma_bus_arbiter_pri is
signal req_i : t_dma_req;
signal select_i : integer range 0 to g_ports-1;
signal select_c : integer range 0 to g_ports-1;
type t_state is (idle, busy_read, busy_write);
signal state : t_state;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_dma_req_init;
select_i <= 0;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
select_i <= i;
exit;
end if;
end loop;
end process;
p_access: process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
req <= req_i;
if req_i.request='1' then
select_c <= select_i;
if req_i.read_writen='0' then
state <= busy_write;
else
state <= busy_read;
end if;
end if;
when busy_read =>
if resp.rack='1' then
req.request <= '0';
end if;
if resp.dack='1' then
state <= idle;
end if;
when busy_write =>
if resp.rack='1' then
req.request <= '0';
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
-- send the reply to everyone, but mask the acks to non-active clients
process(resp, select_c)
begin
for i in resps'range loop
resps(i) <= resp;
if i /= select_c then
resps(i).rack <= '0';
resps(i).dack <= '0';
end if;
end loop;
end process;
end architecture;
| gpl-3.0 | b1d416ad3818336e049367aa72e4e20d | 0.429742 | 4.066667 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate3.vhd | 1 | 4,407 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate3.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate3 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altaccumulate3;
ARCHITECTURE SYN OF altaccumulate3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 8,
width_out => 32
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "1"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate3_inst.vhd TRUE
| gpl-2.0 | dbf4167d95f54bc707aacdfa733f34ea | 0.653279 | 3.779588 | false | false | false | false |
tirfil/VhdI2CSlave | testbenches/tb_i2cslave_write.vhd | 1 | 2,758 | --###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CSLAVE_WRITE is
end TB_I2CSLAVE_WRITE;
architecture stimulus of TB_I2CSLAVE_WRITE is
-- COMPONENTS --
component I2CSLAVE
generic( DEVICE: std_logic_vector(7 downto 0));
port(
MCLK : in std_logic;
nRST : in std_logic;
SDA_IN : in std_logic;
SCL_IN : in std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
ADDRESS : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
WR : out std_logic;
RD : out std_logic;
READ_DONE : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SDA_IN : std_logic;
signal SCL_IN : std_logic;
signal SDA_OUT : std_logic;
signal SCL_OUT : std_logic;
signal ADDRESS : std_logic_vector(7 downto 0);
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_IN : std_logic_vector(7 downto 0);
signal WR : std_logic;
signal RD : std_logic;
--
signal RUNNING : std_logic := '1';
begin
-- PORT MAP --
I_I2CSLAVE_0 : I2CSLAVE
generic map (DEVICE => x"38")
port map (
MCLK => MCLK,
nRST => nRST,
SDA_IN => SDA_IN,
SCL_IN => SCL_IN,
SDA_OUT => SDA_OUT,
SCL_OUT => SCL_OUT,
ADDRESS => ADDRESS,
DATA_OUT => DATA_OUT,
DATA_IN => DATA_IN,
WR => WR,
RD => RD,
READ_DONE => open
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
procedure SendData(data : in std_logic_vector(7 downto 0)) is
variable d : std_logic_vector(7 downto 0);
begin
d := data;
SCL_IN <= '0';
for i in 0 to 7 loop
SDA_IN <= d(7);
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
d(7 downto 1) := d(6 downto 0);
end loop;
SDA_IN <= '1';
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
end SendData;
begin
DATA_IN <= x"AA";
wait for 1 ns;
nRST <= '0';
SDA_IN <= '1';
SCL_IN <= '1';
wait for 1000 ns;
nRST <= '1';
SDA_IN <= '0'; -- start
wait for 80 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"55"); -- address
SendData(x"11");
SendData(x"22");
SendData(x"33");
SendData(x"44");
SDA_IN <= '0';
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SDA_IN <= '1'; -- stop
wait for 1000 ns;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
| gpl-3.0 | 10e6afe1acea31bc8112ec49338e61e6 | 0.554025 | 2.530275 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op986_1.vhdl | 1 | 4,599 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6026d8d821f0e5220ae88f591468461f | 0.582301 | 3.213836 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/RetinaParameters.vhd | 1 | 4,779 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package RetinaParameters is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
constant IMAGE_WIDTH: natural := 640;--640
constant IMAGE_HEIGHT: natural := 480;--480
constant PIXEL_BW : natural := 8;
constant KPT_COORD_BW : natural := 10;
constant KPT_SCALE_BW: natural := 6;
constant KPT_OCTAVE_BW: natural := 2;
--constant OFFSET_COORD_BW : natural := 8;
constant NUM_POINT_SET: natural := 6;
constant COORD_ROM_BW: natural := 2*NUM_POINT_SET;
constant S1_VERT_CONV_BW : natural := PIXEL_BW+1;
constant S2_VERT_CONV_BW : natural := S1_VERT_CONV_BW *2;
constant NUMBER_OF_SCALES: natural := 3;
constant NUMBER_OF_KERNELS: natural := NUMBER_OF_SCALES*7;-- equal to 7*NUMBER_OF_SCALES!!!!!
constant NKERNEL_BY_SCALES: natural := NUMBER_OF_KERNELS/2;
constant N_GAUSS_KERNEL_BW: natural := 6; --proporcional al NUMBER OF KERNELS!!!!!!!
constant GAUSSIAN_COE_BW : natural := 11;
constant SCALE_FACTOR_SH : natural := 10;
constant KERNEL_SIZE : natural := 9;--proporcional al numero de scalas!!!!!!
constant KERNEL_SIZE_ROM : natural := (KERNEL_SIZE-1)/2 +1;--equal to (KERNEL_SIZE-1)/2 +1
constant KERNEL_ROM_BW : natural := KERNEL_SIZE_ROM*GAUSSIAN_COE_BW;
constant S3_VERT_CONV_BW : natural := 20; --24 = log2((2^S2_VERT_CONV_BW -1)*KERNEL_SIZE_ROM)
constant OUT_VERT_CONV_BW : natural := S3_VERT_CONV_BW - SCALE_FACTOR_SH;
constant S1_HORIZ_CONV_BW : natural := OUT_VERT_CONV_BW+1;
constant S2_HORIZ_CONV_BW : natural := S1_HORIZ_CONV_BW *2;
constant S3_HORIZ_CONV_BW : natural := 24;--32 = log2((2^S2_HORIZ_CONV_BW -1)*KERNEL_SIZE_ROM)
constant OUT_HORIZ_CONV_BW : natural := S3_HORIZ_CONV_BW - SCALE_FACTOR_SH;
constant DESCRIPTOR_SIZE: natural := 512;
constant ADDR_MEM_BW: natural := 32;
constant N_POINTS: natural := 43;--total number of points in the retina pattern
--specific data types
--data types used in vertical convolution
type T_INPUT_VERTICAL_CONVOLUTION is array (KERNEL_SIZE-1 downto 0) of std_logic_vector(PIXEL_BW-1 downto 0);
type T_S1_VERT_CONV is array (KERNEL_SIZE_ROM-1 downto 0) of std_logic_vector(S1_VERT_CONV_BW-1 downto 0);
type T_S2_VERT_CONV is array (KERNEL_SIZE_ROM-1 downto 0) of std_logic_vector(S2_VERT_CONV_BW-1 downto 0);
--data types used in horizontal convolution
type T_INPUT_HORIZONTAL_CONVOLUTION is array (KERNEL_SIZE-1 downto 0) of std_logic_vector(OUT_VERT_CONV_BW-1 downto 0);
type T_S1_HORIZ_CONV is array (KERNEL_SIZE_ROM-1 downto 0) of std_logic_vector(S1_HORIZ_CONV_BW-1 downto 0);
type T_S2_HORIZ_CONV is array (KERNEL_SIZE_ROM-1 downto 0) of std_logic_vector(S2_HORIZ_CONV_BW-1 downto 0);
type kpt_coord_type is array (1 downto 0) of std_logic_vector(KPT_COORD_BW-1 downto 0);
type pt_params_type is array (2 downto 0) of std_logic_vector(7-1 downto 0);
type T_POINT_SET is array (N_POINTS-1 downto 0) of std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0);
type T_POINT_INDEX is array (15 downto 0) of std_logic_vector (5 downto 0);
type T_PAIR is array (1 downto 0) of integer range 0 to 42;
type T_ROM_PAIRS is array (DESCRIPTOR_SIZE-1 downto 0) of T_PAIR;
end RetinaParameters;
package body RetinaParameters is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end RetinaParameters;
| gpl-3.0 | 7d38e3c33ffff695dc4e42f644240976 | 0.673572 | 3.097213 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/master_handler.vhd | 3 | 14,865 | -------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generated : Wed Aug 3 14:09:02 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-08 V0.02 zelenkaj Added transfer qualifiers
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- 2011-12-23 V0.04 zelenkaj Fix write hanging
-- 2012-04-17 V0.05 zelenkaj Added forwarding of DMA read length
-- 2012-04-23 V0.06 zelenkaj Fix read length alignment
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= conv_std_logic_vector(conv_integer(tx_rd_cnt), m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if conv_integer(rx_rd_usedw) < rx_burst_size_c then
--start the smaller burst write transfer
m_burstcount_s <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if conv_integer(rx_rd_usedw) = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
| gpl-2.0 | 299980ddcd6feff0f27e039760d79744 | 0.593407 | 3.049231 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/cpu_wrapper_zpu.vhd | 3 | 6,543 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : boolean := true;
g_boot_rom : boolean := false;
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
break_o : out std_logic;
error : out std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end cpu_wrapper_zpu;
architecture logical of cpu_wrapper_zpu is
signal cpu_address : std_logic_vector(26 downto 0);
signal cpu_size : std_logic_vector(1 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_instr : std_logic;
signal cpu_req : std_logic;
signal cpu_rack : std_logic;
signal cpu_dack : std_logic;
signal ram_rack : std_logic := '0';
signal ram_dack : std_logic := '0';
signal ram_claimed : std_logic := '0';
signal ram_rdata : std_logic_vector(7 downto 0) := X"FF";
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal break_o_i : std_logic;
signal reset_cpu : std_logic;
type t_state is (idle, busy);
signal state : t_state;
type t_crash_state is (all_ok, flash_on, flash_off);
signal crash_state : t_crash_state := all_ok;
signal delay : integer range 0 to 8388607 := 0;
begin
break_o <= break_o_i;
core: entity work.zpu
generic map (
g_addr_size => cpu_address'length,
g_stack_size => 12,
g_prog_size => 20, -- Program size
g_dont_care => '-') -- Value used to fill the unused bits, can be '-' or '0'
port map (
clock => clock,
reset => reset_cpu,
interrupt_i => io_resp.irq,
break_o => break_o_i,
mem_address => cpu_address,
mem_instr => cpu_instr,
mem_size => cpu_size,
mem_req => cpu_req,
mem_write => cpu_write,
mem_rack => cpu_rack,
mem_dack => cpu_dack,
mem_wdata => cpu_wdata,
mem_rdata => cpu_rdata );
r_int_ram: if g_internal_prg generate
r_boot: if g_boot_rom generate
i_zpuram: entity work.mem32k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
r_noboot: if not g_boot_rom generate
i_zpuram: entity work.mem4k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
end generate;
cpu_rdata <= io_resp.data when io_resp.ack='1'
else mem_resp.data when mem_dack='1'
else ram_rdata;
cpu_rack <= io_resp.ack or mem_rack or ram_rack;
cpu_dack <= (io_resp.ack and not cpu_write) or mem_dack or ram_dack;
mem_req.request <= '1' when cpu_req='1' and cpu_address(26)='0' and ram_claimed='0'
else '0';
mem_req.tag <= g_mem_tag;
mem_req.address <= unsigned(cpu_address(25 downto 0));
mem_req.read_writen <= not cpu_write;
mem_req.data <= cpu_wdata;
mem_req.size <= "00"; -- to be optimized
mem_rack <= '1' when mem_resp.rack_tag = g_mem_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_mem_tag else '0';
io_req.address(19 downto 2) <= unsigned(cpu_address(19 downto 2));
with cpu_address(24) select
io_req.address( 1 downto 0) <=
unsigned(cpu_address(1 downto 0) xor cpu_size) when '0',
unsigned(cpu_address(1 downto 0)) when others;
io_req.data <= cpu_wdata;
p_io: process(clock)
begin
if rising_edge(clock) then
io_req.read <= '0';
io_req.write <= '0';
case state is
when idle =>
if cpu_req='1' and cpu_address(26)='1' then
io_req.read <= not cpu_write;
io_req.write <= cpu_write;
state <= busy;
end if;
when busy =>
if io_resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
p_crash: process(clock)
begin
if rising_edge(clock) then
case crash_state is
when all_ok =>
reset_cpu <= '0';
error <= '0';
delay <= 6_250_000;
if break_o_i='1' then
reset_cpu <= '1';
crash_state <= flash_on;
end if;
when flash_on =>
reset_cpu <= '1';
error <= '1';
if delay = 0 then
crash_state <= flash_off;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when flash_off =>
reset_cpu <= '1';
error <= '0';
if delay = 0 then
crash_state <= flash_on;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when others =>
crash_state <= flash_on;
end case;
if reset='1' then
error <= '0';
reset_cpu <= '1';
crash_state <= all_ok;
end if;
end if;
end process;
end logical;
| gpl-3.0 | 49dd971dfcc7961524e112508a0f2c84 | 0.48464 | 3.476621 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op974_5.vhdl | 1 | 4,520 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net4
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 7a78cc4f28d3b57de9a3365b2ae04e1f | 0.584071 | 3.214794 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op950_17.vhdl | 1 | 5,941 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net5
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net6
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net7
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net9
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net10,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net10
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 95c42fb7a2a2b805cfe31f955c4e3abe | 0.578017 | 3.125197 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/dpram.vhd | 5 | 3,149 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram : entity is "yes";
end entity;
architecture xilinx of dpram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | df8c4b09d26295c68c2598198ba4c55c | 0.413782 | 4.084306 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem.vhd | 1 | 5,578 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file testmem.vhd when simulating
-- the core, testmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY testmem IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END testmem;
ARCHITECTURE testmem_a OF testmem IS
-- synthesis translate_off
COMPONENT wrapped_testmem
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_testmem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 6,
c_addrb_width => 6,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 64,
c_read_depth_b => 64,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 64,
c_write_depth_b => 64,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_testmem
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END testmem_a;
| mit | df94c9e564fdd238493e6c95778533ae | 0.531015 | 3.950425 | false | true | false | false |
Charlesworth/Albot | Albot VHDL/AddDiv1.vhd | 1 | 1,704 | LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity bit_AddDiv1 is
port
(
denominator : out std_logic_vector(15 downto 0) := "0000000000110100";
out_bus : out std_logic_vector(15 downto 0);
in_Bus : in std_logic_vector(7 downto 0);
WindowEnable : in std_logic;
clk : in std_logic;
U_enable : std_logic;
TrainFlag: in std_logic;
aclr : in std_logic;
AccumulateSIGNAL: in std_logic;
CalculateSIGNAL: in std_logic;
last_row : in std_logic
);
end bit_AddDiv1;
architecture str_AddDiv1 of bit_AddDiv1 is
signal data_total : std_logic_vector (15 downto 0);
signal DT : integer;
signal add : integer;
begin
TRAINaccumulate: process(clk, TrainFlag, aclr, AccumulateSIGNAL,WindowEnable)
variable j : integer;
begin
DT <= to_integer(unsigned(in_Bus)); --transform in bus to integer
if (aclr = '1') then
DT <= 0;
add <= 0;
elsif (clk'event) and (clk='0') then
if (TrainFlag='1')and (AccumulateSIGNAL='1') and (WindowEnable ='1') then
add <= add + DT;
end if;
end if;
end process TRAINaccumulate;
TRAINcalculate: process(TrainFlag,CalculateSIGNAL) -- at end of training period do this, but only at start of a frame (and end of Vsync period)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
data_total <= std_logic_vector(to_unsigned(add, data_total'length)); --s <= std_logic_vector(to_unsigned(i,s'length));
out_bus <= data_total;
if (TrainFlag = '1')then
--here
end if;
end if;
end process TRAINcalculate;
end str_AddDiv1;
--to_integer(unsigned(current_state));
| gpl-2.0 | 6ed753f8689880b10cf6c242c0a9d62c | 0.669601 | 3.103825 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v5_tb.vhd | 3 | 4,342 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_tb is
end ext_mem_ctrl_v5_tb;
architecture tb of ext_mem_ctrl_v5_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_16_req;
signal resp : t_mem_burst_16_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal MEM_A : std_logic_vector(14 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clk_2x <= not clk_2x after 5 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => MEM_D );
SDRAM_A <= transport logic_A after 6 ns;
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_burst_16_req_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '1'; -- read
req.request <= '1';
while true loop
wait until clock='1';
if resp.ready='1' then
req.address <= req.address + 4;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Qd(0)='Z' then
MEM_D <= Qd after 3.6 ns;
else
MEM_D <= Qd after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
| gpl-3.0 | 2a642b9ed084a396f23f4e7bfa3881ec | 0.455781 | 3.762565 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/proc_interrupt.vhd | 3 | 2,441 | library ieee;
use ieee.std_logic_1164.all;
entity proc_interrupt is
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
nmi_n : in std_logic;
i_flag : in std_logic;
clear_b : out std_logic;
vect_bit : in std_logic;
interrupt : out std_logic;
vect_addr : out std_logic_vector(3 downto 0) );
end proc_interrupt;
architecture gideon of proc_interrupt is
signal irq_c : std_logic := '0';
signal nmi_c : std_logic := '0';
signal nmi_d : std_logic := '0';
signal nmi_act : std_logic := '0';
signal vect_h : std_logic_vector(1 downto 0) := "00";
type state_t is (idle, do_irq, do_nmi);
signal state : state_t;
begin
vect_addr <= '1' & vect_h & vect_bit;
interrupt <= irq_c or nmi_act;
process(clock)
begin
if rising_edge(clock) then
irq_c <= not (irq_n or i_flag);
nmi_c <= not nmi_n;
clear_b <= '0';
if clock_en='1' then
nmi_d <= nmi_c;
if nmi_d = '0' and nmi_c = '1' then -- edge
nmi_act <= '1';
end if;
case state is
when idle =>
vect_h <= "11"; -- FE/FF
if nmi_act = '1' then
vect_h <= "01"; -- FA/FB
state <= do_nmi;
elsif irq_c = '1' then
state <= do_irq;
clear_b <= '1';
end if;
when do_irq =>
if vect_bit='0' or irq_c='0' then
state <= idle;
end if;
when do_nmi =>
if vect_bit='0' then
nmi_act <= '0';
state <= idle;
end if;
when others =>
state <= idle;
end case;
end if;
if reset='1' then
vect_h <= "10"; -- FC/FD 1100
state <= do_nmi;
nmi_act <= '0';
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 5aca1a3ffae5b0f61d8b660e81839f98 | 0.373617 | 3.962662 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op956_8.vhdl | 1 | 5,686 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net6
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | abe3d9f18549598b700a09222a3d177b | 0.575097 | 3.103712 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/example_design/ROM_GAUSS_COE_exdes.vhd | 1 | 4,502 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_GAUSS_COE_exdes is
PORT (
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
end ROM_GAUSS_COE_exdes;
architecture xilinx of ROM_GAUSS_COE_exdes is
SIGNAL CLK_i : std_logic;
component ROM_GAUSS_COE is
PORT (
CLK : IN STD_LOGIC;
WE : IN STD_LOGIC;
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_GAUSS_COE
port map (
CLK => CLK_i,
WE => WE,
SPO => SPO,
A => A,
D => D
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
| gpl-3.0 | bebbf1fe6f87a67d0f9db9fc0b0d5748 | 0.541315 | 4.674974 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/mash_tb.vhd | 5 | 4,130 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mash_tb is
end mash_tb;
architecture tb of mash_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal dac_in : signed(11 downto 0);
signal dac_in_u : unsigned(11 downto 0);
signal dac_out : integer;
signal vc : real := 0.0;
signal min_out : integer := 10000;
signal max_out : integer := -10000;
constant R : real := 2200.0;
constant C : real := 0.00000001;
begin
clock <= not clock after 10 ns; -- 50 MHz
reset <= '1', '0' after 100 ns;
dac_in_u(dac_in_u'high) <= not dac_in(dac_in'high);
dac_in_u(dac_in_u'high-1 downto 0) <= unsigned(dac_in(dac_in'high-1 downto 0));
dac: entity work.mash
generic map (4, 12)
port map (
clock => clock,
reset => reset,
dac_in => dac_in_u,
dac_out => dac_out );
test:process
begin
dac_in <= X"000";
wait for 100 us;
for i in 0 to 9 loop
wait until clock='1';
dac_in <= X"7FF";
wait until clock='1';
dac_in <= X"800";
end loop;
dac_in <= X"001";
wait for 100 us;
dac_in <= X"002";
wait for 100 us;
dac_in <= X"003";
wait for 100 us;
dac_in <= X"011";
wait for 100 us;
dac_in <= X"022";
wait for 100 us;
dac_in <= X"033";
wait for 100 us;
dac_in <= X"100";
wait for 100 us;
dac_in <= X"200";
wait for 100 us;
dac_in <= X"400";
wait for 100 us;
dac_in <= X"7FF";
wait for 100 us;
dac_in <= X"800";
wait for 100 us;
dac_in <= X"C00";
wait for 100 us;
dac_in <= X"E00";
wait for 100 us;
dac_in <= X"F00";
wait for 100 us;
dac_in <= X"F80";
wait for 100 us;
dac_in <= X"FC0";
wait for 100 us;
dac_in <= X"FE0";
wait for 100 us;
dac_in <= X"FF0";
wait for 100 us;
dac_in <= X"FF8";
wait for 100 us;
dac_in <= X"FFC";
wait for 100 us;
dac_in <= X"FFE";
wait for 100 us;
dac_in <= X"FFF";
wait for 100 us;
-- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave)
for i in 0 to 400 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 5 us;
end loop;
-- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave)
for i in 0 to 1000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 2 us;
end loop;
-- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave)
for i in 0 to 2000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 1 us;
end loop;
dac_in <= X"000";
wait;
end process;
filter: process(clock)
variable v_dac : real;
variable i_r : real;
variable q_c : real;
begin
if rising_edge(clock) then
if dac_out > max_out then
max_out <= dac_out;
end if;
if dac_out < min_out then
min_out <= dac_out;
end if;
-- if dac_out='0' then
-- v_dac := 0.0;
-- else
-- v_dac := 3.3;
-- end if;
v_dac := real(dac_out);
i_r := (v_dac - vc) / R;
q_c := i_r * 20.0e-9; -- 20 ns;
vc <= vc + (q_c / C);
end if;
end process;
end tb;
| gpl-3.0 | f99dff941ed28028da6fb8538b3125e3 | 0.449637 | 3.491124 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_700a.vhd | 3 | 9,853 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_700a is
generic (
g_version : unsigned(7 downto 0) := X"F8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_700a;
architecture structural of ultimate_1541_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_analyzer => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | 91e9557259a22e5e5c6bd3a8ed1825e8 | 0.476606 | 3.377785 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/nano_cpu/vhdl_source/nano_cpu.vhd | 1 | 6,486 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal i_addr : unsigned(9 downto 0);
signal inst : std_logic_vector(15 downto 11) := (others => '0');
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z, c : boolean;
signal stack_top : std_logic_vector(i_addr'range);
signal push : std_logic;
signal pop : std_logic;
signal update_accu : std_logic;
signal update_flag : std_logic;
signal long_inst : std_logic;
type t_state is (fetch_inst, decode_inst, data_state, external_data);
signal state : t_state;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
c when c_br_c,
not c when c_br_nc,
true when c_br_always,
true when c_br_call,
false when others;
with state select ram_addr <=
std_logic_vector(i_addr) when fetch_inst,
ram_rdata(ram_addr'range) when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
ram_en <= '0' when (state = decode_inst) and (ram_rdata(c_store'range) = c_store) else not stall;
push <= '1' when (state = decode_inst) and (ram_rdata(c_br_call'range) = c_br_call) and (ram_rdata(c_branch'range) = c_branch) else '0';
pop <= '1' when (state = decode_inst) and (ram_rdata(c_return'range) = c_return) else '0';
with ram_rdata(inst'range) select long_inst <=
'1' when c_store,
'1' when c_load_ind,
'1' when c_store_ind,
'0' when others;
process(clock)
begin
if rising_edge(clock) then
if stall='0' then
io_addr <= unsigned(ram_rdata(io_addr'range));
update_accu <= '0';
update_flag <= '0';
end if;
io_write <= '0';
io_read <= '0';
ram_we <= '0';
case state is
when fetch_inst =>
i_addr <= i_addr + 1;
state <= decode_inst;
when decode_inst =>
state <= fetch_inst;
inst <= ram_rdata(inst'range);
update_accu <= ram_rdata(11);
update_flag <= not ram_rdata(15);
-- special instructions
if ram_rdata(c_in'range) = c_in then
io_read <= '1';
state <= external_data;
elsif ram_rdata(c_branch'range) = c_branch then
update_accu <= '0';
update_flag <= '0';
if branch_taken then
i_addr <= unsigned(ram_rdata(i_addr'range));
end if;
elsif ram_rdata(c_return'range) = c_return then
i_addr <= unsigned(stack_top);
update_accu <= '0';
update_flag <= '0';
elsif ram_rdata(c_out'range) = c_out then
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
state <= external_data;
end if;
-- not so special instructions: alu instructions!
else
if long_inst='1' then
state <= data_state;
end if;
if ram_rdata(c_store'range) = c_store then
ram_we <= '1';
end if;
if ram_rdata(c_store_ind'range) = c_store_ind then
ram_we <= '1';
end if;
end if;
when external_data =>
if stall = '0' then
update_accu <= '0';
update_flag <= '0';
state <= fetch_inst;
end if;
when data_state =>
if inst = c_load_ind then
update_accu <= '1';
update_flag <= '1';
end if;
state <= fetch_inst;
when others =>
state <= fetch_inst;
end case;
if reset='1' then
state <= fetch_inst;
i_addr <= (others => '0');
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => inst(14 downto 12),
update_accu => update_accu,
update_flag => update_flag,
accu => accu,
z => z,
n => n,
c => c );
i_stack : entity work.distributed_stack
generic map (
width => i_addr'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
| gpl-3.0 | c48e89327177f660113815f6ccc67e1f | 0.433087 | 4.061365 | false | false | false | false |
KB777/1541UltimateII | fpga/io/c2n_playback/vhdl_source/c2n_playback_io.vhd | 1 | 7,106 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity c2n_playback_io is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
c2n_motor : in std_logic;
c2n_sense : out std_logic;
c2n_out_r : out std_logic;
c2n_out_w : out std_logic );
end c2n_playback_io;
architecture gideon of c2n_playback_io is
signal enabled : std_logic;
signal sense : std_logic;
signal counter : unsigned(23 downto 0);
signal error : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal pulse : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 127;
signal stream_en : std_logic;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
signal mode : std_logic;
signal sel : std_logic_vector(1 downto 0);
signal c2n_out : std_logic;
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
begin
process(clock)
begin
if rising_edge(clock) then
-- c2n pin out and sync
stream_en <= enabled and c2n_motor;
if fifo_empty='1' and stream_en='1' then
error <= '1';
end if;
-- create a pulse of 50 ticks
if cnt2 = 0 then
pulse <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(3);
c2n_sense <= req.data(4);
sel <= req.data(7 downto 6);
end if;
elsif req.read='1' then
resp.ack <= '1';
resp.data <= status;
end if;
case state is
when idle =>
if stream_en='1' and fifo_empty='0' then
if fifo_dout=X"00" then
if mode='1' then
state <= multi1;
else
counter <= to_unsigned(256*8, counter'length);
state <= count_down;
end if;
else
counter <= unsigned("0000000000000" & fifo_dout & "000");
state <= count_down;
end if;
else
toggle <= '0';
end if;
when multi1 =>
if stream_en='1' and fifo_empty='0' then
counter(7 downto 0) <= unsigned(fifo_dout);
state <= multi2;
elsif enabled = '0' then
state <= idle;
end if;
when multi2 =>
if stream_en='1' and fifo_empty='0' then
counter(15 downto 8) <= unsigned(fifo_dout);
state <= multi3;
elsif enabled = '0' then
state <= idle;
end if;
when multi3 =>
if stream_en='1' and fifo_empty='0' then
counter(23 downto 16) <= unsigned(fifo_dout);
state <= count_down;
elsif enabled = '0' then
state <= idle;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' and c64_stopped='0' then
if (counter = 1) or (counter = 0) then
pulse <= '1';
toggle <= not toggle;
cnt2 <= 122;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then -- software disabled the device
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
pulse <= '0';
error <= '0';
mode <= '0';
sel <= "00";
c2n_sense <= '0';
end if;
end if;
end process;
fifo_write <= req.write and req.address(11); -- 0x800-0xFFF (2K)
fifo_read <= '0' when state = count_down else (stream_en and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => req.data,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= fifo_empty;
c2n_out <= not pulse;
with sel select c2n_out_r <=
c2n_out when "00",
pulse when "10",
'1' when others;
c2n_out_w <= pulse when sel="01" else '1';
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when count_down,
"11" when others;
end gideon;
| gpl-3.0 | 745a0c2f446540126866c984cb9e5f60 | 0.41275 | 4.267868 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_8bit_loadb.vhd | 5 | 33,125 | ------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit_loadb(Behave) (Entity and architecture) ----
---- File name: zpu_8bit_loadb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
--use work.tl_string_util_pkg.all;
entity zpu_8bit_loadb is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_size_o : out std_logic_vector(1 downto 0); -- indicates size of transfer 00=byte, 11=dword
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in std_logic_vector(c_opcode_width-1 downto 0);
c_data_o : out std_logic_vector(c_opcode_width-1 downto 0) );
end entity zpu_8bit_loadb;
architecture Behave of zpu_8bit_loadb is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or, st_compare, st_loadb2,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_pop_int, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb, dec_neqbranch,
dec_compare);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
-- helper signals for compare instructions
signal compare_dec : std_logic_vector(2 downto 0);
signal compare_oper : std_logic_vector(2 downto 0);
signal compare_bool : boolean;
signal compare_res : unsigned(31 downto 0);
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= unsigned(c_data_i);
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
c_inst_o <= not c_mux_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
compare_dec <= "000";
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
case opcode(5 downto 0) is
when OPCODE_LOADB =>
d_opcode <= dec_loadb;
when OPCODE_STOREB =>
d_opcode <= dec_storeb;
when OPCODE_NEQBRANCH =>
d_opcode <= dec_neqbranch;
when OPCODE_EQ =>
d_opcode <= dec_compare;
compare_dec <= "001";
when OPCODE_LESSTHAN => -- 00
d_opcode <= dec_compare;
compare_dec <= "100";
when OPCODE_LESSTHANOREQUAL => -- 01
d_opcode <= dec_compare;
compare_dec <= "101";
when OPCODE_ULESSTHAN => -- 10
d_opcode <= dec_compare;
compare_dec <= "110";
when OPCODE_ULESSTHANOREQUAL => -- 11
d_opcode <= dec_compare;
compare_dec <= "111";
when others =>
d_opcode <= dec_emulate;
end case;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when OPCODE_POPINT =>
d_opcode <= dec_pop_int;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
procedure emulate is
begin
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
end procedure;
procedure execute_def is
begin
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
end procedure;
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
compare_oper <= compare_dec;
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
execute_def;
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
emulate;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_pop_int =>
-- Pop(PC)
in_irq_r <= '0'; -- no longer in an interrupt
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_compare =>
-- Push(Compare(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_compare;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_loadb =>
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
state <= st_loadb2;
else
a_r <= (others => '0');
c_req_r <= '1';
c_mux_r <= '1';
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
c_size_o <= "00";
state <= st_read_mem;
end if;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);-- xor "11";
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
-- report "Load: " & hstr(a_i);
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
c_size_o <= "11";
state <= st_read_mem;
end if;
when dec_store =>
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
-- a=Pop(), b=Pop(), [a]=b
state <= st_write_mem;
byte_req_cnt <= "11"; -- 4 bytes
c_size_o <= "11";
end if;
when dec_storeb =>
if a_i(31) = '1' then
emulate;
else
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
c_size_o <= "00";
byte_req_cnt <= "00"; -- 1 byte
state <= st_write_mem;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when dec_neqbranch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
sp_r <= sp_r + 2;
-- Need to fetch stack again.
state <= st_resync;
if b_i/=0 then
pc_r <= pc_r + a_i(pc_r'range);
end if;
when others => -- includes 'nop'
null;
end case;
when st_loadb2 =>
-- select the correct stack byte
if a_en_r='0' then -- wait one cycle until BRAM data is available
a_r <= (others => '0');
case addr_r(1 downto 0) is
when "11" => a_r( 7 downto 0) <= a_i( 7 downto 0);
when "10" => a_r( 7 downto 0) <= a_i(15 downto 8);
when "01" => a_r( 7 downto 0) <= a_i(23 downto 16);
when "00" => a_r( 7 downto 0) <= a_i(31 downto 24);
when others => null;
end case;
-- report "LoadB: " & hstr(a_i) & ", addr: " & hstr(addr_r(1 downto 0));
-- a_r <= a_i; -- dummy
a_addr_r <= sp_r;
a_en_r <= '1';
a_we_r <= '1';
state <= st_fetch;
end if;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
-- when st_storeb =>
-- sp_r <= sp_r+1; -- for a store we need to pop 2!
-- a_we_r <= '1';
-- a_en_r <= '1';
-- a_addr_r <= a_i(g_stack_size-1 downto 2);
-- a_r <= b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0);
-- state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
-- report "Returning " & hstr(a_r(31 downto 8)) & hstr(c_data_i) &
-- " while reading from " & hstr(addr_r);
a_r(7 downto 0) <= unsigned(c_data_i);
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= unsigned(c_data_i);
when "10" =>
a_r(23 downto 16) <= unsigned(c_data_i);
when others => -- 11
a_r(31 downto 24) <= unsigned(c_data_i);
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_compare =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= compare_res;
state <= st_fetch;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
c_size_o <= "11";
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= std_logic_vector(b_i(7 downto 0));
when "01" =>
c_data_o <= std_logic_vector(b_i(15 downto 8));
when "10" =>
c_data_o <= std_logic_vector(b_i(23 downto 16));
when others => -- 11
c_data_o <= std_logic_vector(b_i(31 downto 24));
end case;
end process;
i_compare: entity work.zpu_compare
port map (
a => a_i,
b => b_i,
oper => compare_oper,
y => compare_bool );
compare_res <= X"00000001" when compare_bool else X"00000000";
end architecture Behave; -- Entity: zpu_8bit_loadb
| gpl-3.0 | acf8552761cb576f6d0f9238b6d20853 | 0.352875 | 4.301389 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/floppy_param_mem.vhd | 3 | 2,627 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Parameter memory
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity floppy_param_mem is
port (
clock : in std_logic;
reset : in std_logic;
cpu_write : in std_logic;
cpu_ram_en : in std_logic;
cpu_addr : in std_logic_vector(10 downto 0);
cpu_wdata : in std_logic_vector(7 downto 0);
cpu_rdata : out std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
bit_time : out unsigned(8 downto 0);
track_start : out std_logic_vector(25 downto 0);
max_offset : out std_logic_vector(13 downto 0) );
end floppy_param_mem;
architecture gideon of floppy_param_mem is
signal toggle : std_logic;
signal param_addr : std_logic_vector(8 downto 0);
signal param_data : std_logic_vector(31 downto 0);
begin
ram: RAMB16_S9_S36
port map (
CLKA => clock,
SSRA => reset,
ENA => cpu_ram_en,
WEA => cpu_write,
ADDRA => cpu_addr,
DIA => cpu_wdata,
DIPA => "0",
DOA => cpu_rdata,
DOPA => open,
CLKB => clock,
SSRB => reset,
ENB => '1',
WEB => '0',
ADDRB => param_addr,
DIB => X"00000000",
DIPB => X"0",
DOB => param_data,
DOPB => open );
param_addr <= '0' & track & toggle;
process(clock)
begin
if rising_edge(clock) then
if toggle='1' then -- even addresses (one clock later)
track_start <= param_data(track_start'range);
else
max_offset <= param_data(max_offset'range);
bit_time <= unsigned(param_data(bit_time'high+16 downto 16));
end if;
if reset='1' then
toggle <= '0';
else
toggle <= not toggle;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 85d190854ddbeb07502dba4b26919600 | 0.45984 | 3.909226 | false | false | false | false |
nick1au/Home-Sec-SYS | Alarm.vhd | 1 | 696 | Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity Alarm is
Port(Enable, clockin: IN std_logic;
Y1,Y2,Y3: out std_logic_vector(6 downto 0));
End Alarm;
Architecture structure of Alarm is
component PreScale is
generic (BIT_WIDTH : integer := 19);
Port(inclock: IN std_logic;
outclock: OUT std_logic);
End component;
signal clk, slt: std_logic;
begin
stage1: entity work.PreScale generic map (BIT_WIDTH=>6) port map (inclock => clockin, outclock => clk);
slt <= clk AND enable;
Y1 <= "0011000" when slt ='1' else (others => '1');
Y2 <= "1111001" when slt ='1' else (others => '1');
Y3 <= "1111001" when slt ='1' else (others => '1');
end structure;
| gpl-3.0 | 117a1d170f27e7c1aeaa90ce4acc3c62 | 0.672414 | 2.974359 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op950_15.vhdl | 1 | 5,001 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net5
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 363664ac9f4b4099ea1e638ad9186855 | 0.579484 | 3.171211 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op9.vhdl | 1 | 10,326 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.99e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.99e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_0,
W_0init => 2.25e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.99e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.99e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.035e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.65e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.035e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.65e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.035e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.65e-06,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.035e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.65e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 1.5e-06,
W => Wsrc_1,
Wsrc_1init => 1.665e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 2.666e-12,
symmetry_scope => sym_3
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 1.5e-06,
W => Wsrc_1,
Wsrc_1init => 1.665e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 2.77e-12,
symmetry_scope => sym_3
)
port map(
P => net4,
N => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 3.895e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.62e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 3.895e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.62e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 4.1e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 4.1e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_1,
W_1init => 8.3e-06
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.15e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 6.08e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.15e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 6.08e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 5.7e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 9e-07,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 5.7e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 9e-07,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.97e-05,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.97e-05,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 3.4e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 3.4e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 3.4e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 3.4e-06
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 3.4e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 3.4e-06
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | ff9b378ae909b6c3edc601162133053e | 0.566531 | 2.805978 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_logic.vhd | 3 | 34,603 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_logic is
generic (
g_version : unsigned(7 downto 0) := X"FF";
g_simulation : boolean := true;
g_clock_freq : natural := 50_000_000;
g_baud_rate : natural := 115_200;
g_timer_rate : natural := 200_000;
g_fpga_type : natural := 0;
g_boot_rom : boolean := false;
g_video_overlay : boolean := false;
g_icap : boolean := false;
g_uart : boolean := false;
g_drive_1541 : boolean := false;
g_drive_1541_2 : boolean := false;
g_hardware_gcr : boolean := false;
g_cartridge : boolean := false;
g_command_intf : boolean := false;
g_stereo_sid : boolean := false;
g_ram_expansion : boolean := false;
g_extended_reu : boolean := false;
g_hardware_iec : boolean := false;
g_iec_prog_tim : boolean := false;
g_c2n_streamer : boolean := false;
g_c2n_recorder : boolean := false;
g_drive_sound : boolean := false;
g_rtc_chip : boolean := false;
g_rtc_timer : boolean := false;
g_usb_host : boolean := false;
g_usb_host2 : boolean := false;
g_spi_flash : boolean := false;
g_vic_copper : boolean := false;
g_sampler : boolean := false;
g_analyzer : boolean := false );
port (
-- globals
sys_clock : in std_logic;
sys_reset : in std_logic;
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic := '1';
BUFFER_ENn : out std_logic := '1';
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
mem_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
-- actual levels of the pins --
iec_reset_i : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
iec_clock_i : in std_logic;
iec_srq_i : in std_logic;
iec_reset_o : out std_logic := '1';
iec_atn_o : out std_logic;
iec_data_o : out std_logic;
iec_clock_o : out std_logic;
iec_srq_o : out std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1) := "ZZ";
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Interface to other graphical output (Full HD of course and in 3D!) ;-)
vid_clock : in std_logic := '0';
vid_reset : in std_logic := '0';
vid_h_count : in unsigned(11 downto 0) := (others => '0');
vid_v_count : in unsigned(11 downto 0) := (others => '0');
vid_active : out std_logic;
vid_opaque : out std_logic;
vid_data : out unsigned(3 downto 0);
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
-- Buttons
button : in std_logic_vector(2 downto 0);
-- Simulation port
sim_io_req : in t_io_req := c_io_req_init;
sim_io_resp : out t_io_resp );
end ultimate_logic;
architecture logic of ultimate_logic is
function to_std(b : boolean) return std_logic is
begin
if b then
return '1';
end if;
return '0';
end function;
impure function create_capabilities return std_logic_vector is
variable cap : std_logic_vector(31 downto 0) := (others => '0');
begin
cap(00) := to_std(g_uart);
cap(01) := to_std(g_drive_1541);
cap(02) := to_std(g_drive_1541_2);
cap(03) := to_std(g_drive_sound);
cap(04) := to_std(g_hardware_gcr);
cap(05) := to_std(g_hardware_iec);
cap(06) := to_std(g_iec_prog_tim);
cap(07) := to_std(g_c2n_streamer);
cap(08) := to_std(g_c2n_recorder);
cap(09) := to_std(g_cartridge);
cap(10) := to_std(g_ram_expansion);
cap(11) := to_std(g_usb_host);
cap(12) := to_std(g_rtc_chip);
cap(13) := to_std(g_rtc_timer);
cap(14) := to_std(g_spi_flash);
cap(15) := to_std(g_icap);
cap(16) := to_std(g_extended_reu);
cap(17) := to_std(g_stereo_sid);
cap(18) := to_std(g_command_intf);
cap(19) := to_std(g_vic_copper);
cap(20) := to_std(g_video_overlay);
cap(21) := to_std(g_sampler);
cap(22) := to_std(g_analyzer);
cap(23) := to_std(g_usb_host2);
cap(29 downto 28) := std_logic_vector(to_unsigned(g_fpga_type, 2));
cap(30) := to_std(g_boot_rom);
cap(31) := to_std(g_simulation);
return cap;
end function;
constant c_capabilities : std_logic_vector(31 downto 0) := create_capabilities;
constant c_tag_1541_cpu_1 : std_logic_vector(7 downto 0) := X"01";
constant c_tag_1541_floppy_1 : std_logic_vector(7 downto 0) := X"02";
constant c_tag_1541_audio_1 : std_logic_vector(7 downto 0) := X"03";
constant c_tag_1541_cpu_2 : std_logic_vector(7 downto 0) := X"04";
constant c_tag_1541_floppy_2 : std_logic_vector(7 downto 0) := X"05";
constant c_tag_1541_audio_2 : std_logic_vector(7 downto 0) := X"06";
constant c_tag_cpu : std_logic_vector(7 downto 0) := X"07";
constant c_tag_slot : std_logic_vector(7 downto 0) := X"08";
constant c_tag_reu : std_logic_vector(7 downto 0) := X"09";
constant c_tag_usb2 : std_logic_vector(7 downto 0) := X"0A";
-- Memory interface
signal mem_req_cpu : t_mem_req := c_mem_req_init;
signal mem_resp_cpu : t_mem_resp := c_mem_resp_init;
signal mem_req_1541 : t_mem_req := c_mem_req_init;
signal mem_resp_1541 : t_mem_resp := c_mem_resp_init;
signal mem_req_1541_2 : t_mem_req := c_mem_req_init;
signal mem_resp_1541_2 : t_mem_resp := c_mem_resp_init;
signal mem_req_cart : t_mem_req := c_mem_req_init;
signal mem_resp_cart : t_mem_resp := c_mem_resp_init;
signal mem_req_debug : t_mem_req := c_mem_req_init;
signal mem_resp_debug : t_mem_resp := c_mem_resp_init;
signal mem_req_usb : t_mem_req := c_mem_req_init;
signal mem_resp_usb : t_mem_resp := c_mem_resp_init;
-- IO Bus
signal cpu_io_req : t_io_req;
signal cpu_io_resp : t_io_resp := c_io_resp_init;
signal io_req : t_io_req;
signal io_resp : t_io_resp := c_io_resp_init;
signal io_req_1541 : t_io_req;
signal io_resp_1541 : t_io_resp := c_io_resp_init;
signal io_req_1541_1 : t_io_req;
signal io_resp_1541_1 : t_io_resp := c_io_resp_init;
signal io_req_1541_2 : t_io_req;
signal io_resp_1541_2 : t_io_resp := c_io_resp_init;
signal io_req_itu : t_io_req;
signal io_resp_itu : t_io_resp := c_io_resp_init;
signal io_req_cart : t_io_req;
signal io_resp_cart : t_io_resp := c_io_resp_init;
signal io_req_io : t_io_req;
signal io_resp_io : t_io_resp := c_io_resp_init;
signal io_req_big_io : t_io_req;
signal io_resp_big_io : t_io_resp := c_io_resp_init;
signal io_req_sd : t_io_req;
signal io_resp_sd : t_io_resp := c_io_resp_init;
signal io_req_rtc : t_io_req;
signal io_resp_rtc : t_io_resp := c_io_resp_init;
signal io_req_rtc_tmr : t_io_req;
signal io_resp_rtc_tmr : t_io_resp := c_io_resp_init;
signal io_req_gcr_dec : t_io_req;
signal io_resp_gcr_dec : t_io_resp := c_io_resp_init;
signal io_req_flash : t_io_req;
signal io_resp_flash : t_io_resp := c_io_resp_init;
signal io_req_iec : t_io_req;
signal io_resp_iec : t_io_resp := c_io_resp_init;
signal io_req_usb : t_io_req;
signal io_resp_usb : t_io_resp := c_io_resp_init;
signal io_req_c2n : t_io_req;
signal io_resp_c2n : t_io_resp := c_io_resp_init;
signal io_req_c2n_rec : t_io_req;
signal io_resp_c2n_rec : t_io_resp := c_io_resp_init;
signal io_req_icap : t_io_req;
signal io_resp_icap : t_io_resp := c_io_resp_init;
signal io_req_aud_sel : t_io_req;
signal io_resp_aud_sel : t_io_resp := c_io_resp_init;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp := c_io_resp_init;
-- Audio routing
signal pwm : std_logic;
signal pwm_2 : std_logic := '0';
signal drive_sample : signed(12 downto 0);
signal drive_sample_2 : signed(12 downto 0);
-- IEC signal routing
signal atn_o, atn_i : std_logic := '1';
signal clk_o, clk_i : std_logic := '1';
signal data_o, data_i : std_logic := '1';
signal srq_i : std_logic := '1';
signal atn_o_2 : std_logic := '1';
signal clk_o_2 : std_logic := '1';
signal data_o_2 : std_logic := '1';
signal hw_atn_o : std_logic := '1';
signal hw_clk_o : std_logic := '1';
signal hw_data_o : std_logic := '1';
signal hw_srq_o : std_logic := '1';
-- miscellaneous interconnect
signal irq_i : std_logic := '0';
signal c64_irq_n : std_logic;
signal c64_irq : std_logic;
signal phi2_tick : std_logic;
signal c64_stopped : std_logic;
signal c2n_sense : std_logic := '0';
signal c2n_sense_in : std_logic := '0';
signal c2n_out_r : std_logic := '1';
signal c2n_out_w : std_logic := '1';
signal sd_busy : std_logic;
signal usb_busy : std_logic;
signal sd_act_stretched : std_logic;
signal error : std_logic;
signal act_led_n : std_logic := '1';
signal motor_led_n : std_logic := '1';
signal cart_led_n : std_logic := '1';
signal c2n_pull_sense : std_logic := '0';
signal freezer_state : std_logic_vector(1 downto 0);
signal dirty_led_1_n : std_logic := '1';
signal dirty_led_2_n : std_logic := '1';
signal sid_pwm_left : std_logic;
signal sid_pwm_right : std_logic;
signal samp_pwm_left : std_logic;
signal samp_pwm_right : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
begin
i_cpu: entity work.cpu_wrapper_zpu
generic map (
g_mem_tag => c_tag_cpu,
g_internal_prg => true,
g_boot_rom => g_boot_rom,
g_simulation => g_simulation )
port map (
clock => sys_clock,
reset => sys_reset,
break_o => open,
error => error,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
io_req => cpu_io_req,
io_resp => cpu_io_resp );
i_io_arb: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => sim_io_req,
reqs(1) => cpu_io_req,
resps(0) => sim_io_resp,
resps(1) => cpu_io_resp,
req => io_req,
resp => io_resp );
i_itu: entity work.itu
generic map (
g_version => g_version,
g_capabilities => c_capabilities,
g_uart => g_uart,
g_frequency => g_clock_freq,
g_edge_init => "00000001",
g_edge_write => false,
g_baudrate => g_baud_rate,
g_timer_rate => g_timer_rate)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_itu,
io_resp => io_resp_itu,
irq_in(7) => button(2),
irq_in(6) => button(1),
irq_in(5) => button(0),
irq_in(4) => c64_irq,
irq_in(3) => '0',
irq_in(2) => '0',
uart_txd => UART_TXD,
uart_rxd => UART_RXD );
r_drive: if g_drive_1541 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
-- master port on memory bus
mem_req => mem_req_1541,
mem_resp => mem_resp_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => act_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample,
dac_out => pwm );
end generate;
end generate;
r_drive_2: if g_drive_1541_2 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
-- master port on memory bus
mem_req => mem_req_1541_2,
mem_resp => mem_resp_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => open, --DISK_ACTn,
motor_led_n => open, --MOTOR_LEDn,
dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample_2'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample_2,
dac_out => pwm_2 );
end generate;
end generate;
r_cart: if g_cartridge generate
i_slot_srv: entity work.slot_server_v4
generic map (
g_tag_slot => c_tag_slot,
g_tag_reu => c_tag_reu,
g_ram_base_reu => X"1000000", -- should be on 16M boundary, or should be limited in size
g_rom_base_cart => X"0F00000", -- should be on a 1M boundary
g_ram_base_cart => X"0EF0000", -- should be on a 64K boundary
g_control_read => true,
g_ram_expansion => g_ram_expansion,
g_extended_reu => g_extended_reu,
g_command_intf => g_command_intf,
g_sampler => g_sampler,
g_implement_sid => g_stereo_sid,
g_sid_voices => 16,
g_vic_copper => g_vic_copper )
port map (
clock => sys_clock,
reset => sys_reset,
-- Cartridge pins
RSTn => RSTn,
IRQn => IRQn,
NMIn => NMIn,
PHI2 => PHI2,
IO1n => IO1n,
IO2n => IO2n,
DMAn => DMAn,
BA => BA,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
ADDRESS => SLOT_ADDR,
DATA => SLOT_DATA,
-- other hardware pins
BUFFER_ENn => BUFFER_ENn,
buttons => BUTTON,
cart_led_n => cart_led_n,
-- audio
sid_pwm_left => sid_pwm_left,
sid_pwm_right => sid_pwm_right,
samp_pwm_left => samp_pwm_left,
samp_pwm_right => samp_pwm_right,
-- debug
freezer_state => freezer_state,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
-- timing output
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
-- master on memory bus
memctrl_inhibit => mem_inhibit,
mem_req => mem_req_cart,
mem_resp => mem_resp_cart,
-- slave on io bus
io_req => io_req_cart,
io_resp => io_resp_cart );
end generate;
i_split1: entity work.io_bus_splitter
generic map (
g_range_lo => 17,
g_range_hi => 19,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_itu, -- 4000000 ( 16 ... 400000F)
reqs(1) => io_req_1541, -- 4020000 ( 8K... 4021FFF) & 4024000 for drive B
reqs(2) => io_req_cart, -- 4040000 (128K... 405FFFF)
reqs(3) => io_req_io, -- 4060000 ( 2K... 4060FFF)
reqs(4) => io_req_usb, -- 4080000 ( 8K... 4081FFF)
reqs(5) => io_req_c2n, -- 40A0000 ( 4K... 40A0FFF)
reqs(6) => io_req_c2n_rec, -- 40C0000 ( 4K... 40C0FFF)
reqs(7) => io_req_big_io, -- 40E0000 (128K... 40FFFFF)
resps(0) => io_resp_itu,
resps(1) => io_resp_1541,
resps(2) => io_resp_cart,
resps(3) => io_resp_io,
resps(4) => io_resp_usb,
resps(5) => io_resp_c2n,
resps(6) => io_resp_c2n_rec,
resps(7) => io_resp_big_io );
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 14,
g_range_hi => 15,
g_ports => 3 )
port map (
clock => sys_clock,
req => io_req_1541,
resp => io_resp_1541,
reqs(0) => io_req_1541_1, -- 4020000
reqs(1) => io_req_1541_2, -- 4024000
reqs(2) => io_req_iec, -- 4028000
resps(0) => io_resp_1541_1,
resps(1) => io_resp_1541_2,
resps(2) => io_resp_iec );
i_split3: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 11,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req_io,
resp => io_resp_io,
reqs(0) => io_req_sd, -- 4060000
reqs(1) => io_req_rtc, -- 4060100
reqs(2) => io_req_flash, -- 4060200
reqs(3) => io_req_debug, -- 4060300
reqs(4) => io_req_rtc_tmr, -- 4060400
reqs(5) => io_req_gcr_dec, -- 4060500
reqs(6) => io_req_icap, -- 4060600
reqs(7) => io_req_aud_sel, -- 4060700
resps(0) => io_resp_sd,
resps(1) => io_resp_rtc,
resps(2) => io_resp_flash,
resps(3) => io_resp_debug,
resps(4) => io_resp_rtc_tmr,
resps(5) => io_resp_gcr_dec,
resps(6) => io_resp_icap,
resps(7) => io_resp_aud_sel );
r_usb: if g_usb_host generate
i_usb: entity work.usb_host_io
generic map (
g_simulation => g_simulation )
port map (
ulpi_clock => ULPI_CLOCK,
ulpi_reset => ulpi_reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
usb_busy => usb_busy, -- LED interface
-- register interface bus
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb );
end generate;
r_usb2: if g_usb_host2 generate
i_usb: entity work.usb_controller
generic map (
g_tag => c_tag_usb2 )
port map (
ulpi_clock => ULPI_CLOCK,
ulpi_reset => ulpi_reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
usb_busy => usb_busy, -- LED interface
-- register interface bus
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => mem_req_usb,
sys_mem_resp=> mem_resp_usb,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb );
end generate;
i_sd: entity work.spi_peripheral_io
generic map (
g_fixed_rate => false,
g_init_rate => 500,
g_crc => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_sd,
io_resp => io_resp_sd,
busy => sd_busy,
SD_DETECTn => SD_CARDDETn,
SD_WRPROTn => '1', --SD_WRPROTn,
SPI_SSn => SD_SSn,
SPI_CLK => SD_CLK,
SPI_MOSI => SD_MOSI,
SPI_MISO => SD_MISO );
i_stretch: entity work.pulse_stretch
generic map ( g_clock_freq / 200) -- 5 ms
port map (
clock => sys_clock,
reset => sys_reset,
pulse_in => sd_busy,
pulse_out => sd_act_stretched );
r_spi_flash: if g_spi_flash generate
i_spi_flash: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 0,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_flash,
io_resp => io_resp_flash,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => FLASH_CSn,
SPI_CLK => FLASH_SCK,
SPI_MOSI => FLASH_MOSI,
SPI_MISO => FLASH_MISO );
end generate;
r_no_spi_flash: if not g_spi_flash generate
i_flash_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_flash,
io_resp => io_resp_flash );
end generate;
r_rtc: if g_rtc_chip generate
signal spi_ss_n : std_logic;
begin
i_spi_rtc: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 31,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rtc,
io_resp => io_resp_rtc,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => spi_ss_n,
SPI_CLK => RTC_SCK,
SPI_MOSI => RTC_MOSI,
SPI_MISO => RTC_MISO );
RTC_CS <= not spi_ss_n;
end generate;
r_no_rtc: if not g_rtc_chip generate
i_rtc_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc,
io_resp => io_resp_rtc );
end generate;
r_rtc_timer: if g_rtc_timer generate
i_rtc_timer: entity work.real_time_clock
generic map (
g_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_rtc_tmr,
resp => io_resp_rtc_tmr );
end generate;
r_no_rtc_timer: if not g_rtc_chip generate
i_rtc_timer_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc_tmr,
io_resp => io_resp_rtc_tmr );
end generate;
r_gcr_codec: if g_hardware_gcr generate
i_gcr_codec: entity work.gcr_codec
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_gcr_dec,
resp => io_resp_gcr_dec );
end generate;
r_iec: if g_hardware_iec generate
i_iec: entity work.iec_processor_io
port map (
clock => sys_clock,
reset => sys_reset,
atn_i => atn_i,
atn_o => hw_atn_o,
clk_i => clk_i,
clk_o => hw_clk_o,
data_i => data_i,
data_o => hw_data_o,
req => io_req_iec,
resp => io_resp_iec );
end generate;
r_c2n: if g_c2n_streamer generate
i_c2n: entity work.c2n_playback_io
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n,
resp => io_resp_c2n,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
c2n_sense => c2n_sense,
c2n_motor => CAS_MOTOR,
c2n_out_r => c2n_out_r,
c2n_out_w => c2n_out_w );
end generate;
r_c2n_rec: if g_c2n_recorder generate
i_c2n: entity work.c2n_record
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n_rec,
resp => io_resp_c2n_rec,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
pull_sense => c2n_pull_sense,
c2n_sense => c2n_sense_in,
c2n_motor => CAS_MOTOR,
c2n_write => CAS_WRITE,
c2n_read => CAS_READ );
end generate;
r_icap: if g_icap generate
i_icap: entity work.icap
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_icap,
io_resp => io_resp_icap );
end generate;
r_overlay: if g_video_overlay generate
i_overlay: entity work.char_generator_peripheral
generic map (
g_screen_size => 11,
g_color_ram => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_big_io, -- to be split later
io_resp => io_resp_big_io,
keyb_col => keyb_col,
keyb_row => keyb_row,
overlay_on => overlay_on,
pix_clock => vid_clock,
pix_reset => vid_reset,
h_count => vid_h_count,
v_count => vid_v_count,
pixel_active => vid_active,
pixel_opaque => vid_opaque,
pixel_data => vid_data );
end generate;
CAS_SENSE <= '0' when (c2n_sense='1') or (c2n_pull_sense='1') else 'Z';
CAS_READ <= '0' when c2n_out_r='0' else 'Z';
CAS_WRITE <= '0' when c2n_out_w='0' else 'Z';
-- CAS_READ <= trigger_1;
-- CAS_WRITE <= trigger_2;
c2n_sense_in <= '1' when CAS_SENSE='0' else '0';
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 6,
g_registered => false )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_cart,
reqs(1) => mem_req_1541,
reqs(2) => mem_req_1541_2,
reqs(3) => mem_req_usb,
reqs(4) => mem_req_debug,
reqs(5) => mem_req_cpu,
resps(0) => mem_resp_cart,
resps(1) => mem_resp_1541,
resps(2) => mem_resp_1541_2,
resps(3) => mem_resp_usb,
resps(4) => mem_resp_debug,
resps(5) => mem_resp_cpu,
req => mem_req,
resp => mem_resp );
i_aud_select: entity work.audio_select
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_aud_sel,
resp => io_resp_aud_sel,
drive0 => pwm,
drive1 => pwm_2,
cas_read => CAS_READ,
cas_write => CAS_WRITE,
sid_left => sid_pwm_left,
sid_right => sid_pwm_right,
samp_left => samp_pwm_left,
samp_right => samp_pwm_right,
pwm_out => PWM_OUT );
iec_atn_o <= '0' when atn_o='0' or atn_o_2='0' or hw_atn_o='0' else '1';
iec_clock_o <= '0' when clk_o='0' or clk_o_2='0' or hw_clk_o='0' else '1';
iec_data_o <= '0' when data_o='0' or data_o_2='0' or hw_data_o='0' else '1';
iec_srq_o <= hw_srq_o; -- only source
DISK_ACTn <= act_led_n xor error;
MOTOR_LEDn <= motor_led_n xor error;
CART_LEDn <= cart_led_n xor error;
SDACT_LEDn <= (dirty_led_1_n and dirty_led_2_n and not (sd_act_stretched or usb_busy)) xor error;
-- DISK_ACTn <= not freezer_state(1);
-- MOTOR_LEDn <= not freezer_state(0);
-- CART_LEDn <= IRQn;
-- SDACT_LEDn <= NMIn;
filt1: entity work.spike_filter generic map (10) port map(sys_clock, iec_atn_i, atn_i);
filt2: entity work.spike_filter generic map (10) port map(sys_clock, iec_clock_i, clk_i);
filt3: entity work.spike_filter generic map (10) port map(sys_clock, iec_data_i, data_i);
filt4: entity work.spike_filter generic map (10) port map(sys_clock, iec_srq_i, srq_i);
filt5: entity work.spike_filter port map(sys_clock, IRQn, c64_irq_n);
c64_irq <= not c64_irq_n;
-- dummy
SD_DATA <= "ZZ";
g_ela: if g_analyzer generate
signal ev_data : std_logic_vector(15 downto 0);
begin
i_ela: entity work.logic_analyzer
generic map (
g_timer_div => 50,
g_change_width => 16,
g_data_length => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
ev_dav => '0',
ev_data => ev_data,
---
mem_req => mem_req_debug,
mem_resp => mem_resp_debug,
io_req => io_req_debug,
io_resp => io_resp_debug );
ev_data <= srq_i & atn_i & data_i & clk_i & '1' & atn_o_2 & data_o_2 & clk_o_2 &
'0' & atn_o & data_o & clk_o & hw_srq_o & hw_atn_o & hw_data_o & hw_clk_o;
end generate;
end logic;
| gpl-3.0 | df055e39963c18ccbba315f0306a9864 | 0.462214 | 3.218584 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/VerticalConvolution.vhd | 1 | 4,536 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_6QjEG2
-- /___/ /\ Timestamp : 04/05/2014 20:58:04
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
entity VerticalConvolution is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
gaussianKernel : in std_logic_vector (KERNEL_ROM_BW-1 downto 0);
inputArray : in T_INPUT_VERTICAL_CONVOLUTION;
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_VERT_CONV_BW-1 downto 0)
);
end VerticalConvolution;
architecture BEHAVIORAL of VerticalConvolution is
signal s1_vert_conv_array: T_S1_VERT_CONV;
signal s1_vert_enable: std_logic;
signal s2_vert_conv_array: T_S2_VERT_CONV;
signal s2_vert_enable: std_logic;
signal s3_vert_conv: std_logic_vector(S3_VERT_CONV_BW-1 downto 0);
begin
filtrar: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s1_vert_conv_array <= (others =>(others => '0'));
s1_vert_enable <= '0';
s2_vert_conv_array <= (others =>(others => '0'));
s2_vert_enable <= '0';
s3_vert_conv <= (others => '0');
else
if enableIn = '1' then
--step 1
loop1: for i in 0 to (KERNEL_SIZE_ROM-1)-1 loop
s1_vert_conv_array(KERNEL_SIZE_ROM-1-i) <= std_logic_vector(resize(unsigned(inputArray(i))
+ unsigned(inputArray(KERNEL_SIZE-1-i)),
s1_vert_conv_array(0)'length)
);
end loop loop1;
s1_vert_conv_array(0) <= std_logic_vector(resize(unsigned(inputArray(KERNEL_SIZE_ROM-1)), s1_vert_conv_array(0)'length));
end if;
s1_vert_enable <= enableIn;
if s1_vert_enable = '1' then
--step 2
loop2: for j in 0 to (KERNEL_SIZE_ROM-1) loop
s2_vert_conv_array(j) <= std_logic_vector(resize(unsigned(s1_vert_conv_array(j)) *
unsigned(
gaussianKernel(
GAUSSIAN_COE_BW*(KERNEL_SIZE_ROM-j) -1
downto
GAUSSIAN_COE_BW*(KERNEL_SIZE_ROM -j) -GAUSSIAN_COE_BW
)
),
s2_vert_conv_array(0)'length));
end loop loop2;
end if;
s2_vert_enable <= s1_vert_enable;
if s2_vert_enable = '1' then
--step 3
s3_vert_conv <= std_logic_vector(resize(
((unsigned(s2_vert_conv_array(0)) + unsigned(s2_vert_conv_array(1)))+
(unsigned(s2_vert_conv_array(2)) + unsigned(s2_vert_conv_array(3))))+
(unsigned(s2_vert_conv_array(4)))--+
--(unsigned(s2_vert_conv_array(6)) + unsigned(s2_vert_conv_array(7))))+
--((unsigned(s2_vert_conv_array(8)) + unsigned(s2_vert_conv_array(9)))+
--(unsigned(s2_vert_conv_array(10)) + unsigned(s2_vert_conv_array(11))))+
--((unsigned(s2_vert_conv_array(12)) + unsigned(s2_vert_conv_array(13)))+
--(unsigned(s2_vert_conv_array(14))))
, s3_vert_conv'length));
end if;
enableOut <= s2_vert_enable;
end if;
end if;
end process filtrar;
outputData <= s3_vert_conv(S3_VERT_CONV_BW-1 downto SCALE_FACTOR_SH);
end BEHAVIORAL;
| gpl-3.0 | fcd930baf9dabe246e62927e0f5f1e49 | 0.573633 | 3.165387 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/simulation/vram_synth.vhd | 1 | 10,334 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: vram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY vram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE vram_synth_ARCH OF vram_synth IS
COMPONENT vram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: vram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| mit | 44c0e28155523cbf3066bcad76e3d307 | 0.55448 | 3.601952 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op3.vhdl | 1 | 9,359 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.6e-06,
W => Wdiff_0,
Wdiff_0init => 1.7e-06,
scope => private
)
port map(
D => net5,
G => in1,
S => net3
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.6e-06,
W => Wdiff_0,
Wdiff_0init => 1.7e-06,
scope => private
)
port map(
D => net4,
G => in2,
S => net3
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => W_0,
W_0init => 4.455e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_1,
Wcursrc_1init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_1,
Wcursrc_1init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 5e-06,
W => Wsrc_2,
Wsrc_2init => 7.085e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net1,
G => net4,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 5.7e-06,
W => Wsrc_2,
Wsrc_2init => 7.085e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net2,
G => net5,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcm_3,
Wcm_3init => 3.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcmout_3,
Wcmout_3init => 7.135e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_4,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net1
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcm_3,
Wcm_3init => 3.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 5e-07,
W => Wcmout_3,
Wcmout_3init => 7.135e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net2,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_5,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net2
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.375e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.375e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net8,
N => net6
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => W_1,
W_1init => 1.205e-05
)
port map(
D => net7,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.945e-05,
scope => private
)
port map(
D => net9,
G => vref,
S => net7
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.945e-05,
scope => private
)
port map(
D => net8,
G => net6,
S => net7
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.75e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.75e-06,
scope => private
)
port map(
D => net9,
G => net8,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9e-07,
W => Wcmbias_0,
Wcmbias_0init => 6.825e-05,
scope => private
)
port map(
D => out1,
G => net9,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9e-07,
W => Wcmbias_0,
Wcmbias_0init => 6.825e-05,
scope => private
)
port map(
D => out2,
G => net9,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.75e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.75e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.75e-05
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 8c03e76847f0448a06ed54849ecd0cf2 | 0.569185 | 2.85771 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/alu/alu.vhdl | 1 | 3,369 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.binary16.all;
entity alu is
port (i0, i1 : in binary16;
op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out binary16;
exception: out std_logic -- no semicolon here!
);
end alu;
architecture behv of alu is
procedure bitwise_and(
signal i0, i1: in binary16;
signal result: out binary16;
signal exception: out std_logic
) is
begin
result <= i0 and i1;
exception <= '0';
end;
begin
process(i0, i1, op)
-- process(clk)
variable i0t, i1t, ret: binary16;
variable exp0, exp1: std_logic_vector(4 downto 0);
variable tmp_compl: std_logic_vector(31 downto 0);
begin
exception <= '0';
case op is
-- Standard Logic
when "0000" =>
-- bitwise AND
bitwise_and(i0,i1,result,exception);
when "0001" =>
-- bitwise OR
result <= i0 or i1;
exception <= '0';
when "0010" =>
-- bitwise XOR
result <= i0 xor i1;
exception <= '0';
when "0011" =>
-- bitwise NOT
result <= not i0;
exception <= '0';
-- Arithmic on Complements of Integers
when "0100" =>
-- plus on complements
i0t := not(i0)+2;
i1t := not(i1)+2;
ret := i0t+i1t;
result <= not(ret)+2;
exception <= i0t(0) and i1t(0);
when "0101" =>
-- minus on complements
i0t := not(i0)+2;
i1t := not(i1)+2;
ret := i0t-i1t;
result <= not(ret)+2;
exception <= '0';
when "0110" =>
-- multiplication on complements
i0t := not(i0)+2;
i1t := not(i1)+2;
tmp_compl := i0t*i1t;
ret := tmp_compl(15 downto 0);
result <= not(ret)+2;
if ieee.std_logic_unsigned."="(tmp_compl(31 downto 16),"0000000000000000") then
exception <= '0';
else
exception <= '1';
end if;
-- Shift
when "1000" =>
-- shift left logic
result <= to_stdlogicvector(to_bitvector(i0) sll 1);
exception <= '0';
when "1001" =>
-- shift right logic
result <= to_stdlogicvector(to_bitvector(i0) srl 1);
exception <= '0';
when "1010" =>
-- shift left arithmic
result <= to_stdlogicvector(to_bitvector(i0) sla 1);
exception <= '0';
when "1011" =>
-- shift right arithmic
result <= to_stdlogicvector(to_bitvector(i0) sra 1);
exception <= '0';
when others =>
end case;
end process;
end behv;
| gpl-3.0 | e19e2dc007b91bc9d64e27326cbbe849 | 0.450282 | 4.078692 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/TopDescriptorMaker.vhd | 1 | 4,184 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_3coJ3K
-- /___/ /\ Timestamp : 04/06/2014 00:34:14
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity TopDescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end TopDescriptorMaker;
architecture BEHAVIORAL of TopDescriptorMaker is
signal sPointSet: T_POINT_SET;
signal sEnableOutPBuff: std_logic := '0';
signal addr: std_logic_vector(4 downto 0);
signal points1: T_POINT_INDEX;
signal points2: T_POINT_INDEX;
component ROM_PAIRS
port(
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
points1 : out T_POINT_INDEX;
points2 : out T_POINT_INDEX
);
end component;
component PointBuffer is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
pointSet : out T_POINT_SET
);
end component;
component DescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
pointIndexs1: in T_POINT_INDEX;
pointIndexs2: in T_POINT_INDEX;
enableInPointSet : in std_logic;
pointSet : in T_POINT_SET;
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end component;
begin
--mapping
rom: ROM_PAIRS
port map(
clk => clk,
addr => addr,
points1 => points1,
points2 => points2
);
pointBufferX: PointBuffer
port map( clk => clk,
enableIn => enableIn,
inputValue => inputValue,
rst => rst,
enableOut => sEnableOutPBuff,
pointSet => sPointSet
);
descripMakerX: DescriptorMaker
port map( clk => clk,
rst => rst,
pointIndexs1 => points1,
pointIndexs2 => points2,
enableInPointSet => sEnableOutPBuff,
pointSet => sPointSet,
descriptor => descriptor,
enableOut => enableOut
);
loadPointIndexes: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
addr <= (others => '0');
else
if sEnableOutPBuff = '1' then
addr <= "00001";
elsif addr = "11111" then
addr <= (others => '0');
else
addr <= std_logic_vector(resize(unsigned(addr)+1,addr'length));
end if;
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | d9a766c0469988931394427a5fbdc8bc | 0.575048 | 3.489575 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v7_tb.vhd | 5 | 10,543 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v7_tb is
end ext_mem_ctrl_v7_tb;
architecture tb of ext_mem_ctrl_v7_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 12 ns;
clk_2x <= not clk_2x after 6 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
p_test: process
procedure queue_req(rw : std_logic; bank : integer; row : integer; col : integer) is
begin
req.request <= '1';
req.read_writen <= rw;
req.address <= to_unsigned(bank*8192 + col*8 + row*32768, req.address'length);
wait for 2 ns;
while resp.ready='0' loop
wait until clock='1';
end loop;
wait until clock='1';
req.request <= '0';
end procedure;
begin
req.read_writen <= '1'; -- read
req.request <= '0';
req.address <= unsigned(to_signed(-32, req.address'length));
req.data_pop <= '0';
wait until reset='0';
wait until clock='1';
-- simple write / readback test
queue_req('0', 0, 0, 0);
queue_req('1', 0, 0, 0);
while true loop
-- read-read, other row, other bank
queue_req('1', 0, 16, 127);
queue_req('1', 1, 17, 0);
-- read-read, other row, same bank
queue_req('1', 1, 18, 1);
-- read-read, same row, other bank
queue_req('1', 2, 18, 2);
-- read-read, same row, same bank
queue_req('1', 2, 18, 3);
-- read-write, other row, other bank
queue_req('0', 0, 16, 4);
-- read-write, other row, same bank
queue_req('1', 0, 16, 127);
queue_req('0', 0, 17, 5);
-- read-write, same row, other bank
queue_req('1', 0, 18, 127);
queue_req('0', 1, 18, 6);
-- read-write, same row, same bank
queue_req('1', 2, 19, 127);
queue_req('0', 2, 19, 7);
-- write-read, other row, other bank
queue_req('1', 3, 20, 8);
-- write-read, other row, same bank
queue_req('0', 0, 16, 127);
queue_req('1', 0, 17, 9);
-- write-read, same row, other bank
queue_req('0', 1, 18, 127);
queue_req('1', 2, 18, 10);
-- write-read, same row, same bank
queue_req('0', 3, 19, 127);
queue_req('1', 3, 19, 11);
-- write-write, other row, other bank
queue_req('0', 0, 20, 127);
queue_req('0', 1, 21, 12);
-- write-write, other row, same bank
queue_req('0', 1, 22, 13);
-- write-write, same row, other bank
queue_req('0', 2, 22, 14);
-- write-write, same row, same bank
queue_req('0', 2, 22, 15);
-- read write toggle performance tests..
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 1, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 1, i);
end loop;
for i in 1 to 1000 loop
queue_req('1', 0, 0, i);
end loop;
end loop;
wait;
end process;
p_write: process(clock)
variable v_data : unsigned(31 downto 0) := X"DEAD4001";
begin
if rising_edge(clock) then
if resp.wdata_full='0' and reset='0' then
req.data_push <= '1';
req.data <= std_logic_vector(v_data);
req.byte_en <= "0111";
v_data := v_data + 1;
else
req.data_push <= '0';
end if;
end if;
end process;
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => SDRAM_BA(0),
BA1 => SDRAM_BA(1),
DQMH => dummy_dqm(1),
DQML => SDRAM_DQM,
DQ0 => SDRAM_DQ(0),
DQ1 => SDRAM_DQ(1),
DQ2 => SDRAM_DQ(2),
DQ3 => SDRAM_DQ(3),
DQ4 => SDRAM_DQ(4),
DQ5 => SDRAM_DQ(5),
DQ6 => SDRAM_DQ(6),
DQ7 => SDRAM_DQ(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A0 => SDRAM_A(0),
A1 => SDRAM_A(1),
A2 => SDRAM_A(2),
A3 => SDRAM_A(3),
A4 => SDRAM_A(4),
A5 => SDRAM_A(5),
A6 => SDRAM_A(6),
A7 => SDRAM_A(7),
A8 => SDRAM_A(8),
A9 => SDRAM_A(9),
A10 => SDRAM_A(10),
A11 => SDRAM_A(11),
A12 => SDRAM_A(12),
WENeg => SDRAM_WEn,
RASNeg => SDRAM_RASn,
CSNeg => SDRAM_CSn,
CASNeg => SDRAM_CASn );
end;
| gpl-3.0 | f04a1b6a3c10b450eead32922071eac5 | 0.41639 | 3.673519 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd | 2 | 12,848 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| gpl-2.0 | c09413d1bcbe8ec2c95d35dcf5e146a9 | 0.463263 | 3.860577 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd | 2 | 6,020 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with SD feature set
--
-- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture sd of chip is
component spi_boot
generic (
width_set_sel_g : integer := 4;
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
signal set_sel_s : std_logic_vector(3 downto 0);
begin
set_sel_s <= not set_sel_n_i;
spi_boot_b : spi_boot
generic map (
width_set_sel_g => 4, -- 16 sets
width_bit_cnt_g => 12, -- 512 bytes per block
width_img_cnt_g => 2, -- 4 images
num_bits_per_img_g => 18, -- 256 kByte per image
sd_init_g => 1, -- SD specific initialization
mmc_compat_clk_div_g => 0, -- no MMC compatibility
width_mmc_clk_div_g => 0 -- no MMC compatibility
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end sd;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: chip-sd-a.vhd,v $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:14 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:32 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | e2ad99d72b504659502b3e04bf77ffc8 | 0.538538 | 3.639661 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_250e.vhd | 4 | 9,654 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_250e is
generic (
g_simulation : boolean := false;
g_version : unsigned(7 downto 0) := X"F2" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(21 downto 0); -- 4M linear space
LB_DATA : inout std_logic_vector(7 downto 0);
FLASH_CSn : out std_logic;
SRAM_CSn : out std_logic;
MEM_WEn : out std_logic;
MEM_OEn : out std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USB
USB_IOP : inout std_logic;
USB_ION : inout std_logic;
USB_SEP : in std_logic;
USB_SEN : in std_logic;
USB_DET : inout std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_WP : in std_logic;
SD_CARDDETn : in std_logic;
-- 1-wire Interface
ONE_WIRE : inout std_logic;
-- Ethernet Interface
ETH_CLK : inout std_logic := '0';
ETH_IRQ : in std_logic := '0';
ETH_CSn : out std_logic;
ETH_CS : out std_logic;
ETH_RST : out std_logic;
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic;
CAS_READ : inout std_logic;
CAS_WRITE : inout std_logic;
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
-- attribute iob : string;
-- attribute iob of CAS_SENSE : signal is "false";
end ultimate_1541_250e;
architecture structural of ultimate_1541_250e is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => ETH_CLK );
i_logic: entity work.ultimate_logic
generic map (
g_fpga_type => 2,
g_version => g_version,
g_simulation => g_simulation,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => false,
g_uart => false,
g_drive_1541 => true, --
g_drive_1541_2 => false, --
g_hardware_gcr => true,
g_ram_expansion => true, --
g_hardware_iec => false, --
g_iec_prog_tim => false,
g_stereo_sid => false,
g_command_intf => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => true, --
g_drive_sound => false, --
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_spi_flash => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => sys_clock, -- just in case anything is connected
ulpi_reset => sys_reset, -- just in case anything is connected
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- RTC Interface
RTC_CS => open,
RTC_SCK => open,
RTC_MOSI => open,
RTC_MISO => '0',
-- Flash Interface
FLASH_CSn => open,
FLASH_SCK => open,
FLASH_MOSI => open,
FLASH_MISO => '0',
-- USB Interface (ULPI)
ULPI_NXT => '0',
ULPI_STP => open,
ULPI_DIR => '0',
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Unused
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4_u1
generic map (
g_simulation => g_simulation,
A_Width => LB_ADDR'length )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
ETH_CSn => ETH_CSn,
SRAM_CSn => SRAM_CSn,
FLASH_CSn => FLASH_CSn,
MEM_OEn => MEM_OEn,
MEM_WEn => MEM_WEn,
MEM_BEn => open,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
ETH_RST <= sys_reset;
ETH_CS <= '1'; --config.eth_enable; --'1'; -- addr 8/9
-- tie offs
SDRAM_DQM <= '0';
-- USB
USB_IOP <= USB_SEP;
USB_ION <= USB_SEN;
USB_DET <= 'Z';
ONE_WIRE <= 'Z';
end structural;
| gpl-3.0 | 28ab7800d64ca2fcb0ff74f45d4a0217 | 0.477626 | 3.311835 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op330_3.vhdl | 1 | 4,590 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 65d6ae4fbcc23150ff193e7a688d7aee | 0.58061 | 3.20307 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/alu.vhd | 2 | 4,855 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic;
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : std_logic_vector(7 downto 0) := X"FF";
signal oper4 : std_logic_vector(3 downto 0);
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
with oper4 select data_out_i <=
data_a or data_b when "1000",
data_a and data_b when "1001",
data_a xor data_b when "1010",
sum_result when "1011" | "1110" | "1111",
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
sum: process(data_a, data_b, c_in, operation, d_in)
variable b : std_logic_vector(7 downto 0);
variable sum_l : std_logic_vector(4 downto 0);
variable sum_h : std_logic_vector(4 downto 0);
begin
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := not data_b;
else
b := data_b;
end if;
-- sum_l(4) = carry of lower end, carry in is masked to '1' for CMP
sum_l := ('0' & data_a(3 downto 0)) + ('0' & b(3 downto 0)) + (c_in or not operation(0));
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4)) + sum_l(4);
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= sum_h(4);
sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
-- fix up in decimal mode (not for CMP!)
if d_in='1' and support_bcd then
if operation(2)='0' then -- ADC
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_l := sum_l + (sum_l(4) & X"6"); -- adding sum_l(4) another time, prevents
-- double fixup of high nibble.
end if;
-- negative when sum_h + sum_l(4) = 8
sum_h := sum_h + sum_l(4);
sum_n <= sum_h(3);
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" or
(sum_l(4)='1' and sum_h(3 downto 0)="1001") then -- >9 (10-11, 12-15)
sum_h := sum_h + 6;
end if;
-- carry and overflow are output after fix
sum_c <= sum_h(4);
-- sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
elsif operation(0)='1' then -- SBC
-- flags are not adjusted in subtract mode
if sum_l(4) = '0' then
sum_l := sum_l - 6;
end if;
if sum_h(4) = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
oper4 <= enable & operation;
with oper4 select c_out <=
sum_c when "1011" | "1111" | "1110",
c_in when others;
with oper4 select z_out <=
sum_z when "1011" | "1111" | "1110",
zero when "1000" | "1001" | "1010" | "1101",
z_in when others;
with oper4 select n_out <=
sum_n when "1011" | "1111",
data_out_i(7) when "1000" | "1001" | "1010" | "1101" | "1110",
n_in when others;
with oper4 select v_out <=
sum_v when "1011" | "1111",
v_in when others;
data_out <= data_out_i;
end gideon; | gpl-3.0 | 336222e1d5e8dddbc10c516ecff4acd7 | 0.443048 | 3.348276 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op326_4sk1_0.vhdl | 1 | 5,528 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.8e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.8e-06,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 2.635e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => net2,
G => vbias2,
S => net4
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.55e-06,
W => Wcm_1,
Wcm_1init => 8e-07,
scope => private
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.55e-06,
W => Wcmout_1,
Wcmout_1init => 7.36e-05,
scope => private
)
port map(
D => net5,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net5
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.55e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 43845e680b42c93e7bfae6df73c477df | 0.59081 | 3.019115 | false | false | false | false |
KB777/1541UltimateII | fpga/io/itu/vhdl_source/itu.vhd | 1 | 11,501 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.itu_pkg.all;
entity itu is
generic (
g_version : unsigned(7 downto 0) := X"FE";
g_uart : boolean := true;
g_frequency : integer := 50_000_000;
g_edge_init : std_logic_vector(7 downto 0) := "00000001";
g_capabilities : std_logic_vector(31 downto 0) := X"5555AAAA";
g_flags : std_logic_vector(7 downto 0) := "00000000";
g_edge_write : boolean := true;
g_baudrate : integer := 115_200;
g_timer_rate : integer := 200_000 ); -- 5µs (should not result in more than 8 bits div)
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq_out : out std_logic;
irq_timer_tick : in std_logic := '0';
irq_in : in std_logic_vector(7 downto 2);
irq_flags : out std_logic_vector(7 downto 0);
busy_led : out std_logic;
misc_io : out std_logic_vector(7 downto 0);
uart_txd : out std_logic;
uart_rxd : in std_logic := '1';
uart_rts : out std_logic;
uart_cts : in std_logic := '1' );
end itu;
architecture gideon of itu is
constant c_timer_div : integer := g_frequency / g_timer_rate;
constant c_baud_div : integer := g_frequency / g_baudrate;
constant c_ms_div : integer := g_timer_rate / 1000;
signal imask : std_logic_vector(7 downto 0);
signal iedge : std_logic_vector(7 downto 0) := g_edge_init;
signal timer : unsigned(7 downto 0);
signal timer_tick : std_logic;
signal timer_div : integer range 0 to c_timer_div - 1;
signal irq_timer_val : unsigned(15 downto 0);
signal irq_timer_cnt : unsigned(23 downto 0);
signal irq_timer_en : std_logic;
signal irq_timer_select : std_logic;
signal irq_en : std_logic;
signal irq_c : std_logic_vector(7 downto 0);
signal irq_d : std_logic_vector(7 downto 0);
signal irq_edge_flag : std_logic_vector(7 downto 0);
signal irq_active : std_logic_vector(7 downto 0);
signal uart_irq : std_logic;
signal io_req_it : t_io_req;
signal io_resp_it : t_io_resp;
signal io_req_uart : t_io_req;
signal io_resp_uart : t_io_resp;
signal io_req_ms : t_io_req;
signal io_resp_ms : t_io_resp;
signal ms_timer_presc : integer range 0 to c_ms_div-1 := 0;
signal ms_timer : unsigned(15 downto 0) := (others => '0');
signal usb_busy : std_logic;
signal sd_busy : std_logic;
begin
process(clock)
variable new_irq_edge_flag : std_logic_vector(irq_edge_flag'range);
begin
if rising_edge(clock) then
if timer_div = 0 then
timer_div <= c_timer_div - 1;
timer_tick <= '1';
else
timer_div <= timer_div - 1;
timer_tick <= '0';
end if;
if timer_tick='1' then
if timer /= X"00" then
timer <= timer - 1;
end if;
if ms_timer_presc = 0 then
ms_timer <= ms_timer + 1;
ms_timer_presc <= c_ms_div - 1;
else
ms_timer_presc <= ms_timer_presc - 1;
end if;
end if;
irq_c(7 downto 2) <= irq_in(7 downto 2);
irq_c(1) <= uart_irq;
irq_c(0) <= '0';
if irq_timer_en='1' then
if irq_timer_cnt = 0 then
irq_c(0) <= '1';
if irq_timer_select='1' then
irq_timer_cnt <= X"00" & irq_timer_val;
else
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
elsif irq_timer_select='0' or irq_timer_tick='1' then
irq_timer_cnt <= irq_timer_cnt - 1;
end if;
end if;
irq_d <= irq_c;
io_resp_it <= c_io_resp_init;
new_irq_edge_flag := irq_edge_flag;
if io_req_it.write='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
irq_en <= io_req_it.data(0);
when c_itu_irq_enable =>
imask <= imask or io_req_it.data;
when c_itu_irq_disable =>
imask <= imask and not io_req_it.data;
when c_itu_irq_edge =>
if g_edge_write then
iedge <= io_req_it.data;
end if;
when c_itu_irq_clear =>
new_irq_edge_flag := new_irq_edge_flag and not io_req_it.data;
when c_itu_timer =>
timer <= unsigned(io_req_it.data);
when c_itu_irq_timer_en =>
irq_timer_en <= io_req_it.data(0);
irq_timer_select <= io_req_it.data(1);
if irq_timer_en='0' then
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
when c_itu_irq_timer_lo =>
irq_timer_val(7 downto 0) <= unsigned(io_req_it.data);
when c_itu_irq_timer_hi =>
irq_timer_val(15 downto 8) <= unsigned(io_req_it.data);
when others =>
null;
end case;
elsif io_req_it.read='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
io_resp_it.data(0) <= irq_en;
when c_itu_irq_enable =>
io_resp_it.data <= imask;
when c_itu_irq_edge =>
io_resp_it.data <= iedge;
when c_itu_irq_active =>
io_resp_it.data <= irq_active;
when c_itu_timer =>
io_resp_it.data <= std_logic_vector(timer);
when c_itu_irq_timer_en =>
io_resp_it.data(0) <= irq_timer_en;
io_resp_it.data(1) <= irq_timer_select;
when c_itu_irq_timer_lo =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(7 downto 0));
when c_itu_irq_timer_hi =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(15 downto 8));
when c_itu_fpga_version =>
io_resp_it.data <= std_logic_vector(g_version);
when c_itu_capabilities0 =>
io_resp_it.data <= g_capabilities(31 downto 24);
when c_itu_capabilities1 =>
io_resp_it.data <= g_capabilities(23 downto 16);
when c_itu_capabilities2 =>
io_resp_it.data <= g_capabilities(15 downto 8);
when c_itu_capabilities3 =>
io_resp_it.data <= g_capabilities( 7 downto 0);
when c_itu_hw_flags =>
io_resp_it.data <= g_flags;
when others =>
null;
end case;
end if;
io_resp_ms <= c_io_resp_init;
if io_req_ms.write='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_usb_busy =>
usb_busy <= io_req_ms.data(0);
when c_itu_sd_busy =>
sd_busy <= io_req_ms.data(0);
when c_itu_misc_io =>
misc_io <= io_req_ms.data;
when others =>
null;
end case;
elsif io_req_ms.read='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_ms_timer_lo =>
io_resp_ms.data <= std_logic_vector(ms_timer(7 downto 0));
when c_itu_ms_timer_hi =>
io_resp_ms.data <= std_logic_vector(ms_timer(15 downto 8));
when others =>
null;
end case;
end if;
for i in 0 to 7 loop
if iedge(i)='1' then
if irq_c(i)='1' and irq_d(i)='0' then
new_irq_edge_flag(i) := '1';
end if;
end if;
end loop;
irq_edge_flag <= new_irq_edge_flag;
irq_out <= '0';
if irq_en = '1' then
if (irq_active and imask) /= X"00" then
irq_out <= '1';
end if;
end if;
if reset='1' then
irq_en <= '1';
imask <= (others => '0');
iedge <= g_edge_init;
irq_edge_flag <= (others => '0');
timer <= (others => '0');
irq_timer_en <= '0';
irq_timer_select <= '0';
irq_timer_val <= X"8000";
irq_timer_cnt <= (others => '0');
ms_timer <= (others => '0');
usb_busy <= '0';
sd_busy <= '0';
misc_io <= (others => '0');
end if;
end if;
end process;
irq_active <= irq_edge_flag or (irq_c and not iedge);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_it,
reqs(1) => io_req_uart,
reqs(2) => io_req_ms,
resps(0) => io_resp_it,
resps(1) => io_resp_uart,
resps(2) => io_resp_ms );
r_uart: if g_uart generate
uart: entity work.uart_peripheral_io
generic map (
g_divisor => c_baud_div )
port map (
clock => clock,
reset => reset,
io_req => io_req_uart,
io_resp => io_resp_uart,
irq => uart_irq,
rts => uart_rts,
cts => uart_cts,
txd => uart_txd,
rxd => uart_rxd );
end generate;
no_uart: if not g_uart generate
process(clock)
begin
if rising_edge(clock) then
io_resp_uart <= c_io_resp_init;
io_resp_uart.ack <= io_req_uart.read or io_req_uart.write;
end if;
end process;
end generate;
busy_led <= usb_busy or sd_busy;
irq_flags <= irq_active;
end architecture;
| gpl-3.0 | 21c2d257b6d69aea83c284861dd2aa68 | 0.424224 | 3.789456 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op324_4sk1_0.vhdl | 1 | 5,540 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.335e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.335e-05,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 7.45e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 3.595e-05,
scope => Wprivate
)
port map(
D => net2,
G => vbias3,
S => net4
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7e-06,
W => Wcm_1,
Wcm_1init => 8.9e-06,
scope => private
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7e-06,
W => Wcmout_1,
Wcmout_1init => 4.795e-05,
scope => private
)
port map(
D => net5,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 3.595e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net5
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.5e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 721aac1916ddb0fab92ee329df11a80c | 0.590253 | 2.999459 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_hardware_gcr.vhd | 5 | 3,010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tb_hardware_gcr is
end tb_hardware_gcr;
architecture tb of tb_hardware_gcr is
signal clock : std_logic := '0';
signal reset : std_logic;
signal cpu_clock_en: std_logic := '1';
signal cpu_addr : std_logic_vector(2 downto 0) := "000";
signal cpu_access : std_logic := '0';
signal cpu_write : std_logic := '0';
signal cpu_wdata : std_logic_vector(7 downto 0) := X"00";
signal cpu_rdata : std_logic_vector(7 downto 0) := X"00";
signal busy : std_logic;
signal mem_req : std_logic;
signal mem_ack : std_logic := '1';
signal mem_addr : std_logic_vector(23 downto 0);
signal mem_rwn : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
hw: entity work.hardware_gcr
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
cpu_addr => cpu_addr,
cpu_access => cpu_access,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
busy => busy,
---
mem_req => mem_req,
mem_ack => mem_ack,
mem_addr => mem_addr,
mem_rwn => mem_rwn,
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
process
procedure do_write(a: std_logic_vector(2 downto 0);
d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
cpu_access <= '1';
cpu_write <= '1';
cpu_addr <= a;
cpu_wdata <= d;
wait until clock='1';
cpu_access <= '0';
cpu_write <= '0';
for i in 0 to 9 loop
wait until clock='1';
end loop;
end procedure do_write;
begin
wait until reset='0';
do_write("000", X"56");
do_write("001", X"34");
do_write("010", X"12");
do_write("100", X"47");
do_write("100", X"47");
do_write("100", X"47");
do_write("100", X"47");
do_write("101", X"00");
do_write("101", X"00");
do_write("101", X"00");
do_write("101", X"00");
do_write("101", X"00");
do_write("101", X"00");
do_write("101", X"00");
do_write("100", X"47");
do_write("100", X"47");
do_write("100", X"47");
do_write("100", X"47");
wait;
end process;
end tb;
| gpl-3.0 | 4a78dfa43efb20de38927a5a9f622535 | 0.445183 | 3.635266 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op957_9.vhdl | 1 | 5,686 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net6
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fb0091e6c190e7a7d123da7d9fe92a37 | 0.575097 | 3.103712 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/phase_detector.vhd | 5 | 2,122 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phase_detector is
port (
n : in unsigned(11 downto 0);
pll_clock : in std_logic;
h_sync : in std_logic;
mute : in std_logic;
reference : out std_logic;
pulse_level : out std_logic;
pulse_enable: out std_logic;
up : out std_logic;
down : out std_logic;
analog : out std_logic );
end phase_detector;
architecture gideon of phase_detector is
signal div_count : unsigned(n'range) := (others => '0');
signal divided : std_logic;
signal h_latch : std_logic;
signal ref_latch : std_logic;
signal release : std_logic;
signal up_i : std_logic;
signal down_i : std_logic;
begin
reference <= divided;
process(pll_clock)
begin
if rising_edge(pll_clock) then
if div_count = 0 then
div_count <= n;
divided <= '1';
else
div_count <= div_count - 1;
if div_count = ('0' & n(11 downto 1)) then
divided <= '0';
end if;
end if;
end if;
end process;
process(h_sync, release)
begin
if release='1' then
h_latch <= '0';
elsif rising_edge(h_sync) then
h_latch <= '1';
end if;
end process;
process(divided, release)
begin
if release='1' then
ref_latch <= '0';
elsif rising_edge(divided) then
ref_latch <= '1';
end if;
end process;
up_i <= h_latch and not ref_latch;
down_i <= ref_latch and not h_latch;
release <= h_latch and ref_latch;
pulse_enable <= (up_i or down_i) and not mute;
pulse_level <= up_i;
analog <= '0' when (down_i='1' and up_i='0' and mute='0') else
'1' when (up_i='1' and down_i='0' and mute='0') else
'Z';
up <= up_i;
down <= down_i;
end gideon;
| gpl-3.0 | 1be42453590ead8fb5f6041495dfe313 | 0.485862 | 3.602716 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/freezer.vhd | 4 | 2,667 | library ieee;
use ieee.std_logic_1164.all;
entity freezer is
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
button_freeze : in std_logic;
cpu_cycle_done : in std_logic;
cpu_write : in std_logic;
freezer_state : out std_logic_vector(1 downto 0); -- debug
unfreeze : in std_logic; -- could be software driven, or automatic, depending on cartridge
freeze_trig : out std_logic;
freeze_act : out std_logic );
end freezer;
architecture gideon of freezer is
signal reset_in : std_logic;
signal wr_cnt : integer range 0 to 3;
signal do_freeze : std_logic;
signal do_freeze_d : std_logic;
type t_state is (idle, triggered, enter_freeze, button);
signal state : t_state;
begin
freeze_trig <= '1' when (state = triggered) else '0';
process(clock)
begin
if rising_edge(clock) then
do_freeze <= button_freeze;
do_freeze_d <= do_freeze;
reset_in <= reset or RST_in;
if cpu_cycle_done='1' then
if cpu_write='1' then
if wr_cnt/=3 then
wr_cnt <= wr_cnt + 1;
end if;
else
wr_cnt <= 0;
end if;
end if;
case state is
when idle =>
freeze_act <= '0';
if do_freeze_d='0' and do_freeze='1' then -- push
state <= triggered;
end if;
when triggered =>
if wr_cnt=3 then
state <= enter_freeze;
freeze_act <= '1';
end if;
when enter_freeze =>
if unfreeze='1' then
freeze_act <= '0';
state <= button;
end if;
when button =>
if do_freeze='0' then -- wait until button is not pressed anymore
state <= idle;
end if;
when others =>
state <= idle;
end case;
if reset_in='1' then
state <= idle;
wr_cnt <= 0;
end if;
end if;
end process;
with state select freezer_state <=
"00" when idle,
"01" when triggered,
"10" when enter_freeze,
"11" when button,
"00" when others;
end gideon;
| gpl-3.0 | 958935ff7996764cf3688cd3b9620b4d | 0.434946 | 4.336585 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/memory/memory_tb.vhdl | 1 | 1,952 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity memory_tb is
end memory_tb;
architecture behav of memory_tb is
component memory
port (
cs : in std_logic; -- Chip select
re, we : in std_logic; -- Read / Write Enable
clk : in std_logic;
addr_h, addr_l
: in std_logic_vector(4 downto 0);
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end component;
for memory_0: memory use entity work.memory;
signal cs : std_logic; -- Chip select
signal re, we : std_logic; -- Read / Write Enable
signal clk : std_logic;
signal addr_h, addr_l : std_logic_vector(4 downto 0);
signal data_in : std_logic_vector(15 downto 0);
signal data_out : std_logic_vector(15 downto 0);
begin
memory_0: memory port map (
cs => cs,
re => re,
we => we,
clk => clk,
addr_h => addr_h,
addr_l => addr_l,
data_in => data_in,
data_out => data_out
);
process
begin
cs<='1';
we<='1';
re<='0';
clk<='0';
addr_h<="00000";
addr_l<="11111";
data_in<="0101011010100101";
wait for 10 ms;
clk<='1';
wait for 10 ms;
we<='0';
cs<='1';
re<='1';
clk<='0';
addr_h<="00000";
addr_l<="11111";
data_in<="ZZZZZZZZZZZZZZZZ";
wait for 10 ms;
clk<='0';
clk<='1';
wait for 10 ms;
assert false report "have a nice day!" severity note;
wait;
end process;
end behav;
| gpl-3.0 | 452d2838a3951082f77590ac20ab243d | 0.464139 | 3.935484 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op13.vhdl | 1 | 11,715 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => W_0,
W_0init => 3.35e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 4.6e-06,
W => Wsrc_1,
Wsrc_1init => 2.87e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 2.9e-06,
W => Wsrc_1,
Wsrc_1init => 2.87e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.245e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 3.63e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => C_4,
C_4init => 2.257e-12,
symmetry_scope => sym_4
)
port map(
P => net5,
N => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.245e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 3.63e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet4_c1 : entity cap(behave)
generic map(
C => C_5,
C_5init => 2.958e-12,
symmetry_scope => sym_4
)
port map(
P => net6,
N => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.185e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.31e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_6,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net5
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.185e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.31e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_7,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net6
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.67e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.67e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net12,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net11,
N => net9
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => W_1,
W_1init => 4.285e-05
)
port map(
D => net10,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.105e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 4.57e-05,
scope => private
)
port map(
D => net12,
G => vref,
S => net10
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.105e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 4.57e-05,
scope => private
)
port map(
D => net11,
G => net9,
S => net10
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 4.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net11,
G => net11,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 4.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net12,
G => net11,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.6e-06,
W => Wcmbias_0,
Wcmbias_0init => 4.725e-05,
scope => private
)
port map(
D => out1,
G => net12,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.6e-06,
W => Wcmbias_0,
Wcmbias_0init => 4.725e-05,
scope => private
)
port map(
D => out2,
G => net12,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => (pfak)*(WBias),
WBiasinit => 4.45e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.3e-06,
W => (pfak)*(WBias),
WBiasinit => 4.45e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1605704bf5e988ac5bb2332171e487a2 | 0.563807 | 2.774751 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/io_bus_pkg.vhd | 3 | 1,416 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp is record
data : std_logic_vector(7 downto 0);
ack : std_logic;
irq : std_logic;
end record;
constant c_io_req_init : t_io_req := (
read => '0',
write => '0',
address => X"00000",
data => X"00" );
constant c_io_resp_init : t_io_resp := (
data => X"00",
irq => '0',
ack => '0' );
type t_io_req_array is array(natural range <>) of t_io_req;
type t_io_resp_array is array(natural range <>) of t_io_resp;
function or_reduce(ar: t_io_resp_array) return t_io_resp;
end package;
package body io_bus_pkg is
function or_reduce(ar: t_io_resp_array) return t_io_resp is
variable ret : t_io_resp;
begin
ret := c_io_resp_init;
for i in ar'range loop
ret.ack := ret.ack or ar(i).ack;
ret.irq := ret.irq or ar(i).irq;
ret.data := ret.data or ar(i).data;
end loop;
return ret;
end function or_reduce;
end package body;
| gpl-3.0 | 1cdebbd207e4ea3ac9cbcc5c51bf21e0 | 0.504944 | 3.36342 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_profiler.vhd | 5 | 4,692 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zpu_profiler is
port (
clock : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(26 downto 0);
cpu_instr : in std_logic;
cpu_req : in std_logic;
cpu_write : in std_logic;
cpu_rack : in std_logic;
cpu_dack : in std_logic;
enable : in std_logic;
clear : in std_logic;
section : in std_logic_vector(3 downto 0);
match : in std_logic_vector(3 downto 0);
my_read : in std_logic;
my_rack : out std_logic;
my_dack : out std_logic;
rdata : out std_logic_vector(7 downto 0) );
end zpu_profiler;
architecture gideon of zpu_profiler is
type t_count_array is array (natural range <>) of unsigned(31 downto 0);
signal counters : t_count_array(0 to 7) := (others => (others => '0'));
signal emulation_access : std_logic;
signal io_access : std_logic;
signal instruction_access : std_logic;
signal other_access : std_logic;
signal writes : std_logic;
signal req_d : std_logic;
signal count_out : std_logic_vector(31 downto 0) := (others => '0');
signal cpu_address_d : std_logic_vector(1 downto 0);
signal section_d : std_logic_vector(section'range);
signal section_entry : std_logic;
signal section_match : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
emulation_access <= '0';
io_access <= '0';
instruction_access <= '0';
other_access <= '0';
writes <= '0';
section_entry <= '0';
section_match <= '0';
-- first, split time in different "enables" for the counters
if cpu_rack='1' then
if cpu_address(26 downto 10) = "00000000000000000" then
emulation_access <= '1';
elsif cpu_address(26)='1' then
io_access <= '1';
elsif cpu_instr = '1' then
instruction_access <= '1';
else
other_access <= '1';
end if;
if cpu_write = '1' then
writes <= '1';
end if;
end if;
section_d <= section;
if section = match and section_d /= match then
section_entry <= '1';
end if;
if section = match then
section_match <= '1';
end if;
-- now, count our stuff
if clear='1' then
counters <= (others => (others => '0'));
elsif enable='1' then
counters(0) <= counters(0) + 1;
if emulation_access = '1' then
counters(1) <= counters(1) + 1;
end if;
if io_access = '1' then
counters(2) <= counters(2) + 1;
end if;
if instruction_access = '1' then
counters(3) <= counters(3) + 1;
end if;
if other_access = '1' then
counters(4) <= counters(4) + 1;
end if;
if writes = '1' then
counters(5) <= counters(5) + 1;
end if;
if section_entry='1' then
counters(6) <= counters(6) + 1;
end if;
if section_match = '1' then
counters(7) <= counters(7) + 1;
end if;
end if;
-- output register (read)
if my_read='1' then
if cpu_address(1 downto 0)="00" then
count_out <= std_logic_vector(counters(to_integer(unsigned(cpu_address(4 downto 2)))));
end if;
end if;
cpu_address_d <= cpu_address(1 downto 0);
case cpu_address_d is
when "00" => rdata <= count_out(31 downto 24);
when "01" => rdata <= count_out(23 downto 16);
when "10" => rdata <= count_out(15 downto 8);
when others => rdata <= count_out(7 downto 0);
end case;
req_d <= my_read;
my_dack <= req_d;
end if;
end process;
my_rack <= my_read;
end gideon; | gpl-3.0 | dc54d20c9bdd1aa8dc531e1e7dec515e | 0.442882 | 4.133921 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_13sk1_0.vhdl | 1 | 7,020 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.215e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.215e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => W_0,
W_0init => 2.22e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 5.2e-06,
W => Wcm_2,
Wcm_2init => 1.35e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 5.2e-06,
W => Wcmcout_2,
Wcmcout_2init => 6.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 5.2e-06,
W => Wcm_2,
Wcm_2init => 1.35e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 5.2e-06,
W => Wcmcout_2,
Wcmcout_2init => 6.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 2.775e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.1e-06,
W => Wcm_1,
Wcm_1init => 4.01e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.1e-06,
W => Wcmout_1,
Wcmout_1init => 3.145e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 2.775e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => (pfak)*(WBias),
WBiasinit => 1.38e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.25e-06,
W => (pfak)*(WBias),
WBiasinit => 1.38e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.25e-06,
W => WBias,
WBiasinit => 1.38e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => WBias,
WBiasinit => 1.38e-05
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => WBias,
WBiasinit => 1.38e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.25e-06,
W => WBias,
WBiasinit => 1.38e-05
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | d488db333b91ff697eb8578098bc23aa | 0.583761 | 2.916494 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_10sk1_0.vhdl | 1 | 7,982 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.35e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.35e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => W_0,
W_0init => 7.525e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.35e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.35e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.52e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.52e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.52e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.52e-05,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.03e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.03e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.74e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.3e-06,
W => Wcm_1,
Wcm_1init => 3.71e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.3e-06,
W => Wcmout_1,
Wcmout_1init => 3.535e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.74e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => (pfak)*(WBias),
WBiasinit => 1.1e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.35e-06,
W => (pfak)*(WBias),
WBiasinit => 1.1e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.35e-06,
W => WBias,
WBiasinit => 1.1e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => WBias,
WBiasinit => 1.1e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => WBias,
WBiasinit => 1.1e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.35e-06,
W => WBias,
WBiasinit => 1.1e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | ca1393fe37d00327a5ea06c0d2fad5ee | 0.581433 | 2.858883 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/uart_peripheral.vhd | 5 | 4,651 | library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
| gpl-3.0 | 9cd0d7ab2725192d2b8e6717ee3060b3 | 0.508493 | 3.358123 | false | false | false | false |
daringer/schemmaker | testdata/circuit_op324_0.vhdl | 1 | 2,225 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opamp is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical);
end opamp;
architecture simple of opamp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
terminal net1: electrical;
terminal net4: electrical;
begin
subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff,
W => Wdiff,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff,
W => Wdiff,
scope => private
)
port map(
D => out1,
G => in2,
S => net4
);
subnet0_m3 : entity pmos(behave)
generic map(
L => LBias
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm,
W => Wcm,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm,
W => Wcmcout,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir,
scope => private
)
port map(
P => out1,
N => net1
);
end simple;
| apache-2.0 | f57777ca79afd20525e5542c19130c68 | 0.6 | 3.612013 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/harness_1541.vhd | 5 | 5,864 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std_logic_vector(17 downto 0);
signal sram_dq : std_logic_vector(31 downto 0);
signal sram_csn : std_logic;
signal sram_oen : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector(3 downto 0);
signal iec_atn : std_logic;
signal iec_data : std_logic;
signal iec_clock : std_logic;
---
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal mem_req : std_logic;
signal mem_readwriten : std_logic;
signal mem_address : std_logic_vector(19 downto 0) := (others => '0');
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
begin
-- 4 MHz clock
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
cpu: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
drive_select(0) => '0',
drive_select(1) => '0',
motor_on => motor_on,
mode => mode,
write_prot_n => '1',
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led );
iec_atn <= '0' when atn_o='0' else 'H'; -- open drain, with pull up
iec_clock <= '0' when clk_o='0' else 'H'; -- open drain, with pull up
iec_data <= '0' when data_o='0' else 'H'; -- open drain, with pull up
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
flop: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => '1', -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
-- signals from MOS 6522 VIA
motor_on => motor_on,
mode => mode,
write_prot_n => '1',
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
---
mem_clock => clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_readwriten,
mem_addr => mem_address,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
ram_ctrl: entity work.sram_8bit32
generic map (
SRAM_WR_ASU => 0,
SRAM_WR_Pulse => 1,
SRAM_WR_Hold => 2,
SRAM_RD_ASU => 0,
SRAM_RD_Pulse => 1,
SRAM_RD_Hold => 2 ) -- recovery time (bus turnaround)
port map (
clock => clock,
reset => reset,
req => mem_req,
readwriten => mem_readwriten,
address => mem_address,
rack => mem_rack,
dack => mem_dack,
wdata => mem_wdata,
rdata => mem_rdata,
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_DQ,
SRAM_BEn => SRAM_BEn );
sram: entity work.sram_model_32
generic map(18, 50 ns)
port map (SRAM_A, SRAM_DQ, SRAM_CSn, SRAM_BEn, SRAM_OEn, SRAM_WEn);
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
end structural;
| gpl-3.0 | 6bbd28784a33a61781333765a8b3c70d | 0.43895 | 3.790562 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom/example_design/rom_exdes.vhd | 1 | 4,302 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END rom_exdes;
ARCHITECTURE xilinx OF rom_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT rom IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : rom
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 2a558aa0853a91653c0100c582e7ae31 | 0.572757 | 4.828283 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/implied.vhd | 3 | 4,764 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
enable : in std_logic;
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
d_in : in std_logic;
v_in : in std_logic;
reg_a : in std_logic_vector(7 downto 0);
reg_x : in std_logic_vector(7 downto 0);
reg_y : in std_logic_vector(7 downto 0);
reg_s : in std_logic_vector(7 downto 0);
c_out : out std_logic;
i_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
d_out : out std_logic;
v_out : out std_logic;
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end implied;
architecture gideon of implied is
type t_int4_array is array(natural range <>) of integer range 0 to 3;
-- ROMS for the upper (negative) implied instructions
constant reg_sel_rom : t_int4_array(0 to 15) := ( 2,0,2,1,1,0,1,1,2,0,2,1,1,3,1,1 ); -- 0=A, 1=X, 2=Y, 3=S
constant decr_rom : std_logic_vector(0 to 15) := "1000001000000000";
constant incr_rom : std_logic_vector(0 to 15) := "0011000000000000";
constant nz_flags : std_logic_vector(0 to 15) := "1111111010000100";
constant v_flag : std_logic_vector(0 to 15) := "0000000001000000";
constant d_flag : std_logic_vector(0 to 15) := "0000000000110000";
constant set_a_rom : std_logic_vector(0 to 15) := "0000100010000000";
constant set_x_rom : std_logic_vector(0 to 15) := "0001011000000100";
constant set_y_rom : std_logic_vector(0 to 15) := "1110000000000000";
constant set_s_rom : std_logic_vector(0 to 15) := "0000000000001000";
-- ROMS for the lower (positive) implied instructions
constant shft_rom : std_logic_vector(0 to 15) := "0000111100000000";
constant c_flag : std_logic_vector(0 to 15) := "0000000011000000";
constant i_flag : std_logic_vector(0 to 15) := "0000000000110000";
signal selected_reg : std_logic_vector(7 downto 0) := X"00";
signal operation : integer range 0 to 15;
signal reg_sel : integer range 0 to 3;
signal result : std_logic_vector(7 downto 0) := X"00";
signal add : std_logic_vector(7 downto 0) := X"00";
signal carry : std_logic := '0';
signal zero : std_logic := '0';
signal n_hi : std_logic;
signal z_hi : std_logic;
signal v_hi : std_logic;
signal d_hi : std_logic;
signal n_lo : std_logic;
signal z_lo : std_logic;
signal c_lo : std_logic;
signal i_lo : std_logic;
begin
operation <= conv_integer(inst(4) & inst(1) & inst(6 downto 5));
reg_sel <= reg_sel_rom(operation);
with reg_sel select selected_reg <=
reg_a when 0,
reg_x when 1,
reg_y when 2,
reg_s when others;
add <= (others => decr_rom(operation));
carry <= incr_rom(operation);
result <= selected_reg + add + carry;
zero <= '1' when result = X"00" else '0';
data_out <= result;
n_hi <= result(7) when nz_flags(operation)='1' else n_in;
z_hi <= zero when nz_flags(operation)='1' else z_in;
v_hi <= '0' when v_flag(operation)='1' else v_in;
d_hi <= inst(5) when d_flag(operation)='1' else d_in;
-- in high, C and I are never set
c_lo <= inst(5) when c_flag(operation)='1' else c_in;
i_lo <= inst(5) when i_flag(operation)='1' else i_in;
-- in low, V, N, Z and D are never set
set_a <= set_a_rom(operation) and inst(7) and enable;
set_x <= set_x_rom(operation) and inst(7) and enable;
set_y <= set_y_rom(operation) and inst(7) and enable;
set_s <= set_s_rom(operation) and inst(7) and enable;
c_out <= c_in when inst(7)='1' else c_lo; -- C can only be set in lo
i_out <= i_in when inst(7)='1' else i_lo; -- I can only be set in lo
v_out <= v_hi when inst(7)='1' else v_in; -- V can only be set in hi
d_out <= d_hi when inst(7)='1' else d_in; -- D can only be set in hi
n_out <= n_hi when inst(7)='1' else n_in; -- N can only be set in hi
z_out <= z_hi when inst(7)='1' else z_in; -- Z can only be set in hi
end gideon; | gpl-3.0 | 33b3a8616e5fa03a35ce428e74a8b011 | 0.537993 | 3.205922 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/decoder/decoder_tb.vhdl | 1 | 1,381 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity decoder_tb is
end decoder_tb;
architecture behav of decoder_tb is
component decoder
port (op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end component;
for decoder_0: decoder use entity work.decoder;
signal op : std_logic_vector(3 downto 0);
signal clk : std_logic;
signal result : std_logic_vector(15 downto 0);
begin
decoder_0: decoder port map (op=>op, clk=>clk, result => result);
process
type op_array is array (natural range <>) of std_logic_vector(3 downto 0);
constant ops : op_array :=
("0000", -- bitwise AND
"0001", -- OR
"0010", -- XOR
"0011", -- NOT (1st op)
"0100", -- addition on complements
"0101", -- minus
"0110", -- multiplication
"1000", -- logic shl
"1001", -- shr
"1010", -- arithmetic shl
"1011" -- shr
);
begin
for i in ops'range loop
op <= ops(i);
wait for 10 ms;
end loop;
assert false report "have a nice day!" severity note;
wait;
end process;
end behav;
| gpl-3.0 | 347f03b01e5ffb50013b81222acfc81b | 0.55105 | 3.846797 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op950_5.vhdl | 1 | 5,525 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net5
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net6
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net7
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 37fec347aae6d5fbf40b500283f572b4 | 0.578462 | 3.144565 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_sim/harness_reu.vhd | 5 | 2,141 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
--use work.slot_bus_master_bfm_pkg.all;
entity harness_reu is
end harness_reu;
architecture harness of harness_reu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp;
signal phi2_tick : std_logic := '0';
signal reu_dma_n : std_logic := '1';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_reu: entity work.reu
generic map (
g_ram_tag => X"10",
g_extended => false,
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp,
-- system interface
phi2_tick => phi2_tick,
reu_dma_n => reu_dma_n,
size_ctrl => "111",
enable => '1',
-- memory interface
mem_req => mem_req,
mem_resp => mem_resp,
dma_req => dma_req,
dma_resp => dma_resp );
i_slot_master: entity work.slot_bus_master_bfm
generic map (
g_name => "slot master" )
port map (
clock => clock,
req => slot_req,
resp => slot_resp );
i_c64_memory: entity work.dma_bus_slave_bfm
generic map (
g_name => "c64_memory",
g_latency => 4 )
port map (
clock => clock,
req => dma_req,
resp => dma_resp );
i_reu_memory: entity work.mem_bus_slave_bfm
generic map (
g_name => "reu_memory",
g_latency => 2 )
port map (
clock => clock,
req => mem_req,
resp => mem_resp );
end harness;
| gpl-3.0 | 1687e2445e1ad1091edfd80a00e3baf2 | 0.493695 | 3.16716 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/mem_bus_pkg.vhd | 3 | 4,603 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mem_bus_pkg is
type t_mem_req is record
tag : std_logic_vector(7 downto 0);
request : std_logic;
read_writen : std_logic;
size : unsigned(1 downto 0); -- +1 for reads only
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_mem_resp is record
data : std_logic_vector(7 downto 0);
rack : std_logic;
rack_tag : std_logic_vector(7 downto 0);
dack_tag : std_logic_vector(7 downto 0);
count : unsigned(1 downto 0);
end record;
constant c_mem_req_init : t_mem_req := (
tag => X"00",
request => '0',
read_writen => '1',
size => "00",
address => (others => '0'),
data => X"00" );
constant c_mem_resp_init : t_mem_resp := (
data => X"00",
rack => '0',
rack_tag => X"00",
dack_tag => X"00",
count => "00" );
type t_mem_req_array is array(natural range <>) of t_mem_req;
type t_mem_resp_array is array(natural range <>) of t_mem_resp;
-- 8 bits memory bus with burst --
type t_mem_burst_req is record
request : std_logic;
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
data_push : std_logic;
data_pop : std_logic;
byte_en : std_logic;
end record;
type t_mem_burst_resp is record
data : std_logic_vector(7 downto 0);
ready : std_logic; -- can accept requests
rdata_av : std_logic; -- indicates if there is data in read fifo
wdata_full : std_logic; -- indicates if there is space in write fifo
end record;
constant c_mem_burst_req_init : t_mem_burst_req := (
request => '0',
read_writen => '1',
address => (others => '0'),
data => X"00",
data_push => '0',
data_pop => '0',
byte_en => '1' );
constant c_mem_burst_resp_init : t_mem_burst_resp := (
data => X"00",
ready => '0',
rdata_av => '0',
wdata_full => '0' );
-- 16 bits memory bus with burst --
type t_mem_burst_16_req is record
request : std_logic;
request_tag : std_logic_vector(7 downto 0);
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(15 downto 0);
byte_en : std_logic_vector(1 downto 0);
data_push : std_logic;
data_pop : std_logic;
end record;
type t_mem_burst_16_resp is record
data : std_logic_vector(15 downto 0);
data_tag : std_logic_vector(7 downto 0);
ready : std_logic;
rdata_av : std_logic;
wdata_full : std_logic;
end record;
constant c_mem_burst_16_req_init : t_mem_burst_16_req := (
request => '0',
request_tag => X"00",
read_writen => '1',
address => (others => '0'),
data => X"0000",
data_push => '0',
data_pop => '0',
byte_en => "11" );
-- 32 bits memory bus --
type t_mem_burst_32_req is record
request : std_logic;
request_tag : std_logic_vector(7 downto 0);
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(31 downto 0);
byte_en : std_logic_vector(3 downto 0);
data_push : std_logic;
data_pop : std_logic;
end record;
type t_mem_burst_32_resp is record
data : std_logic_vector(31 downto 0);
data_tag : std_logic_vector(7 downto 0);
ready : std_logic;
rdata_av : std_logic;
wdata_full : std_logic;
end record;
constant c_mem_burst_32_req_init : t_mem_burst_32_req := (
request => '0',
request_tag => X"00",
read_writen => '1',
address => (others => '0'),
data => X"00000000",
data_push => '0',
data_pop => '0',
byte_en => "1111" );
end package;
package body mem_bus_pkg is
end package body;
| gpl-3.0 | c7dcfd17e386991790ee022b1f5f9551 | 0.475125 | 3.601721 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/nano_minimal_io.vhd | 1 | 8,379 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.usb_pkg.all;
entity nano_minimal_io is
generic (
g_support_suspend : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_address : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- Low level
do_chirp : out std_logic;
chirp_data : out std_logic;
-- Functional Level
frame_count : in unsigned(15 downto 0) := (others => '0');
mem_ctrl_ready : in std_logic := '0';
connected : out std_logic; -- '1' when a USB device is connected
operational : out std_logic; -- '1' when a USB device is successfully reset
suspended : out std_logic; -- '1' when the USB bus is in the suspended state
sof_enable : out std_logic; -- '1' when SOFs shall be generated
sof_tick : in std_logic := '0';
interrupt_out : out std_logic := '0';
speed : out std_logic_vector(1 downto 0) ); -- speed indicator of current link
end entity;
architecture gideon of nano_minimal_io is
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal filter_cnt2 : unsigned(8 downto 0);
signal bus_low : std_logic := '0';
signal speed_i : std_logic_vector(1 downto 0);
signal reset_filter_st1 : std_logic;
signal disconn : std_logic;
signal disconn_latched : std_logic;
signal sof_tick_latch : std_logic;
begin
disconn <= '1' when (status(5 downto 4) = "10") or (bus_low = '1' and speed_i(1)='0') else '0';
speed <= speed_i;
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
-- filter for chirp detection
if reset_filter_st1 = '1' then
filter_cnt <= (others => '0');
filter_st1 <= '0';
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else -- status(1) = '1'
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 then
filter_st1 <= '1';
end if;
end if;
-- filter for disconnect detection
if status(1 downto 0) = "00" then
filter_cnt2 <= filter_cnt2 + 1;
if filter_cnt2 = 511 then
bus_low <= '1';
end if;
else
filter_cnt2 <= (others => '0');
bus_low <= '0';
end if;
-- register access defaults
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
interrupt_out <= '0';
reset_filter_st1 <= '0';
if io_write='1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
case adhi is
-- set registers
when X"2" =>
case adlo is
when X"0" =>
do_chirp <= '1';
when X"1" =>
chirp_data <= '1';
when X"2" =>
connected <= '1';
when X"3" =>
operational <= '1';
when X"4" =>
suspended <= '1';
when X"6" =>
speed_i <= io_wdata(1 downto 0);
when X"7" =>
sof_enable <= '1';
when X"8" =>
interrupt_out <= '1';
when X"9" =>
reset_filter_st1 <= '1';
when others =>
null;
end case;
-- clear registers
when X"3" =>
case adlo is
when X"0" =>
do_chirp <= '0';
when X"1" =>
chirp_data <= '0';
when X"2" =>
connected <= '0';
when X"3" =>
operational <= '0';
when X"4" =>
suspended <= '0';
when X"7" =>
sof_enable <= '0';
when X"E" =>
disconn_latched <= '0';
when X"C" =>
sof_tick_latch <= '0';
when others =>
null;
end case;
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if sof_tick = '1' then
sof_tick_latch <= '1';
end if;
if io_read = '1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
if disconn='1' then
disconn_latched <= '1';
end if;
if reset='1' then
do_chirp <= '0';
chirp_data <= '0';
connected <= '0';
operational <= '0';
suspended <= '0';
sof_enable <= '0';
disconn_latched <= '0';
filter_st1 <= '0';
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
speed_i <= "01";
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process( reg_rdata, io_addr, status, disconn_latched, filter_st1, mem_ctrl_ready, frame_count, sof_tick_latch)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"3" =>
case adlo(3 downto 0) is
when X"9" =>
io_rdata(15) <= filter_st1;
when X"B" =>
io_rdata <= std_logic_vector(frame_count);
when X"C" =>
io_rdata(15) <= sof_tick_latch;
when X"D" =>
io_rdata(15) <= mem_ctrl_ready;
when X"E" =>
io_rdata(15) <= disconn_latched;
when X"F" =>
io_rdata(7 downto 0) <= status;
when others =>
null;
end case;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 | c178b2a03b4ba9ddcd413236de9561fb | 0.399212 | 4.145967 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sampler/vhdl_source/sampler_regs.vhd | 5 | 7,386 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler_regs is
generic (
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
rd_addr : in integer range 0 to g_num_voices-1;
control : out t_voice_control;
irq_status : in std_logic_vector(g_num_voices-1 downto 0);
irq_clear : out std_logic_vector(g_num_voices-1 downto 0) );
end entity;
architecture gideon of sampler_regs is
type t_boolean_array is array (natural range <>) of boolean;
type t_mode_array is array (natural range <>) of t_sample_mode;
type t_u8_array is array (natural range <>) of unsigned(7 downto 0);
type t_u6_array is array (natural range <>) of unsigned(5 downto 0);
type t_u4_array is array (natural range <>) of unsigned(3 downto 0);
type t_u2_array is array (natural range <>) of unsigned(1 downto 0);
signal enable : t_boolean_array(0 to g_num_voices-1) := (others => false);
signal repeat : t_boolean_array(0 to g_num_voices-1) := (others => false);
signal interrupt : t_boolean_array(0 to g_num_voices-1) := (others => false);
signal interleave : t_boolean_array(0 to g_num_voices-1) := (others => false);
signal mode : t_mode_array(0 to g_num_voices-1);
signal rep_a_pos2 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rep_a_pos1 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rep_a_pos0 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rep_b_pos2 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rep_b_pos1 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rep_b_pos0 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal start_addr3 : t_u2_array(0 to g_num_voices-1) := (others => "00");
signal start_addr2 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal start_addr1 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal start_addr0 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal length2 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal length1 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal length0 : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rate_h : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal rate_l : t_u8_array(0 to g_num_voices-1) := (others => X"00");
signal volume : t_u6_array(0 to g_num_voices-1) := (others => "100000");
signal pan : t_u4_array(0 to g_num_voices-1) := (others => X"8");
signal wr_addr : integer range 0 to g_num_voices-1;
begin
wr_addr <= to_integer(io_req.address(7 downto 5));
control.enable <= enable(rd_addr);
control.repeat <= repeat(rd_addr);
control.interleave <= interleave(rd_addr);
control.interrupt <= interrupt(rd_addr);
control.mode <= mode(rd_addr);
control.start_addr <= start_addr3(rd_addr) & start_addr2(rd_addr) & start_addr1(rd_addr) & start_addr0(rd_addr);
control.repeat_a <= rep_a_pos2(rd_addr) & rep_a_pos1(rd_addr) & rep_a_pos0(rd_addr);
control.repeat_b <= rep_b_pos2(rd_addr) & rep_b_pos1(rd_addr) & rep_b_pos0(rd_addr);
control.length <= length2(rd_addr) & length1(rd_addr) & length0(rd_addr);
control.rate <= rate_h(rd_addr) & rate_l(rd_addr);
control.volume <= volume(rd_addr);
control.pan <= pan(rd_addr);
process(clock)
begin
if rising_edge(clock) then
-- write port - control -
io_resp <= c_io_resp_init;
io_resp.ack <= io_req.read or io_req.write;
irq_clear <= (others => '0');
if io_req.read='1' then
if io_req.address(0)='0' then
io_resp.data(irq_status'range) <= irq_status;
else
io_resp.data <= X"10";
end if;
end if;
if io_req.write='1' then
case io_req.address(4 downto 0) is
when c_sample_control =>
enable(wr_addr) <= (io_req.data(0) = '1');
repeat(wr_addr) <= (io_req.data(1) = '1');
interrupt(wr_addr) <= (io_req.data(2) = '1');
interleave(wr_addr) <= (io_req.data(6) = '1');
if io_req.data(5 downto 4) = "00" then
mode(wr_addr) <= mono8;
else
mode(wr_addr) <= mono16;
end if;
when c_sample_volume =>
volume(wr_addr) <= unsigned(io_req.data(5 downto 0));
when c_sample_pan =>
pan(wr_addr) <= unsigned(io_req.data(3 downto 0));
when c_sample_start_addr_h =>
start_addr3(wr_addr) <= unsigned(io_req.data(1 downto 0));
when c_sample_start_addr_mh =>
start_addr2(wr_addr) <= unsigned(io_req.data);
when c_sample_start_addr_ml =>
start_addr1(wr_addr) <= unsigned(io_req.data);
when c_sample_start_addr_l =>
start_addr0(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_a_pos_h =>
rep_a_pos2(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_a_pos_m =>
rep_a_pos1(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_a_pos_l =>
rep_a_pos0(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_b_pos_h =>
rep_b_pos2(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_b_pos_m =>
rep_b_pos1(wr_addr) <= unsigned(io_req.data);
when c_sample_rep_b_pos_l =>
rep_b_pos0(wr_addr) <= unsigned(io_req.data);
when c_sample_length_h =>
length2(wr_addr) <= unsigned(io_req.data);
when c_sample_length_m =>
length1(wr_addr) <= unsigned(io_req.data);
when c_sample_length_l =>
length0(wr_addr) <= unsigned(io_req.data);
when c_sample_rate_h =>
rate_h(wr_addr) <= unsigned(io_req.data);
when c_sample_rate_l =>
rate_l(wr_addr) <= unsigned(io_req.data);
when c_sample_clear_irq =>
irq_clear(wr_addr) <= io_req.data(0);
if io_req.data=X"FF" then
irq_clear <= (others => '1');
end if;
when others =>
null;
end case;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 4c5106b66b29f59cdd3e980d05b9b050 | 0.491741 | 3.25805 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/gcr2bin.vhd | 5 | 1,154 | library ieee;
use ieee.std_logic_1164.all;
entity gcr2bin is
port (
d_in : in std_logic_vector(4 downto 0);
d_out : out std_logic_vector(3 downto 0);
error : out std_logic );
end gcr2bin;
architecture rom of gcr2bin is
begin
process(d_in)
begin
d_out <= X"0";
error <= '0';
case d_in is
when "01010" => d_out <= "0000";
when "01011" => d_out <= "0001";
when "10010" => d_out <= "0010";
when "10011" => d_out <= "0011";
when "01110" => d_out <= "0100";
when "01111" => d_out <= "0101";
when "10110" => d_out <= "0110";
when "10111" => d_out <= "0111";
when "01001" => d_out <= "1000";
when "11001" => d_out <= "1001";
when "11010" => d_out <= "1010";
when "11011" => d_out <= "1011";
when "01101" => d_out <= "1100";
when "11101" => d_out <= "1101";
when "11110" => d_out <= "1110";
when "10101" => d_out <= "1111";
when others =>
error <= '1';
end case;
end process;
end rom;
| gpl-3.0 | 043fb17659b4b15f983e9edac51eb3a8 | 0.443674 | 3.250704 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op326_2sk1_0.vhdl | 1 | 5,133 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.6e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.6e-06,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 5.89e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.55e-06,
W => Wcm_1,
Wcm_1init => 8.5e-07,
scope => private
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.55e-06,
W => Wcmout_1,
Wcmout_1init => 6.28e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net2
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | ec596e3582dbd1ec55d987853035ee9c | 0.591467 | 3.042679 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_pkg.vhd | 1 | 5,878 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE ROM_GAUSS_COE_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END ROM_GAUSS_COE_TB_PKG;
PACKAGE BODY ROM_GAUSS_COE_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END ROM_GAUSS_COE_TB_PKG;
| gpl-3.0 | a8000944c357833f85b4a514c9497cf7 | 0.596632 | 4.439577 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/cpu6502.vhd | 2 | 1,430 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_reset : in std_logic;
cpu_ready : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
attribute optimize : string;
attribute optimize of cpu6502 : entity is "SPEED";
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_ready,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
| gpl-3.0 | b381ce0ad8994ecf3b2b1f0fb778361a | 0.517483 | 3.504902 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_cmd_pkg.vhd | 1 | 3,637 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2015
-- Entity: usb_cmd_pkg
-- Date:2015-01-18
-- Author: Gideon
-- Description: This package defines the commands that can be sent to the
-- sequencer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
package usb_cmd_pkg is
-- Protocol Event
type t_usb_command is ( setup, out_data, in_request, ping );
type t_usb_result is ( res_data, res_ack, res_nak, res_nyet, res_stall, res_error );
type t_usb_cmd_req is record
request : std_logic;
-- command and modifiers (4 bits?)
command : t_usb_command;
do_split : std_logic;
do_data : std_logic;
-- data buffer controls (14 bits)
buffer_index : unsigned(1 downto 0);
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
-- USB addressing (11 bits)
device_addr : unsigned(6 downto 0);
endp_addr : unsigned(3 downto 0);
-- USB addressing (15 bits)
split_hub_addr : unsigned(6 downto 0);
split_port_addr : unsigned(3 downto 0); -- hubs with more than 16 ports are not supported
split_sc : std_logic; -- 0=start 1=complete
split_sp : std_logic; -- 0=full, 1=low
split_et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
type t_usb_cmd_resp is record
done : std_logic;
result : t_usb_result;
-- data descriptor
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
end record;
-- type t_usb_result_encoded is array (t_usb_result range<>) of std_logic_vector(2 downto 0);
-- constant c_usb_result_encoded : t_usb_result_encoded := (
-- res_data => "001",
-- res_ack => "010",
-- res_nak => "011",
-- res_nyet => "100",
-- res_error => "111" );
type t_usb_command_array is array(natural range <>) of t_usb_command;
constant c_usb_commands_decoded : t_usb_command_array(0 to 3) := ( setup, out_data, in_request, ping );
constant c_usb_cmd_init : t_usb_cmd_req := (
request => '0',
command => setup,
do_split => '0',
do_data => '0',
buffer_index => "00",
data_length => "0000000000",
togglebit => '0',
no_data => '1',
device_addr => "0000000",
endp_addr => X"0",
split_hub_addr => "0000000",
split_port_addr => X"0",
split_sc => '0',
split_sp => '0',
split_et => "00" );
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result;
end package;
package body usb_cmd_pkg is
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result is
variable res : t_usb_result;
begin
case pid is
when c_pid_ack => res := res_ack;
when c_pid_nak => res := res_nak;
when c_pid_nyet => res := res_nyet;
when c_pid_stall => res := res_stall;
when others => res := res_error;
end case;
return res;
end function;
end package body;
| gpl-3.0 | 24d420be6c55fffdcfb1003f87eac4bb | 0.499863 | 3.711224 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op12.vhdl | 1 | 12,611 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
terminal net15: electrical;
terminal net16: electrical;
terminal net17: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.75e-06,
W => Wdiff_0,
Wdiff_0init => 3.05e-06,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.75e-06,
W => Wdiff_0,
Wdiff_0init => 3.05e-06,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => W_0,
W_0init => 3.6e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.75e-06,
W => Wdiff_0,
Wdiff_0init => 3.05e-06,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.75e-06,
W => Wdiff_0,
Wdiff_0init => 3.05e-06,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.9e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.9e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.9e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.9e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 1.1e-06,
W => Wsrc_1,
Wsrc_1init => 7.62e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 7.87e-13,
symmetry_scope => sym_3
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 1.1e-06,
W => Wsrc_1,
Wsrc_1init => 7.62e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 1.126e-12,
symmetry_scope => sym_3
)
port map(
P => net4,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 6.875e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net3,
G => vbias3,
S => net9
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 3.06e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmout_2,
Wcmout_2init => 4.015e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net10,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 6.875e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net5,
G => vbias3,
S => net10
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 6.875e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net4,
G => vbias3,
S => net11
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 3.06e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmout_2,
Wcmout_2init => 4.015e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net12,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 6.875e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net6,
G => vbias3,
S => net12
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4.5e-07,
W => Wcm_3,
Wcm_3init => 5.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.81e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4.5e-07,
W => Wcm_3,
Wcm_3init => 5.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.81e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcursrc_4,
Wcursrc_4init => 1.42e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcursrc_4,
Wcursrc_4init => 1.42e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net13,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net13,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net16,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net15,
N => net13
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => W_1,
W_1init => 4.455e-05
)
port map(
D => net14,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.1e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.325e-05,
scope => private
)
port map(
D => net16,
G => vref,
S => net14
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 6.1e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.325e-05,
scope => private
)
port map(
D => net15,
G => net13,
S => net14
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.45e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net15,
G => net15,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.45e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net16,
G => net15,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.925e-05,
scope => private
)
port map(
D => out1,
G => net16,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.925e-05,
scope => private
)
port map(
D => out2,
G => net16,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => (pfak)*(WBias),
WBiasinit => 1.49e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.65e-06,
W => (pfak)*(WBias),
WBiasinit => 1.49e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias2,
G => vbias3,
S => net17
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => net17,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d1643b4bfc0096ca23f7e983ad9a51cd | 0.5653 | 2.778978 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_32_tb.vhd | 5 | 7,761 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32_tb is
end ext_mem_test_32_tb;
architecture tb of ext_mem_test_32_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp_16 : t_mem_burst_16_resp;
signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp_32 : t_mem_burst_32_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req_32,
resp => resp_32,
okay => okay );
i_convert: entity work.mem_16to32
port map (
clock => clock,
reset => reset,
req_16 => req_16,
resp_16 => resp_16,
req_32 => req_32,
resp_32 => resp_32 );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req_16,
resp => resp_16,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
| gpl-3.0 | 5143960bd0a004a4adc900e0cbd98490 | 0.421853 | 3.538988 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op981_3.vhdl | 1 | 5,443 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | f49166432d1862ecb1371c98e57ed97a | 0.573948 | 3.133564 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/cpu_part_1541.vhd | 1 | 14,342 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity cpu_part_1541 is
generic (
g_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- trace out
cpu_pc : out std_logic_vector(15 downto 0);
-- configuration
bank_is_ram : in std_logic_vector(7 downto 0);
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
motor_on : out std_logic;
mode : out std_logic;
write_prot_n : in std_logic;
step : out std_logic_vector(1 downto 0);
soe : out std_logic;
rate_ctrl : out std_logic_vector(1 downto 0);
byte_ready : in std_logic;
sync : in std_logic;
track_is_0 : in std_logic;
drv_rdata : in std_logic_vector(7 downto 0);
drv_wdata : out std_logic_vector(7 downto 0);
act_led : out std_logic );
end cpu_part_1541;
architecture structural of cpu_part_1541 is
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal io_rdata : std_logic_vector(7 downto 0);
signal via1_data : std_logic_vector(7 downto 0);
signal via2_data : std_logic_vector(7 downto 0);
signal ram_en : std_logic;
signal via1_wen : std_logic;
signal via1_ren : std_logic;
signal via2_wen : std_logic;
signal via2_ren : std_logic;
signal via1_port_a_o : std_logic_vector(7 downto 0);
signal via1_port_a_t : std_logic_vector(7 downto 0);
signal via1_port_a_i : std_logic_vector(7 downto 0);
signal via1_port_b_o : std_logic_vector(7 downto 0);
signal via1_port_b_t : std_logic_vector(7 downto 0);
signal via1_port_b_i : std_logic_vector(7 downto 0);
signal via1_ca1 : std_logic;
signal via1_ca2 : std_logic;
signal via1_cb1 : std_logic;
signal via1_cb2 : std_logic;
signal via1_irq : std_logic;
signal via2_port_b_o : std_logic_vector(7 downto 0);
signal via2_port_b_t : std_logic_vector(7 downto 0);
signal via2_port_b_i : std_logic_vector(7 downto 0);
signal via2_ca2_o : std_logic;
signal via2_ca2_i : std_logic;
signal via2_ca2_t : std_logic;
signal via2_cb1_o : std_logic;
signal via2_cb1_i : std_logic;
signal via2_cb1_t : std_logic;
signal via2_cb2_o : std_logic;
signal via2_cb2_i : std_logic;
signal via2_cb2_t : std_logic;
signal via2_irq : std_logic;
signal bank_is_io : std_logic_vector(7 downto 0);
signal io_select : std_logic;
signal rdata_mux : std_logic;
signal cpu_ready : std_logic;
signal need_cycle : unsigned(2 downto 0);
signal done_cycle : unsigned(2 downto 0);
type t_mem_state is (idle, cpubusy, newcycle, extcycle);
signal mem_state : t_mem_state;
signal clock_en_d : std_logic;
signal clock_en_dd : std_logic;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
begin
mem_req.request <= mem_request;
mem_req.address <= mem_addr;
mem_req.read_writen <= mem_rwn;
mem_req.data <= mem_wdata;
mem_req.tag <= g_tag;
mem_req.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_reset => reset,
cpu_ready => cpu_ready,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
cpu_pc => cpu_pc,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => byte_ready );
via1: entity work.via6522
port map (
clock => clock,
clock_en => cpu_ready,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via1_wen,
ren => via1_ren,
data_in => cpu_wdata,
data_out => via1_data,
-- pio --
port_a_o => via1_port_a_o,
port_a_t => via1_port_a_t,
port_a_i => via1_port_a_i,
port_b_o => via1_port_b_o,
port_b_t => via1_port_b_t,
port_b_i => via1_port_b_i,
-- handshake pins
ca1_i => via1_ca1,
ca2_o => via1_ca2,
ca2_i => via1_ca2,
ca2_t => open,
cb1_o => via1_cb1,
cb1_i => via1_cb1,
cb1_t => open,
cb2_o => via1_cb2,
cb2_i => via1_cb2,
cb2_t => open,
irq => via1_irq );
via2: entity work.via6522
port map (
clock => clock,
clock_en => cpu_ready,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via2_wen,
ren => via2_ren,
data_in => cpu_wdata,
data_out => via2_data,
-- pio --
port_a_o => drv_wdata,
port_a_t => open,
port_a_i => drv_rdata,
port_b_o => via2_port_b_o,
port_b_t => via2_port_b_t,
port_b_i => via2_port_b_i,
-- handshake pins
ca1_i => byte_ready,
ca2_o => via2_ca2_o,
ca2_i => via2_ca2_i,
ca2_t => via2_ca2_t,
cb1_o => via2_cb1_o,
cb1_i => via2_cb1_i,
cb1_t => via2_cb1_t,
cb2_o => via2_cb2_o,
cb2_i => via2_cb2_i,
cb2_t => via2_cb2_t,
irq => via2_irq );
cpu_irqn <= not(via1_irq or via2_irq);
-- Fetch ROM byte
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
need_cycle <= need_cycle + 1;
end if;
bank_is_io <= "0000" & not bank_is_ram(3 downto 1) & '1';
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
clock_en_d <= clock_en;
clock_en_dd <= clock_en_d;
cpu_ready <= '0';
case mem_state is
when idle =>
if need_cycle /= done_cycle then
cpu_ready <= '1';
mem_state <= cpubusy;
end if;
when cpubusy =>
mem_state <= newcycle;
when newcycle => -- we have a new address now
io_select <= '0';
if bank_is_io(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then
rdata_mux <= '1'; -- io
if cpu_addr(12)='0' then -- lower 4K of IO block is possibly RAM
mem_request <= '1';
mem_state <= extcycle;
mem_addr(14 downto 13) <= "00"; -- cause mirroring
else
io_select <= '1';
done_cycle <= done_cycle + 1;
mem_state <= idle;
end if;
elsif cpu_write='0' or bank_is_ram(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then -- ram is writeable, rom is not
rdata_mux <= '0';
mem_request <= '1';
mem_state <= extcycle;
else -- write to rom -> ignore
done_cycle <= done_cycle + 1;
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
done_cycle <= done_cycle + 1;
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp.data;
done_cycle <= done_cycle + 1;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
rdata_mux <= '0';
io_select <= '0';
cpu_ready <= '0';
mem_request <= '0';
mem_state <= idle;
need_cycle <= "000";
done_cycle <= "000";
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- address decoding and data muxing
with cpu_addr(12 downto 10) select io_rdata <=
ext_rdata when "000",
ext_rdata when "001",
via1_data when "110",
via2_data when "111",
X"FF" when others;
cpu_rdata <= io_rdata when rdata_mux='1' else ext_rdata;
via1_wen <= '1' when cpu_write='1' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0';
via1_ren <= '1' when cpu_write='0' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0';
via2_wen <= '1' when cpu_write='1' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0';
via2_ren <= '1' when cpu_write='0' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0';
-- correctly attach the VIA pins to the outside world
-- pull up when not driven...
via1_port_a_i(7 downto 1) <= via1_port_a_o(7 downto 1) or not via1_port_a_t(7 downto 1);
via1_port_a_i(0) <= track_is_0;
via1_ca1 <= not atn_i;
via1_port_b_i(7) <= not atn_i;
-- the following bits should read 0 when the jumper is closed (drive select = 0) or when driven low by the VIA itself
via1_port_b_i(6) <= drive_address(1) and (not via1_port_b_t(6) or via1_port_b_o(6)); -- drive select
via1_port_b_i(5) <= drive_address(0) and (not via1_port_b_t(5) or via1_port_b_o(5)); -- drive select;
via1_port_b_i(4) <= via1_port_b_o(4) or not via1_port_b_t(4); -- atn a - PUP
via1_port_b_i(3) <= via1_port_b_o(3) or not via1_port_b_t(3); -- clock out - PUP
via1_port_b_i(2) <= not clk_i;
via1_port_b_i(1) <= via1_port_b_o(1) or not via1_port_b_t(1); -- data out - PUP
via1_port_b_i(0) <= not data_i;
-- auto_o <= not power or via1_port_b_i(4);
data_o <= not power or ((not via1_port_b_i(1)) and (not (via1_port_b_i(4) xor via1_port_b_i(7))));
clk_o <= not power or not via1_port_b_i(3);
atn_o <= '1';
-- Do the same for VIA 2
via2_port_b_i(7) <= sync;
via2_port_b_i(6) <= via2_port_b_o(6) or not via2_port_b_t(6);
via2_port_b_i(5) <= via2_port_b_o(5) or not via2_port_b_t(5);
via2_port_b_i(4) <= write_prot_n;
via2_port_b_i(3) <= via2_port_b_o(3) or not via2_port_b_t(3);
via2_port_b_i(2) <= via2_port_b_o(2) or not via2_port_b_t(2);
via2_port_b_i(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
via2_port_b_i(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
via2_cb1_i <= via2_cb1_o or not via2_cb1_t;
via2_cb2_i <= via2_cb2_o or not via2_cb2_t;
via2_ca2_i <= via2_ca2_o or not via2_ca2_t;
act_led <= not via2_port_b_i(3) or not power;
mode <= via2_cb2_i;
step(0) <= via2_port_b_i(0);
step(1) <= via2_port_b_i(1);
motor_on <= via2_port_b_i(2) and power;
soe <= via2_ca2_i;
rate_ctrl(0) <= via2_port_b_i(5);
rate_ctrl(1) <= via2_port_b_i(6);
end structural;
-- Original mapping:
-- 0000-07FF RAM
-- 0800-17FF open
-- 1800-1BFF VIA 1
-- 1C00-1CFF VIA 2
-- 2000-27FF RAM
-- 2800-37FF open
-- 3800-3BFF VIA 1
-- 3C00-3CFF VIA 2
-- 4000-47FF RAM
-- 4800-57FF open
-- 5800-5BFF VIA 1
-- 5C00-5CFF VIA 2
-- 6000-67FF RAM
-- 6800-77FF open
-- 7800-7BFF VIA 1
-- 7C00-7CFF VIA 2
-- 8000-BFFF ROM image (mirror)
-- C000-FFFF ROM image
| gpl-3.0 | 605d16335af588f0bab854630f5466a2 | 0.45677 | 3.237472 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem/example_design/testmem_exdes.vhd | 1 | 4,601 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: testmem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY testmem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END testmem_exdes;
ARCHITECTURE xilinx OF testmem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT testmem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : testmem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | a921c3bab33f655c4e246754c4248a05 | 0.567268 | 4.748194 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op954_0.vhdl | 1 | 4,201 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | b5fb9ecd3628d9d04039f55e5ae345fa | 0.587479 | 3.259116 | false | false | false | false |
nick1au/Home-Sec-SYS | AlrTest.vhd | 1 | 2,085 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity AlrTest is
Port (KEY, SW: IN std_logic_vector ( 17 downto 0);
CLOCK_50: IN std_logic;
LEDG: OUT std_logic_vector (3 downto 0);
LEDR: OUT std_logic_vector (17 downto 0);
HEX0, HEX1, HEX2: OUT std_logic_vector(6 downto 0));
end AlrTest;
Architecture structure of AlrTest is
Component PreScale is
generic (BIT_WIDTH : integer := 19);
Port(inclock: IN std_logic;
outclock: OUT std_logic);
End component;
Component System is
Port(door: IN std_logic_vector(3 downto 0);
ARM, clock : IN std_logic;
ready, SysArm, AlrOn: OUT std_logic);
end component;
Component Alarm is
Port(Enable, clockin: IN std_logic;
Y1,Y2,Y3: out std_logic_vector(6 downto 0));
end component;
component halfSecDelay is
Port (load, clock: in std_logic;
TC: out std_logic);
End component halfSecDelay;
component JamesBond is
port( Go, clock: in std_logic;
Digit: in std_logic_vector(2 downto 0);
GetCode: out std_logic);
End component;
signal srdy, sarm, salron, soutclock, sload, sclock, sTC, skey, JB: std_logic;
begin
stage4: entity work.JamesBond port map (Go => sTC, clock => soutclock, Digit => SW(17 downto 15), GetCode => JB);
LEDG(2) <= srdy;
LEDG(1) <= sarm;
LEDG(0) <= salron;
LEDR(3 downto 0) <= SW(3 downto 0);
LEDR(17 downto 15) <= SW(17 downto 15);
--skey <= '1' when stc ='0' else '0';
sload <= not KEY(3);
stage0: entity work.Alarm Port map (Enable => salron,Y1=> HEX2, Y2=> HEX1, Y3=> HEX0, clockin => soutclock);
stage1: entity work.System (thelayed) port map (delay => LEDG(3), ARM => JB, door=> SW(3 downto 0), ready => srdy, sysarm=> sarm, alron=> salron, clock=>soutclock);
stage2: entity work.pREScale port map (inclock => CLOCK_50, outclock=>soutclock);
stage3: entity work.halfSecDelay port map (load=>sload, clock=>soutclock, TC=>sTC);
--stage1: entity work.System (thelayed) port map (delay => LEDG(3), ARM => KEY(3), door=> SW(3 downto 0), ready => srdy, sysarm=> sarm, alron=> salron, clock=>soutclock);
end structure; | gpl-3.0 | 95466a888bacd28ebf1c9c93899104bb | 0.674341 | 2.864011 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_7sk1_0.vhdl | 1 | 6,116 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8e-07,
W => Wdiff_0,
Wdiff_0init => 2.55e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8e-07,
W => Wdiff_0,
Wdiff_0init => 2.55e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => W_0,
W_0init => 3.95e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcmout_2,
Wcmout_2init => 7.545e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcmout_2,
Wcmout_2init => 7.545e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.85e-06,
W => Wcm_1,
Wcm_1init => 1.035e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.85e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.77e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => (pfak)*(WBias),
WBiasinit => 9.35e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.95e-06,
W => (pfak)*(WBias),
WBiasinit => 9.35e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 955b40ac70171f3641d9c79776ce87c8 | 0.584696 | 2.956017 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/tb_simple_sram.vhd | 5 | 2,631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_simple_sram is
end tb_simple_sram;
architecture tb of tb_simple_sram is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : std_logic := '0';
signal readwriten : std_logic := '1';
signal address : std_logic_vector(15 downto 0) := (others => '0');
signal rack : std_logic;
signal dack : std_logic;
signal wdata : std_logic_vector(31 downto 0) := X"12345678";
signal wdata_mask : std_logic_vector(3 downto 0) := X"5";
signal rdata : std_logic_vector(31 downto 0);
signal SRAM_A : std_logic_vector(15 downto 0);
signal SRAM_OEn : std_logic;
signal SRAM_WEn : std_logic;
signal SRAM_CSn : std_logic;
signal SRAM_D : std_logic_vector(31 downto 0) := (others => 'Z');
signal SRAM_BEn : std_logic_vector(3 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
mut: entity work.simple_sram
generic map (
SRAM_Byte_Lanes => 4,
SRAM_Data_Width => 32,
SRAM_WR_ASU => 1,
SRAM_WR_Pulse => 2,
SRAM_WR_Hold => 2,
SRAM_RD_ASU => 0,
SRAM_RD_Pulse => 5,
SRAM_RD_Hold => 1, -- recovery time (bus turnaround)
SRAM_A_Width => 16 )
port map (
clock => clock,
reset => reset,
req => req,
readwriten => readwriten,
address => address,
rack => rack,
dack => dack,
wdata => wdata,
wdata_mask => wdata_mask,
rdata => rdata,
--
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_D,
SRAM_BEn => SRAM_BEn );
test: process
procedure do_access(a : std_logic_vector; rw : std_logic; d : std_logic_vector) is
begin
req <= '1';
readwriten <= rw;
address <= a;
wdata <= d;
wait until clock='1';
while rack='0' loop
wait until clock='1';
end loop;
req <= '0';
-- while dack='0' loop
-- wait until clock='1';
-- end loop;
end do_access;
begin
wait until reset='0';
wait until clock='1';
do_access(X"1111", '1', X"00000000");
do_access(X"2233", '1', X"00000000");
do_access(X"4444", '0', X"55AA9933");
do_access(X"5678", '0', X"12345678");
do_access(X"9999", '1', X"00000000");
wait;
end process;
end tb;
| gpl-3.0 | 7236074d10eeb6f238fb38d9999c9b0f | 0.524515 | 3.066434 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sampler/vhdl_source/sampler_pkg.vhd | 4 | 3,556 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigned(23 downto 0);
divider : unsigned(15 downto 0);
sample_out : signed(15 downto 0);
end record;
constant c_voice_state_init : t_voice_state := (
state => idle,
position => to_unsigned(0, 24),
divider => to_unsigned(0, 16),
sample_out => to_signed(0, 16) );
type t_voice_control is record
enable : boolean;
repeat : boolean;
interrupt : boolean;
interleave : boolean;
mode : t_sample_mode;
start_addr : unsigned(25 downto 0);
repeat_a : unsigned(23 downto 0);
repeat_b : unsigned(23 downto 0);
length : unsigned(23 downto 0);
rate : unsigned(15 downto 0);
volume : unsigned(5 downto 0);
pan : unsigned(3 downto 0); -- 0000 = left, 1111 = right
end record;
constant c_voice_control_init : t_voice_control := (
enable => false,
repeat => false,
interrupt => false,
interleave => false,
mode => mono8,
start_addr => to_unsigned(16*1024*1024, 26),
repeat_a => to_unsigned(32768, 24),
repeat_b => to_unsigned(49152, 24),
length => to_unsigned(65536, 24),
rate => to_unsigned(283, 16),
volume => to_unsigned(63, 6),
pan => X"7" );
type t_voice_control_array is array(natural range <>) of t_voice_control;
type t_voice_state_array is array(natural range <>) of t_voice_state;
type t_voice_sample_array is array(natural range <>) of signed(15 downto 0);
type t_sample_byte_array is array(natural range <>) of signed(7 downto 0);
constant c_sample_control : unsigned(4 downto 0) := '0' & X"0";
constant c_sample_volume : unsigned(4 downto 0) := '0' & X"1";
constant c_sample_pan : unsigned(4 downto 0) := '0' & X"2";
constant c_sample_start_addr_h : unsigned(4 downto 0) := '0' & X"4";
constant c_sample_start_addr_mh : unsigned(4 downto 0) := '0' & X"5";
constant c_sample_start_addr_ml : unsigned(4 downto 0) := '0' & X"6";
constant c_sample_start_addr_l : unsigned(4 downto 0) := '0' & X"7";
constant c_sample_length_h : unsigned(4 downto 0) := '0' & X"9";
constant c_sample_length_m : unsigned(4 downto 0) := '0' & X"A";
constant c_sample_length_l : unsigned(4 downto 0) := '0' & X"B";
constant c_sample_rate_h : unsigned(4 downto 0) := '0' & X"E";
constant c_sample_rate_l : unsigned(4 downto 0) := '0' & X"F";
constant c_sample_rep_a_pos_h : unsigned(4 downto 0) := '1' & X"1";
constant c_sample_rep_a_pos_m : unsigned(4 downto 0) := '1' & X"2";
constant c_sample_rep_a_pos_l : unsigned(4 downto 0) := '1' & X"3";
constant c_sample_rep_b_pos_h : unsigned(4 downto 0) := '1' & X"5";
constant c_sample_rep_b_pos_m : unsigned(4 downto 0) := '1' & X"6";
constant c_sample_rep_b_pos_l : unsigned(4 downto 0) := '1' & X"7";
constant c_sample_clear_irq : unsigned(4 downto 0) := '1' & X"F";
end package;
| gpl-3.0 | fb3e18a37ea2d81866e27a722b2d3efc | 0.540776 | 3.298701 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/tb_math.vhd | 5 | 883 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_math_pkg.all;
entity tb_math is
end tb_math;
architecture tb of tb_math is
signal i1 : signed(3 downto 0);
signal i2 : signed(3 downto 0);
signal sum : signed(3 downto 0);
signal diff : signed(3 downto 0);
signal sum_i: integer;
signal diff_i: integer;
begin
process
variable k,p: signed(3 downto 0);
begin
for i in -8 to 7 loop
for j in -8 to 7 loop
k := to_signed(i, 4);
p := to_signed(j, 4);
sum <= sum_limit(k, p);
diff <= sub_limit(k, p);
i1 <= k;
i2 <= p;
sum_i <= i + j;
diff_i <= i - j;
wait for 1 us;
end loop;
end loop;
wait;
end process;
end tb;
| gpl-3.0 | 667a5d909fc4096d45c31ed2627aeed6 | 0.481314 | 3.422481 | false | false | false | false |
tirfil/VhdI2CSlave | vhdl/sp256x8.vhd | 1 | 914 | --###############################
--# Project Name : I2C Slave
--# File : ALTERA compatible
--# Project : VHDL RAM model
--# Engineer : Philippe THIRION
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sp256x8 is
port(
address : in std_logic_vector(7 downto 0);
clock : in std_logic;
data : in std_logic_vector(7 downto 0);
wren : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end sp256x8;
architecture rtl of sp256x8 is
type memory is array(0 to 255) of std_logic_vector(7 downto 0);
signal mem : memory;
begin
RAM : process(clock)
begin
if (clock'event and clock='1') then
if (wren = '0') then
q <= mem(to_integer(unsigned(address)));
else
mem(to_integer(unsigned(address))) <= data;
q <= data; -- ????
end if;
end if;
end process RAM;
end rtl;
| gpl-3.0 | 127575e012485a0d17931f13941c786c | 0.592998 | 2.986928 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_stim_gen.vhd | 1 | 7,511 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For Single Port RAM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_TB_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0');
D : OUT STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0');
WE : OUT STD_LOGIC := '0';
DATA_IN : IN STD_LOGIC_VECTOR (134 DOWNTO 0); --OUTPUT VECTOR
CHECK_DATA : OUT STD_LOGIC:= '0'
);
END ROM_GAUSS_COE_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF ROM_GAUSS_COE_TB_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:=1;
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_INT : STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
A <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT);
D <= D_INT;
CHECK_DATA <= DO_READ;
RD_AGEN_INST:ENTITY work.ROM_GAUSS_COE_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_AGEN_INST:ENTITY work.ROM_GAUSS_COE_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DGEN_INST:ENTITY work.ROM_GAUSS_COE_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH => 135,
DOUT_WIDTH => 135,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => D_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WE <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 | 62ef3b9c0f1ecbe0e5b23cba6c2fbf1a | 0.562508 | 3.69454 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/c1541_pkg.vhd | 4 | 1,032 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_sensor : unsigned(3 downto 0) := X"3";
constant c_drvreg_inserted : unsigned(3 downto 0) := X"4";
constant c_drvreg_rammap : unsigned(3 downto 0) := X"5";
constant c_drvreg_anydirty : unsigned(3 downto 0) := X"6";
constant c_drvreg_dirtyirq : unsigned(3 downto 0) := X"7";
constant c_drvreg_track : unsigned(3 downto 0) := X"8";
constant c_drvreg_status : unsigned(3 downto 0) := X"9";
constant c_drvreg_memmap : unsigned(3 downto 0) := X"A";
constant c_drvreg_audiomap : unsigned(3 downto 0) := X"B";
constant c_drv_dirty_base : unsigned(15 downto 0) := X"0800";
constant c_drv_param_base : unsigned(15 downto 0) := X"1000";
end;
| gpl-3.0 | ade05b2fd6d4992fa4884c96d4bdac2d | 0.613372 | 3.008746 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/gcr_encoder.vhd | 5 | 1,636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_encoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_encoder;
architecture regmap of gcr_encoder is
signal shift_reg : std_logic_vector(0 to 31);
signal encoded : std_logic_vector(0 to 39);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 31) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= encoded(0 to 7);
when X"1" =>
resp.data <= encoded(8 to 15);
when X"2" =>
resp.data <= encoded(16 to 23);
when X"3" =>
resp.data <= encoded(24 to 31);
when others =>
resp.data <= encoded(32 to 39);
end case;
end if;
if reset='1' then
shift_reg <= X"00000000";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(4*i to 3+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
end;
| gpl-3.0 | 276e8f888ea94e14fae41743dcb0011f | 0.448044 | 3.676404 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/c2n_playback/vhdl_source/c2n_playback.vhd | 5 | 4,623 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c2n_playback is
port (
clock : in std_logic;
reset : in std_logic;
phi2_tick : in std_logic;
stream_en : in std_logic;
cmd_write : in std_logic;
fifo_write : in std_logic;
wdata : in std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
c2n_sense : out std_logic;
c2n_out : out std_logic );
end c2n_playback;
architecture gideon of c2n_playback is
signal enabled : std_logic;
signal counter : std_logic_vector(23 downto 0);
signal error : std_logic;
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 15;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
c2n_sense <= not fifo_empty;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
if cnt2 = 0 then
toggle <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
if cmd_write='1' then
enabled <= wdata(0);
if wdata(1)='1' then
error <= '0';
end if;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
state <= multi1;
else
counter <= "0000000000000" & fifo_dout & "000";
state <= count_down;
end if;
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= fifo_dout;
state <= multi2;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= fifo_dout;
state <= multi3;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= fifo_dout;
state <= count_down;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' then
if counter = 1 then
toggle <= '1';
cnt2 <= 15;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
end if;
end if;
end process;
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => wdata,
dout => fifo_dout,
flush => '0',
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= '0';
status(5) <= '0';
status(6) <= '0';
status(7) <= fifo_empty;
c2n_out <= not toggle;
end gideon;
| gpl-3.0 | 178d256b718eb61f3956a82d7fbceb92 | 0.407095 | 4.320561 | false | false | false | false |
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