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daringer/schemmaker | testdata/hardest/circuit_op7.vhdl | 1 | 8,011 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.14e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net1
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.14e-05,
scope => private
)
port map(
D => net3,
G => in2,
S => net1
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => W_0,
W_0init => 5.575e-05
)
port map(
D => net1,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_1,
Wcursrc_1init => 9.4e-06,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_1,
Wcursrc_1init => 9.4e-06,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 3.35e-06,
W => Wsrc_2,
Wsrc_2init => 7.415e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 3.65e-06,
W => Wsrc_2,
Wsrc_2init => 7.415e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net3,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_3,
Wcursrc_3init => 8e-07,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_3,
Wcursrc_3init => 8e-07,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net4,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net4,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net7,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net6,
N => net4
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => W_1,
W_1init => 6.03e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.39e-05,
scope => private
)
port map(
D => net7,
G => vref,
S => net5
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.9e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 4.39e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => net5
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 7.15e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.35e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 7.15e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.35e-06,
scope => private
)
port map(
D => net7,
G => net6,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 3.55e-06,
W => Wcmbias_0,
Wcmbias_0init => 2.465e-05,
scope => private
)
port map(
D => out1,
G => net7,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 3.55e-06,
W => Wcmbias_0,
Wcmbias_0init => 2.465e-05,
scope => private
)
port map(
D => out2,
G => net7,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.22e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.22e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 2.22e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 2.22e-05
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 2.22e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 2.22e-05
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d536aaa5f91c013ab7e1b74f424e8b4f | 0.573961 | 2.901485 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom/simulation/rom_tb.vhd | 1 | 4,325 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: rom_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY rom_tb IS
END ENTITY;
ARCHITECTURE rom_tb_ARCH OF rom_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
rom_synth_inst:ENTITY work.rom_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | fc53c7cd2ae73af24d6ad3aa3429a248 | 0.617803 | 4.650538 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_dgen.vhd | 1 | 5,007 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_GAUSS_COE_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF ROM_GAUSS_COE_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.ROM_GAUSS_COE_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-3.0 | 23d60759758912c1568b9a89352bf75b | 0.594767 | 4.127782 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op975_5.vhdl | 1 | 4,520 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net4
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 5b92378db793dc1ed9f126275cc74a6c | 0.584071 | 3.214794 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/example_design/vram_prod.vhd | 1 | 10,495 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: vram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 7168
-- C_READ_DEPTH_A : 7168
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 7168
-- C_READ_DEPTH_B : 7168
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY vram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END vram_prod;
ARCHITECTURE xilinx OF vram_prod IS
COMPONENT vram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : vram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | 607e587d3ca1826b7a08940c942f0901 | 0.489185 | 3.838698 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_3.vhdl | 1 | 5,055 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6b26b64f82b69b1209422284bf683586 | 0.579228 | 3.173258 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4_u1.vhd | 5 | 14,386 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4_u1 is
generic (
g_simulation : boolean := false;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
ETH_Acc_Time : integer := 9;
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 4;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
ETH_CSn : out std_logic := '1';
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z');
MEM_BEn : out std_logic );
end ext_mem_ctrl_v4_u1;
-- ADDR: 25 24 23 22 21 20 19 ...
-- 0 0 0 0 0 0 0 SRAM
-- 0 x x x x x x SDRAM
-- 1 0 x x x x x Flash
-- 1 1 x x x x x Ethernet
architecture Gideon of ext_mem_ctrl_v4_u1 is
type t_init is record
addr : std_logic_vector(23 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"000400", "010" ), -- auto precharge
( X"000220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ), -- auto refresh
( X"000000", "001" ) );
type t_state is (boot, init, idle, setup, pulse, hold, sd_cas, sd_wait, eth_pulse);
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(7 downto 0);
signal memsel : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal dack : std_logic; -- for simulation handy to see
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
resp.data <= rdata_i;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
resp.rack <= '1';
resp.rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
mem_a_i <= std_logic_vector(req.address(MEM_A'range));
sram_d_t <= not req.read_writen;
sram_d_o <= req.data;
SRAM_CSn <= '1';
FLASH_CSn <= '1';
ETH_CSn <= '1';
SDRAM_CSn <= '1';
memsel <= '0';
if req.address(25 downto 24) = "11" then
ETH_CSn <= '0';
delay <= ETH_Acc_Time;
state <= eth_pulse;
elsif req.address(25 downto 24) = "10" then
memsel <= '1';
FLASH_CSn <= '0';
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if req.read_writen='0' then -- write
MEM_BEn <= '0';
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif req.address(25 downto 19)=0 then
SRAM_CSn <= '0';
if req.read_writen='0' then -- write
MEM_BEn <= '0';
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= '0';
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
else -- SDRAM
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(17 downto 16) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end if;
end procedure;
begin
if rising_edge(clock) then
resp.rack <= '0';
dack <= '0';
resp.rack_tag <= (others => '0');
resp.dack_tag <= (others => '0');
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
send_refresh_cmd;
elsif inhibit='0' then
if req.request='1' and refr_delay=0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
if rwn_i='1' then
dack <= '1';
resp.dack_tag <= tag;
end if;
if memsel='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when eth_pulse =>
delay <= delay - 1;
case delay is
when 2 =>
dack <= '1';
resp.dack_tag <= tag;
MEM_WEn <= '1';
MEM_OEn <= '1';
when 1 =>
sram_d_t <= '0';
ETH_CSn <= '1';
state <= idle;
when others =>
MEM_WEn <= rwn_i;
MEM_OEn <= not rwn_i;
end case;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
ETH_CSn <= '1';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
MEM_BEn <= '1';
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 2c06a790e5138eb755540da3dd3723ec | 0.429862 | 3.647566 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op978_7.vhdl | 1 | 5,054 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | ba4445ef67f87c4bbc93153d552df9c7 | 0.579145 | 3.17263 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op337_11sk1_0.vhdl | 1 | 7,981 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => W_0,
W_0init => 7.525e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.35e-06,
W => Wcm_1,
Wcm_1init => 3.75e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.35e-06,
W => Wcmout_1,
Wcmout_1init => 3.575e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.12e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.12e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 46fd5ee2eb1b79f7eccd4f9c2fef31c6 | 0.581381 | 2.858524 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/command_interface/vhdl_source/command_interface.vhd | 3 | 3,296 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get an 8K range
io_resp : out t_io_resp );
end entity;
architecture gideon of command_interface is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal io_ram_en : std_logic;
signal io_ram_rdata : std_logic_vector(7 downto 0);
signal io_ram_ack : std_logic;
signal b_address : unsigned(10 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0);
signal b_en : std_logic;
signal b_we : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
process(clock)
begin
if rising_edge(clock) then
io_ram_ack <= io_ram_en;
end if;
end process;
io_ram_en <= io_req_ram.read or io_req_ram.write;
io_resp_ram.data <= X"00" when io_ram_ack='0' else io_ram_rdata;
io_resp_ram.ack <= io_ram_ack;
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(10 downto 0),
a_rdata => io_ram_rdata,
a_wdata => io_req_ram.data,
a_en => io_ram_en,
a_we => io_req_ram.write,
b_clock => clock,
b_address => b_address,
b_rdata => b_rdata,
b_wdata => b_wdata,
b_en => b_en,
b_we => b_we );
i_protocol: entity work.command_protocol
port map (
clock => clock,
reset => reset,
-- Local CPU side
io_req => io_req_regs,
io_resp => io_resp_regs,
-- slot
slot_req => slot_req,
slot_resp => slot_resp,
freeze => freeze,
-- memory
address => b_address,
rdata => b_rdata,
wdata => b_wdata,
en => b_en,
we => b_we );
end architecture;
| gpl-3.0 | 8441a1fe5ecb2f6a91dc43dae2ff0696 | 0.45449 | 3.47313 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_syn/ulpi_host_wrap.vhd | 3 | 4,552 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity ulpi_host_wrap is
port (
clock : in std_logic;
reset : in std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
do_reset : out std_logic;
reset_done : in std_logic;
speed : in std_logic_vector(1 downto 0);
reset_pkt : in std_logic;
reset_data : in std_logic_vector(7 downto 0);
reset_last : in std_logic;
reset_valid : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end ulpi_host_wrap;
architecture wrap of ulpi_host_wrap is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
begin
i_mut: entity work.ulpi_host
port map (
clock => clock,
reset => reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to bus initialization unit
do_reset => do_reset,
reset_done => reset_done,
speed => speed,
reset_pkt => reset_pkt,
reset_data => reset_data,
reset_last => reset_last,
reset_valid => reset_valid,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S36
port map (
CLK => clock,
SSR => reset,
EN => descr_en,
WE => descr_we,
ADDR => descr_addr,
DI => descr_wdata,
DIP => X"0",
DO => descr_rdata );
i_buf_ram: RAMB16_S9
port map (
CLK => clock,
SSR => reset,
EN => buf_en,
WE => buf_we,
ADDR => buf_addr(10 downto 0),
DI => buf_wdata,
DIP => "0",
DO => buf_rdata );
end wrap;
| gpl-3.0 | dddcfaa83f3095951f182b65622e4478 | 0.506591 | 3.553474 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op332_1.vhdl | 1 | 4,729 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fe8c69052dfcdfa2040c5f11e90587e2 | 0.580038 | 3.186658 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/PointBuffer.vhd | 1 | 2,599 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F9LRRL
-- /___/ /\ Timestamp : 04/06/2014 00:33:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity PointBuffer is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
pointSet : out T_POINT_SET
);
end PointBuffer;
architecture BEHAVIORAL of PointBuffer is
signal sPointSet: T_POINT_SET := (others => (others => '0'));
signal counter: integer range 0 to N_POINTS-1 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= 0;
enableOut <= '0';
sPointSet <= (others => (others => '0'));
else
if enableIn = '1' then
sPointSet(0) <= inputValue;
for i in 1 to N_POINTS-1 loop
sPointSet(i) <= sPointSet(i-1);
end loop;
if counter = N_POINTS-1 then
counter <= 0;
enableOut <= '1';
else
counter <= counter+1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
pointSet <= sPointSet;
end BEHAVIORAL;
| gpl-3.0 | 1d81260ce1a7503b5f30aa3c7457c06e | 0.581377 | 3.419737 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op992_13.vhdl | 1 | 6,129 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4a57e5c39c49188700f718f1ded6183d | 0.570566 | 3.076807 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_io_regs_pkg.vhd | 5 | 2,668 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_io_regs_pkg is
constant c_sid_voices : unsigned(3 downto 0) := X"0";
constant c_sid_filter_div : unsigned(3 downto 0) := X"1";
constant c_sid_base_left : unsigned(3 downto 0) := X"2";
constant c_sid_base_right : unsigned(3 downto 0) := X"3";
constant c_sid_snoop_left : unsigned(3 downto 0) := X"4";
constant c_sid_snoop_right : unsigned(3 downto 0) := X"5";
constant c_sid_enable_left : unsigned(3 downto 0) := X"6";
constant c_sid_enable_right : unsigned(3 downto 0) := X"7";
constant c_sid_extend_left : unsigned(3 downto 0) := X"8";
constant c_sid_extend_right : unsigned(3 downto 0) := X"9";
constant c_sid_wavesel_left : unsigned(3 downto 0) := X"A";
constant c_sid_wavesel_right : unsigned(3 downto 0) := X"B";
type t_sid_control is record
base_left : unsigned(11 downto 4);
snoop_left : std_logic;
enable_left : std_logic;
extend_left : std_logic;
comb_wave_left : std_logic;
base_right : unsigned(11 downto 4);
snoop_right : std_logic;
enable_right : std_logic;
extend_right : std_logic;
comb_wave_right : std_logic;
end record;
constant c_sid_control_init : t_sid_control := (
base_left => X"40",
snoop_left => '1',
enable_left => '1',
extend_left => '0',
comb_wave_left => '0',
base_right => X"40",
snoop_right => '1',
enable_right => '1',
extend_right => '0',
comb_wave_right => '0' );
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 7...1 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 4...1 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 4...3 are significant)
-- .. etc
end package;
| gpl-3.0 | 736b49c843e35bd47e3f754742554e23 | 0.513493 | 3.447028 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op324_2.vhdl | 1 | 3,737 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | c9956dbf4fcd4346e24fe57084a54ceb | 0.590313 | 3.310009 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_9sk1_0.vhdl | 1 | 6,252 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.1e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.1e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => W_0,
W_0init => 7.025e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.25e-06,
W => Wcm_2,
Wcm_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.25e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.865e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.25e-06,
W => Wcm_2,
Wcm_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.25e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.865e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcm_1,
Wcm_1init => 7.2e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcmout_1,
Wcmout_1init => 2.97e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => (pfak)*(WBias),
WBiasinit => 8.15e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5e-07,
W => (pfak)*(WBias),
WBiasinit => 8.15e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 8.15e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 8.15e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 8.15e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 8.15e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | ee6fe41f81421fdc9b09940a2feaf35f | 0.584293 | 2.953236 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_0sk1_0.vhdl | 1 | 7,067 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.4e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.4e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => W_0,
W_0init => 3.3e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.4e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 5.4e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.3e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.3e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.3e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.3e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 3.6e-06,
W => Wsrc_2,
Wsrc_2init => 4.45e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 3.6e-06,
W => Wsrc_2,
Wsrc_2init => 4.45e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.05e-06,
W => Wcm_1,
Wcm_1init => 9.9e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.05e-06,
W => Wcmout_1,
Wcmout_1init => 6.77e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => (pfak)*(WBias),
WBiasinit => 1.65e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.8e-06,
W => (pfak)*(WBias),
WBiasinit => 1.65e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.65e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.65e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.65e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.65e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 3dba3ec7d23964a603cfd1653ad7dcb9 | 0.581293 | 2.875102 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_sim/usb_test_nano1.vhd | 1 | 6,061 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 1 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
entity usb_test_nano1 is
end entity;
architecture arch of usb_test_nano1 is
signal clocks_stopped : boolean := false;
constant Command : unsigned(19 downto 0) := X"007E0";
constant Command_DevEP : unsigned(19 downto 0) := X"007E2";
constant Command_Length : unsigned(19 downto 0) := X"007E4";
constant Command_MaxTrans : unsigned(19 downto 0) := X"007E6";
constant Command_MemHi : unsigned(19 downto 0) := X"007E8";
constant Command_MemLo : unsigned(19 downto 0) := X"007EA";
constant Command_SplitCtl : unsigned(19 downto 0) := X"007EC";
constant Command_Result : unsigned(19 downto 0) := X"007EE";
constant c_rx_size : integer := 4096 + 512;
constant c_tx_size : integer := 4096 + 512;
begin
i_harness: entity work.usb_harness_nano
port map (
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable start, stop : time;
variable transferred : integer;
variable micros, kbps : real;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 1), data => word(7 downto 0));
io_write(io => io, addr => (addr + 0), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 1), data => word(7 downto 0));
io_read(io => io, addr => (addr + 0), data => word(15 downto 8));
end procedure;
procedure wait_command_done is
begin
L1: while true loop
io_read(io => io, addr => Command, data => res);
if res = X"00" then
exit L1;
end if;
end loop;
end procedure;
begin
bind_io_bus_bfm("io", io);
sctb_open_simulation("path:path", "usb_test_nano1.tcr");
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write(io => io, addr => X"007fe", data => X"01" ); -- set nano to simulation mode
io_write(io => io, addr => X"007fd", data => X"02" ); -- set bus speed to HS
io_write(io => io, addr => X"00800", data => X"01" ); -- enable nano
wait for 4 us;
io_write_word(Command_DevEP, X"0000");
io_write_word(Command_MaxTrans, X"0040");
io_write_word(Command_MemHi, X"0004");
io_write_word(Command_MemLo, X"132A");
io_write_word(Command_Length, X"0008");
io_write_word(Command, X"8040"); -- setup with mem read
wait_command_done;
sctb_close_region;
sctb_open_region("Testing In request", 0);
io_write_word(Command_DevEP, X"0006");
io_write_word(Command_Length, X"0FFF");
io_write_word(Command, X"4042"); -- in with mem write
wait_command_done;
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length, data);
transferred := 4095 - to_integer(signed(data));
sctb_trace("Transferred: " & integer'image(transferred));
sctb_assert(transferred = 139, "Expected 4096 bytes.");
start := now;
io_write_word(Command_MaxTrans, X"0200");
io_write_word(Command_DevEP, X"0004");
io_write_word(Command_Length, std_logic_vector(to_unsigned(c_rx_size, 16)));
io_write_word(Command, X"4042"); -- in with mem write
wait_command_done;
stop := now;
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length, data);
transferred := c_rx_size - to_integer(signed(data));
sctb_trace("Transferred: " & integer'image(transferred));
sctb_check(transferred, c_rx_size, "Expected c_rx_size bytes.");
micros := real((stop - start) / 1.0 us);
kbps := (real(transferred) * 1000.0) / micros;
sctb_trace("Got " & integer'image(integer(kbps)) & " KB/s");
sctb_close_region;
sctb_open_region("Testing Out request", 0);
start := now;
io_write_word(Command_MemHi, X"0001");
io_write_word(Command_MemLo, X"0402");
io_write_word(Command_MaxTrans, X"0200");
io_write_word(Command_DevEP, X"0005");
io_write_word(Command_Length, std_logic_vector(to_unsigned(c_tx_size, 16)));
io_write_word(Command, X"8041"); -- out with mem read
wait_command_done;
stop := now;
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
io_read_word(Command_Length, data);
transferred := c_tx_size - to_integer(signed(data));
sctb_trace("Transferred: " & integer'image(transferred));
sctb_check(transferred, c_tx_size, "Expected to send c_tx_size bytes.");
micros := real((stop - start) / 1.0 us);
kbps := (real(transferred) * 1000.0) / micros;
sctb_trace("Got " & integer'image(integer(kbps)) & " KB/s");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
| gpl-3.0 | 4eb83e6b378ada4a6412d29d75100801 | 0.560799 | 3.503468 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/spram.vhd | 5 | 1,660 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
address : in unsigned(g_depth_bits-1 downto 0);
rdata : out std_logic_vector(g_width_bits-1 downto 0);
wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
en : in std_logic := '1';
we : in std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of spram : entity is "yes";
end entity;
architecture xilinx of spram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_port: process(clock)
begin
if rising_edge(clock) then
if en = '1' then
if g_read_first then
rdata <= ram(to_integer(address));
end if;
if we = '1' then
ram(to_integer(address)) := wdata;
end if;
if not g_read_first then
rdata <= ram(to_integer(address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 768e56066a69238aeee0a2885a4f8a59 | 0.516265 | 3.833718 | false | false | false | false |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/tbOpenMAC.vhd | 1 | 22,541 | -------------------------------------------------------------------------------
-- Entity : openMAC Testbench
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use global.all;
entity tbOpenMAC is
end tbOpenMAC;
architecture bhv of tbOpenMAC is
---- Component declarations -----
component busMaster
generic(
gAddrWidth : integer := 32;
gDataWidth : integer := 32;
gStimuliFile : string := "name_TB_stim.txt"
);
port (
iAck : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iRst : in std_logic;
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oByteenable : out std_logic_vector(gDataWidth/8-1 downto 0);
oDone : out std_logic;
oRead : out std_logic;
oSelect : out std_logic;
oWrite : out std_logic;
oWritedata : out std_logic_vector(gDataWidth-1 downto 0)
);
end component;
component clkgen
generic(
gPeriod : time := 20 ns
);
port (
iDone : in std_logic;
oClk : out std_logic
);
end component;
component edgeDet
port (
clk : in std_logic;
din : in std_logic;
rst : in std_logic;
any : out std_logic;
falling : out std_logic;
rising : out std_logic
);
end component;
component enableGen
generic(
gEnableDelay : time := 100 ns
);
port (
iReset : in std_logic;
oEnable : out std_logic;
onEnable : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component openmac_ethernet
generic(
dma_highadr_g : integer := 31;
endian_g : string := "little";
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
genHub_g : boolean := false;
genPhyActLed_g : boolean := false;
genSmiIO : boolean := true;
gen_dma_observer_g : boolean := true;
iPktBufSizeLog2_g : integer := 10;
iPktBufSize_g : integer := 1024;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
simulate : boolean := false;
useIntPktBuf_g : boolean := false;
useRmii_g : boolean := true;
useRxIntPktBuf_g : boolean := false
);
port (
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0) := (others => '0');
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
pkt_writedata : in std_logic_vector(31 downto 0);
rst : in std_logic;
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_en : out std_logic;
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii0_tx_en : out std_logic;
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_readdata : out std_logic_vector(31 downto 0);
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_readdata : out std_logic_vector(15 downto 0);
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_readdata : out std_logic_vector(31 downto 0);
t_tog : out std_logic;
t_waitrequest : out std_logic;
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
---- Architecture declarations -----
-- Click here to add additional declarations --
constant cAddrwidth : integer := 32;
constant cDatawidth : integer := 16;
constant cEnableLoop : boolean := true;
constant cRmiiDelayExp : integer := 20; -- 2**10
constant cGenManCol : boolean := false; --collision with manual tx frame
constant cGenAutoCol : boolean := false; --collision with auto tx frame
constant cDmaDataWidth : integer := 32;
constant cDmaBurstWidth : integer := 6;
---- Constants -----
constant DANGLING_INPUT_CONSTANT : std_logic := 'Z';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ack : std_logic;
signal busMasterDone : std_logic;
signal clk100 : std_logic;
signal clk50 : std_logic;
signal done : std_logic := '1';
signal enable : std_logic;
signal fifo_rd_empty : std_logic;
signal fifo_rd_req : std_logic;
signal fifo_wr_req : std_logic;
signal fifo_wr_req_falling : std_logic;
signal GND : std_logic;
signal macDone : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET799 : std_logic;
signal NET808 : std_logic;
signal phy0_rx_dv : std_logic;
signal phy0_rx_err : std_logic;
signal phy0_tx_en : std_logic;
signal phy1_rx_dv : std_logic;
signal phy1_rx_err : std_logic;
signal phy1_tx_en : std_logic;
signal read : std_logic;
signal reset : std_logic;
signal rst : std_logic;
signal sel : std_logic;
signal s_chipselect : std_logic;
signal s_read : std_logic;
signal s_waitrequest : std_logic;
signal s_write : std_logic;
signal write : std_logic;
signal address : std_logic_vector (cAddrwidth-1 downto 0);
signal byteenable : std_logic_vector (cDatawidth/8-1 downto 0);
signal fifo_rd_data : std_logic_vector (1 downto 0);
signal fifo_rd_usedw : std_logic_vector (cRmiiDelayExp-1 downto 0);
signal fifo_wr_data : std_logic_vector (1 downto 0);
signal fifo_wr_done : std_logic_vector (31 downto 0);
signal m_burstcount : std_logic_vector (cDmaBurstWidth-1 downto 0);
signal m_burstcounter : std_logic_vector (cDmaBurstWidth-1 downto 0);
signal phy0_rx_dat : std_logic_vector (1 downto 0);
signal phy0_tx_dat : std_logic_vector (1 downto 0);
signal phy1_rx_dat : std_logic_vector (1 downto 0);
signal phy1_tx_dat : std_logic_vector (1 downto 0);
signal readdata : std_logic_vector (cDatawidth-1 downto 0);
signal s_address : std_logic_vector (11 downto 0);
signal s_byteenable : std_logic_vector (1 downto 0);
signal s_readdata : std_logic_vector (15 downto 0);
signal s_writedata : std_logic_vector (15 downto 0);
signal writedata : std_logic_vector (cDatawidth-1 downto 0);
---- Declaration for Dangling input ----
signal Dangling_Input_Signal : STD_LOGIC;
begin
---- User Signal Assignments ----
--generate done signal
done <= busMasterDone and macDone;
--mac
macDone <= '1';
-- write
s_chipselect <= sel;
s_read <= read;
s_write <= write;
s_address <= address(s_address'high+1 downto 1);
s_byteenable <= byteenable;
s_writedata <= writedata;
-- read
readdata <= s_readdata;
ack <= not s_waitrequest;
--master
m_waitrequest <= not(m_read or m_write);
m_readdatavalid <= '0' when unsigned(m_burstcounter) = 0 or m_write = '1' else not m_read;
--phy if
genNoRx : if not cEnableLoop generate
begin
phy0_rx_dv <= '0';
phy0_rx_err <= '0';
phy0_rx_dat <= "00";
end generate;
phy1_rx_dv <=
phy0_tx_en after 2500 ns when cGenManCol else
phy0_tx_en after 2500 ns when cGenAutoCol and unsigned(fifo_wr_done) = 1 else
'0';
phy1_rx_err <= '0';
phy1_rx_dat <=
phy0_tx_dat after 2500 ns when cGenManCol else
phy0_tx_dat after 2500 ns when cGenAutoCol and unsigned(fifo_wr_done) = 1 else
"00";
fifo_wr_req <= phy0_tx_en;
genLoop : if cEnableLoop generate
begin
fifo_wr_data <= phy0_tx_dat;
phy0_rx_dv <= fifo_rd_req;
phy0_rx_dat <= fifo_rd_data(1 downto 0);
phy0_rx_err <= '0';
end generate;
procFifoRdReq : process(clk50, reset)
begin
if reset = '1' then
fifo_rd_req <= '0';
fifo_wr_done <= (others => '0');
elsif rising_edge(clk50) then
if fifo_rd_empty = '1' then
fifo_rd_req <= '0';
elsif fifo_wr_req_falling = '1' then
fifo_rd_req <= '1' after 1 us;
fifo_wr_done <= std_logic_vector(unsigned(fifo_wr_done) + 1);
-- elsif unsigned(fifo_rd_usedw) > 106 and unsigned(fifo_wr_done) = 0 then
-- fifo_rd_req <= '1'; -- after 1 us;
-- fifo_wr_done <= std_logic_vector(unsigned(fifo_wr_done) + 1);
end if;
end if;
end process;
---- Component instantiations ----
DUT : openmac_ethernet
generic map (
dma_highadr_g => 29,
endian_g => "little",
gNumSmi => 2,
gen2ndCmpTimer_g => false,
genHub_g => true,
genPhyActLed_g => false,
genSmiIO => true,
gen_dma_observer_g => true,
iPktBufSizeLog2_g => 10,
iPktBufSize_g => 1024,
m_burstcount_const_g => true,
m_burstcount_width_g => cDmaBurstWidth,
m_data_width_g => cDmaDataWidth,
m_rx_burst_size_g => 2**(cDmaBurstWidth-1),
m_rx_fifo_size_g => 3*2**cDmaBurstWidth,
m_tx_burst_size_g => 2**(cDmaBurstWidth-1),
m_tx_fifo_size_g => 3*2**cDmaBurstWidth,
simulate => false,
useIntPktBuf_g => false,
useRmii_g => true,
useRxIntPktBuf_g => false
)
port map(
phyMii0_rx_dat(0) => Dangling_Input_Signal,
phyMii0_rx_dat(1) => Dangling_Input_Signal,
phyMii0_rx_dat(2) => Dangling_Input_Signal,
phyMii0_rx_dat(3) => Dangling_Input_Signal,
phyMii1_rx_dat(0) => Dangling_Input_Signal,
phyMii1_rx_dat(1) => Dangling_Input_Signal,
phyMii1_rx_dat(2) => Dangling_Input_Signal,
phyMii1_rx_dat(3) => Dangling_Input_Signal,
pkt_byteenable(0) => Dangling_Input_Signal,
pkt_byteenable(1) => Dangling_Input_Signal,
pkt_byteenable(2) => Dangling_Input_Signal,
pkt_byteenable(3) => Dangling_Input_Signal,
pkt_writedata(0) => Dangling_Input_Signal,
pkt_writedata(1) => Dangling_Input_Signal,
pkt_writedata(2) => Dangling_Input_Signal,
pkt_writedata(3) => Dangling_Input_Signal,
pkt_writedata(4) => Dangling_Input_Signal,
pkt_writedata(5) => Dangling_Input_Signal,
pkt_writedata(6) => Dangling_Input_Signal,
pkt_writedata(7) => Dangling_Input_Signal,
pkt_writedata(8) => Dangling_Input_Signal,
pkt_writedata(9) => Dangling_Input_Signal,
pkt_writedata(10) => Dangling_Input_Signal,
pkt_writedata(11) => Dangling_Input_Signal,
pkt_writedata(12) => Dangling_Input_Signal,
pkt_writedata(13) => Dangling_Input_Signal,
pkt_writedata(14) => Dangling_Input_Signal,
pkt_writedata(15) => Dangling_Input_Signal,
pkt_writedata(16) => Dangling_Input_Signal,
pkt_writedata(17) => Dangling_Input_Signal,
pkt_writedata(18) => Dangling_Input_Signal,
pkt_writedata(19) => Dangling_Input_Signal,
pkt_writedata(20) => Dangling_Input_Signal,
pkt_writedata(21) => Dangling_Input_Signal,
pkt_writedata(22) => Dangling_Input_Signal,
pkt_writedata(23) => Dangling_Input_Signal,
pkt_writedata(24) => Dangling_Input_Signal,
pkt_writedata(25) => Dangling_Input_Signal,
pkt_writedata(26) => Dangling_Input_Signal,
pkt_writedata(27) => Dangling_Input_Signal,
pkt_writedata(28) => Dangling_Input_Signal,
pkt_writedata(29) => Dangling_Input_Signal,
pkt_writedata(30) => Dangling_Input_Signal,
pkt_writedata(31) => Dangling_Input_Signal,
t_address(0) => Dangling_Input_Signal,
t_address(1) => Dangling_Input_Signal,
t_byteenable(0) => Dangling_Input_Signal,
t_byteenable(1) => Dangling_Input_Signal,
t_byteenable(2) => Dangling_Input_Signal,
t_byteenable(3) => Dangling_Input_Signal,
t_writedata(0) => Dangling_Input_Signal,
t_writedata(1) => Dangling_Input_Signal,
t_writedata(2) => Dangling_Input_Signal,
t_writedata(3) => Dangling_Input_Signal,
t_writedata(4) => Dangling_Input_Signal,
t_writedata(5) => Dangling_Input_Signal,
t_writedata(6) => Dangling_Input_Signal,
t_writedata(7) => Dangling_Input_Signal,
t_writedata(8) => Dangling_Input_Signal,
t_writedata(9) => Dangling_Input_Signal,
t_writedata(10) => Dangling_Input_Signal,
t_writedata(11) => Dangling_Input_Signal,
t_writedata(12) => Dangling_Input_Signal,
t_writedata(13) => Dangling_Input_Signal,
t_writedata(14) => Dangling_Input_Signal,
t_writedata(15) => Dangling_Input_Signal,
t_writedata(16) => Dangling_Input_Signal,
t_writedata(17) => Dangling_Input_Signal,
t_writedata(18) => Dangling_Input_Signal,
t_writedata(19) => Dangling_Input_Signal,
t_writedata(20) => Dangling_Input_Signal,
t_writedata(21) => Dangling_Input_Signal,
t_writedata(22) => Dangling_Input_Signal,
t_writedata(23) => Dangling_Input_Signal,
t_writedata(24) => Dangling_Input_Signal,
t_writedata(25) => Dangling_Input_Signal,
t_writedata(26) => Dangling_Input_Signal,
t_writedata(27) => Dangling_Input_Signal,
t_writedata(28) => Dangling_Input_Signal,
t_writedata(29) => Dangling_Input_Signal,
t_writedata(30) => Dangling_Input_Signal,
t_writedata(31) => Dangling_Input_Signal,
clk => clk50,
clkx2 => clk100,
m_burstcount => m_burstcount( cDmaBurstWidth-1 downto 0 ),
m_burstcounter => m_burstcounter( cDmaBurstWidth-1 downto 0 ),
m_clk => clk100,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
phy0_rx_dat => phy0_rx_dat,
phy0_rx_dv => phy0_rx_dv,
phy0_rx_err => phy0_rx_err,
phy0_smi_dio_I => Dangling_Input_Signal,
phy0_tx_dat => phy0_tx_dat,
phy0_tx_en => phy0_tx_en,
phy1_rx_dat => phy1_rx_dat,
phy1_rx_dv => phy1_rx_dv,
phy1_rx_err => phy1_rx_err,
phy1_smi_dio_I => Dangling_Input_Signal,
phy1_tx_dat => phy1_tx_dat,
phy1_tx_en => phy1_tx_en,
phyMii0_rx_clk => Dangling_Input_Signal,
phyMii0_rx_dv => Dangling_Input_Signal,
phyMii0_rx_err => Dangling_Input_Signal,
phyMii0_tx_clk => Dangling_Input_Signal,
phyMii1_rx_clk => Dangling_Input_Signal,
phyMii1_rx_dv => Dangling_Input_Signal,
phyMii1_rx_err => Dangling_Input_Signal,
phyMii1_tx_clk => Dangling_Input_Signal,
phy_smi_dio_I => Dangling_Input_Signal,
pkt_chipselect => Dangling_Input_Signal,
pkt_clk => Dangling_Input_Signal,
pkt_read => Dangling_Input_Signal,
pkt_write => Dangling_Input_Signal,
rst => reset,
s_address => s_address,
s_byteenable => s_byteenable,
s_chipselect => s_chipselect,
s_read => s_read,
s_readdata => s_readdata,
s_waitrequest => s_waitrequest,
s_write => s_write,
s_writedata => s_writedata,
t_chipselect => Dangling_Input_Signal,
t_read => Dangling_Input_Signal,
t_write => Dangling_Input_Signal
);
RMII_DELAY : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => 2,
fifo_word_size_g => 2**cRmiiDelayExp,
fifo_word_size_log2_g => cRmiiDelayExp
)
port map(
aclr => reset,
rd_clk => clk50,
rd_data => fifo_rd_data( 1 downto 0 ),
rd_empty => fifo_rd_empty,
rd_req => fifo_rd_req,
rd_usedw => fifo_rd_usedw( cRmiiDelayExp-1 downto 0 ),
wr_clk => clk50,
wr_data => fifo_wr_data( 1 downto 0 ),
wr_req => fifo_wr_req
);
TRIG_READ : edgeDet
port map(
clk => clk50,
din => fifo_wr_req,
falling => fifo_wr_req_falling,
rst => rst
);
U1 : clkgen
generic map (
gPeriod => 20 ns
)
port map(
iDone => done,
oClk => clk50
);
U2 : enableGen
generic map (
gEnableDelay => 50 ns
)
port map(
iReset => GND,
onEnable => reset
);
U3 : enableGen
generic map (
gEnableDelay => 100 ns
)
port map(
iReset => reset,
oEnable => enable
);
U4 : busMaster
generic map (
gAddrWidth => cAddrwidth,
gDataWidth => cDatawidth,
gStimuliFile => "openMAC/tb/tbOpenMAC_stim.txt"
)
port map(
iAck => ack,
iClk => clk50,
iEnable => enable,
iReaddata => readdata( cDatawidth-1 downto 0 ),
iRst => reset,
oAddress => address( cAddrwidth-1 downto 0 ),
oByteenable => byteenable( cDatawidth/8-1 downto 0 ),
oDone => busMasterDone,
oRead => read,
oSelect => sel,
oWrite => write,
oWritedata => writedata( cDatawidth-1 downto 0 )
);
U5 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => NET799,
clk => clk50,
enable => write,
rst => reset
);
U6 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => NET808,
clk => clk50,
enable => read,
rst => reset
);
ack <= NET808 or NET799;
U8 : clkgen
generic map (
gPeriod => 10 ns
)
port map(
iDone => done,
oClk => clk100
);
---- Power , ground assignment ----
GND <= GND_CONSTANT;
---- Dangling input signal assignment ----
Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT;
end bhv;
| gpl-2.0 | a30fd2bef2677c142d4587d1b43fb506 | 0.614835 | 3.236324 | false | false | false | false |
KB777/1541UltimateII | fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v5_tb.vhd | 3 | 4,834 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_tb is
end ext_mem_ctrl_v5_tb;
architecture tb of ext_mem_ctrl_v5_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_req_32;
signal resp : t_mem_resp_32;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clk_2x <= not clk_2x after 5 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_A => logic_A,
SDRAM_BA => logic_BA,
SDRAM_DQ => SDRAM_DQ );
SDRAM_A <= transport logic_A after 6 ns;
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_req_32_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '1'; -- read
req.read_writen <= '0'; -- write
req.request <= '1';
req.size <= '1';
req.data <= X"44332211";
req.byte_en <= "0111";
req.tag <= X"34";
while true loop
wait until clock='1';
if resp.rack='1' then
if req.read_writen = '0' then
req.address <= req.address + 4;
end if;
req.read_writen <= not req.read_writen;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Qd(0)='Z' then
SDRAM_DQ <= Qd after 3.6 ns;
else
SDRAM_DQ <= Qd after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
| gpl-3.0 | 04fefd6686fb83cce6ae0d61e897bd1a | 0.459661 | 3.753106 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate2.vhd | 1 | 4,416 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate2.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate2 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altaccumulate2;
ARCHITECTURE SYN OF altaccumulate2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 16,
width_out => 32
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2_inst.vhd TRUE
| gpl-2.0 | 8013b0a18166026484587e296cbb75e9 | 0.653986 | 3.787307 | false | false | false | false |
chrismasters/fpga-space-invaders | project/registerarray.vhd | 1 | 3,350 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- selector encoding
-- 00000001 - B
-- 00000010 - C
-- 00000100 - D
-- 00001000 - E
-- 00010000 - H
-- 00100000 - L
-- 00000011 - BC
-- 00001100 - DE
-- 00110000 - HL
-- 01000000 - SP
-- 10000000 - PC
entity RegisterArray is
Port (
clk : in STD_LOGIC;
selector : in STD_LOGIC_VECTOR (7 downto 0);
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
dataOut : out STD_LOGIC_VECTOR (15 downto 0);
load : in STD_LOGIC
);
end RegisterArray;
architecture Behavioral of RegisterArray is
COMPONENT OneByteRegister
PORT(
clk : IN std_logic;
load : IN std_logic;
dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT DoubleByteRegister
PORT(
clk : IN std_logic;
load : IN std_logic;
dataIn : IN std_logic_vector(15 downto 0);
dataOut : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal bIn : std_logic_vector(7 downto 0);
signal cIn : std_logic_vector(7 downto 0);
signal dIn : std_logic_vector(7 downto 0);
signal eIn : std_logic_vector(7 downto 0);
signal hIn : std_logic_vector(7 downto 0);
signal lIn : std_logic_vector(7 downto 0);
signal spIn : std_logic_vector(15 downto 0);
--signal pcIn : std_logic_vector(15 downto 0);
signal bOut : std_logic_vector(7 downto 0);
signal cOut : std_logic_vector(7 downto 0);
signal dOut : std_logic_vector(7 downto 0);
signal eOut : std_logic_vector(7 downto 0);
signal hOut : std_logic_vector(7 downto 0);
signal lOut : std_logic_vector(7 downto 0);
signal spOut : std_logic_vector(15 downto 0);
begin
dataOut <=
"00000000" & bOut when selector = "00000001" else
"00000000" & cOut when selector = "00000010" else
"00000000" & dOut when selector = "00000100" else
"00000000" & eOut when selector = "00001000" else
"00000000" & hOut when selector = "00010000" else
"00000000" & lOut when selector = "00100000" else
bOut & cOut when selector = "00000011" else
dOut & eOut when selector = "00001100" else
hOut & lOut when selector = "00110000" else
spOut when selector = "01000000" else
--pcOut when selector = "10000000" else
(others => '0');
bIn <= dataIn(15 downto 8) when selector(0) = '1' and selector(1) = '1' else dataIn(7 downto 0);
cIn <= dataIn(7 downto 0);
dIn <= dataIn(15 downto 8) when selector(2) = '1' and selector(3) = '1' else dataIn(7 downto 0);
eIn <= dataIn(7 downto 0);
hIn <= dataIn(15 downto 8) when selector(4) = '1' and selector(5) = '1' else dataIn(7 downto 0);
lIn <= dataIn(7 downto 0);
b: OneByteRegister PORT MAP(clk => clk, load => load and selector(0), dataIn => bIn, dataOut => bOut);
c: OneByteRegister PORT MAP(clk => clk, load => load and selector(1), dataIn => cIn, dataOut => cOut);
d: OneByteRegister PORT MAP(clk => clk, load => load and selector(2), dataIn => dIn, dataOut => dOut);
e: OneByteRegister PORT MAP(clk => clk, load => load and selector(3), dataIn => eIn, dataOut => eOut);
h: OneByteRegister PORT MAP(clk => clk, load => load and selector(4), dataIn => hIn, dataOut => hOut);
l: OneByteRegister PORT MAP(clk => clk, load => load and selector(5), dataIn => lIn, dataOut => lOut);
sp: DoubleByteRegister PORT MAP(clk => clk, load => load and selector(6), dataIn => dataIn, dataOut => spOut);
--pc: DoubleByteRegister PORT MAP(clk => clk, load => load(7), dataIn => dataIn, dataOut => pcOut);
end Behavioral;
| mit | 75c54ad2ce2ed9774355eaa6e5b171c9 | 0.685373 | 3.127918 | false | false | false | false |
mprska/vhdmake | test/test.vhd | 1 | 2,939 | -- comment
library ieee;
use ieee.std_logic_1164.all;
--use work.abc.all;
entity enti is
generic (
bla : std_ulogic := '1';
bla1 : std_ulogic_vector(1 downto 0) := "-0";
bla2 : natural := 1;
bla3 : std_ulogic_vector := "00");
port (
bla4 : in std_ulogic;
bla5 : in std_ulogic);
end;
architecture rtl of enti is
begin -- architecture rtl
end architecture rtl;
architecture bhv of enti is
begin -- architecture bhv
end architecture bhv;
package pd is
constant c : natural;
end package pd;
package body pd is
constant c : natural := 1;
end package body pd;
entity enti2 is
end entity enti2;
entity enti3 is
begin
end entity;
architecture rtl of enti3 is
begin -- architecture rtl
end architecture rtl;
entity enti4 is
end enti4;
library ieee;
use ieee.std_logic_1164.all;
use work.pd.all;
architecture Rtl of enti4 is
constant c : natural := 1;
signal s : std_ulogic := '1';
type t1 is array (0 to 1) of std_ulogic_vector(7 downto 0);
type t2 is array (natural range <>) of std_ulogic_vector;
function f1 (
signal sig : std_ulogic_vector(1 to 9); constant c : in natural) return boolean is
variable v : natural := c;
begin
return false;
end;
signal d : std_ulogic_vector(8 downto 0);
component compi is
generic (
foo : std_ulogic);
port (
bar : in std_ulogic);
end component compi;
begin -- architecture rtl
enti_1 : entity work.enti
port map (
bla4 => '0',
bla5 => '0');
a : s <= '0';
d(1 downto 0) <= '1' & s;
g : for i in 1 to 3 generate
enti_2 : entity work.enti(rtl)
port map (
bla4 => '0',
bla5 => not s);
foo : if c = 1 generate
enti_3 : entity work.enti(bhv)
port map (
bla4 => '0',
bla5 => not s);
enti_4 : compi
generic map (
foo => '0')
port map (
bar => s);
end generate foo;
d(2) <= not s;
end generate;
p : process (s) is
constant s1 : integer := 2;
begin -- process bla
if s = '0' then -- asynchronous reset (active low)
elsif rising_edge(s) then -- rising clock edge
d(4) <= '1';
else
d(4) <=
d
(
d'left
)
nand
d(1);
end if;
assert d = "000000000" report "blubb";
assert d(s1) report "blubb";
assert d(s1) = not d(1) report "blubb";
for i in 0 to 1 loop
if i = 0 then
assert d(s1) = d(d'left) report "blubb" & integer'image(s1);
end if;
end loop; -- i
while true loop
case d is
when "111100000" => d <= "000000000";
when "111100001" => d <= (others => '0');
when others => null;
end case;
end loop;
end process p;
end architecture rtl;
| gpl-3.0 | 10176c283fb6b184d6aaa12bdbab6aa9 | 0.538959 | 3.317156 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/sine_osc.vhd | 5 | 901 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sine_osc is
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
sine : out signed(15 downto 0);
cosine : out signed(15 downto 0) );
end sine_osc;
architecture gideon of sine_osc is
signal cos_i : signed(15 downto 0);
signal sin_i : signed(15 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
sin_i <= X"0000";
cos_i <= X"7FFF";
elsif enable='1' then
sin_i <= sum_limit(shift_right(cos_i, 8), sin_i);
cos_i <= sub_limit(cos_i, shift_right(sin_i, 8));
end if;
end if;
end process;
sine <= sin_i;
cosine <= cos_i;
end gideon;
| gpl-3.0 | 14b2a486ffd060a5d7f44a12f4a7c4f0 | 0.534961 | 3.217857 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op992_25.vhdl | 1 | 6,541 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 243cb875c6ec9f1f9a168bf27ff21f33 | 0.570402 | 3.062266 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/Slowcounter.vhd | 1 | 1,217 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- not both this and below -- USE ieee.std_logic_arith.all;
--use IEEE.numeric_bit.all; -- for integer to bit_vector conversion
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
-- VGA std format 640 by 480 pixels in a frame
-- register them, count line by line
--
ENTITY SlowCounter IS
PORT
(
Clk : IN std_logic;
ClockOUT : OUT std_logic
);
END SlowCounter;
-- first register the pixel stream
ARCHITECTURE SlowCounter_v1 OF SlowCounter IS
CONSTANT maxval: natural := 100; -- **************NOTE: this is carefully chosen to ensure TrainFLAG (in Debouncer)is only one frame long
signal Counter: natural range 0 to maxval; -- reduce clock to approx 500ms from 64uS (Hsync input)
signal Ctemp: std_logic := '0';
begin
---------------------------------------------------------------------------
process (clk)
begin
if (clk'event) and (clk ='1') then
Counter <= Counter +1;
if Counter = 0 then
Ctemp <= '0';
end if;
if Counter = maxval then
Ctemp <= not(Ctemp);
end if;
end if;
end process;
Clockout <= Ctemp;
---------------------------------------------------------------------------
END SlowCounter_v1; | gpl-2.0 | 4bb956de6fb3e835d541d853ef407160 | 0.597371 | 3.665663 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/td_GaussianFilter.vhd | 1 | 5,574 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:53:34 11/28/2013
-- Design Name:
-- Module Name: /media/DATA42/Projects/ComputerVision/RetinaDescriptors/td_GaussianFilter.vhd
-- Project Name: RetinaDescriptors
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: GaussianFilter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY td_GaussianFilter IS
END td_GaussianFilter;
ARCHITECTURE behavior OF td_GaussianFilter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT GaussianFilter
PORT(
CLK : in std_logic;
ENABLEIN : in std_logic;
RST : in std_logic;
ADDR : in std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
INPUTARRAY : in T_INPUT_VERTICAL_CONVOLUTION;
OUTPUTDATA : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
ENABLEOUT : out std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enable : std_logic := '0';
signal reset : std_logic := '0';
signal address : std_logic_vector(N_GAUSS_KERNEL_BW-1 downto 0) := (others => '0');
signal input_array : T_INPUT_VERTICAL_CONVOLUTION := (others => (others => '0'));
--Outputs
signal output_data : std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0);
signal output_enable : std_logic;
signal counter: std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
--others
signal j: integer range -1 to 10 := 10;
--image data
type image_row_type is array (10 downto 0) of integer range 0 to 10;
type image_data_type is array (10 downto 0) of image_row_type;
constant image_data : image_data_type :=
(
0 => (0,1,2,3,4,5,6,7,8,9,10),
1 => (0,1,2,3,4,5,6,7,8,9,10),
2 => (0,1,2,3,4,5,6,7,8,9,10),
3 => (0,1,2,3,4,5,6,7,8,9,10),
4 => (0,1,2,3,4,5,6,7,8,9,10),
5 => (0,1,2,3,4,5,6,7,8,9,10),
6 => (0,1,2,3,4,5,6,7,8,9,10),
7 => (0,1,2,3,4,5,6,7,8,9,10),
8 => (0,1,2,3,4,5,6,7,8,9,10),
9 => (0,1,2,3,4,5,6,7,8,9,10),
10 => (0,1,2,3,4,5,6,7,8,9,10)
);
--end image data
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: GaussianFilter PORT MAP (
CLK => clk,
ENABLEIN => enable,
RST => reset,
ADDR => address,
INPUTARRAY => input_array,
OUTPUTDATA => output_data,
ENABLEOUT => output_enable
);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
--wait for clk_period*35;
--assert False
--report "The special time has arrived!"
--severity Failure;
wait;
end process;
-- Stimulus process
stim_proc: process(clk)
variable array_data: T_INPUT_VERTICAL_CONVOLUTION;
--variable image_row: image_row_type;
begin
if rising_edge(clk) then
if reset = '0' then
if j >= 0 then
for i in 0 to 10 loop
--image_row := image_data(i);
array_data(i) := std_logic_vector(to_unsigned(image_data(i)(j), PIXEL_BW));
end loop;
input_array <= array_data;
enable <= '1';
if counter = '1' then
address <= "0111";
counter <= '0';
j <= j -1;
else
counter <= '1';
address <= "0000";
end if;
else
enable <= '0';
end if;
end if;
end if;
end process;
END;
| gpl-3.0 | f6d6747b6e794d2efa6aec947d9233a0 | 0.571941 | 3.47723 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op966_11.vhdl | 1 | 6,386 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | b80975ab7e18a205dc8fa06693079c8b | 0.573598 | 3.098496 | false | false | false | false |
tirfil/VhdI2CSlave | testbenches/tb_i2cslave_read.vhd | 1 | 3,731 | --###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CSLAVE_READ is
end TB_I2CSLAVE_READ;
architecture stimulus of TB_I2CSLAVE_READ is
-- COMPONENTS --
component I2CSLAVE
port(
MCLK : in std_logic;
nRST : in std_logic;
SDA_IN : in std_logic;
SCL_IN : in std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
ADDRESS : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
WR : out std_logic;
RD : out std_logic;
READ_DONE : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SDA_IN : std_logic;
signal SCL_IN : std_logic;
signal SDA_OUT : std_logic;
signal SCL_OUT : std_logic;
signal ADDRESS : std_logic_vector(7 downto 0);
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_IN : std_logic_vector(7 downto 0);
signal WR : std_logic;
signal RD : std_logic;
signal READ_DONE : std_logic;
--
signal RUNNING : std_logic := '1';
signal result : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_I2CSLAVE_0 : I2CSLAVE
port map (
MCLK => MCLK,
nRST => nRST,
SDA_IN => SDA_IN,
SCL_IN => SCL_IN,
SDA_OUT => SDA_OUT,
SCL_OUT => SCL_OUT,
ADDRESS => ADDRESS,
DATA_OUT => DATA_OUT,
DATA_IN => DATA_IN,
WR => WR,
RD => RD,
READ_DONE => READ_DONE
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
procedure SendData(data : in std_logic_vector(7 downto 0)) is
variable d : std_logic_vector(7 downto 0);
begin
d := data;
SCL_IN <= '0';
for i in 0 to 7 loop
SDA_IN <= d(7);
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
end loop;
SDA_IN <= '1';
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
end SendData;
procedure ReadData(nack: in std_logic) is
variable d: std_logic_vector(7 downto 0);
begin
SCL_IN <= '0';
for i in 0 to 7 loop
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
SCL_IN <= '1';
d(0) := SDA_OUT;
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
end loop;
SDA_IN <= nack;
result <= d;
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
SDA_IN <= '1';
end ReadData;
begin
result <= x"FF";
wait for 1 ns;
nRST <= '0';
SDA_IN <= '1';
SCL_IN <= '1';
wait for 1000 ns;
nRST <= '1';
SDA_IN <= '0'; -- start
wait for 80 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"55"); -- address
SDA_IN <= '0'; -- prepare stop bit
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SDA_IN <= '1';
wait for 80 ns;
SDA_IN <= '0'; -- start2
wait for 80 ns;
SendData(x"71"); -- 38 < 1 + read
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('1'); -- nack
SDA_IN <= '0'; -- prepare stop bit
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SDA_IN <= '1'; -- stop
wait for 1000 ns;
RUNNING <= '0';
wait;
end process GO;
P_READ: process
begin
wait for 100 ns;
DATA_IN <= x"FF";
wait until RD'event and RD='0';
DATA_IN <= x"66";
wait until RD'event and RD='0';
DATA_IN <= x"77";
wait until RD'event and RD='0';
DATA_IN <= x"88";
wait;
end process P_READ;
end stimulus;
| gpl-3.0 | e34323e0e85c964772407a904b000256 | 0.546502 | 2.55373 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_agen.vhd | 1 | 4,348 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_GAUSS_COE_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_GAUSS_COE_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF ROM_GAUSS_COE_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | 1bf4e88164428dbaad0a1eed415d4fa4 | 0.596366 | 4.405268 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/mem_bus_master_bfm.vhd | 5 | 2,769 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
library std;
use std.textio.all;
entity mem_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_mem_req := c_mem_req_init;
resp : in t_mem_resp );
end mem_bus_master_bfm;
architecture bfm of mem_bus_master_bfm is
shared variable this : p_mem_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_rack, wait_for_data);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process
procedure check_command is
begin
if this.command = e_mem_read then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '1';
state <= wait_for_data;
elsif this.command = e_mem_write then
req.tag <= this.tag;
req.address <= this.address;
req.request <= '1';
req.read_writen <= '0';
req.data <= this.data;
state <= wait_for_rack;
else
req.request <= '0';
req.data <= (others => '1');
req.address <= (others => '1');
state <= idle;
end if;
end procedure;
begin
wait until rising_edge(clock);
case state is
when idle =>
req <= c_mem_req_init;
req.data <= (others => '1');
req.address <= (others => '1');
if bound then
check_command;
end if;
when wait_for_rack =>
if resp.rack='1' then
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when wait_for_data =>
if resp.rack='1' then
req.request <= '0';
req.address <= (others => '1');
end if;
if to_integer(unsigned(resp.dack_tag)) /= 0 then
this.data := resp.data;
this.command := e_mem_none;
wait for 2*this.poll_time;
check_command;
end if;
when others =>
null;
end case;
end process;
end bfm;
| gpl-3.0 | e8351cc62b7d19baf1cd3eb82641913c | 0.464428 | 4.013043 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/mem_addr_counter.vhd | 3 | 939 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_addr_counter is
port (
clock : in std_logic;
load_value : in unsigned(25 downto 0);
do_load : in std_logic;
do_inc : in std_logic;
inc_by_4 : in std_logic;
address : out unsigned(25 downto 0) );
end mem_addr_counter;
architecture test of mem_addr_counter is
signal addr_i : unsigned(address'range) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
if do_load='1' then
addr_i <= load_value;
elsif do_inc='1' then
if inc_by_4='1' then
addr_i <= addr_i + 4;
else
addr_i <= addr_i + 1;
end if;
end if;
end if;
end process;
address <= addr_i;
end architecture;
| gpl-3.0 | 784faab671b98eecf2b7c716b7fa8aca | 0.490948 | 3.556818 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op952_13.vhdl | 1 | 4,999 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net5
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d570ece4cf297d147c5d66ff74e3a629 | 0.579316 | 3.169943 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op993_12.vhdl | 1 | 6,129 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 78f3c390bd5eb41c7bef997dff3b3177 | 0.570566 | 3.076807 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd | 2 | 5,910 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Testbench
--
-- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
entity tb is
end tb;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb is
component tb_elem
generic (
chip_type_g : string := "none";
has_sd_card_g : integer := 1
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
eos_o : out boolean
);
end component;
constant period_c : time := 100 ns;
constant reset_level_c : integer := 0;
signal clk_s : std_logic;
signal reset_s : std_logic;
signal eos_full_s,
eos_mmc_s,
eos_sd_s,
eos_minimal_s : boolean;
begin
-----------------------------------------------------------------------------
-- Testbench element including full featured chip
-----------------------------------------------------------------------------
tb_elem_full_b : tb_elem
generic map (
chip_type_g => "Full Chip",
has_sd_card_g => 1
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_full_s
);
-----------------------------------------------------------------------------
-- Testbench element including MMC chip
-----------------------------------------------------------------------------
tb_elem_mmc_b : tb_elem
generic map (
chip_type_g => "MMC Chip",
has_sd_card_g => 0
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_mmc_s
);
-----------------------------------------------------------------------------
-- Testbench element including SD chip
-----------------------------------------------------------------------------
tb_elem_sd_b : tb_elem
generic map (
chip_type_g => "SD Chip",
has_sd_card_g => 1
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_sd_s
);
-----------------------------------------------------------------------------
-- Testbench element including cip with minimal features
-----------------------------------------------------------------------------
tb_elem_minimal_b : tb_elem
generic map (
chip_type_g => "Minimal Chip",
has_sd_card_g => 0
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_minimal_s
);
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End Of Simulation Detection
-----------------------------------------------------------------------------
eos: process (eos_full_s,
eos_mmc_s,
eos_sd_s,
eos_minimal_s)
begin
if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
assert false
report "End of Simulation."
severity failure;
end if;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb.vhd,v $
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 21d0d5681251028da006bf8452de9a8f | 0.476819 | 4.646226 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/floppy_mem.vhd | 5 | 3,736 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy
-------------------------------------------------------------------------------
-- File : floppy_mem.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the interface to the buffer, for the
-- floppy model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_mem is
generic (
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
drv_wdata : in std_logic_vector(7 downto 0);
drv_rdata : out std_logic_vector(7 downto 0);
do_read : in std_logic;
do_write : in std_logic;
do_advance : in std_logic;
track_start : in std_logic_vector(25 downto 0);
max_offset : in std_logic_vector(13 downto 0);
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy_mem;
architecture gideon of floppy_mem is
type t_state is (idle, reading, writing);
signal state : t_state;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable offset_count : unsigned(13 downto 0);
procedure advance is
begin
if offset_count >= unsigned(max_offset) then
offset_count := (others => '0');
else
offset_count := offset_count + 1;
end if;
end procedure;
begin
if rising_edge(clock) then
case state is
when idle =>
if do_read='1' then
advance;
state <= reading;
mem_req.read_writen <= '1';
mem_req.request <= '1';
elsif do_write='1' then
advance;
state <= writing;
mem_req.read_writen <= '0';
mem_req.request <= '1';
elsif do_advance='1' then
advance;
end if;
mem_req.data <= drv_wdata;
mem_req.address <= unsigned(track_start) + offset_count;
when reading =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when writing =>
if mem_rack='1' then
mem_req.request <= '0';
drv_rdata <= mem_resp.data;
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
offset_count := (others => '0');
state <= idle;
mem_req <= c_mem_req_init;
mem_req.tag <= g_tag;
drv_rdata <= X"FF";
end if;
end if;
end process;
end gideon;
| gpl-3.0 | c2aa2a1689b4865114687cf07d70c96b | 0.402302 | 4.374707 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/clocks.vhd | 1 | 6,868 | -- file: clocks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____10.000______0.000______50.0______439.530____196.077
-- CLK_OUT2___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT3___133.333____180.000______50.0______230.136____196.077
-- CLK_OUT4____25.000______0.000______50.0______364.543____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocks is
port
(-- Clock in ports
clkin : in std_logic;
-- Clock out ports
clk10mhz : out std_logic;
clk133mhz : out std_logic;
clk133mhzinv : out std_logic;
clk25mhz : out std_logic
);
end clocks;
architecture xilinx of clocks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocks,clk_wiz_v3_6,{component_name=clocks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clkin);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 80,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 6,
CLKOUT2_PHASE => 180.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 32,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk10mhz,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk133mhz,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk133mhzinv,
I => clkout2);
clkout4_buf : BUFG
port map
(O => clk25mhz,
I => clkout3);
end xilinx;
| mit | 328016ac0d9906d7bae88a822c6743d3 | 0.586342 | 4.063905 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_source/iec_interface.vhd | 5 | 13,941 | -------------------------------------------------------------------------------
-- Title : IEC Interface
-------------------------------------------------------------------------------
-- File : iec_interface.vhd
-- Created : 2008-01-17
-- Last update: 2008-01-17
-------------------------------------------------------------------------------
-- Description: This module implements a simple IEC transceiver.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_interface is
generic (
g_state_readback : boolean := false;
programmable_timing : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
timer_tick : in std_logic;
iec_atn_i : in std_logic;
iec_atn_o : out std_logic;
iec_clk_i : in std_logic;
iec_clk_o : out std_logic;
iec_data_i : in std_logic;
iec_data_o : out std_logic;
-- debug
iec_state : out std_logic_vector(3 downto 0);
iec_dbg : out std_logic_vector(1 downto 0);
-- end debug
cpu_addr : in std_logic_vector(2 downto 0);
cpu_wdata : in std_logic_vector(7 downto 0);
cpu_rdata : out std_logic_vector(7 downto 0);
cpu_write : in std_logic);
end iec_interface;
architecture erno of iec_interface is
signal bit_cnt : integer range 0 to 8;
signal data_reg : std_logic_vector(7 downto 0);
signal send_data : std_logic_vector(7 downto 0);
signal delay : integer range 0 to 255;
signal clk_d : std_logic;
signal atn_d : std_logic;
signal flag_eoi : std_logic;
signal flag_atn : std_logic;
signal flag_data_av : std_logic;
signal flag_clr2send : std_logic;
signal flag_byte_sent: std_logic;
signal ctrl_data_av : std_logic;
signal ctrl_nodata : std_logic;
signal ctrl_talker : std_logic;
signal ctrl_listener : std_logic;
signal ctrl_eoi : std_logic;
signal ctrl_swready : std_logic;
signal ctrl_swreset : std_logic;
signal ctrl_killed : std_logic;
signal ctrl_address : std_logic_vector(4 downto 0);
signal clk_edge_seen : std_logic;
signal clk_edge_d : std_logic := '1';
signal atn_edge_d : std_logic := '1';
type t_state is ( idle, prep_recv, reoi_chk, reoi_ack, recv, rack_wait4sw, prep_talk, turn_around,
wait4listener, teoi, teoi_ack, trans1, trans2, twait4ack, sw_byte, ack_byte, prep_atn);
signal state : t_state;
signal time1 : std_logic_vector(5 downto 0) := "010100";
signal time2 : std_logic_vector(5 downto 0) := "010100";
signal time3 : std_logic_vector(5 downto 0) := "010100";
signal time4 : std_logic_vector(5 downto 0) := "010100";
-- comment these two lines when done
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal encoded_state : std_logic_vector(3 downto 0) := X"0";
begin
process(clock)
procedure continue_next is
begin
if ctrl_talker = '1' and iec_atn_i = '1' and iec_clk_i = '1' then
iec_clk_o <= '0';
iec_data_o <= '1';
state <= prep_talk;
elsif iec_atn_i = '0' then
state <= prep_recv;
elsif ctrl_listener = '1' and flag_eoi='0' then
state <= prep_recv;
else
state <= idle;
end if;
end procedure continue_next;
begin
if rising_edge(clock) then
atn_d <= iec_atn_i;
clk_d <= iec_clk_i;
flag_clr2send <= '0';
if delay /= 0 and timer_tick = '1' then
delay <= delay - 1;
end if;
if iec_clk_i='1' and clk_d='0' then
clk_edge_seen <= '1';
end if;
case state is
when idle =>
iec_data_o <= '1';
iec_clk_o <= '1';
when prep_recv =>
if clk_edge_seen = '1' and ctrl_swready='1' then
iec_data_o <= '1';
delay <= 40;
bit_cnt <= 8;
flag_eoi <= '0';
state <= reoi_chk;
elsif ctrl_talker = '1' and iec_atn_i = '1' then
iec_data_o <= '1';
state <= turn_around;
elsif ctrl_talker = '0' and ctrl_listener = '0' and iec_atn_i = '1' then
state <= idle;
end if;
when reoi_chk =>
if iec_clk_i = '0' then
flag_atn <= not iec_atn_i;
state <= recv;
elsif delay = 0 then
iec_data_o <= '0';
delay <= 20;
flag_eoi <= '1';
state <= reoi_ack;
end if;
when reoi_ack =>
if iec_clk_i = '0' then
iec_data_o <= '1';
flag_atn <= not iec_atn_i;
state <= recv;
elsif delay = 0 then
iec_data_o <= '1';
end if;
when recv =>
if iec_clk_i='1' and clk_d='0' then
bit_cnt <= bit_cnt - 1;
data_reg <= iec_data_i & data_reg(7 downto 1);
end if;
if iec_clk_i='0' and bit_cnt = 0 then -- end of transfer
delay <= 20;
if flag_atn='1' then
if data_reg(7 downto 5)="001" then -- listen
ctrl_talker <= '0';
ctrl_listener <= '0';
if data_reg(4 downto 0) = ctrl_address then
ctrl_listener <= '1';
state <= ack_byte;
end if;
elsif data_reg(7 downto 5)="010" then -- talk
ctrl_talker <= '0';
ctrl_listener <= '0';
if data_reg(4 downto 0) = ctrl_address then
ctrl_talker <= '1';
state <= ack_byte;
end if;
elsif ctrl_talker='1' or ctrl_listener='1' then -- other atn byte
state <= sw_byte;
else
state <= idle;
end if;
else -- byte without atn.. we can only be here if we were listener!
state <= sw_byte;
end if;
end if;
when ack_byte =>
iec_data_o <= '0';
clk_edge_seen <= '0';
if delay=0 then
continue_next;
end if;
when sw_byte =>
iec_data_o <= '0';
flag_data_av <= '1';
ctrl_swready <= '0';
clk_edge_seen <= '0';
state <= rack_wait4sw;
when rack_wait4sw =>
if ctrl_swready = '1' then
continue_next;
end if;
when prep_talk =>
flag_clr2send <= '1';
if ctrl_data_av = '1' and delay = 0 then
data_reg <= send_data; -- copy
flag_byte_sent <= '0';
iec_clk_o <= '1';
bit_cnt <= 8;
state <= wait4listener;
end if;
when wait4listener =>
if iec_data_i = '1' then
if ctrl_eoi = '1' then
state <= teoi;
else
iec_clk_o <= '0';
iec_data_o <= data_reg(0);
delay <= to_integer(unsigned(time1));
state <= trans1;
end if;
end if;
when teoi =>
if iec_data_i = '0' then
state <= teoi_ack;
end if;
when teoi_ack =>
if ctrl_nodata = '1' then
state <= idle;
elsif iec_data_i = '1' then
iec_clk_o <= '0';
iec_data_o <= data_reg(0);
delay <= to_integer(unsigned(time1));
state <= trans1;
end if;
when trans1 =>
if delay = 0 then
iec_clk_o <= '1';
data_reg <= '1' & data_reg(7 downto 1);
delay <= to_integer(unsigned(time2));
state <= trans2;
end if;
when trans2 =>
if delay = 0 then
iec_data_o <= data_reg(0);
iec_clk_o <= '0';
if bit_cnt = 1 then
state <= twait4ack;
else
bit_cnt <= bit_cnt - 1;
delay <= to_integer(unsigned(time3));
state <= trans1;
end if;
end if;
when twait4ack =>
if iec_data_i = '0' and timer_tick='1' then
ctrl_data_av <= '0';
flag_byte_sent <= '1';
if ctrl_eoi = '0' then
state <= prep_talk;
else
state <= idle;
ctrl_talker <= '0';
end if;
end if;
when turn_around =>
if iec_clk_i='1' then
iec_clk_o <= '0';
delay <= 20;
state <= prep_talk;
end if;
when prep_atn =>
if timer_tick='1' then
clk_edge_seen <= '0';
state <= prep_recv;
end if;
when others =>
null;
end case;
if ctrl_killed = '0' then
if iec_atn_i = '0' and atn_d = '1' then -- falling edge attention
iec_data_o <= '0';
iec_clk_o <= '1';
ctrl_data_av <= '0';
clk_edge_seen <= '0';
if timer_tick='0' then
atn_d <= '1'; -- delay edge detection until clock is also seen high
else
state <= prep_atn;
end if;
end if;
end if;
if cpu_write='1' then
if cpu_addr(2)='0' then
case cpu_addr(1 downto 0) is
when "00" =>
send_data <= cpu_wdata;
when "01" =>
if cpu_wdata(7)='1' then
flag_data_av <= '0';
end if;
ctrl_swready <= cpu_wdata(7);
ctrl_nodata <= cpu_wdata(6);
-- ctrl_talker <= cpu_wdata(5);
-- ctrl_listener <= cpu_wdata(4);
ctrl_data_av <= cpu_wdata(3);
ctrl_swreset <= cpu_wdata(2);
ctrl_killed <= cpu_wdata(1);
ctrl_eoi <= cpu_wdata(0);
when "10" =>
ctrl_address <= cpu_wdata(4 downto 0);
when others =>
null;
end case;
elsif programmable_timing then -- note: cpu_addr(2) = '1'
case cpu_addr(1 downto 0) is
when "00" =>
time1 <= cpu_wdata(5 downto 0);
when "01" =>
time2 <= cpu_wdata(5 downto 0);
when "10" =>
time3 <= cpu_wdata(5 downto 0);
when "11" =>
time4 <= cpu_wdata(5 downto 0);
when others =>
null;
end case;
end if;
end if;
if reset='1' or ctrl_swreset='1' then
state <= idle;
iec_data_o <= '1';
iec_clk_o <= '1';
clk_edge_seen <= '0';
flag_eoi <= '0';
flag_atn <= '0';
flag_data_av <= '0';
flag_clr2send <= '0';
flag_byte_sent <= '0';
ctrl_swreset <= '0';
ctrl_swready <= '0';
ctrl_data_av <= '0';
ctrl_nodata <= '0';
ctrl_talker <= '0';
ctrl_listener <= '0';
ctrl_eoi <= '0';
ctrl_killed <= '1';
ctrl_address <= "01001"; -- 9
end if;
end if;
end process;
r_state: if g_state_readback generate
with state select encoded_state <=
X"0" when idle,
X"1" when prep_recv,
X"2" when reoi_chk,
X"3" when reoi_ack,
X"4" when recv,
X"5" when rack_wait4sw,
X"6" when prep_talk,
X"7" when wait4listener,
X"8" when teoi,
X"9" when teoi_ack,
X"A" when trans1,
X"B" when trans2,
X"C" when twait4ack,
X"D" when sw_byte,
X"E" when ack_byte,
X"F" when others;
end generate;
p_readback: process(cpu_addr, flag_eoi, flag_atn, flag_data_av, data_reg,
ctrl_data_av, ctrl_talker, ctrl_listener)
begin
cpu_rdata <= X"00";
case cpu_addr(1 downto 0) is
when "00" =>
cpu_rdata <= data_reg;
when "01" =>
cpu_rdata(7) <= flag_data_av;
cpu_rdata(1) <= flag_atn;
cpu_rdata(5) <= ctrl_talker;
cpu_rdata(4) <= ctrl_listener;
cpu_rdata(3) <= flag_clr2send;
cpu_rdata(2) <= flag_byte_sent;
cpu_rdata(0) <= flag_eoi;
when "11" =>
cpu_rdata(3 downto 0) <= encoded_state;
when others =>
null;
end case;
end process;
iec_atn_o <= '1';
iec_state <= encoded_state;
iec_dbg(0) <= ctrl_data_av;
iec_dbg(1) <= ctrl_swready;
end erno;
| gpl-3.0 | 4a8ffe724aa6eaadba2018368902ec8d | 0.412739 | 3.614467 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op963_3.vhdl | 1 | 4,111 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4817ec3eb66d8502d11e7474d16939ad | 0.585989 | 3.257528 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_usb_host.vhd | 3 | 4,985 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_usb_host is
end entity;
architecture tb of tb_usb_host is
signal ulpi_clock : std_logic := '0';
signal ulpi_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal status : std_logic_vector(7 downto 0) := X"55";
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal sys_address : std_logic_vector(12 downto 0) := (others => '0'); -- 8K block
signal sys_write : std_logic := '0';
signal sys_request : std_logic := '0';
signal sys_wdata : std_logic_vector(7 downto 0) := X"22";
signal sys_rdata : std_logic_vector(7 downto 0);
signal sys_rack : std_logic;
signal sys_dack : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
ulpi_clock <= not ulpi_clock after 8.33 ns;
ulpi_reset <= '1', '0' after 100 ns;
sys_clock <= not sys_clock after 10 ns;
sys_reset <= '1', '0' after 100 ns;
i_mut: entity work.usb_host
generic map (
g_simulation => true )
port map (
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_address => sys_address, -- 8K block
sys_write => sys_write,
sys_request => sys_request,
sys_wdata => sys_wdata,
sys_rdata => sys_rdata,
sys_rack => sys_rack,
sys_dack => sys_dack );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure write_data(addr : unsigned(15 downto 0);
j: t_std_logic_8_vector ) is
variable a : unsigned(addr'range);
begin
a := addr;
for i in j'range loop
wait until sys_clock='1';
sys_address <= std_logic_vector(a(12 downto 0));
sys_write <= '1';
sys_wdata <= j(i);
sys_request <= '1';
a := a + 1;
-- write cycles can be done every clock cycle
end loop;
wait until sys_clock='1';
sys_write <= '0';
sys_request <= '0';
end procedure write_data;
procedure write_word(addr : unsigned(15 downto 0);
j : std_logic_vector(31 downto 0)) is
variable h : t_std_logic_8_vector(0 to 3);
begin
h(0) := j(7 downto 0);
h(1) := j(15 downto 8);
h(2) := j(23 downto 16);
h(3) := j(31 downto 24);
write_data(addr, h);
end procedure write_word;
begin
wait for 500 ns;
write_word(X"0000", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(64, 11),
data_toggle => '0',
control => '1' ) ));
write_word(X"0004", t_pipe_to_data((
state => initialized,
direction => dir_in,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(64, 11),
data_toggle => '0',
control => '1' ) ));
write_data(X"1000", (X"80", X"06", X"00", X"01", X"00", X"00", X"40", X"00"));
write_word(X"0100", t_transaction_to_data((
transaction_type => control,
state => busy, -- activate
pipe_pointer => "00000",
transfer_length => to_unsigned(8, 11),
buffer_address => to_unsigned(0, 12) )));
write_word(X"0104", t_transaction_to_data((
transaction_type => bulk,
state => busy, -- activate
pipe_pointer => "00001",
transfer_length => to_unsigned(60, 11),
buffer_address => to_unsigned(256, 12) )));
wait for 50 us;
wait;
end process;
end tb;
| gpl-3.0 | 635008a5c752fa8f6795b260bb389063 | 0.461986 | 3.822853 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_memory_ctrl.vhd | 1 | 8,173 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_bus_pkg.all;
-- This module performs the memory operations that are instructed
-- by the nano_cpu. This controller copies data to or from a
-- designated BRAM, and notifies the nano_cpu that the transfer
-- is complete.
entity usb_memory_ctrl is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
clock : in std_logic;
reset : in std_logic;
-- cmd interface
cmd_addr : in std_logic_vector(3 downto 0);
cmd_valid : in std_logic;
cmd_write : in std_logic;
cmd_wdata : in std_logic_vector(15 downto 0);
cmd_ack : out std_logic;
cmd_done : out std_logic;
cmd_ready : out std_logic;
-- BRAM interface
ram_addr : out std_logic_vector(10 downto 2);
ram_en : out std_logic;
ram_we : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- memory interface
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture gideon of usb_memory_ctrl is
type t_state is (idle, reading, writing, init);
signal state : t_state;
signal mem_addr_r : unsigned(25 downto 0) := (others => '0');
signal mem_addr_i : unsigned(25 downto 2) := (others => '0');
signal ram_addr_i : unsigned(8 downto 2) := (others => '0');
signal mreq : std_logic := '0';
signal rwn : std_logic := '1';
signal addr_do_load : std_logic := '0';
signal new_addr : std_logic := '0';
signal addr_do_inc : std_logic := '0';
signal rem_do_load : std_logic;
signal rem_do_dec : std_logic;
signal remain_is_0 : std_logic;
signal remain_is_1 : std_logic;
signal buffer_idx : std_logic_vector(10 downto 9) := "00";
signal ram_we_i : std_logic_vector(3 downto 0);
signal ram_wnext : std_logic;
signal rdata_valid : std_logic;
signal first_req : std_logic;
signal last_req : std_logic;
begin
mem_req.tag(7) <= last_req;
mem_req.tag(6) <= first_req;
mem_req.tag(5 downto 0) <= g_tag(5 downto 0);
mem_req.request <= mreq;
mem_req.address <= mem_addr_i & mem_addr_r(1 downto 0);
mem_req.read_writen <= rwn;
mem_req.data <= ram_rdata;
mem_req.byte_en <= "1111";
-- pop from fifo when we process the access
cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0';
process(buffer_idx, state, mreq, mem_resp, ram_addr_i)
begin
ram_addr <= buffer_idx & std_logic_vector(ram_addr_i);
ram_en <= '0';
-- for writing to memory, we enable the BRAM only when we are going to set
-- the request, such that the data and the request comes at the same time
case state is
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then
ram_en <= '1';
end if;
when others =>
null;
end case;
-- for reading from memory, it doesn't matter in which state we are:
if ram_we_i /= "0000" then
ram_en <= '1';
end if;
end process;
ram_we <= ram_we_i;
process(clock)
begin
if rising_edge(clock) then
rem_do_dec <= '0';
case state is
when idle =>
rwn <= '1';
if cmd_valid='1' then
if cmd_write='1' then
cmd_done <= '0';
case cmd_addr is
when X"0" =>
mem_addr_r(15 downto 0) <= unsigned(cmd_wdata(15 downto 0));
new_addr <= '1';
when X"1" =>
mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0));
new_addr <= '1';
when X"2" =>
rwn <= '0';
state <= init;
when X"3" =>
state <= init;
when X"4" =>
buffer_idx <= cmd_wdata(15 downto 14);
when others =>
null;
end case;
end if;
end if;
when init =>
new_addr <= '0';
ram_addr_i <= (others => '0');
if rwn='1' then
state <= reading;
else
state <= writing;
end if;
when reading =>
rwn <= '1';
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then
if remain_is_0 = '1' then
state <= idle;
cmd_done <= '1';
mreq <= '0';
else
first_req <= not mreq;
last_req <= remain_is_1;
mreq <= '1';
rem_do_dec <= '1';
end if;
end if;
when writing =>
rwn <= '0';
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then
ram_addr_i <= ram_addr_i + 1;
if remain_is_0 = '1' then
state <= idle;
cmd_done <= '1';
mreq <= '0';
else
first_req <= not mreq;
last_req <= remain_is_1;
mreq <= '1';
rem_do_dec <= '1';
end if;
end if;
when others =>
null;
end case;
if ram_wnext = '1' then
ram_addr_i <= ram_addr_i + 1;
end if;
if reset='1' then
state <= idle;
mreq <= '0';
cmd_done <= '0';
new_addr <= '0';
first_req <= '0';
end if;
end if;
end process;
cmd_ready <= '1' when (state = idle) else '0';
addr_do_load <= new_addr when (state = init) else '0';
addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) else '0';
i_addr: entity work.mem_addr_counter
port map (
clock => clock,
load_value => mem_addr_r(25 downto 2),
do_load => addr_do_load,
do_inc => addr_do_inc,
address => mem_addr_i );
rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0';
i_rem: entity work.mem_remain_counter
port map (
clock => clock,
load_value => unsigned(cmd_wdata(9 downto 2)),
do_load => rem_do_load,
do_dec => rem_do_dec,
remain => open,
remain_is_1 => remain_is_1,
remain_is_0 => remain_is_0 );
rdata_valid <= '1' when mem_resp.dack_tag(5 downto 0) = g_tag(5 downto 0) else '0';
i_align: entity work.align_read_to_bram
port map (
clock => clock,
rdata => mem_resp.data,
rdata_valid => rdata_valid,
first_word => mem_resp.dack_tag(6),
last_word => mem_resp.dack_tag(7),
offset => mem_addr_r(1 downto 0),
wdata => ram_wdata,
wmask => ram_we_i,
wnext => ram_wnext );
end architecture;
| gpl-3.0 | 417603ea972b5a89e71034f239d99686 | 0.434479 | 3.810256 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/io_bus_arbiter_pri.vhd | 4 | 2,183 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity io_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_io_req_array(0 to g_ports-1);
resps : out t_io_resp_array(0 to g_ports-1);
req : out t_io_req;
resp : in t_io_resp );
end entity;
architecture rtl of io_bus_arbiter_pri is
signal req_i : t_io_req;
signal select_i : integer range 0 to g_ports-1;
signal select_c : integer range 0 to g_ports-1;
type t_state is (idle, busy);
signal state : t_state;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_io_req_init;
select_i <= 0;
for i in reqs'range loop
if reqs(i).read='1' or reqs(i).write='1' then
req_i <= reqs(i);
select_i <= i;
exit;
end if;
end loop;
end process;
p_access: process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
req <= req_i;
if req_i.read='1' then
select_c <= select_i;
state <= busy;
elsif req_i.write='1' then
select_c <= select_i;
state <= busy;
end if;
when busy =>
req <= reqs(select_c);
if resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
-- send the reply to everyone, but mask the acks to non-active clients
process(resp, select_c)
begin
for i in resps'range loop
resps(i) <= resp;
if i /= select_c then
resps(i).ack <= '0';
end if;
end loop;
end process;
end architecture;
| gpl-3.0 | bf6ebb5d4f027bd47560d26b23b93173 | 0.454879 | 3.796522 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper_pkg.vhd | 5 | 3,337 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package copper_pkg is
constant c_copper_command : unsigned(3 downto 0) := X"0";
constant c_copper_status : unsigned(3 downto 0) := X"1";
constant c_copper_measure_l : unsigned(3 downto 0) := X"2";
constant c_copper_measure_h : unsigned(3 downto 0) := X"3";
constant c_copper_framelen_l : unsigned(3 downto 0) := X"4";
constant c_copper_framelen_h : unsigned(3 downto 0) := X"5";
constant c_copper_break : unsigned(3 downto 0) := X"6";
constant c_copper_cmd_play : std_logic_vector(3 downto 0) := X"1"; -- starts program in ram
constant c_copper_cmd_record : std_logic_vector(3 downto 0) := X"2"; -- waits for sync, records all writes until next sync.
constant c_copcode_write_reg : std_logic_vector(7 downto 0) := X"00"; -- starting from 00-2F or so.. takes 1 argument
constant c_copcode_read_reg : std_logic_vector(7 downto 0) := X"40"; -- starting from 40-6F or so.. no arguments
constant c_copcode_wait_irq : std_logic_vector(7 downto 0) := X"81"; -- waits until falling edge of IRQn
constant c_copcode_wait_sync : std_logic_vector(7 downto 0) := X"82"; -- waits until sync pulse from timer
constant c_copcode_timer_clr : std_logic_vector(7 downto 0) := X"83"; -- clears timer
constant c_copcode_capture : std_logic_vector(7 downto 0) := X"84"; -- copies timer to measure register
constant c_copcode_wait_for : std_logic_vector(7 downto 0) := X"85"; -- takes a 1 byte argument
constant c_copcode_wait_until: std_logic_vector(7 downto 0) := X"86"; -- takes 2 bytes argument (wait until timer match)
constant c_copcode_repeat : std_logic_vector(7 downto 0) := X"87"; -- restart at program address 0.
constant c_copcode_end : std_logic_vector(7 downto 0) := X"88"; -- ends operation and return to idle
constant c_copcode_trigger_1 : std_logic_vector(7 downto 0) := X"89"; -- pulses on trigger_1 output
constant c_copcode_trigger_2 : std_logic_vector(7 downto 0) := X"8A"; -- pulses on trigger_1 output
type t_copper_control is record
command : std_logic_vector(3 downto 0);
frame_length : unsigned(15 downto 0);
stop : std_logic;
end record;
constant c_copper_control_init : t_copper_control := (
command => X"0",
frame_length => X"4D07", -- 313 lines of 63.. (is incorrect, is one line too long, but to init is fine!)
stop => '0' );
type t_copper_status is record
running : std_logic;
measured_time : unsigned(15 downto 0);
end record;
constant c_copper_status_init : t_copper_status := (
running => '0',
measured_time => X"FFFF" );
end package;
| gpl-3.0 | 12c1a1d211556b4b0973af182c9cdc22 | 0.589152 | 3.576635 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_interface.vhd | 3 | 2,473 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_interface is
end entity;
architecture tb of tb_ulpi_interface is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- fifo interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_command => rx_command,
rx_last => rx_last,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 | 3e165d9b67e52b9c9659d404901c56f4 | 0.446826 | 3.752656 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/video_fpga/vhdl_source/video_fpga.vhd | 5 | 8,722 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_fpga is
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic; -- IBUF only
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic; -- IBUF ONLY
ROMLn : out std_logic;
IO1n : in std_logic; -- IBUF ONLY
IO2n : out std_logic;
IRQn : out std_logic;
NMIn : out std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(21 downto 0); -- 4M linear space
LB_DATA : inout std_logic_vector(7 downto 0);
FLASH_CSn : out std_logic;
SRAM_CSn : out std_logic;
MEM_WEn : out std_logic;
MEM_OEn : out std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USB
USB_IOP : inout std_logic;
USB_ION : inout std_logic;
USB_SEP : in std_logic;
USB_SEN : in std_logic;
USB_DET : inout std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_WP : in std_logic;
SD_CARDDETn : in std_logic;
-- 1-wire Interface
ONE_WIRE : inout std_logic;
-- Ethernet Interface
ETH_CLK : inout std_logic := '0';
ETH_IRQ : in std_logic := '0';
ETH_CSn : out std_logic;
ETH_CS : out std_logic;
ETH_RST : out std_logic;
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic;
CAS_READ : inout std_logic;
CAS_WRITE : inout std_logic;
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end video_fpga;
architecture structural of video_fpga is
constant c_default_divider : integer := 896;
-- attribute IFD_DELAY_VALUE : string;
-- attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
-- signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal button_c : std_logic_vector(2 downto 0);
signal button_d : std_logic_vector(2 downto 0);
signal pix_clock : std_logic;
signal pix_clock_en : std_logic;
signal pix_reset : std_logic;
signal pix_clock_pll: std_logic;
----------------------------------------------
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal n : unsigned(11 downto 0) := to_unsigned(c_default_divider-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal reference : std_logic;
signal mute : std_logic;
signal pulse_level : std_logic;
signal pulse_enable: std_logic;
type t_state is (idle, waiting);
signal wait_count : integer range 0 to 16383;
signal state : t_state;
----------------------------------------------
signal div_count : integer range 0 to 1599 := 0;
signal toggle_15k : std_logic := '0';
signal toggle_25M : std_logic := '0';
----------------------------------------------
signal pixel_active : std_logic;
signal pixel_data : std_logic;
signal sync_out_n : std_logic;
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
--sys_clock_2x => sys_clock_2x,
pix_clock => pix_clock,
pix_reset => pix_reset );
ETH_CLK <= '0';
i_clock_buf: BUFG port map (I => pll_clock, O => pix_clock_pll);
process(sys_clock)
begin
if rising_edge(sys_clock) then
button_c <= button_i;
button_d <= button_c;
case state is
when idle =>
wait_count <= 10000;
if button_d(0)='1' and button_c(0)='0' then
n <= n + 5;
state <= waiting;
elsif button_d(2)='1' and button_c(2)='0' then
n <= n - 4;
state <= waiting;
elsif button_d(1)='1' and button_c(1)='0' then
n <= to_unsigned(c_default_divider-1, n'length);
state <= waiting;
end if;
when waiting =>
if wait_count = 0 then
state <= idle;
else
wait_count <= wait_count - 1;
end if;
when others =>
null;
end case;
if sys_reset='1' then
n <= to_unsigned(c_default_divider-1, n'length);
end if;
end if;
end process;
p_15khz: process(sys_clock)
begin
if rising_edge(sys_clock) then
toggle_25M <= not toggle_25M;
if div_count = 0 then
div_count <= 1599;
toggle_15k <= not toggle_15k;
else
div_count <= div_count - 1;
end if;
end if;
end process;
i_sep: entity work.sync_separator
generic map (
g_clock_mhz => 50 )
port map (
clock => sys_clock,
sync_in => sync_in,
mute => mute,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => toggle_15k, --h_sync,
reference => reference,
mute => '0', --mute,
up => up,
down => down,
pulse_level => pulse_level,
pulse_enable=> pulse_enable,
analog => analog );
i_chargen: entity work.char_generator
generic map (
g_divider => 11 )
port map (
clock => pix_clock,
reset => pix_reset,
io_req => c_io_req_init,
io_resp => open,
h_sync => h_sync,
v_sync => v_sync,
pixel_active => pixel_active,
pixel_data => pixel_data,
sync_out_n => sync_out_n );
-------------------------------------------------------
sync_in <= IO1n;
pll_clock <= DOTCLK;
-- front row
IRQn <= reference;
GAMEn <= h_sync;
EXROMn <= v_sync;
IO2n <= not pulse_enable;
ROMLn <= pulse_level;
DMAn <= mute;
-- back row
NMIn <= toggle_15k;
RSTn <= toggle_25M;
SLOT_ADDR(15) <= '1'; --sync_in; --sync_out_n;
SLOT_ADDR(14) <= pixel_active;
SLOT_ADDR(13) <= pixel_data;
-------------------------------------------------------
BUFFER_ENn <= '0';
ETH_RST <= sys_reset;
ETH_CS <= '1';
-- tie offs
SDRAM_DQM <= '0';
-- USB
USB_IOP <= USB_SEP;
USB_ION <= USB_SEN;
USB_DET <= 'Z';
ONE_WIRE <= 'Z';
end structural;
| gpl-3.0 | 4e19205489eea0ed265ecdf7c37b741a | 0.471222 | 3.529745 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi_peripheral_io.vhd | 5 | 5,372 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity spi_peripheral_io is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
busy : out std_logic;
SD_DETECTn : in std_logic := '1';
SD_WRPROTn : in std_logic := '1';
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral_io;
architecture gideon of spi_peripheral_io is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy_i : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
type t_state is (idle, writing, reading, receive);
signal state : t_state;
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy_i,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
state <= writing;
elsif io_req.read='1' then
state <= reading;
end if;
when writing =>
if busy_i='0' then
io_resp.ack <= '1';
state <= idle;
case io_req.address(3 downto 2) is
when "00" =>
do_send <= '1';
wdata <= io_req.data;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= io_req.data;
rate(8) <= io_req.data(7);
end if;
when "10" =>
force_ss <= io_req.data(0);
level_ss <= io_req.data(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
when reading =>
if busy_i='0' then
case io_req.address(3 downto 2) is
when "00" =>
do_send <= '1';
wdata <= X"FF";
state <= receive;
when "01" =>
io_resp.data <= rate(7 downto 0);
io_resp.ack <= '1';
state <= idle;
when "10" =>
io_resp.data <= "0000" & not SD_WRPROTn & not SD_DETECTn & level_ss & force_ss;
io_resp.ack <= '1';
state <= idle;
when "11" =>
io_resp.data <= crc_out;
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
end if;
when receive =>
if do_send = '0' and busy_i = '0' then
io_resp.data <= rdata;
io_resp.ack <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
if not g_fixed_rate then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
end if;
force_ss <= '0';
level_ss <= '1';
wdata <= X"FF";
end if;
end if;
end process;
busy <= busy_i;
end gideon;
| gpl-3.0 | 400bc7d966698a7da086de869a91fe9c | 0.347729 | 4.469218 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/alu/alu_tb.vhdl | 1 | 1,590 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.binary16.all;
entity alu_tb is
end alu_tb;
architecture behav of alu_tb is
component alu
port (i0, i1 : in binary16;
op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out binary16;
exception: out std_logic
);
end component;
for alu_0: alu use entity work.alu;
signal i0, i1 : binary16;
signal op : std_logic_vector(3 downto 0);
signal clk : std_logic;
signal result : binary16;
begin
alu_0: alu port map (i0 => i0, i1 => i1, op=>op, clk=>clk, result => result);
process
type op_array is array (natural range <>) of std_logic_vector(3 downto 0);
constant ops : op_array :=
("0000", -- bitwise AND
"0001", -- OR
"0010", -- XOR
"0011", -- NOT (1st op)
"0100", -- addition on complements
"0101", -- minus
"0110", -- multiplication
"1000", -- logic shl
"1001", -- shr
"1010", -- arithmetic shl
"1011" -- shr
);
begin
for i in ops'range loop
i0 <= "1010010101011010";
i1 <= "0101101010100101";
op <= ops(i);
wait for 10 ms;
end loop;
assert false report "have a nice day!" severity note;
wait;
end process;
end behav;
| gpl-3.0 | 50d5de95f42c2e3e9785f79656b3ffad | 0.542767 | 3.597285 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_2sk1_0.vhdl | 1 | 7,400 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 4.5e-07
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.5e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 7e-07,
W => Wsrc_2,
Wsrc_2init => 2.085e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 7e-07,
W => Wsrc_2,
Wsrc_2init => 2.085e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.5e-07,
W => Wcm_1,
Wcm_1init => 1.365e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.5e-07,
W => Wcmout_1,
Wcmout_1init => 7.995e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 6.9e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 6.9e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 6.9e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 6b106fcccee660aac96fe8a889e7522b | 0.580811 | 2.879377 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op324_0sk1_0.vhdl | 1 | 5,158 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.865e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.865e-05,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 7.395e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.8e-06,
W => Wcm_1,
Wcm_1init => 6.2e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.8e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.09e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net2
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 5033f35cafbbaff204054ca09b120945 | 0.59209 | 3.032334 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd | 3 | 2,517 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_cpu_pkg is
-- Instruction bit 14..12: alu operation
-- Instruction bit 11: when 1, accu is updated
-- Instruction bit 15: when 0, flags are updated
-- Instruction Set (bit 10...0) are address when needed
-- ALU
constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
constant c_in : std_logic_vector(15 downto 11) := X"6" & '1'; -- ext
-- no update flags
constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- Specials
constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
constant c_branch : std_logic_vector(15 downto 14) := "11";
-- Branches (bit 10..0) are address
constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
-- ALU operations
constant c_alu_load : std_logic_vector(2 downto 0) := "000";
constant c_alu_or : std_logic_vector(2 downto 0) := "001";
constant c_alu_and : std_logic_vector(2 downto 0) := "010";
constant c_alu_xor : std_logic_vector(2 downto 0) := "011";
constant c_alu_add : std_logic_vector(2 downto 0) := "100";
constant c_alu_sub : std_logic_vector(2 downto 0) := "101";
end;
| gpl-3.0 | ef8ec1e71c208b1769227d26773b0bdf | 0.563369 | 3.14625 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op966_16.vhdl | 1 | 7,747 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
terminal net15: electrical;
terminal net16: electrical;
terminal net17: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net11
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net12,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net12
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net13
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net13,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net14,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net14
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net15
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net15,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net16,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net16
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net17
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net17,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 53e17a7c17d82c1317a1a95523a2cc5d | 0.573383 | 3.063266 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/noise_generator.vhd | 5 | 2,044 | library ieee;
use ieee.std_logic_1164.all;
entity noise_generator is
generic (
g_type : string := "Fibonacci"; -- can also be "Galois"
g_polynom : std_logic_vector := X"E10000";
g_fixed_polynom : boolean := true;
g_seed : std_logic_vector := X"000001" );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
polynom : in std_logic_vector(g_polynom'length-1 downto 0) := (others => '0');
q : out std_logic_vector(g_polynom'length-1 downto 0) );
end noise_generator;
architecture gideon of noise_generator is
signal c_poly : std_logic_vector(g_polynom'length-1 downto 0);
signal reg : std_logic_vector(g_polynom'length-1 downto 0);
begin
assert (g_type = "Fibonacci") or (g_type = "Galois")
report "Type of LFSR should be Fibonacci or Galois.."
severity failure;
c_poly <= g_polynom when g_fixed_polynom else polynom;
process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
if enable='1' then
if g_type = "Fibonacci" then
new_bit := '0';
for i in c_poly'range loop
if c_poly(i)='1' then
new_bit := new_bit xor reg(i);
end if;
end loop;
reg <= reg(reg'high-1 downto 0) & new_bit;
else -- "Galois", enforced by assert
if reg(reg'high)='1' then
reg <= (reg(reg'high-1 downto 0) & '0') xor c_poly;
else
reg <= reg(reg'high-1 downto 0) & '1';
end if;
end if;
end if;
if reset='1' then
reg <= g_seed;
end if;
end if;
end process;
q <= reg;
end gideon;
| gpl-3.0 | bc7f0bf3d3671e7ee418a74b2260e48c | 0.46771 | 3.757353 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd | 1 | 2,780 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
entity zpu_wb_bridge is
port ( -- Native ZPU interface
clk : in std_logic;
areset : in std_logic;
mem_req : in std_logic;
mem_we : in std_logic;
mem_ack : out std_logic;
mem_read : out std_logic_vector(wordSize-1 downto 0);
mem_write : in std_logic_vector(wordSize-1 downto 0);
out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
-- Wishbone from ZPU
zpu_wb_i : in wishbone_bus_out;
zpu_wb_o : out wishbone_bus_in);
end zpu_wb_bridge;
architecture behave of zpu_wb_bridge is
begin
mem_read <= zpu_wb_i.dat;
mem_ack <= zpu_wb_i.ack;
zpu_wb_o.adr <= out_mem_addr;
zpu_wb_o.dat <= mem_write;
zpu_wb_o.sel <= mem_writeMask;
zpu_wb_o.stb <= mem_req;
zpu_wb_o.cyc <= mem_req;
zpu_wb_o.we <= mem_we;
end behave;
| gpl-2.0 | 53911de4f0cf961ba06450bf494fd81e | 0.691727 | 3.289941 | false | false | false | false |
chrismasters/fpga-space-invaders | project/spaceinvaders_testbench.vhd | 1 | 1,597 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT spaceinvaders
PORT(
clk : IN std_logic;
reset : IN std_logic;
red : OUT std_logic_vector(3 downto 0);
green : OUT std_logic_vector(3 downto 0);
blue : OUT std_logic_vector(3 downto 0);
hsync : OUT std_logic;
vsync : OUT std_logic;
leds : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal red : STD_LOGIC_VECTOR (3 downto 0);
signal green : STD_LOGIC_VECTOR (3 downto 0);
signal blue : STD_LOGIC_VECTOR (3 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal reset : std_logic;
signal leds : STD_LOGIC_VECTOR (3 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
--constant clk_period : time := 10 ns;
--constant clk_period : time := 7.518ns;
BEGIN
-- Component Instantiation
uut: spaceinvaders PORT MAP(
clk => clk,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vsync,
reset => reset,
leds => leds
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
wait;
end process;
END;
| mit | d64338f27f9d660bc49dc8bec533c07a | 0.627426 | 3.4197 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op331_5sk1_0.vhdl | 1 | 7,268 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 5.805e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 5.805e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => W_0,
W_0init => 6.635e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.2e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1e-06,
W => Wcm_2,
Wcm_2init => 2.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1e-06,
W => Wcmout_2,
Wcmout_2init => 2.75e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.2e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.2e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1e-06,
W => Wcm_2,
Wcm_2init => 2.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1e-06,
W => Wcmout_2,
Wcmout_2init => 2.75e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.2e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.5e-07,
W => Wcm_1,
Wcm_1init => 6.55e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.5e-07,
W => Wcmout_1,
Wcmout_1init => 1.33e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 6b770926becbe75a036ed672c3187628 | 0.582416 | 2.922396 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_sim/dual_iec_processor_tb.vhd | 5 | 5,118 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity dual_iec_processor_tb is
end dual_iec_processor_tb;
architecture tb of dual_iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal master_req : t_io_req;
signal master_resp : t_io_resp;
signal slave_req : t_io_req;
signal slave_resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_master: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => master_req,
resp => master_resp,
clk_o => master_clk_o,
clk_i => iec_clock,
data_o => master_data_o,
data_i => iec_data,
atn_o => master_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
i_slave: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => slave_req,
resp => slave_resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => open,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_master" )
port map (
clock => clock,
req => master_req,
resp => master_resp );
i_io_bfm2: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_slave" )
port map (
clock => clock,
req => slave_req,
resp => slave_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_master", iom);
io_write(iom, X"3", X"01"); -- enable master
io_write(iom, X"5", X"4D"); -- switch to master mode
io_write(iom, X"4", X"2A"); -- listen 10
io_write(iom, X"4", X"F0"); -- open file on channel 0
io_write(iom, X"5", X"4C"); -- attention to TX
io_write(iom, X"4", X"41"); -- 'A'
io_write(iom, X"5", X"01"); -- EOI
io_write(iom, X"4", X"42"); -- 'B'
io_write(iom, X"5", X"4D"); -- again, be master
io_write(iom, X"4", X"3F"); -- unlisten
io_write(iom, X"4", X"4A"); -- talk #10!
io_write(iom, X"4", X"60"); -- give data from channel 0
io_write(iom, X"5", X"4A"); -- attention to RX turnaround
wait;
end process;
process
variable ios : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_slave", ios);
io_write(ios, X"3", X"01"); -- enable slave
while true loop
io_read(ios, X"2", stat);
if stat(0)='0' then -- byte available
io_read(ios, X"6", data);
if stat(7)='1' then -- control byte
report "Control byte received: " & hstr(data);
if (data = X"43") then
report "Talk back!";
io_write(ios, X"4", X"31");
io_write(ios, X"4", X"32");
io_write(ios, X"4", X"33");
io_write(ios, X"5", X"01"); -- EOI
io_write(ios, X"4", X"34");
end if;
else
report "Data byte received: " & hstr(data);
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 | 9eeac5ad7e46a53e6a678be28c4d7629 | 0.44744 | 3.474542 | false | false | false | false |
pemb/siphash | tb_siphash.vhd | 1 | 3,533 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.siphash_package.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity tb_siphash is
end entity;
architecture testbench of tb_siphash is
signal m : std_logic_vector(BLOCK_WIDTH-1 downto 0) := (others => '0');
signal b : std_logic_vector(BYTES_WIDTH-1 downto 0) := (others => '0');
signal rst_n: std_logic := '0';
signal clk : std_logic := '0';
signal init : std_logic := '0';
signal load_k : std_logic := '0';
signal init_ready, hash_ready : std_logic;
signal hash : std_logic_vector(HASH_WIDTH-1 downto 0);
signal counter : integer := 0;
signal test_finished : boolean := false;
signal key_m : std_logic_vector(BLOCK_WIDTH-1 downto 0);
signal blk_m : std_logic_vector(BLOCK_WIDTH-1 downto 0);
begin
m <= key_m when load_k = '1' else blk_m;
hash_core: siphash
port map(m, b, rst_n, clk, init, load_k, init_ready, hash_ready, hash);
reset: process
begin
wait for 1 ns;
rst_n <= '1';
wait;
end process;
clock: process
begin
wait for 2 ns;
clk <= not clk;
if clk = '0' and test_finished then
wait;
end if;
end process;
-- uncomment this process to get clock by clock debug info
--print: process (clk)
-- variable s: line;
--begin
-- if rising_edge(clk) then
-- counter <= counter + 1;
-- write (s, String'(lf & "clock edge "));
-- write (s, counter);
-- write (s, String'(lf & "m: "));
-- hwrite (s, m);
-- write (s, String'(lf & "b: "));
-- hwrite (s, b);
-- write (s, String'(lf & "rst_n: "));
-- write (s, rst_n);
-- write (s, String'(lf & "init: "));
-- write (s, init);
-- write (s, String'(lf & "load_k: "));
-- write (s, load_k);
-- write (s, String'(lf & "init_ready: "));
-- write (s, init_ready);
-- write (s, String'(lf & "hash_ready: "));
-- write (s, hash_ready);
-- write (s, String'(lf & "hash: "));
-- hwrite (s, hash);
-- writeline (output, s);
-- end if;
--end process;
key: process
begin
wait until rst_n = '1';
load_k <= '1';
key_m <= x"0706050403020100";
wait until clk = '1';
key_m <= x"0f0e0d0c0b0a0908";
wait until clk = '1';
load_k <= '0';
wait;
end process;
data: process
variable bytes: integer;
variable l : line;
variable real_hash : std_logic_vector(HASH_WIDTH-1 downto 0);
variable success : boolean := true;
begin
wait until load_k = '0';
for i in 0 to 63 loop
init <= '1';
for blocks in 0 to i/8 loop
if (blocks+1) * 8 < i then
bytes := 8;
else
bytes := i-(blocks*8);
end if;
b <= std_logic_vector(to_unsigned(bytes,BYTES_WIDTH));
blk_m <= (others => '0');
for count in 0 to bytes-1 loop
blk_m(count*8+7 downto count*8) <=
std_logic_vector(to_unsigned(count+blocks*8,8));
end loop;
wait until clk = '1';
init <= '0';
end loop;
b <= "0000";
wait until hash_ready = '1';
readline(input, l);
hread(l, real_hash);
assert hash = real_hash report
"test vector failed for " & integer'image(i) & " bytes"
severity error;
success := hash = real_hash and success;
end loop;
test_finished <= true;
if success then
write (l, String'("test vector ok"));
writeline(output, l);
end if;
wait;
end process;
end testbench;
| gpl-3.0 | d4793798f93c99eb0e1ed889e5270154 | 0.556468 | 3.140444 | false | true | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/hf_noise_tb.vhd | 5 | 1,386 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity hf_noise_tb is
end;
architecture tb of hf_noise_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : signed(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_hf: entity work.hf_noise
generic map (
g_hp_filter => true )
port map (
clock => clock,
reset => reset,
q => q );
process
variable stat : file_open_status;
file myfile : text;
variable v_line : line;
constant c_filename : string := "hello";
begin
-- open file
file_open(stat, myfile, c_filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & c_filename & " for writing."
severity failure;
wait until reset='0';
wait until clock='1';
for i in 1 to 1024*1024 loop
wait until clock='1';
write(v_line, integer'image(to_integer(q)));
writeline(myfile, v_line);
end loop;
file_close(myfile);
report "Done!" severity failure;
wait;
end process;
end tb;
| gpl-3.0 | 58ac7b8c85141b71be79ef3ddd240031 | 0.504329 | 3.904225 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd | 2 | 18,273 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
slave_wait <= dscl_oen and not sSCL;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ( (cnt = 0) or (ena = '0') ) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= scl_i;
sSDA <= sda_i;
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen);
else
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
| gpl-2.0 | fb8b2b557e0d77a8854cb62983793b99 | 0.453346 | 3.896993 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_15.vhdl | 1 | 5,465 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 39573aef3bd310a9481c5d92f75618f5 | 0.578225 | 3.146229 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_sim/mblite_simu.vhd | 1 | 4,848 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
core0 : core
port map (
imem_o => imem_o,
imem_i => imem_i,
dmem_o => dmem_o,
dmem_i => dmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
-- IRQ generation @ 250 kHz (every 4 us)
process
begin
for i in 1 to 50 loop
wait for 4 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
for i in 1 to 10 loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait for 10 us;
wait until clock='1';
irq_i <= '0';
end loop;
wait;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if imem_o.ena_o = '1' then
imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2))));
-- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then
-- report "Suspicious CMPS" severity warning;
-- end if;
end if;
if dmem_o.ena_o = '1' then
if dmem_o.adr_o(31 downto 25) = "0000000" then
if dmem_o.we_o = '1' then
for i in 0 to 3 loop
if dmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if dmem_o.we_o = '1' then -- write
case dmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := dmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(dmem_o.adr_o) & " dropped";
end case;
else -- read
case dmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
dmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
dmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
dmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
dmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(dmem_o.adr_o) & " dropped";
dmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
imem_i.ena_i <= '1';
dmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | d3594afcb5f03739fb33e4c364a8dd65 | 0.422236 | 3.906527 | false | false | false | false |
KB777/1541UltimateII | fpga/io/command_interface/vhdl_source/command_protocol.vhd | 1 | 13,404 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
io_irq : out std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal irq_mask : std_logic_vector(2 downto 0);
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_cif_io_irq_mask =>
irq_mask <= io_req.data(2 downto 0);
when c_cif_io_irq_mask_set =>
irq_mask <= irq_mask or io_req.data(2 downto 0);
when c_cif_io_irq_mask_clear =>
irq_mask <= irq_mask and not io_req.data(2 downto 0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when c_cif_io_irq_mask =>
io_resp.data(2 downto 0) <= irq_mask;
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
irq_mask <= "111";
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
io_irq <= '1' when (handshake_in and not irq_mask) /= "000" else '0';
end architecture;
| gpl-3.0 | 40d9f6897439fa22110044880a276934 | 0.497463 | 4.027644 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/delta_sigma_2to5.vhd | 5 | 2,460 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 5630f8596817a523cbb9d8c67b420b4b | 0.444715 | 3.855799 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op336_2.vhdl | 1 | 5,750 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | dffe009c9413e64438c8cebe0b99d434 | 0.574435 | 3.093061 | false | false | false | false |
KB777/1541UltimateII | fpga/1541/vhdl_source/floppy_param_mem.vhd | 1 | 2,862 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Parameter memory
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity floppy_param_mem is
port (
clock : in std_logic;
reset : in std_logic;
cpu_write : in std_logic;
cpu_ram_en : in std_logic;
cpu_addr : in std_logic_vector(10 downto 0);
cpu_wdata : in std_logic_vector(7 downto 0);
cpu_rdata : out std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
bit_time : out unsigned(8 downto 0);
track_start : out std_logic_vector(25 downto 0);
max_offset : out std_logic_vector(13 downto 0) );
end floppy_param_mem;
architecture gideon of floppy_param_mem is
signal toggle : std_logic;
signal param_addr : std_logic_vector(8 downto 0);
signal param_data : std_logic_vector(31 downto 0);
begin
ram: RAMB16_S9_S36
port map (
CLKA => clock,
SSRA => reset,
ENA => cpu_ram_en,
WEA => cpu_write,
ADDRA => cpu_addr,
DIA => cpu_wdata,
DIPA => "0",
DOA => cpu_rdata,
DOPA => open,
CLKB => clock,
SSRB => reset,
ENB => '1',
WEB => '0',
ADDRB => param_addr,
DIB => X"00000000",
DIPB => X"0",
DOB(31 downto 24) => param_data(7 downto 0), -- CPU writes big endian, bram is little endian
DOB(23 downto 16) => param_data(15 downto 8),
DOB(15 downto 8) => param_data(23 downto 16),
DOB(7 downto 0) => param_data(31 downto 24),
DOPB => open );
param_addr <= '0' & track & toggle;
process(clock)
begin
if rising_edge(clock) then
if toggle='1' then -- even addresses (one clock later)
track_start <= param_data(track_start'range);
else
max_offset <= param_data(max_offset'range);
bit_time <= unsigned(param_data(bit_time'high+16 downto 16));
end if;
if reset='1' then
toggle <= '0';
else
toggle <= not toggle;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | b2e2d3177187e7e9c0ca783428fb134a | 0.473096 | 3.857143 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/all_carts_v4.vhd | 3 | 19,965 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0ECC000"; -- multiple of 16K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
ethernet_enable : in std_logic := '1';
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
cart_logic : in std_logic_vector(3 downto 0); -- 1 out of 16 logic emulations
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ram_select : std_logic;
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal eth_addr : boolean;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(3 downto 0) := "0000";
constant c_8k : std_logic_vector(3 downto 0) := "0001";
constant c_16k : std_logic_vector(3 downto 0) := "0010";
constant c_16k_umax : std_logic_vector(3 downto 0) := "0011";
constant c_fc3 : std_logic_vector(3 downto 0) := "0100";
constant c_ss5 : std_logic_vector(3 downto 0) := "0101";
constant c_retro : std_logic_vector(3 downto 0) := "0110";
constant c_action : std_logic_vector(3 downto 0) := "0111";
constant c_system3 : std_logic_vector(3 downto 0) := "1000";
constant c_domark : std_logic_vector(3 downto 0) := "1001";
constant c_ocean128 : std_logic_vector(3 downto 0) := "1010";
constant c_ocean256 : std_logic_vector(3 downto 0) := "1011";
constant c_easy_flash : std_logic_vector(3 downto 0) := "1100";
constant c_epyx : std_logic_vector(3 downto 0) := "1110";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
begin
serve_enable <= cart_en or kernal_enable;
slot_addr <= std_logic_vector(slot_req.bus_address);
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
allow_bank <= '0';
ram_select <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
ram_select <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_retro | c_action =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(1)='0' then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
else -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
-- if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
-- cart_en <= '0'; -- permanent off
-- end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- decode address DE02-DE0F
eth_addr <= slot_addr(15 downto 4) = X"DE0" and slot_addr(3 downto 1) /= "000" and ethernet_enable='1';
-- determine address
-- process(cart_logic_d, cart_base_d, slot_addr, mode_bits, bank_bits, do_io2, allow_bank, eth_addr)
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank, eth_addr, kernal_area)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 32K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
when c_fc3 =>
mem_addr_i(15 downto 0) <= bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when others =>
null;
end case;
if kernal_area='1' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
end if;
-- if eth_addr then
-- mem_addr_i(25 downto 21) <= eth_base(25 downto 21);
-- mem_addr_i(20) <= '1'; -- indicate it is a slot access
-- allow_write <= '1'; -- we should also be able to write to the ethernet chip
-- -- invert bit 3
-- mem_addr_i(3) <= not slot_addr(3);
-- -- leave other bits in tact
-- end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
slot_resp.irq <= '0';
end gideon;
| gpl-3.0 | 56b6238c151c05e3e1eea8694b1722f3 | 0.42289 | 3.613575 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_7sk1_0.vhdl | 1 | 6,610 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 8.7e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 8.7e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 4.15e-06
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.5e-06,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.5e-06,
W => Wcmcout_2,
Wcmcout_2init => 6.235e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.5e-06,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.5e-06,
W => Wcmcout_2,
Wcmcout_2init => 6.235e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.3e-06,
W => Wcm_1,
Wcm_1init => 3.555e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.3e-06,
W => Wcmout_1,
Wcmout_1init => 2.335e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 3.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 3.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 3.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 3.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 3.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 3.45e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 04858ceb010af6e46002e169e67b2ac3 | 0.583661 | 2.933866 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/c2n_record/vhdl_sim/c2n_record_tb.vhd | 5 | 3,986 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/148/132/1
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity c2n_record_tb is
end c2n_record_tb;
architecture tb of c2n_record_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal phi2_tick : std_logic := '0';
signal c64_stopped : std_logic := '0';
signal c2n_motor : std_logic := '0';
signal c2n_sense : std_logic := '0';
signal c2n_read : std_logic := '0';
signal c2n_write : std_logic := '0';
type t_int_vec is array(natural range <>) of integer;
constant c_test_vector : t_int_vec := ( 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53,
100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
2000, 2010, 2020, 2030, 2040, 2041, 2042, 2043, 2044, 2045,
2046, 2046, 2046, 2047, 2047, 2047, 2047, 2047, 2047, 2048,
2048, 2048, 2048, 2048, 2048, 2050, 2060, 2070, 2080,
2090, 2090, 2090, 2090, 2090, 2090, 2090, 2090 );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.c2n_record
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
phi2_tick => phi2_tick,
c64_stopped => c64_stopped,
c2n_motor => c2n_motor,
c2n_sense => c2n_sense,
c2n_read => c2n_read,
c2n_write => c2n_write );
i_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
if count = 9 then
count := 0;
phi2_tick <= '1';
else
count := count + 1;
phi2_tick <= '0';
end if;
end if;
end process;
p_generate: process
begin
-- for i in 0 to 511 loop
-- wait for 3200 ns; -- 02
-- c2n_read <= '1', '0' after 600 ns;
-- end loop;
for i in c_test_vector'range loop
wait for c_test_vector(i) * 200 ns; -- 200 ns is one phi2_tick.
c2n_read <= '1', '0' after 600 ns;
end loop;
wait;
end process;
p_test: process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable received : integer := 0;
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"00", X"01"); -- enable rising edge recording
wait for 1 us;
c2n_sense <= '1';
wait for 1 us;
c2n_motor <= '1';
while true loop
io_read(io, X"00", data);
if data(7)='1' then
io_read(io, X"800", data);
report hstr(data);
received := received + 1;
if received = 50 then
wait for 10 us;
io_write(io, X"00", X"00"); -- disable
wait;
end if;
end if;
end loop;
wait;
end process;
end tb;
| gpl-3.0 | bd63f7d082f2261ccaf3f84a5351441b | 0.421977 | 3.714818 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd | 2 | 1,133 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spi_boot_pack is
function "=" (a : std_logic; b : integer) return boolean;
end spi_boot_pack;
package body spi_boot_pack is
function "=" (a : std_logic; b : integer) return boolean is
variable result_v : boolean;
begin
result_v := false;
case a is
when '0' =>
if b = 0 then
result_v := true;
end if;
when '1' =>
if b = 1 then
result_v := true;
end if;
when others =>
null;
end case;
return result_v;
end;
end spi_boot_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: spi_boot_pack-p.vhd,v $
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | fce1a81df1095556cc4ad43f378fecc2 | 0.402471 | 4.060932 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/deserializer/vhdl_source/deserializer.vhd | 5 | 1,272 |
library ieee;
use ieee.std_logic_1164.all;
entity deserializer is
port (
clock : in std_logic;
sync : in std_logic;
rxd : in std_logic;
txd : out std_logic;
io : inout std_logic_vector(11 downto 0) );
end deserializer;
architecture gideon of deserializer is
signal index : integer range 0 to 31;
signal io_t : std_logic_vector(io'range) := (others => '0');
signal io_o : std_logic_vector(io'range) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
if sync='1' then
index <= 0;
elsif index /= 31 then
index <= index + 1;
end if;
if index <= io'high then
txd <= io(index);
else
txd <= '0';
end if;
if index <= io'high then
io_o(index) <= rxd;
elsif index < (2*io'length) then
io_t(index - io'length) <= rxd;
end if;
end if;
end process;
r_out: for i in io'range generate
io(i) <= io_o(i) when io_t(i)='1' else 'Z';
end generate;
end gideon;
| gpl-3.0 | d264efc0cf163873a44337d462b23e34 | 0.457547 | 3.797015 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op954_4.vhdl | 1 | 4,611 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net5
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4abc049f50524b58e56151565dde74fe | 0.585556 | 3.217725 | false | false | false | false |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/pdi_dpr_Altera.vhd | 1 | 6,139 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.02 zelenkaj changed header
-- 2012-01-03 V0.03 zelenkaj added initialization file (mif)
-- 2012-02-21 V0.05 zelenkaj replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "../mif/pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | a99963dfd4fa41251a5415099f4756e4 | 0.609383 | 3.153056 | false | false | false | false |
ferdoctor/I2S_RX | receiver.vhd | 1 | 5,276 | ----------------------------------------------------------------------------------
-- I2S Receiver Module
-- Copyright (c) Fernando Rodriguez, 2007
--
-- Create Date: 14:16:59 06/21/2007
-- Design Name: I2S
-- Module Name: receiver - Behavioral
-- Project Name: I2S Receiver
--
-- This file is part of I2S_RX.
-- I2S_RX is free software: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- I2S_RX is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with I2S_RX. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.i2s.ALL;
entity receiver is
Port (
--I2S INPUTS (NOTE ALL INPUTS NEED TO BE SYNCHRONOUS TO EACH OTHER)
LRCK : in STD_LOGIC; --I2S L/R INPUT
BCK : in STD_LOGIC; --I2S CLOCK INPUT
DIN : in STD_LOGIC_VECTOR (num_inputs-1 downto 0); --I2S DATA INPUTS
--HOST CPU BUS INTERFACE
INT : out std_logic; --INTerrupt signal (When FIFO is close to full)
OVERFLOW: out std_logic; --Signal that an OVERFLOW occurred (data was not read fast enough)
RESET : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0); --ADRESS bus
D : inout STD_LOGIC_VECTOR (7 downto 0); --Data Bus
NCS : in STD_LOGIC; --Chip Select
NRD : in STD_LOGIC; --Read Select
NWR : in STD_LOGIC); --Write Select
end receiver;
architecture Behavioral of receiver is
component i2s_fifo
port (
din: IN std_logic_VECTOR(27 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(27 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(9 downto 0));
end component;
signal fifo_din: std_logic_VECTOR(27 downto 0);
signal fifo_dout : std_logic_VECTOR(27 downto 0);
signal fifo_rd_en : std_logic;
signal fifo_wr_en : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_wr_count : std_logic_VECTOR(9 downto 0);
signal bus_clk : std_logic;
signal sr : sr_type; --shift registers to receive data
signal sr_latch : sr_type; --place to hold data when assembled
signal LRCKo : std_logic; --to detect change of LRCK signal
signal count : integer range 0 to 24;
signal sync :std_logic; --Determines when we are in sync with frame
begin
bus_clk <= not (NRD and NWR);
--This make fifo output data when CPU reads register 0.
fifo_rd_en <= '1' when (NCS='0' and NRD='0' and A(7 downto 2)="000000") else '0';
data_fifo : i2s_fifo
port map (
din => fifo_din,
rd_clk => bus_clk,
rd_en => fifo_rd_en,
rst => RESET,
wr_clk => BCK,
wr_en => fifo_wr_en,
dout => fifo_dout,
empty => fifo_empty,
full => fifo_full,
overflow => OVERFLOW,
wr_data_count => fifo_wr_count);
businterface:process (NCS, NRD, NWR, RESET)
begin
D <= (others => 'Z');
if (RESET='1') then
--fifo_out<=0;
elsif (NCS='0' and NRD='0') then
if (A(1 downto 0)="11") then
D<= "0000" & fifo_dout (27 downto 24);
else
D <= fifo_dout( 7+8*conv_integer(A(1 downto 0)) downto 8*conv_integer(A(1 downto 0)) ); --pass fifo data
end if;
end if;
end process; --businterface
sample : process (BCK)
begin
--fifo_wr_en<='0';
if (RESET='1') then
INT <='1';
LRCKo <= '0';
count<=0;
sync<='0';
elsif (BCK'event and BCK='1') then
fifo_wr_en<='0';
count<=count+1;
--first capture data
for i in num_inputs-1 downto 0 loop
sr(i)(23 downto 1) <= sr(i)(22 downto 0); --shift
sr(i)(0) <= DIN(i); --and read new data
end loop;
--check to see if LRCK has changed (meaning we have new data)
if (LRCK/=LRCKo) then
LRCKo<=LRCK;
count<=0; --reset at each change of LRCK
if (LRCK='0') then
sync<='1'; --we are synchronized
end if;
--latch all data of channel just received
for i in num_inputs-1 downto 0 loop
sr_latch(i)<=sr(i);
end loop;
end if; --LRCK\=LRCKo
--Now put the data in the fifo if needed
--We do this at time n for the Nth channel
--Remeber there are 2 channels, hence LRCK appears as MSB.
if (sync='1' and count>0 and count<num_inputs+1) then
fifo_wr_en<='1';
fifo_din<= LRCK & CONV_STD_LOGIC_VECTOR(count,log_num_inputs+1) & sr_latch(count-1);
end if;
--Check to see if we should interrupt
if (conv_integer(fifo_wr_count)>512) then
INT <= '0';
else
INT <='1';
end if;
end if;
end process; --sample
end Behavioral;
| lgpl-3.0 | 893f21ea35d1667183b727083cb7c3fd | 0.606141 | 3.099882 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/busses/vhdl_source/io_bus_bridge.vhd | 1 | 7,405 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_bridge is
generic (
g_addr_width : natural := 8 );
port (
clock_a : in std_logic;
reset_a : in std_logic;
req_a : in t_io_req;
resp_a : out t_io_resp;
clock_b : in std_logic;
reset_b : in std_logic;
req_b : out t_io_req;
resp_b : in t_io_resp );
end entity;
architecture rtl of io_bus_bridge is
-- CLOCK_A
signal to_wr_en : std_logic;
signal to_wr_din : std_logic_vector(g_addr_width+8 downto 0);
signal to_wr_full : std_logic;
signal from_rd_en : std_logic;
signal from_rd_dout : std_logic_vector(7 downto 0);
signal from_rd_empty: std_logic;
type t_state_a is (idle, pending_w, pending_r, wait_rdata);
signal state_a : t_state_a;
-- CLOCK B
signal from_wr_en : std_logic;
signal to_rd_en : std_logic;
signal to_rd_dout : std_logic_vector(g_addr_width+8 downto 0);
signal to_rd_empty : std_logic;
type t_state_b is (idle, start_tr, do_write, do_read);
signal state_b : t_state_b;
signal resp_ack : std_logic;
signal resp_ackr : std_logic;
begin
-- generate ack
process(clock_a)
begin
if rising_edge(clock_a) then
resp_ack <= '0';
resp_ackr <= '0';
case state_a is
when idle =>
if req_a.write='1' then
if to_wr_full = '1' then
state_a <= pending_w;
else
resp_ack <= '1';
end if;
elsif req_a.read='1' then
if to_wr_full = '1' then
state_a <= pending_r;
else
state_a <= wait_rdata;
end if;
end if;
when pending_w =>
if to_wr_full = '0' then
state_a <= idle;
resp_ack <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
state_a <= wait_rdata;
end if;
when wait_rdata =>
if from_rd_empty = '0' then
resp_ack <= '1';
resp_ackr <= '1';
state_a <= idle;
end if;
when others =>
null;
end case;
if reset_a = '1' then
state_a <= idle;
end if;
end if;
end process;
resp_a.data <= X"00" when resp_ackr = '0' else from_rd_dout;
resp_a.ack <= resp_ack;
process (state_a, to_wr_full, from_rd_empty, req_a)
begin
to_wr_en <= '0';
to_wr_din <= std_logic_vector(req_a.address(g_addr_width-1 downto 0)) & '0' & req_a.data;
from_rd_en <= '0';
case state_a is
when idle =>
if to_wr_full = '0' then
to_wr_en <= req_a.write or req_a.read;
to_wr_din(8) <= req_a.write;
end if;
when pending_w =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '0';
end if;
when wait_rdata =>
if from_rd_empty='0' then
from_rd_en <= '1';
end if;
end case;
end process;
i_heen: entity work.async_fifo
generic map (
g_data_width => g_addr_width + 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 5,
g_storage => "auto" )
port map (
wr_clock => clock_a,
wr_reset => reset_a,
wr_en => to_wr_en,
wr_din => to_wr_din,
wr_flush => '0',
wr_count => open,
wr_full => to_wr_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
rd_clock => clock_b,
rd_reset => reset_b,
rd_en => to_rd_en,
rd_dout => to_rd_dout,
rd_count => open,
rd_empty => to_rd_empty,
rd_almost_empty => open,
rd_error => open );
i_weer: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 5,
g_storage => "auto" )
port map (
wr_clock => clock_b,
wr_reset => reset_b,
wr_en => from_wr_en,
wr_din => resp_b.data,
wr_flush => '0',
wr_count => open,
wr_full => open, -- there are never more answers than questions, how polite
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
rd_clock => clock_a,
rd_reset => reset_a,
rd_en => from_rd_en,
rd_dout => from_rd_dout,
rd_count => open,
rd_empty => from_rd_empty,
rd_almost_empty => open,
rd_error => open );
process(clock_b)
begin
if rising_edge(clock_b) then
req_b.read <= '0';
req_b.write <= '0';
case state_b is
when idle =>
if to_rd_empty='0' then
state_b <= start_tr;
end if;
when start_tr =>
req_b.address(g_addr_width-1 downto 0) <= unsigned(to_rd_dout(g_addr_width+8 downto 9));
req_b.data <= to_rd_dout(7 downto 0);
if to_rd_dout(8)='1' then
req_b.write <= '1';
state_b <= do_write;
else
req_b.read <= '1';
state_b <= do_read;
end if;
when do_write =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
when do_read =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
end case;
if reset_b='1' then
state_b <= idle;
req_b <= c_io_req_init;
end if;
end if;
end process;
process(state_b, to_rd_empty, resp_b)
begin
to_rd_en <= '0';
from_wr_en <= '0';
case state_b is
when idle =>
if to_rd_empty = '0' then
to_rd_en <= '1';
end if;
when do_read =>
if resp_b.ack = '1' then
from_wr_en <= '1';
end if;
when others =>
null;
end case;
end process;
end rtl;
| gpl-3.0 | 106e9d79b09e925203cf5e246bbfa18d | 0.391762 | 3.708062 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/powerlink.vhd | 3 | 34,378 | ------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-23 V0.01 zelenkaj First version
-- 2010-09-13 V0.02 zelenkaj added selection Rmii / Mii
-- 2010-10-18 V0.03 zelenkaj added selection Big/Little Endian (pdi_par)
-- use bidirectional bus (pdi_par)
-- 2010-11-23 V0.04 zelenkaj Added 2 GPIO signals to parallel interface
-- Added Operational Flag to simple I/O interface
-- Omitted T/RPDO descriptor sections in DPR
-- Added generic to set duration of valid assertion (portio)
-- 2010-11-29 V0.05 zelenkaj Added Big/Little Endian (pdi_spi)
-- 2010-12-06 V0.06 zelenkaj Bugfix: ap_irq was not driven in SPI configuration
-- 2011-01-10 V0.07 zelenkaj Added 2-stage sync to SPI input pins
-- 2011-02-24 V0.08 zelenkaj minor changes (naming conventions Mii->SMI)
-- 2011-03-14 V0.09 zelenkaj minor change, added generic for rx packet buffer location
-- 2011-03-21 V0.10 zelenkaj clean up
-- 2011-03-28 V0.20 zelenkaj Changed: Structure of Control/Status Register
-- Added: LED
-- Added: Events
-- Added/Changed: Asynchronous buffer 2x Ping-Pong
-- 2011-04-04 V0.21 zelenkaj parallel interface, sync moved to pdi_par
-- minor: led_status is the official name
-- 2011-04-26 V0.22 zelenkaj generic for clock domain selection
-- 2011-04-28 V0.23 zelenkaj second cmp timer of openMAC is optinal by generic
-- generic for second phy port of openMAC
-- 2011-05-06 V0.24 zelenkaj some naming convention changes
-- bug fix: use the RX_ER signal, it has important meaning!
-- 2011-05-09 V0.25 zelenkaj Hardware Acceleration (HW ACC) added.
-- 2011-07-23 V0.26 zelenkaj openFILTER enhanced by RxErr signal
-- 2011-07-25 V0.27 zelenkaj LED gadget and asynchronous buffer optional
-- 2011-08-08 V0.28 zelenkaj LED gadget enhancement -> added 8 general purpose outputs
-- 2011-08-02 V1.00 zelenkaj exchanged Avalon interface with entity openMAC_Ethernet
-- 2011-09-05 V1.01 zelenkaj SPI PDI missed to connect async irq to toplevel
-- 2011-10-20 V1.02 zelenkaj SMI export of in, out and tristate, endian generic
-- 2011-11-07 V1.03 zelenkaj dma generic for PLB/AXI support necessary
-- 2011-11-21 V1.04 zelenkaj added time synchronization feature
-- 2011-11-28 V1.05 zelenkaj added waitrequest signals to pdi pcp/ap
-- 2011-11-29 V1.06 zelenkaj event is optional
-- 2011-11-30 V1.07 zelenkaj Added generic for DMA observer
-- 2011-12-02 V1.08 zelenkaj Added I, O and T instead of IO ports
-- 2012-01-09 V1.09 zelenkaj Added ap_syncIrq for external AP
-- 2012-01-26 V1.10 zelenkaj Added generic for SMI generation and one SMI ports
-- Omit hwacc options, since we are fast enough!
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity powerlink is
generic(
-- GENERAL GENERICS --
endian_g : string := "little";
genOnePdiClkDomain_g : boolean := false;
genPdi_g : boolean := true;
genInternalAp_g : boolean := true;
genSimpleIO_g : boolean := false;
genSpiAp_g : boolean := false;
-- OPENMAC GENERICS
Simulate : boolean := false;
iBufSize_g : integer := 1024;
iBufSizeLOG2_g : integer := 10;
useRmii_g : boolean := true; --use Rmii
useIntPacketBuf_g : boolean := true; --internal packet buffer
useRxIntPacketBuf_g : boolean := true; --rx buffer located in internal packet buffer
use2ndCmpTimer_g : boolean := true; --use second cmp timer (used in PDI)
use2ndPhy_g : boolean := true; --use second phy (introduces openHUB)
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true; --hold burst value during transfer
m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g
m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
genSmiIO : boolean := true; --drive SMI IO if true
gNumSmi : integer range 1 to 2 := 2; --number of SMI used
-- PDI GENERICS
iRpdos_g : integer := 3;
iTpdos_g : integer := 1;
genABuf1_g : boolean := true; --if false iABuf1_g must be set to 0!
genABuf2_g : boolean := true; --if false iABuf2_g must be set to 0!
genLedGadget_g : boolean := false;
genTimeSync_g : boolean := false;
genEvent_g : boolean := false;
--PDO buffer size *3
iTpdoBufSize_g : integer := 100;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
--asynchronous buffer size
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iPdiRev_g : integer := 16#55AA#;
-- 8/16bit PARALLEL PDI GENERICS
papDataWidth_g : integer := 8;
papLowAct_g : boolean := false;
papBigEnd_g : boolean := false;
-- SPI GENERICS
spiCPOL_g : boolean := false;
spiCPHA_g : boolean := false;
spiBigEnd_g : boolean := false;
-- PORTIO
pioValLen_g : integer := 50; --clock ticks of pcp_clk
-- GENERAL TARGET DEPENDINGS
genIoBuf_g : boolean := true --generates IO buffers
);
port(
-- CLOCK / RESET PORTS
clk50 : in std_logic; --RMII clk
rst : in std_logic; --general reset
clkEth : in std_logic; --Tx Reg clk
m_clk : in std_logic; --openMAC DMA master clock
pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..)
clkPcp : in std_logic; --pcp clk
clkAp : in std_logic; --ap clk
rstPcp : in std_logic; --rst from pcp side
rstAp : in std_logic; --rst ap
-- OPENMAC
--- OPENMAC PORTS
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_byteenable : in std_logic_vector(1 downto 0);
mac_address : in std_logic_vector(11 downto 0);
mac_writedata : in std_logic_vector(15 downto 0);
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mac_irq : out std_logic := '0';
--- TIMER COMPARE PORTS
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_address : in std_logic_vector(1 downto 0);
tcp_writedata : in std_logic_vector(31 downto 0);
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
tcp_irq : out std_logic := '0';
--- MAC BUFFER PORTS
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_writedata : in std_logic_vector(31 downto 0);
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
--- OPENMAC DMA PORTS
m_read : OUT STD_LOGIC := '0';
m_write : OUT STD_LOGIC := '0';
m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0');
m_address : OUT STD_LOGIC_VECTOR(29 DOWNTO 0) := (others => '0');
m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0');
m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0');
m_waitrequest : IN STD_LOGIC;
m_readdatavalid : in STD_LOGIC := '0';
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
-- PDI
--- PCP PORTS
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_address : in std_logic_vector(12 downto 0);
pcp_writedata : in std_logic_vector(31 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
--- AP PORTS
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
---- AVALON
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_byteenable : in std_logic_vector(3 downto 0);
ap_address : in std_logic_vector(12 downto 0);
ap_writedata : in std_logic_vector(31 downto 0);
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_waitrequest : out std_logic;
---- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs_n : in std_logic;
pap_rd_n : in std_logic;
pap_wr_n : in std_logic;
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
---- SPI
spi_clk : in std_logic;
spi_sel_n : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic := '0';
---- simple I/O
smp_address : in std_logic;
smp_read : in std_logic;
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
smp_byteenable : in std_logic_vector(3 downto 0);
smp_waitrequest : out std_logic;
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0');
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
pio_operational : out std_logic := '0';
-- EXTERNAL
--- PHY MANAGEMENT
---- shared (valid if gNumSmi = 1)
phy_SMIClk : out std_logic := '0';
phy_SMIDat : inout std_logic := '1';
phy_SMIDat_I : in std_logic := '1';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
phy_Rst_n : out std_logic := '1';
---- PHY0 (valid if gNumSmi = 2)
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat : inout std_logic := '1';
phy0_SMIDat_I : in std_logic := '1';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_link : in std_logic := '0';
---- PHY1 (valid if gNumSmi = 2)
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat : inout std_logic := '1';
phy1_SMIDat_I : in std_logic := '1';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_Rst_n : out std_logic := '1';
phy1_link : in std_logic := '0';
--- RMII PORTS
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
--- MII PORTS
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
--- LEDs
led_error : out std_logic := '0';
led_status : out std_logic := '0';
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_gpo : out std_logic_vector(7 downto 0) := (others => '0')
);
end powerlink;
architecture rtl of powerlink is
signal smi_Clk : std_logic := '0';
signal smi_Di : std_logic := '0';
signal smi_Do : std_logic := '0';
signal smi_Doe : std_logic := '0';
signal phy_nResetOut : std_logic := '0';
signal irqToggle : std_logic := '0';
signal ap_chipselect_s : std_logic := '0';
signal ap_read_s : std_logic := '0';
signal ap_write_s : std_logic := '0';
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0');
signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0');
signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0');
signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0');
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic;
signal pap_wr_s : std_logic;
signal pap_be_s : std_logic_vector(pap_be'range);
signal pap_ack_s : std_logic;
signal ap_irq_s : std_logic;
signal ap_asyncIrq_s : std_logic;
signal spi_sel_s : std_logic;
signal spi_sel_s1 : std_logic;
signal spi_sel_s2 : std_logic;
signal spi_clk_s : std_logic;
signal spi_clk_s1 : std_logic;
signal spi_clk_s2 : std_logic;
signal spi_mosi_s : std_logic;
signal spi_mosi_s1 : std_logic;
signal spi_mosi_s2 : std_logic;
signal phyLink, phyAct : std_logic_vector(1 downto 0);
signal led_s : std_logic_vector(15 downto 0);
signal clkAp_s, rstAp_s : std_logic;
--PDI change buffer triggers for hw acc to pdi
signal rpdo_change_tog : std_logic_vector(2 downto 0);
signal tpdo_change_tog : std_logic;
begin
--general signals
clkAp_s <= clkAp when genOnePdiClkDomain_g = FALSE else clkPcp;
rstAp_s <= rstAp when genOnePdiClkDomain_g = FALSE else rstPcp;
phyLink <= phy1_link & phy0_link;
--LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S
led_error <= led_s(1);
led_status <= led_s(0);
led_phyLink <= led_s(4) & led_s(2);
led_phyAct <= led_s(5) & led_s(3);
led_opt <= led_s(7) & led_s(6);
led_gpo <= led_s(15 downto 8);
------------------------------------------------------------------------------------------------------------------------
--PCP + AP
genPdi : if genPdi_g and genInternalAp_g and not genSpiAp_g generate
--sync and async interrupt are driven by only one line
-- this gives some effort for Nios II AP ;)
ap_irq <= ap_irq_s or ap_asyncIrq_s;
-- added by mairt (2.3.2012)
-- microblaze can handle 2 interrupts
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
theAvalonPdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
iPdiRev_g => iPdiRev_g,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => genABuf1_g,
genABuf2_g => genABuf2_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rstAp_s,
ap_clk => clkAp_s,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_write => ap_write,
ap_byteenable => ap_byteenable,
ap_address => ap_address,
ap_writedata => ap_writedata,
ap_readdata => ap_readdata,
ap_waitrequest => ap_waitrequest,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdi;
--AP is external connected via parallel interface
genPdiPar : if genPdi_g and not genInternalAp_g and not genSpiAp_g generate
--only 8 or 16bit data width is allowed
ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 )
REPORT "External parallel port only allows 8 or 16bit data width!"
severity failure;
-------------------------------------------------------------------------------------
--convert active low signals to active high - respectively assign active high signals
theActiveLowGen : if papLowAct_g generate
pap_wr_s <= not pap_wr_n;
pap_rd_s <= not pap_rd_n;
pap_cs_s <= not pap_cs_n;
pap_be_s <= not pap_be_n;
end generate;
theActiveHighGen : if not papLowAct_g generate
pap_wr_s <= pap_wr;
pap_rd_s <= pap_rd;
pap_cs_s <= pap_cs;
pap_be_s <= pap_be;
end generate;
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
pap_ack <= pap_ack_s;
pap_ack_n <= not pap_ack_s;
--
-------------------------------------------------------------------------------------
theParPort : entity work.pdi_par
generic map (
papDataWidth_g => papDataWidth_g,
papBigEnd_g => papBigEnd_g,
papGenIoBuf_g => genIoBuf_g
)
port map (
-- 8/16bit parallel
pap_cs => pap_cs_s,
pap_rd => pap_rd_s,
pap_wr => pap_wr_s,
pap_be => pap_be_s,
pap_addr => pap_addr,
pap_data => pap_data,
pap_data_I => pap_data_I,
pap_data_O => pap_data_O,
pap_data_T => pap_data_T,
pap_ack => pap_ack_s,
pap_gpio => pap_gpio,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
-- clock for AP side
ap_reset => rstPcp,
ap_clk => clk50,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s
);
thePdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
iPdiRev_g => iPdiRev_g,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => genABuf1_g,
genABuf2_g => genABuf2_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rst,
ap_clk => clk50,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s,
ap_waitrequest => open,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdiPar;
--AP is extern connected via SPI
genPdiSpi : if genPdi_g and genSpiAp_g generate
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
spi_clk_s <= spi_clk;
spi_sel_s <= not spi_sel_n;
spi_mosi_s <= spi_mosi;
theSyncProc : process(clk50, rst)
begin
if rst = '1' then
spi_sel_s1 <= '0';
spi_sel_s2 <= '0';
spi_clk_s1 <= '0';
spi_clk_s2 <= '0';
spi_mosi_s1 <= '0';
spi_mosi_s2 <= '0';
elsif clk50 = '1' and clk50'event then
spi_sel_s1 <= spi_sel_s;
spi_sel_s2 <= spi_sel_s1;
spi_clk_s1 <= spi_clk_s;
spi_clk_s2 <= spi_clk_s1;
spi_mosi_s1 <= spi_mosi_s;
spi_mosi_s2 <= spi_mosi_s1;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------
thePdiSpi : entity work.pdi_spi
generic map (
spiSize_g => 8, --fixed value!
cpol_g => spiCPOL_g,
cpha_g => spiCPHA_g,
spiBigEnd_g => spiBigEnd_g
)
port map (
-- SPI
spi_clk => spi_clk_s2,
spi_sel => spi_sel_s2,
spi_miso => spi_miso,
spi_mosi => spi_mosi_s2,
-- clock for AP side
ap_reset => rstPcp,
ap_clk => clk50,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s
);
thePdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => genOnePdiClkDomain_g,
iPdiRev_g => iPdiRev_g,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => genABuf1_g,
genABuf2_g => genABuf2_g,
genLedGadget_g => genLedGadget_g,
genTimeSync_g => genTimeSync_g,
genEvent_g => genEvent_g,
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rst,
ap_clk => clk50,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s,
ap_waitrequest => open,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdiSpi;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--SIMPLE I/O CN
genSimpleIO : if genSimpleIO_g generate
thePortIO : entity work.portio
generic map (
pioValLen_g => pioValLen_g,
pioGenIoBuf_g => genIoBuf_g
)
port map (
s0_address => smp_address,
s0_read => smp_read,
s0_readdata => smp_readdata,
s0_write => smp_write,
s0_writedata => smp_writedata,
s0_byteenable => smp_byteenable,
s0_waitrequest => smp_waitrequest,
clk => clkPcp,
reset => rstPcp,
x_pconfig => pio_pconfig,
x_portInLatch => pio_portInLatch,
x_portOutValid => pio_portOutValid,
x_portio => pio_portio,
x_portio_I => pio_portio_I,
x_portio_O => pio_portio_O,
x_portio_T => pio_portio_T,
x_operational => pio_operational
);
end generate genSimpleIO;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT)
theOpenMac : entity work.openMAC_Ethernet
generic map (
endian_g => endian_g,
dma_highadr_g => m_address'high,
gen2ndCmpTimer_g => use2ndCmpTimer_g,
genHub_g => use2ndPhy_g,
iPktBufSizeLog2_g => iBufSizeLOG2_g,
iPktBufSize_g => iBufSize_g,
simulate => false,
useIntPktBuf_g => useIntPacketBuf_g,
useRmii_g => useRmii_g,
useRxIntPktBuf_g => useRxIntPacketBuf_g,
m_burstcount_width_g => m_burstcount_width_g,
m_burstcount_const_g => m_burstcount_const_g,
m_data_width_g => m_data_width_g,
m_tx_fifo_size_g => m_tx_fifo_size_g,
m_rx_fifo_size_g => m_rx_fifo_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
m_rx_burst_size_g => m_rx_burst_size_g,
genSmiIO => genSmiIO,
gNumSmi => gNumSmi,
genPhyActLed_g => genLedGadget_g,
gen_dma_observer_g => gen_dma_observer_g
)
port map(
clk => clk50,
clkx2 => clkEth,
pkt_clk => pkt_clk,
m_clk => m_clk,
rst => rst,
m_address => m_address,
m_burstcount => m_burstcount,
m_burstcounter => m_burstcounter,
m_byteenable => m_byteenable,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_write => m_write,
m_writedata => m_writedata,
m_waitrequest => m_waitrequest,
mac_rx_irq => open,
mac_tx_irq => open,
act_led => phyAct(0),
phy0_rst_n => phy0_Rst_n,
phy0_rx_dat => phy0_RxDat,
phy0_rx_dv => phy0_RxDv,
phy0_rx_err => phy0_RxErr,
phy0_smi_clk => phy0_SMICLK,
phy0_smi_dio => phy0_SMIDat,
phy0_smi_dio_I => phy0_SMIDat_I,
phy0_smi_dio_O => phy0_SMIDat_O,
phy0_smi_dio_T => phy0_SMIDat_T,
phy0_tx_dat => phy0_TxDat,
phy0_tx_en => phy0_TxEn,
phy1_rst_n => phy1_Rst_n,
phy1_rx_dat => phy1_RxDat,
phy1_rx_dv => phy1_RxDv,
phy1_rx_err => phy1_RxErr,
phy1_smi_clk => phy1_SMICLK,
phy1_smi_dio => phy1_SMIDat,
phy1_smi_dio_I => phy1_SMIDat_I,
phy1_smi_dio_O => phy1_SMIDat_O,
phy1_smi_dio_T => phy1_SMIDat_T,
phy1_tx_dat => phy1_TxDat,
phy1_tx_en => phy1_TxEn,
phyMii0_rx_clk => phyMii0_RxClk,
phyMii0_rx_dat => phyMii0_RxDat,
phyMii0_rx_dv => phyMii0_RxDv,
phyMii0_rx_err => phyMii0_RxEr,
phyMii0_tx_clk => phyMii0_TxClk,
phyMii0_tx_dat => phyMii0_TxDat,
phyMii0_tx_en => phyMii0_TxEn,
phyMii1_rx_clk => phyMii1_RxClk,
phyMii1_rx_dat => phyMii1_RxDat,
phyMii1_rx_dv => phyMii1_RxDv,
phyMii1_rx_err => phyMii1_RxEr,
phyMii1_tx_clk => phyMii1_TxClk,
phyMii1_tx_dat => phyMii1_TxDat,
phyMii1_tx_en => phyMii1_TxEn,
phy_rst_n => phy_Rst_n,
phy_smi_clk => phy_SMIClk,
phy_smi_dio_I => phy_SMIDat_I,
phy_smi_dio_O => phy_SMIDat_O,
phy_smi_dio_T => phy_SMIDat_T,
phy_smi_dio => phy_SMIDat,
pkt_address => mbf_address,
pkt_byteenable => mbf_byteenable,
pkt_chipselect => mbf_chipselect,
pkt_read => mbf_read,
pkt_readdata => mbf_readdata,
pkt_waitrequest => mbf_waitrequest,
pkt_write => mbf_write,
pkt_writedata => mbf_writedata,
s_address => mac_address,
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_irq => mac_irq,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata,
t_address => tcp_address,
t_byteenable => tcp_byteenable,
t_chipselect => tcp_chipselect,
t_irq => tcp_irq,
t_read => tcp_read,
t_readdata => tcp_readdata,
t_tog => irqToggle,
t_waitrequest => tcp_waitrequest,
t_write => tcp_write,
t_writedata => tcp_writedata
);
phyAct(1) <= phyAct(0);
--
------------------------------------------------------------------------------------------------------------------------
end rtl;
| gpl-2.0 | f77d4c35cc2f3303b34b49fa051380b6 | 0.54692 | 2.973618 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | brainfuck-machine/implementation/bfp.vhdl | 1 | 4,496 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use std.textio.all;
entity bfp is
port (ins_in : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
clk : in std_logic;
data_out: out std_logic_vector(7 downto 0);
halt : out std_logic -- no semicolon here!
);
end bfp;
architecture behv of bfp is
subtype bfp_instruction is std_logic_vector(2 downto 0);
subtype bfp_data is std_logic_vector(7 downto 0);
type insm_type is array(4095 downto 0) of bfp_instruction;
type datam_type is array(4095 downto 0) of bfp_data;
type stackm_type is array(4095 downto 0) of integer range 0 to 4095;
signal stage: integer range 0 to 2 := 0;
signal pc: integer range 0 to 4095 := 0;
signal ic: integer range 0 to 4095 := 0;
signal P: integer range 0 to 4095 := 0;
signal st: integer range 0 to 4095 := 0;
signal insm: insm_type;
signal datam: datam_type;
signal stackm: stackm_type;
begin
process(clk)
variable l: line;
variable bv: bit_vector(2 downto 0);
variable bv1: bit_vector(7 downto 0);
variable tst, tpc: integer;
begin
if clk = '1' then
case stage is
when 0 =>
-- input instructions
insm(ic) <= ins_in;
ic <= ic + 1;
bv := to_bitvector(ins_in);
if ieee.std_logic_1164."="(ins_in, "ZZZ") then
stage <= 1;
halt <= '0';
st <= 0;
for i in 0 to 4095 loop
datam(i) <= "00000000";
end loop;
end if;
when 1 =>
-- running
data_out <= "ZZZZZZZZ";
case insm(pc) is
when "000" =>
P <= P + 1;
pc <= pc + 1;
when "001" =>
P <= P - 1;
pc <= pc + 1;
when "010" =>
datam(P) <= datam(P) + 1;
pc <= pc + 1;
when "011" =>
datam(P) <= datam(P) - 1;
pc <= pc + 1;
when "100" =>
bv1 := to_bitvector(datam(P));
if ieee.std_logic_unsigned."/="(datam(P), "00000000") then
stackm(st) <= pc;
st <= st + 1;
end if;
if ieee.std_logic_1164."="(datam(P), "00000000") then
tst:=1;
tpc := pc;
while(tst/=0) loop
tpc := tpc + 1;
if ieee.std_logic_1164."="(insm(tpc), "100") then
tst := tst + 1;
end if;
if ieee.std_logic_1164."="(insm(tpc), "101") then
tst := tst - 1;
end if;
end loop;
pc <= tpc;
end if;
pc <= pc + 1;
when "101" =>
pc <= pc + 1;
if ieee.std_logic_unsigned."/="(datam(P), "00000000") then
pc <= stackm(st - 1);
end if;
st <= st - 1;
when "110" =>
data_out <= datam(P);
pc <= pc + 1;
when others =>
pc <= pc + 1;
end case;
if pc>ic then
stage <= 2;
end if;
when 2 =>
-- halt
halt <= '1';
end case;
end if;
end process;
end behv;
| gpl-3.0 | 96cdb21dc1944656dd893e4c74cc4972 | 0.358763 | 4.688217 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/sigma_delta_dac.vhd | 4 | 2,810 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sigma_delta_dac is
generic (
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end sigma_delta_dac;
architecture gideon of sigma_delta_dac is
-- signal converted : unsigned(g_width-1 downto 0);
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : unsigned(2 downto 0) := "000";
signal sine : signed(15 downto 0);
signal sine_enable : std_logic;
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
-- converted <= not sine(sine'high) & unsigned(sine(sine'high downto 0));
-- i_pilot: entity work.sine_osc
-- port map (
-- clock => clock,
-- enable => sine_enable,
-- reset => reset,
--
-- sine => sine,
-- cosine => open );
--
-- sine_enable <= '1' when divider="001" else '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
divider <= divider + 1;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
end if;
end if;
end process;
dac_out <= out_i;
end gideon;
| gpl-3.0 | 65d01a70c261e783f09e3e81d36b3226 | 0.523488 | 3.447853 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd | 2 | 7,821 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Testbench for ram_loader
--
-- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
entity tb_rl is
end tb_rl;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_rl is
component chip
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_n_i : in std_logic_vector(3 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
component card
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end component;
component ram_loader
port (
clk_i : in std_logic;
reset_i : in std_logic;
lamp_o : out std_logic;
cfg_clk_i : in std_logic;
cfg_data_i : in std_logic;
start_o : out std_logic;
mode_o : out std_logic;
done_o : out std_logic;
detached_i : in std_logic;
ram_addr_o : out std_logic_vector(15 downto 0);
ram_data_b : out std_logic_vector( 7 downto 0);
ram_ce_no : out std_logic_vector( 3 downto 0);
ram_oe_no : out std_logic;
ram_we_no : out std_logic
);
end component;
constant period_c : time := 100 ns;
constant rl_period_c : time := 20 ns;
constant reset_level_c : integer := 0;
signal clk_s : std_logic;
signal rl_clk_s: std_logic;
signal reset_s : std_logic;
-- SPI interface signals
signal spi_clk_s : std_logic;
signal spi_data_to_card_s : std_logic;
signal spi_data_from_card_s : std_logic;
signal spi_cs_n_s : std_logic;
-- config related signals
signal start_s : std_logic;
signal mode_s : std_logic;
signal config_n_s : std_logic;
signal cfg_init_n_s : std_logic;
signal cfg_done_s : std_logic;
signal dat_done_s : std_logic;
signal cfg_clk_s : std_logic;
signal cfg_dat_s : std_logic;
signal detached_s : std_logic;
signal set_sel_n_s : std_logic_vector(3 downto 0);
begin
set_sel_n_s <= (others => '1');
cfg_init_n_s <= '1';
cfg_done_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
dut_b : chip
port map (
clk_i => clk_s,
reset_i => reset_s,
set_sel_n_i => set_sel_n_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_from_card_s,
spi_data_out_o => spi_data_to_card_s,
start_i => start_s,
mode_i => mode_s,
config_n_o => config_n_s,
detached_o => detached_s,
cfg_init_n_i => cfg_init_n_s,
cfg_done_i => cfg_done_s,
dat_done_i => dat_done_s,
cfg_clk_o => cfg_clk_s,
cfg_dat_o => cfg_dat_s
);
card_b : card
generic map (
card_type_g => "Full Chip",
is_sd_card_g => 1
)
port map (
spi_clk_i => spi_clk_s,
spi_cs_n_i => spi_cs_n_s,
spi_data_i => spi_data_to_card_s,
spi_data_o => spi_data_from_card_s
);
rl_b : ram_loader
port map (
clk_i => rl_clk_s,
reset_i => reset_s,
lamp_o => open,
cfg_clk_i => cfg_clk_s,
cfg_data_i => cfg_dat_s,
start_o => start_s,
mode_o => mode_s,
done_o => dat_done_s,
detached_i => detached_s,
ram_addr_o => open,
ram_data_b => open,
ram_ce_no => open,
ram_oe_no => open,
ram_we_no => open
);
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
rl_clk: process
begin
rl_clk_s <= '0';
wait for rl_period_c / 2;
rl_clk_s <= '1';
wait for rl_period_c / 2;
end process rl_clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End of Simulation
-----------------------------------------------------------------------------
eos: process
begin
wait for 4 ms;
assert false
report "No checks have been performed. Investigate waveforms."
severity note;
assert false
report "End of simulation."
severity failure;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_rl.vhd,v $
-- Revision 1.1 2005/04/10 18:07:25 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 15208522177950172d4c6c2d81d5313e | 0.516686 | 3.612471 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op946_4.vhdl | 1 | 4,147 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | e127d789802de06c34e0e1f28481d0aa | 0.587895 | 3.257659 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/slot_timing.vhd | 4 | 5,720 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 63 := 0;
signal phase_l : integer range 0 to 63 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
constant c_sample : integer := 6;
constant c_probe_end : integer := 11;
constant c_sample_vic : integer := 10;
constant c_io : integer := 19;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- if (phi2_rec_i='0' and allow_tick_h) or
-- (phi2_rec_i='1' and allow_tick_l) then
-- phi2_rec_i <= PHI2;
-- end if;
-- related to rising edge
-- if then -- rising edge
if ((edge_recover = '1') and (phase_l = 24)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 63 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 46 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 63 then
phase_l <= phase_l + 1;
end if;
if phase_l = 46 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
if phase_h = 0 then
inhibit <= serve_en_i;
elsif phase_h = c_sample then
inhibit <= '0';
end if;
do_sample_addr <= '0';
if phase_h = timing_addr then
do_sample_addr <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
if serve_vic='1' then
if phase_l = (c_sample_vic - c_memdelay) then
inhibit <= serve_en_i;
elsif phase_l = (c_sample_vic - 1) then
do_sample_addr <= '1';
end if;
end if;
if phase_l = c_sample_vic then
inhibit <= '0';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 63;
phase_l <= 63;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
| gpl-3.0 | aa01c25f9deb0eb68282b86db7fdb3d1 | 0.427972 | 3.728814 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/usb_pkg.vhd | 3 | 10,573 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb_pkg is
type t_transaction_type is ( control, bulk, interrupt, isochronous );
type t_transaction_state is ( none, busy, done, error );
type t_pipe_state is ( invalid, initialized, stalled, aborted );
type t_direction is ( dir_in, dir_out );
type t_transfer_mode is ( direct, use_preamble, use_split );
type t_pipe is record
state : t_pipe_state;
direction : t_direction;
device_address : std_logic_vector(6 downto 0);
device_endpoint : std_logic_vector(3 downto 0);
max_transfer : unsigned(10 downto 0); -- could be encoded in less (3) bits (only 2^x)
data_toggle : std_logic;
control : std_logic; -- '1' if this pipe is treated as a control pipe
timeout : std_logic;
--transfer_mode : t_transfer_mode;
end record; -- 18 bits now with encoded max transfer, otherwise 26
type t_transaction is record
transaction_type : t_transaction_type;
state : t_transaction_state;
pipe_pointer : unsigned(4 downto 0); -- 32 pipes enough?
transfer_length : unsigned(10 downto 0); -- max 2K
buffer_address : unsigned(10 downto 0); -- 2K buffer
link_to_next : std_logic; -- when '1', no other events will take place (such as sof)
end record; -- 32 bits now
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe;
function t_pipe_to_data(i: t_pipe) return std_logic_vector;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction;
function t_transaction_to_data(i: t_transaction) return std_logic_vector;
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
constant c_cmd_get_status : std_logic_vector(3 downto 0) := X"1";
constant c_cmd_get_speed : std_logic_vector(3 downto 0) := X"2";
constant c_cmd_get_done : std_logic_vector(3 downto 0) := X"3";
constant c_cmd_do_reset_hs : std_logic_vector(3 downto 0) := X"4";
constant c_cmd_do_reset_fs : std_logic_vector(3 downto 0) := X"5";
constant c_cmd_disable_host : std_logic_vector(3 downto 0) := X"6";
constant c_cmd_abort : std_logic_vector(3 downto 0) := X"7";
constant c_cmd_sof_enable : std_logic_vector(3 downto 0) := X"8";
constant c_cmd_sof_disable : std_logic_vector(3 downto 0) := X"9";
constant c_cmd_set_gap : std_logic_vector(3 downto 0) := X"A";
constant c_cmd_set_busy : std_logic_vector(3 downto 0) := X"B";
constant c_cmd_clear_busy : std_logic_vector(3 downto 0) := X"C";
constant c_cmd_set_debug : std_logic_vector(3 downto 0) := X"D";
constant c_cmd_disable_scan : std_logic_vector(3 downto 0) := X"E";
constant c_cmd_enable_scan : std_logic_vector(3 downto 0) := X"F";
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector;
end package;
package body usb_pkg is
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe is
variable ret : t_pipe;
begin
case i(1 downto 0) is
when "01" =>
ret.state := initialized;
when "10" =>
ret.state := stalled;
when "11" =>
ret.state := aborted;
when others =>
ret.state := invalid;
end case;
if i(2) = '1' then
ret.direction := dir_out;
else
ret.direction := dir_in;
end if;
ret.device_address := i(9 downto 3);
ret.device_endpoint := i(13 downto 10);
ret.max_transfer := unsigned(i(24 downto 14));
-- max_transfer(3 + to_integer(unsigned(i(16 downto 14)))) <= '1'; -- set one bit
ret.data_toggle := i(25);
ret.control := i(26);
ret.timeout := i(31);
-- case i(28 downto 27) is
-- when "00" =>
-- ret.transfer_mode := direct;
-- when "01" =>
-- ret.transfer_mode := use_preamble;
-- when "10" =>
-- ret.transfer_mode := use_split;
-- when others =>
-- ret.transfer_mode := direct;
-- end case;
return ret;
end function;
function t_pipe_to_data(i: t_pipe) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when initialized => ret(1 downto 0) := "01";
when stalled => ret(1 downto 0) := "10";
when aborted => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "00";
end case;
if i.direction = dir_out then
ret(2) := '1';
else
ret(2) := '0';
end if;
ret(9 downto 3) := i.device_address;
ret(13 downto 10) := i.device_endpoint;
ret(24 downto 14) := std_logic_vector(i.max_transfer);
ret(25) := i.data_toggle;
ret(26) := i.control;
ret(31) := i.timeout;
-- case i.transfer_mode is
-- when direct => ret(28 downto 27) := "00";
-- when use_preamble => ret(28 downto 27) := "01";
-- when use_split => ret(28 downto 27) := "10";
-- when others => ret(28 downto 27) := "00";
-- end case;
return ret;
end function;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction is
variable ret : t_transaction;
begin
case i(1 downto 0) is
when "00" => ret.state := none;
when "01" => ret.state := busy;
when "10" => ret.state := done;
when others => ret.state := error;
end case;
case i(3 downto 2) is
when "00" => ret.transaction_type := control;
when "01" => ret.transaction_type := bulk;
when "10" => ret.transaction_type := interrupt;
when others => ret.transaction_type := isochronous;
end case;
ret.pipe_pointer := unsigned(i(8 downto 4));
ret.transfer_length := unsigned(i(19 downto 9));
ret.buffer_address := unsigned(i(30 downto 20));
ret.link_to_next := i(31);
return ret;
end function;
function t_transaction_to_data(i: t_transaction) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when none => ret(1 downto 0) := "00";
when busy => ret(1 downto 0) := "01";
when done => ret(1 downto 0) := "10";
when error => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "11";
end case;
case i.transaction_type is
when control => ret(3 downto 2) := "00";
when bulk => ret(3 downto 2) := "01";
when interrupt => ret(3 downto 2) := "10";
when isochronous => ret(3 downto 2) := "11";
when others => ret(3 downto 2) := "11";
end case;
ret(8 downto 4) := std_logic_vector(i.pipe_pointer);
ret(19 downto 9) := std_logic_vector(i.transfer_length);
ret(30 downto 20):= std_logic_vector(i.buffer_address);
ret(31) := i.link_to_next;
return ret;
end function;
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_split => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused!
when others => return false;
end case;
return false;
end function;
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
case i is
when "00" =>
return X"46"; -- LS mode
when "01" =>
return X"45"; -- FS mode
when "10" =>
return X"40"; -- HS mode
when others =>
return X"50"; -- stay in chirp mode
end case;
return X"00";
end function;
end;
| gpl-3.0 | ee0dafa7246942bc9ba1108e4fd7cea4 | 0.530502 | 3.543231 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_source/nano_cpu.vhd | 3 | 6,402 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal i_addr : unsigned(9 downto 0);
signal inst : std_logic_vector(15 downto 11) := (others => '0');
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z : boolean;
signal stack_top : std_logic_vector(i_addr'range);
signal push : std_logic;
signal pop : std_logic;
signal update_accu : std_logic;
signal update_flag : std_logic;
signal long_inst : std_logic;
type t_state is (fetch_inst, decode_inst, data_state, external_data);
signal state : t_state;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
true when c_br_always,
true when c_br_call,
false when others;
with state select ram_addr <=
std_logic_vector(i_addr) when fetch_inst,
ram_rdata(ram_addr'range) when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
ram_en <= '0' when (state = decode_inst) and (ram_rdata(c_store'range) = c_store) else not stall;
push <= '1' when (state = decode_inst) and (ram_rdata(c_br_call'range) = c_br_call) and (ram_rdata(c_branch'range) = c_branch) else '0';
pop <= '1' when (state = decode_inst) and (ram_rdata(c_return'range) = c_return) else '0';
with ram_rdata(inst'range) select long_inst <=
'1' when c_store,
'1' when c_load_ind,
'1' when c_store_ind,
'0' when others;
process(clock)
begin
if rising_edge(clock) then
if stall='0' then
io_addr <= unsigned(ram_rdata(io_addr'range));
update_accu <= '0';
update_flag <= '0';
end if;
io_write <= '0';
io_read <= '0';
ram_we <= '0';
case state is
when fetch_inst =>
i_addr <= i_addr + 1;
state <= decode_inst;
when decode_inst =>
state <= fetch_inst;
inst <= ram_rdata(inst'range);
update_accu <= ram_rdata(11);
update_flag <= not ram_rdata(15);
-- special instructions
if ram_rdata(c_in'range) = c_in then
io_read <= '1';
state <= external_data;
elsif ram_rdata(c_branch'range) = c_branch then
update_accu <= '0';
update_flag <= '0';
if branch_taken then
i_addr <= unsigned(ram_rdata(i_addr'range));
end if;
elsif ram_rdata(c_return'range) = c_return then
i_addr <= unsigned(stack_top);
update_accu <= '0';
update_flag <= '0';
elsif ram_rdata(c_out'range) = c_out then
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
state <= external_data;
end if;
-- not so special instructions: alu instructions!
else
if long_inst='1' then
state <= data_state;
end if;
if ram_rdata(c_store'range) = c_store then
ram_we <= '1';
end if;
if ram_rdata(c_store_ind'range) = c_store_ind then
ram_we <= '1';
end if;
end if;
when external_data =>
if stall = '0' then
update_accu <= '0';
update_flag <= '0';
state <= fetch_inst;
end if;
when data_state =>
if inst = c_load_ind then
update_accu <= '1';
update_flag <= '1';
end if;
state <= fetch_inst;
when others =>
state <= fetch_inst;
end case;
if reset='1' then
state <= fetch_inst;
i_addr <= (others => '0');
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => inst(14 downto 12),
update_accu => update_accu,
update_flag => update_flag,
accu => accu,
z => z,
n => n );
i_stack : entity work.distributed_stack
generic map (
width => i_addr'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
| gpl-3.0 | 4f4cd1b9d30c8fc1f939e73469666935 | 0.434864 | 4.080306 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_host.vhd | 3 | 9,976 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_logic := '0';
signal reset : std_logic;
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
begin
i_mut: entity work.ulpi_host
port map (
clock => clock,
reset => reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
do_reset => open,
power_en => open,
reset_done => '1',
speed => "10",
reset_pkt => '0',
reset_data => X"00",
reset_last => '0',
reset_valid => '0',
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_descr_ram: entity work.bram_model_32sp
generic map("descriptors", 9)
port map (
CLK => clock,
SSR => reset,
EN => descr_en,
WE => descr_we,
ADDR => descr_addr,
DI => descr_wdata,
DO => descr_rdata );
i_buf_ram: entity work.bram_model_8sp
generic map("buffer", 12)
port map (
CLK => clock,
SSR => reset,
EN => buf_en,
WE => buf_we,
ADDR => buf_addr,
DI => buf_wdata,
DO => buf_rdata );
b_tx_bfm: block
signal tx_delay : integer range 0 to 31 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
tx_ack <= '0';
user_next <= '0';
if tx_delay = 28 then -- transmit packet
user_next <= '1';
if user_last='1' and user_valid='1' then
tx_delay <= 0; -- done;
user_next <= '0';
end if;
elsif tx_delay = 0 then
if send_token='1' then
tx_delay <= 6;
tx_ack <= '1';
elsif send_handsh='1' then
tx_delay <= 4;
tx_ack <= '1';
elsif send_data='1' then
tx_ack <= '1';
if no_data='1' then
tx_delay <= 5;
else
tx_delay <= 31;
end if;
end if;
else
tx_delay <= tx_delay - 1;
end if;
end if;
end process;
tx_busy <= '0' when tx_delay = 0 else '1';
end block;
p_test: process
variable desc : h_mem_object;
variable buf : h_mem_object;
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
data_out <= pkt(i);
data_valid <= '1';
if i = pkt'left then
data_start <= '1';
else
data_start <= '0';
end if;
end loop;
wait until clock='1';
data_valid <= '0';
data_start <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
bind_mem_model("descriptors", desc);
bind_mem_model("buffer", buf);
wait until reset='0';
write_memory_32(desc, X"0000_0100", t_transaction_to_data((
transaction_type => control,
state => busy, -- activate
pipe_pointer => "00000",
transfer_length => to_unsigned(8, 11),
buffer_address => to_unsigned(100, 12) )));
write_memory_32(desc, X"0000_0104", t_transaction_to_data((
transaction_type => bulk,
state => busy, -- activate
pipe_pointer => "00001",
transfer_length => to_unsigned(60, 11),
buffer_address => to_unsigned(256, 12) )));
write_memory_32(desc, X"0000_0000", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(64, 11),
data_toggle => '0' ) ));
write_memory_32(desc, X"0000_0004", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(8, 11),
data_toggle => '0' ) ));
for i in 0 to 7 loop
write_memory_8(buf, std_logic_vector(to_unsigned(100+i,32)),
std_logic_vector(to_unsigned(33+i,8)));
end loop;
wait until tx_busy='0'; -- first sof token
wait until tx_busy='0'; -- setup token
wait until tx_busy='0'; -- setup data
wait until tx_busy='0'; -- retried setup token
wait until tx_busy='0'; -- retried setup data
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
-- control out
for i in 0 to 7 loop
wait until tx_busy='0'; -- out token
wait until tx_busy='0'; -- out data
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
end loop;
wait until tx_busy='0'; -- in token
assert tx_pid = c_pid_in
report "Expected in token! (pid = " & hstr(tx_pid) & ")"
severity error;
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_packet <= '1';
wait until clock='1';
valid_packet <= '0';
-- -- control in..
-- wait until send_token='1';
-- wait until tx_busy='0'; -- in token done
-- wait until clock='1';
-- wait until clock='1';
-- wait until clock='1';
-- packet((X"01", X"02", X"03", X"04", X"05", X"06"));
-- valid_packet <= '1';
-- wait until clock='1';
-- valid_packet <= '0';
wait;
end process;
end tb;
| gpl-3.0 | a03512296002eb8dbdc999608b582231 | 0.442863 | 3.946203 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_via6522.vhd | 4 | 22,866 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
clock_en => clock_en, -- for counters and stuff
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
data_in <= d;
wen <= '1';
wait until clock='1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
ren <= '1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 12 report "Timing error serial mode 1." severity error;
-- report "Receiving byte. Bit time: " & integer'image(integer((now - start)/7 us)) severity note;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 150 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
do_write(X"8", X"03"); -- timer 2 latch = 3 (8 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
-- TEST TIMER 1 --
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
wait until irq='1';
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
wait until irq='1';
start := now;
do_read(X"4", read_data);
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong." severity error;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 68 report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
wait until irq='1';
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until clock_en='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 16#233# report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until clock_en='1';
do_write(X"1", X"32"); -- write to port A
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until clock_en='1';
do_write(X"0", X"32"); -- write to port B
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
wait;
end process;
end tb;
| gpl-3.0 | 9d0956fb8019966fab5cef375ac04f7e | 0.50363 | 3.668538 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_11sk1_0.vhdl | 1 | 7,262 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 4e-07
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcm_1,
Wcm_1init => 7.935e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcmcout_1,
Wcmcout_1init => 3.735e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | bf0fcbc166ce80f2d39d919c62142b59 | 0.582209 | 2.922334 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_rng.vhd | 1 | 4,137 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM_GAUSS_COE_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END ROM_GAUSS_COE_TB_RNG;
ARCHITECTURE BEHAVIORAL OF ROM_GAUSS_COE_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | 2d4fb19b07c2424df9d3c340a8a5ddbb | 0.599468 | 4.571271 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/proc_registers.vhd | 2 | 10,129 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
new_flags : in std_logic_vector(7 downto 0);
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
interrupt : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
set_b : in std_logic;
clear_b : in std_logic;
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
latch_dreg : in std_logic;
vect_bit : in std_logic;
reg_update : in std_logic;
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
-- signal a_reg : std_logic_vector(7 downto 0);
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : std_logic_vector(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : std_logic_vector(7 downto 0) := X"FF";
signal adl, adh : std_logic_vector(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal vect : std_logic_vector(3 downto 0) := "1111";
signal dreg_zero : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
begin
dreg_zero <= '1' when dreg=X"00" else '0';
process(clock)
variable pcl_t : std_logic_vector(8 downto 0);
variable adl_t : std_logic_vector(8 downto 0);
begin
if rising_edge(clock) then
if clock_en='1' then
-- Data Register
if latch_dreg='1' then
dreg <= data_in;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
end if;
if vect_bit='0' then
I_flag <= '1';
end if;
if set_b='1' then
B_flag <= '1';
elsif clear_b='1' then
B_flag <= '0';
end if;
if so_n='0' then -- only 1 bit is affected, so no syncronization needed
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
i_reg_i <= data_in;
-- Fix for PLA only :(
if load_a(i_reg_i) then
a_reg_i <= dreg;
N_flag <= dreg(7);
Z_flag <= dreg_zero;
end if;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= data_in;
when from_alu =>
pcl_t := ('0' & pcl) + (dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := ('0' & dreg) + ('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= data_in;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= data_in;
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data; --dreg; -- alu is okay, too (they should be the same)
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if set_s='1' then
s_reg_i <= set_data;
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
adh & adl when 1,
X"01" & s_reg_i when 2,
pch & pcl when 3;
with i_reg_i(1 downto 0) select reg_out <=
y_reg_i when "00",
a_reg_i when "01",
x_reg_i when "10",
a_reg_i and x_reg_i when others;
with dout_mux select data_out <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_i when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
mem_data when shift_res,
X"FF" when others;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= s_reg_i;
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= pch & pcl;
end gideon;
| gpl-3.0 | 919719093de5edeb3eb25d67627bd72b | 0.416428 | 3.614918 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAFifo_Xilinx.vhd | 2 | 6,421 | -------------------------------------------------------------------------------
-- Entity : OpenMAC_DMAFifo_Xilinx
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file of the dual clocked DMA FIFO
-- for Xilinx FPGAs.
--
-------------------------------------------------------------------------------
--
-- 2011-10-13 V0.01 mairt First version
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openMAC_DMAfifo is
generic(
fifo_data_width_g : NATURAL := 16;
fifo_word_size_g : NATURAL := 32;
fifo_word_size_log2_g : NATURAL := 5
);
port(
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g - 1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
wr_empty : out std_logic;
wr_full : out std_logic;
rd_data : out std_logic_vector(fifo_data_width_g - 1 downto 0);
rd_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0);
wr_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0)
);
end openMAC_DMAfifo;
architecture struct of openMAC_DMAfifo is
---- Component declarations -----
component async_fifo_ctrl
generic(
ADDR_WIDTH : natural := 5
);
port (
clkr : in std_logic;
clkw : in std_logic;
rd : in std_logic;
resetr : in std_logic;
resetw : in std_logic;
wr : in std_logic;
r_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
r_empty : out std_logic;
r_full : out std_logic;
rd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0);
w_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
w_empty : out std_logic;
w_full : out std_logic;
wd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0)
);
end component;
component dc_dpr
generic(
ADDRWIDTH : integer := 7;
SIZE : integer := 128;
WIDTH : integer := 16
);
port (
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
clkA : in std_logic;
clkB : in std_logic;
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
---- Signal declarations used on the diagram ----
signal enA : std_logic;
signal enB : std_logic;
signal wea : std_logic;
signal weB : std_logic;
signal wr_full_s : std_logic;
signal diB : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rd_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0);
signal wr_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0);
begin
---- User Signal Assignments ----
--assignments
---port a writes only
enA <= wea;
---port b reads only
enB <= rd_req;
weB <= '0';
diB <= (others => '0');
---- Component instantiations ----
THE_FIFO_CONTROL : async_fifo_ctrl
generic map (
ADDR_WIDTH => fifo_word_size_log2_g
)
port map(
clkr => rd_clk,
clkw => wr_clk,
r_addr => rd_addr( fifo_word_size_log2_g-1 downto 0 ),
r_empty => rd_empty,
r_full => rd_full,
rd => rd_req,
rd_used_w => rd_usedw( fifo_word_size_log2_g - 1 downto 0 ),
resetr => aclr,
resetw => aclr,
w_addr => wr_addr( fifo_word_size_log2_g-1 downto 0 ),
w_empty => wr_empty,
w_full => wr_full_s,
wd_used_w => wr_usedw( fifo_word_size_log2_g - 1 downto 0 ),
wr => wr_req
);
THE_FIFO_DPR : dc_dpr
generic map (
ADDRWIDTH => fifo_word_size_log2_g,
SIZE => fifo_word_size_g,
WIDTH => fifo_data_width_g
)
port map(
addrA => wr_addr( fifo_word_size_log2_g-1 downto 0 ),
addrB => rd_addr( fifo_word_size_log2_g-1 downto 0 ),
clkA => wr_clk,
clkB => rd_clk,
diA => wr_data( fifo_data_width_g - 1 downto 0 ),
diB => diB( fifo_data_width_g-1 downto 0 ),
doB => rd_data( fifo_data_width_g - 1 downto 0 ),
enA => enA,
enB => enB,
weA => wea,
weB => weB
);
wea <= not(wr_full_s) and wr_req;
---- Terminal assignment ----
-- Output\buffer terminals
wr_full <= wr_full_s;
end struct;
| gpl-2.0 | 86a69e872db12188ba940473261d1e33 | 0.5848 | 3.617465 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/gcr_codec.vhd | 5 | 2,406 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_codec is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_codec;
architecture regmap of gcr_codec is
signal shift_reg : std_logic_vector(0 to 39);
signal encoded : std_logic_vector(0 to 39);
signal decoded : std_logic_vector(0 to 31);
signal errors : std_logic_vector(0 to 7);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 39) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= decoded(0 to 7);
when X"1" =>
resp.data <= decoded(8 to 15);
when X"2" =>
resp.data <= decoded(16 to 23);
when X"3" =>
resp.data <= decoded(24 to 31);
when X"4"|X"5"|X"6"|X"7" =>
resp.data <= errors;
when X"8" =>
resp.data <= encoded(0 to 7);
when X"9" =>
resp.data <= encoded(8 to 15);
when X"A" =>
resp.data <= encoded(16 to 23);
when X"B" =>
resp.data <= encoded(24 to 31);
when X"C" =>
resp.data <= encoded(32 to 39);
when others =>
null;
end case;
end if;
if reset='1' then
shift_reg <= X"5555555555";
end if;
end if;
end process;
r_encoders: for i in 0 to 7 generate
i_bin2gcr: entity work.bin2gcr
port map (
d_in => shift_reg(8+4*i to 11+4*i),
d_out => encoded(5*i to 4+5*i) );
end generate;
r_decoders: for i in 0 to 7 generate
i_gcr2bin: entity work.gcr2bin
port map (
d_in => shift_reg(5*i to 4+5*i),
d_out => decoded(4*i to 3+4*i),
error => errors(i) );
end generate;
end;
| gpl-3.0 | 8b53ec82580edc7b5c02f559bd88018e | 0.43724 | 3.596413 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/busses/vhdl_source/mem_to_mem32.vhd | 1 | 1,729 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mem_to_mem32
-- Date:2015-01-05
-- Author: Gideon
-- Description: Adapter to attach an 8 bit memory slave to a 32 bit memory controller port.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_to_mem32 is
port (
clock : in std_logic;
reset : in std_logic;
mem_req_8 : in t_mem_req;
mem_resp_8 : out t_mem_resp;
mem_req_32 : out t_mem_req_32;
mem_resp_32 : in t_mem_resp_32 );
end entity;
architecture route_through of mem_to_mem32 is
begin
-- this adapter is the most simple variant; it just routes through the data and address
-- no support for count and burst.
mem_resp_8.data <= mem_resp_32.data(31 downto 24);
mem_resp_8.rack <= mem_resp_32.rack;
mem_resp_8.rack_tag <= mem_resp_32.rack_tag;
mem_resp_8.dack_tag <= mem_resp_32.dack_tag;
mem_resp_8.count <= "00";
mem_req_32.tag <= mem_req_8.tag;
mem_req_32.request <= mem_req_8.request;
mem_req_32.read_writen <= mem_req_8.read_writen;
mem_req_32.address <= mem_req_8.address;
mem_req_32.data <= mem_req_8.data & X"000000";
mem_req_32.byte_en <= "1000";
-- with mem_req_8.address(1 downto 0) select
-- mem_req_32.byte_en <=
-- "1000" when "00",
-- "0100" when "01",
-- "0010" when "10",
-- "0001" when others;
end architecture;
| gpl-3.0 | 7a27e833a03a3025ce81ea5f6c8f52cf | 0.526316 | 3.237828 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_1400a.vhd | 4 | 9,786 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_1400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_1400a;
architecture structural of ultimate_1541_1400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => true,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | a8a79e152f8f8348a4ebfee6f5629553 | 0.477212 | 3.375647 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/dmem_splitter.vhd | 1 | 6,220 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: dmem_splitter
-- Date:2015-02-28
-- Author: Gideon
-- Description: This module takes the Wishbone alike memory bus and splits it
-- into a 32 bit DRAM bus and an 8-bit IO bus
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity dmem_splitter is
generic (
g_tag : std_logic_vector(7 downto 0) := X"AE";
g_support_io : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
dmem_i : out dmem_in_type;
dmem_o : in dmem_out_type;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : out t_io_req;
io_resp : in t_io_resp );
end entity;
architecture arch of dmem_splitter is
type t_state is (idle, mem_read, mem_write, io_access);
signal state : t_state;
signal mem_req_i : t_mem_req_32 := c_mem_req_32_init;
signal io_req_i : t_io_req;
type t_int4_array is array(natural range <>) of integer range 0 to 3;
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F => 1,2,4,8 byte, 3,C word, F dword
constant c_remain : t_int4_array(0 to 15) := ( 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 3 );
signal remain : integer range 0 to 3;
begin
io_req <= io_req_i;
mem_req <= mem_req_i;
process(state, mem_resp)
begin
dmem_i.ena_i <= '0';
case state is
when idle =>
dmem_i.ena_i <= '1';
when mem_read | io_access =>
dmem_i.ena_i <= '0';
when mem_write =>
-- if mem_resp.rack = '1' then
-- dmem_i.ena_i <= '1';
-- end if;
when others =>
dmem_i.ena_i <= '0';
end case;
end process;
process(clock)
impure function get_next_io_byte(a : unsigned(1 downto 0)) return std_logic_vector is
begin
case a is
when "00" =>
return dmem_o.dat_o(23 downto 16);
when "01" =>
return dmem_o.dat_o(15 downto 8);
when "10" =>
return dmem_o.dat_o(7 downto 0);
when "11" =>
return dmem_o.dat_o(31 downto 24);
when others =>
return "XXXXXXXX";
end case;
end function;
begin
if rising_edge(clock) then
io_req_i.read <= '0';
io_req_i.write <= '0';
case state is
when idle =>
dmem_i.dat_i <= (others => 'X');
if dmem_o.ena_o = '1' then
mem_req_i.address <= unsigned(dmem_o.adr_o(mem_req_i.address'range));
mem_req_i.address(1 downto 0) <= "00";
mem_req_i.byte_en <= dmem_o.sel_o;
mem_req_i.data <= dmem_o.dat_o;
mem_req_i.read_writen <= not dmem_o.we_o;
mem_req_i.tag <= g_tag;
io_req_i.address <= unsigned(dmem_o.adr_o(19 downto 0));
io_req_i.data <= get_next_io_byte("11");
if dmem_o.adr_o(26) = '0' or not g_support_io then
mem_req_i.request <= '1';
if dmem_o.we_o = '1' then
state <= mem_write;
else
state <= mem_read;
end if;
else -- I/O
remain <= c_remain(to_integer(unsigned(dmem_o.sel_o)));
if dmem_o.we_o = '1' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
state <= io_access;
end if;
end if;
when mem_read =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
end if;
if mem_resp.dack_tag = g_tag then
dmem_i.dat_i <= mem_resp.data;
state <= idle;
end if;
when mem_write =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
state <= idle;
end if;
when io_access =>
case io_req_i.address(1 downto 0) is
when "00" =>
dmem_i.dat_i(31 downto 24) <= io_resp.data;
when "01" =>
dmem_i.dat_i(23 downto 16) <= io_resp.data;
when "10" =>
dmem_i.dat_i(15 downto 8) <= io_resp.data;
when "11" =>
dmem_i.dat_i(7 downto 0) <= io_resp.data;
when others =>
null;
end case;
if io_resp.ack = '1' then
io_req_i.data <= get_next_io_byte(io_req_i.address(1 downto 0));
if remain = 0 then
state <= idle;
else
remain <= remain - 1;
io_req_i.address(1 downto 0) <= io_req_i.address(1 downto 0) + 1;
if mem_req_i.read_writen = '0' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
end arch;
| gpl-3.0 | acb78c66cd8b147e366d16e69203fe7b | 0.397428 | 3.841878 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd | 2 | 3,719 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Generic counter module
--
-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_counter is
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end spi_counter;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_counter is
signal cnt_q : unsigned(cnt_width_g-1 downto 0);
signal cnt_ovfl_s : boolean;
begin
cnt: process (clk_i, reset_i)
begin
if reset_i then
cnt_q <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if cnt_en_i then
if not cnt_ovfl_s then
cnt_q <= cnt_q + 1;
else
cnt_q <= (others => '0');
end if;
end if;
end if;
end process cnt;
cnt_ovfl_s <= cnt_q = cnt_max_g;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
cnt_ovfl_o <= cnt_ovfl_s;
cnt_o <= std_logic_vector(cnt_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: spi_counter.vhd,v $
-- Revision 1.2 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | fdaa9ccd76df101d7805313b4ba3880a | 0.598279 | 4.132222 | false | false | false | false |
chrismasters/fpga-space-invaders | project/video.vhd | 1 | 2,464 |
-- Fairly simple VGA (640x480 @ 60hz) output for the machine.
-- Connected to some memory so that it can get bytes in and then outputs the right RGB based
-- on the corresponding bit value in each byte. Fakes the cellophane overlays from the original
-- if colourOutput is high.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
port (
clkin25mhz : in STD_LOGIC;
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
vramAddr : out STD_LOGIC_VECTOR (12 downto 0);
vramData : in STD_LOGIC_VECTOR (7 downto 0);
colourOutput : in STD_LOGIC
);
end video;
architecture Behavioral of video is
signal hcount : unsigned(9 downto 0) := (others => '0');
signal vcount : unsigned(9 downto 0) := (others => '0');
signal hindex : unsigned(7 downto 0) := (others => '0');
signal vindex : unsigned(7 downto 0) := "11111111";
begin
vramAddr <= std_logic_vector(hindex) & std_logic_vector(vindex(7 downto 3));
process (clkin25mhz)
begin
if rising_edge(clkin25mhz) then
if (hcount = 799) then
hcount <= (others => '0');
hindex <= (others => '0');
if vcount = 524 then
vcount <= (others => '0');
else
vcount <= vcount + 1;
if (vcount > 111 and vcount < 368) then
vindex <= vindex - 1;
else
vindex <= "11111111";
end if;
end if;
else
hcount <= hcount + 1;
end if;
if vcount >= 490 and vcount < 492 then
vsync <= '0';
else
vsync <= '1';
end if;
if hcount >= 656 and hcount < 752 then
hsync <= '0';
else
hsync <= '1';
end if;
if (vcount > 111 and vcount < 368 and hcount > 207 and hcount < 432) then
if (colourOutput = '1' and vramData(to_integer(unsigned(vindex(2 downto 0)))) = '1') then
if ((vcount > 111+191 and vcount < 111+241)
or (vcount >= 352 and hcount > 232 and hcount < 344)) then
red<="0000";
green<="1111";
blue<="0000";
elsif (vcount > 143 and vcount < 161) then -- was > 142
red<="1111";
green<="0000";
blue<="0000";
else
red<="1111";
green<="1111";
blue<="1111";
end if;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
hindex <= hindex + 1;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
| mit | 0baa6909f96cffac7915a8e5e6944c78 | 0.599432 | 3.08 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4b.vhd | 3 | 12,673 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4b is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4b;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4b is
-- SRCW
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0222", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=1, CAS lat = 2
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
type t_state is (boot, init, idle, sd_read, read_single, read_single_end, sd_write, wait_for_precharge, delay_to_terminate);
signal state : t_state;
signal sdram_cmd : std_logic_vector(3 downto 0) := "1111";
signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sdram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal refresh_inhibit: std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack_count : unsigned(1 downto 0) := "00";
signal count_out : unsigned(1 downto 0) := "00";
signal dack : std_logic := '0';
signal dack_pre : std_logic := '0';
signal rack : std_logic := '0';
signal dack_tag_pre : std_logic_vector(req.tag'range) := (others => '0');
signal rack_tag : std_logic_vector(req.tag'range) := (others => '0');
signal dack_tag : std_logic_vector(req.tag'range) := (others => '0');
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of sdram_cmd : signal is "true";
attribute iob of mem_a_i : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
resp.count <= count_out;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
sdram_cmd <= c_cmd_refresh;
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
dack_count <= req.size;
sdram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
sdram_cmd <= c_cmd_active;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
rack_tag <= (others => '0');
dack_pre <= '0';
dack_tag_pre <= (others => '0');
dack <= dack_pre;
dack_tag <= dack_tag_pre;
if dack='1' then
count_out <= count_out + 1;
else
count_out <= "00";
end if;
dout_sel <= '0';
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
sdram_cmd <= c_cmd_inactive;
SDRAM_CKE <= enable_sdram;
sdram_d_t <= '0';
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
if inhibit='1' then
refresh_inhibit <= '1';
end if;
case state is
when boot =>
refresh_inhibit <= '0';
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
sdram_cmd(3) <= '1';
sdram_cmd(2 downto 0) <= c_init_array(init_cnt).cmd(2 downto 0);
if delay = 0 then
delay <= 7;
sdram_cmd(3) <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if do_refresh='1' and refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req_i='1' and refr_delay = 0 then
accept_req;
refresh_inhibit <= '0';
if req.read_writen = '1' then
state <= sd_read;
else
state <= sd_write;
end if;
end if;
end if;
when sd_read =>
mem_a_i(10) <= '0'; -- no auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_read;
if dack_count = "00" then
state <= read_single;
else
state <= delay_to_terminate;
end if;
when read_single =>
dack_pre <= '1';
dack_tag_pre <= tag;
sdram_cmd <= c_cmd_bterm;
state <= read_single_end;
when read_single_end =>
sdram_cmd <= c_cmd_precharge;
state <= idle;
when delay_to_terminate =>
dack_pre <= '1';
dack_tag_pre <= tag;
dack_count <= dack_count - 1;
delay <= 2;
if dack_count = "00" then
sdram_cmd <= c_cmd_precharge;
state <= idle;
end if;
when sd_write =>
if delay = 0 then
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_write;
sdram_d_t <= '1';
delay <= 2;
state <= wait_for_precharge;
end if;
when wait_for_precharge =>
if delay = 0 then
state <= idle;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sdram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
refresh_inhibit <= '0';
end if;
end if;
end process;
MEM_D <= sdram_d_o when sdram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
SDRAM_CSn <= sdram_cmd(3);
SDRAM_RASn <= sdram_cmd(2);
SDRAM_CASn <= sdram_cmd(1);
SDRAM_WEn <= sdram_cmd(0);
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
-- ACT to READ: tRCD = 20 ns ( = 1 CLK)
-- ACT to PRCH: tRAS = 44 ns ( = 3 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 4 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 1 CLK)
-- PRCH time; tRP = 20 ns ( = 1 CLK)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A R P +
-- - - - D
-- +: ONLY if same bank, otherwise we don't meet tRC.
-- BL2 A R - P
-- - - - D D
-- BL3 A R - - P
-- - - - D D D
-- BL4 A r - - - p
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
-- BL4 A r - - - p - A
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
| gpl-3.0 | c4d51099de9c12dff02ad69ecedec3ef | 0.446698 | 3.70339 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_sim/harness_dm_cache.vhd | 5 | 4,099 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
| gpl-3.0 | f3a85be7db591ee552290b71e6e3f309 | 0.522079 | 3.300322 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/ulpi_rx.vhd | 3 | 5,919 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
| gpl-3.0 | eb4a78dcf48d973dc4c144febd2b2b38 | 0.377598 | 4.599068 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op961_14.vhdl | 1 | 5,465 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 48f5e565ab555aca6474040ca2a48693 | 0.578225 | 3.146229 | false | false | false | false |
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