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KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/dpram_rdw_byte.vhd | 5 | 2,599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw_byte is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 32;
g_depth_bits : positive := 9;
g_init_file : string := "none";
g_storage : string := "block" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_byte_en : in std_logic_vector((g_width_bits/8)-1 downto 0) := (others => '1');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw_byte : entity is "yes";
end entity;
architecture xilinx of dpram_rdw_byte is
signal b_we_i : std_logic_vector(b_byte_en'range) := (others => '0');
begin
assert (g_width_bits mod 8) = 0
report "Width of ram with byte enables should be a multiple of 8."
severity failure;
b_we_i <= b_byte_en when b_we='1' else (others => '0');
r_byte: for i in b_we_i'range generate
i_byte_ram: entity work.dpram_rdw
generic map (
g_rdw_check => g_rdw_check,
g_width_bits => 8,
g_depth_bits => g_depth_bits,
g_init_value => X"00",
g_init_file => g_init_file,
g_init_width => (g_width_bits/8),
g_init_offset => i,
g_storage => g_storage )
port map (
clock => clock,
a_address => a_address,
a_rdata => a_rdata(8*i+7 downto 8*i),
a_en => a_en,
b_address => b_address,
b_rdata => b_rdata(8*i+7 downto 8*i),
b_wdata => b_wdata(8*i+7 downto 8*i),
b_en => b_en,
b_we => b_we_i(i) );
end generate;
end architecture;
| gpl-3.0 | 3787ab2a351eeb6026d1f024dbf02665 | 0.466333 | 3.424242 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_4sk1_0.vhdl | 1 | 7,093 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.75e-06,
W => W_0,
W_0init => 2.85e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.4e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.065e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.4e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.065e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.4e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.065e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.4e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.065e-05,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 1.455e-05,
W => Wsrc_2,
Wsrc_2init => 7.99e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 1.455e-05,
W => Wsrc_2,
Wsrc_2init => 7.99e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 9.5e-07,
W => Wcm_1,
Wcm_1init => 3.25e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 9.5e-07,
W => Wcmcout_1,
Wcmcout_1init => 2.4e-06,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9.75e-06,
W => (pfak)*(WBias),
WBiasinit => 3.455e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.75e-06,
W => (pfak)*(WBias),
WBiasinit => 3.455e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.75e-06,
W => WBias,
WBiasinit => 3.455e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.75e-06,
W => WBias,
WBiasinit => 3.455e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.75e-06,
W => WBias,
WBiasinit => 3.455e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.75e-06,
W => WBias,
WBiasinit => 3.455e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 1b15bad272b3ccad608cd4df166bceb9 | 0.582828 | 2.885679 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op982_11.vhdl | 1 | 5,996 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 5f097d7cdbaf80fcd9a8a74a4b9eafa5 | 0.577885 | 3.127804 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_host_interface.vhd | 1 | 5,543 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
entity usb_host_interface is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
usb_rx : out t_usb_rx;
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp;
-- low level ulpi interfacing
reg_read : in std_logic := '0';
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_rdata : out std_logic_vector(7 downto 0);
reg_ack : out std_logic;
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
status : out std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_dir : in std_logic;
ulpi_data : inout std_logic_vector(7 downto 0) );
end entity;
architecture structural of usb_host_interface is
signal status_i : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_register : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal rx_crc_sync : std_logic;
signal rx_crc_dvalid : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal crc_dvalid : std_logic;
signal tx_data_to_crc: std_logic_vector(7 downto 0);
signal crc_data_in : std_logic_vector(7 downto 0);
signal data_crc : std_logic_vector(15 downto 0);
begin
i_ulpi: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ulpi_data,
ULPI_DIR => ulpi_dir,
ULPI_NXT => ulpi_nxt,
ULPI_STP => ulpi_stp,
-- status
status => status_i,
operational => '1',
-- chirp interface
do_chirp => do_chirp,
chirp_data => chirp_data,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store );
i_rx: entity work.ulpi_rx
generic map (
g_support_split => false,
g_support_token => false ) -- hosts do not receive tokens
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
status => status_i,
-- interface to DATA CRC (shared resource)
crc_sync => rx_crc_sync,
crc_dvalid => rx_crc_dvalid,
data_crc => data_crc,
usb_rx => usb_rx );
crc_sync <= rx_crc_sync or tx_crc_sync;
crc_dvalid <= rx_crc_dvalid or tx_crc_dvalid;
crc_data_in <= rx_data when rx_crc_dvalid='1' else tx_data_to_crc;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => crc_data_in,
crc => data_crc );
i_tx: entity work.ulpi_tx
generic map (
g_simulation => g_simulation,
g_support_split => true,
g_support_token => true ) -- hosts do send tokens
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_busy => rx_store,
-- interface to DATA CRC (shared resource)
crc_sync => tx_crc_sync,
crc_dvalid => tx_crc_dvalid,
data_crc => data_crc,
data_to_crc => tx_data_to_crc,
-- Status
status => status_i,
speed => speed,
-- Interface to send tokens and handshakes
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
status <= status_i;
reg_rdata <= rx_data;
end architecture;
| gpl-3.0 | 5530d38074b6133b3dc4213349200fcf | 0.455349 | 3.742741 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/dm_with_invalidate.vhd | 1 | 11,353 | --------------------------------------------------------------------------------
-- Entity: dm_with_invalidate
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- D bus of the mblite. This version has an invalidate port.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
entity dm_with_invalidate is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000" );
port (
clock : in std_logic;
reset : in std_logic;
invalidate : in std_logic;
inv_addr : in std_logic_vector(31 downto 0);
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_with_invalidate is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, invalidate, inv_addr)
begin
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if invalidate = '1' then
tag_ram_a_address <= get_tag_index(inv_addr);
tag_ram_a_wdata <= tag_to_vector(address_to_tag(inv_addr, '0')); -- invalid
tag_ram_a_en <= '1';
tag_ram_a_we <= '1';
elsif dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
if is_cacheable(dmem_i.adr_o) then
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
end if;
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
if dmem_r.we_o='0' and is_cacheable(dmem_r.adr_o) then -- was a read
-- assert dmem_r.sel_o = X"F"
-- report "Cache write of less than a word? " & hstr(dmem_r.adr_o)
-- severity error;
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
end case;
end process;
dmem_o.dat_i <= dmem_o_reg.dat_i;
dmem_o.ena_i <= dmem_o_reg.ena_i and not invalidate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
-- dmem_r.ena_o <= '0';
state <= idle;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
dmem_r.ena_o <= '0';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
| gpl-3.0 | 80ab235f9c8f6dd97be264aa7619f6b6 | 0.489474 | 3.300291 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_pkg.vhd | 4 | 4,512 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Definitions for the video character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package char_generator_pkg is
type t_chargen_control is record
clocks_per_line : unsigned(11 downto 0);
char_width : unsigned(2 downto 0);
char_height : unsigned(3 downto 0);
chars_per_line : unsigned(7 downto 0);
active_lines : unsigned(5 downto 0);
x_on : unsigned(11 downto 0);
y_on : unsigned(11 downto 0);
pointer : unsigned(14 downto 0);
perform_sync : std_logic;
overlay_on : std_logic;
transparent : std_logic_vector(3 downto 0);
end record;
constant c_chargen_control_init : t_chargen_control := (
clocks_per_line => to_unsigned(672, 12),
char_width => to_unsigned(0, 3),
char_height => to_unsigned(9, 4),
chars_per_line => to_unsigned(60, 8),
active_lines => to_unsigned(30, 6),
x_on => to_unsigned(15, 12),
y_on => to_unsigned(6, 12),
pointer => to_unsigned(0, 15),
perform_sync => '0',
overlay_on => '0',
transparent => X"5" );
-- 640x225 (80x25 => 8x9 chars, in 45 C64 chars width)
constant c_chargen_control_init_orig : t_chargen_control := (
clocks_per_line => to_unsigned(896, 12),
char_width => to_unsigned(0, 3),
char_height => to_unsigned(8, 4),
chars_per_line => to_unsigned(80, 8),
active_lines => to_unsigned(25, 6),
x_on => to_unsigned(190, 12),
y_on => to_unsigned(46, 12),
pointer => to_unsigned(0, 15),
overlay_on => '0',
perform_sync => '0',
transparent => X"5" );
-- 480x200 (80x25 => 6x8 chars, in 45 C64 chars width)
constant c_chargen_control_init_480 : t_chargen_control := (
clocks_per_line => to_unsigned(672, 12),
char_width => to_unsigned(6, 3),
char_height => to_unsigned(8, 4),
chars_per_line => to_unsigned(80, 8),
active_lines => to_unsigned(25, 6),
x_on => to_unsigned(142, 12),
y_on => to_unsigned(48, 12),
pointer => to_unsigned(0, 15),
overlay_on => '0',
perform_sync => '0',
transparent => X"5" );
constant c_chargen_line_clocks_hi : unsigned(3 downto 0) := X"0";
constant c_chargen_line_clocks_lo : unsigned(3 downto 0) := X"1";
constant c_chargen_char_width : unsigned(3 downto 0) := X"2";
constant c_chargen_char_height : unsigned(3 downto 0) := X"3";
constant c_chargen_chars_per_line : unsigned(3 downto 0) := X"4";
constant c_chargen_active_lines : unsigned(3 downto 0) := X"5";
constant c_chargen_x_on_hi : unsigned(3 downto 0) := X"6";
constant c_chargen_x_on_lo : unsigned(3 downto 0) := X"7";
constant c_chargen_y_on_hi : unsigned(3 downto 0) := X"8";
constant c_chargen_y_on_lo : unsigned(3 downto 0) := X"9";
constant c_chargen_pointer_hi : unsigned(3 downto 0) := X"A";
constant c_chargen_pointer_lo : unsigned(3 downto 0) := X"B";
constant c_chargen_perform_sync : unsigned(3 downto 0) := X"C";
constant c_chargen_transparency : unsigned(3 downto 0) := X"D";
constant c_chargen_keyb_row : unsigned(3 downto 0) := X"E";
constant c_chargen_keyb_col : unsigned(3 downto 0) := X"F";
end package;
| gpl-3.0 | 31cb83ba4c3c9c594918bac20d529182 | 0.463874 | 3.817259 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op332_9.vhdl | 1 | 4,927 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | c7c2cc1333aa549cc88ddc1c9c2833cb | 0.579663 | 3.172569 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_regs.vhd | 4 | 11,455 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_regs is
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
---
comb_wave_l : in std_logic;
comb_wave_r : in std_logic;
---
voice_osc : in unsigned(3 downto 0);
voice_wave : in unsigned(3 downto 0);
voice_adsr : in unsigned(3 downto 0);
voice_mul : in unsigned(3 downto 0);
-- Oscillator parameters
freq : out unsigned(15 downto 0);
test : out std_logic;
sync : out std_logic;
-- Wave map parameters
comb_mode : out std_logic;
ring_mod : out std_logic;
wave_sel : out std_logic_vector(3 downto 0);
sq_width : out unsigned(11 downto 0);
-- ADSR parameters
gate : out std_logic;
attack : out std_logic_vector(3 downto 0);
decay : out std_logic_vector(3 downto 0);
sustain : out std_logic_vector(3 downto 0);
release : out std_logic_vector(3 downto 0);
-- mixer 1 parameters
filter_en : out std_logic;
-- globals
volume_l : out unsigned(3 downto 0) := (others => '0');
filter_co_l : out unsigned(10 downto 0) := (others => '0');
filter_res_l : out unsigned(3 downto 0) := (others => '0');
filter_ex_l : out std_logic := '0';
filter_hp_l : out std_logic := '0';
filter_bp_l : out std_logic := '0';
filter_lp_l : out std_logic := '0';
voice3_off_l : out std_logic := '0';
volume_r : out unsigned(3 downto 0) := (others => '0');
filter_co_r : out unsigned(10 downto 0) := (others => '0');
filter_res_r : out unsigned(3 downto 0) := (others => '0');
filter_ex_r : out std_logic := '0';
filter_hp_r : out std_logic := '0';
filter_bp_r : out std_logic := '0';
filter_lp_r : out std_logic := '0';
voice3_off_r : out std_logic := '0';
-- readback
osc3 : in std_logic_vector(7 downto 0);
env3 : in std_logic_vector(7 downto 0) );
attribute keep_hierarchy : string;
attribute keep_hierarchy of sid_regs : entity is "yes";
end sid_regs;
architecture gideon of sid_regs is
type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0);
signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0'));
signal control : byte_array_t(0 to 15) := (others => (others => '0'));
signal att_dec : byte_array_t(0 to 15) := (others => (others => '0'));
signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0'));
signal do_write : std_logic;
signal wdata_d : std_logic_vector(7 downto 0);
signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0');
constant address_remap : byte_array_t(0 to 255) := (
X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1
X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2
X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3
X"08", X"09", X"0A", X"0B", -- 15
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19
X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4
X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5
X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6
X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7
X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8
X"0C", X"0D", X"0E", -- 43
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77
X"FF", X"FF", -- 7E
X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9
X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10
X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11
X"88", X"89", X"8A", X"8B", -- 95
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99
X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12
X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13
X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14
X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15
X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16
X"8C", X"8D", X"8E", -- C3
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7
X"FF", X"FF" ); -- FE
signal address : unsigned(7 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
address <= unsigned(address_remap(to_integer(addr)));
do_write <= wren;
wdata_d <= wdata;
if do_write='1' then
if address(3)='0' then -- Voice register
case address(2 downto 0) is
when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d;
when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata_d;
when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata_d;
when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata_d(3 downto 0);
when "100" => control(to_integer(address(7 downto 4))) <= wdata_d;
when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata_d;
when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata_d;
when others => null;
end case;
elsif address(7)='0' then -- Global register for left
case address(2 downto 0) is
when "000" => filter_co_l(2 downto 0) <= unsigned(wdata_d(2 downto 0));
when "001" => filter_co_l(10 downto 3) <= unsigned(wdata_d);
when "010" => filter_res_l <= unsigned(wdata_d(7 downto 4));
filter_ex_l <= wdata_d(3);
filt_en_i(2 downto 0) <= wdata_d(2 downto 0);
when "011" => voice3_off_l <= wdata_d(7);
filter_hp_l <= wdata_d(6);
filter_bp_l <= wdata_d(5);
filter_lp_l <= wdata_d(4);
volume_l <= unsigned(wdata_d(3 downto 0));
when "100" => filt_en_i(7 downto 0) <= wdata_d;
when others => null;
end case;
else -- Global register for right
case address(2 downto 0) is
when "000" => filter_co_r(2 downto 0) <= unsigned(wdata_d(2 downto 0));
when "001" => filter_co_r(10 downto 3) <= unsigned(wdata_d);
when "010" => filter_res_r <= unsigned(wdata_d(7 downto 4));
filter_ex_r <= wdata_d(3);
filt_en_i(10 downto 8) <= wdata_d(2 downto 0);
when "011" => voice3_off_r <= wdata_d(7);
filter_hp_r <= wdata_d(6);
filter_bp_r <= wdata_d(5);
filter_lp_r <= wdata_d(4);
volume_r <= unsigned(wdata_d(3 downto 0));
when "100" => filt_en_i(15 downto 8) <= wdata_d;
when others => null;
end case;
end if;
end if;
-- Readback (unmapped address)
case addr is
when "00011011" => rdata <= osc3;
when "00011100" => rdata <= env3;
when others => rdata <= (others => '0');
end case;
if reset='1' then
filt_en_i <= (others => '0');
voice3_off_l <= '0';
voice3_off_r <= '0';
volume_l <= X"0";
volume_r <= X"0";
end if;
end if;
end process;
freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc)));
test <= control(to_integer(voice_osc))(3);
sync <= control(to_integer(voice_osc))(1);
-- Wave map parameters
ring_mod <= control(to_integer(voice_wave))(2);
wave_sel <= control(to_integer(voice_wave))(7 downto 4);
sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave)));
comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l);
-- ADSR parameters
gate <= control(to_integer(voice_adsr))(0);
attack <= att_dec(to_integer(voice_adsr))(7 downto 4);
decay <= att_dec(to_integer(voice_adsr))(3 downto 0);
sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4);
release <= sust_rel(to_integer(voice_adsr))(3 downto 0);
-- Mixer 1 parameters
filter_en <= filt_en_i(to_integer(voice_mul));
end gideon;
| gpl-3.0 | d7bea00b17fd32802fa922418a787e6c | 0.442951 | 3.156517 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/s3e_clockgen.vhd | 5 | 2,942 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3e_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_shifted : out std_logic;
eth_clock : out std_logic ); -- / 2.5 (20 MHz)
end s3e_clockgen;
architecture Gideon of s3e_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
signal sysrst_cnt : integer range 0 to 63;
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_270_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK270 => clk_270_pre,
CLKDV => eth_clock,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_shft: BUFG port map (I => clk_270_pre, O => sys_shifted);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
end Gideon;
| gpl-3.0 | eec04665cef38d3ea2597ef29a0daa7c | 0.49932 | 3.187432 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_compare2.vhd | 1 | 3,968 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- lpm_compare
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare2 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AgeB : OUT STD_LOGIC
);
END lpm_compare2;
ARCHITECTURE SYN OF lpm_compare2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AgeB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AgeB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
AgeB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: AgeB 0 0 0 0 OUTPUT NODEFVAL AgeB
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: CONNECT: AgeB 0 0 0 0 @AgeB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_inst.vhd TRUE
| gpl-2.0 | 88ab2f6c81137f011ca34ad98562516a | 0.65121 | 3.81172 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op993_24.vhdl | 1 | 6,541 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 26f28b70169ea3faec91d0c9c0b54d32 | 0.570402 | 3.062266 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE.vhd | 1 | 4,597 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file ROM_GAUSS_COE.vhd when simulating
-- the core, ROM_GAUSS_COE. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY ROM_GAUSS_COE IS
PORT (
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(134 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(134 DOWNTO 0)
);
END ROM_GAUSS_COE;
ARCHITECTURE ROM_GAUSS_COE_a OF ROM_GAUSS_COE IS
-- synthesis translate_off
COMPONENT wrapped_ROM_GAUSS_COE
PORT (
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(134 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(134 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_ROM_GAUSS_COE USE ENTITY XilinxCoreLib.dist_mem_gen_v7_2(behavioral)
GENERIC MAP (
c_addr_width => 4,
c_default_data => "0",
c_depth => 16,
c_family => "virtex5",
c_has_clk => 1,
c_has_d => 1,
c_has_dpo => 0,
c_has_dpra => 0,
c_has_i_ce => 0,
c_has_qdpo => 0,
c_has_qdpo_ce => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_rst => 0,
c_has_qdpo_srst => 0,
c_has_qspo => 0,
c_has_qspo_ce => 0,
c_has_qspo_rst => 0,
c_has_qspo_srst => 0,
c_has_spo => 1,
c_has_spra => 0,
c_has_we => 1,
c_mem_init_file => "ROM_GAUSS_COE.mif",
c_mem_type => 1,
c_parser_type => 1,
c_pipeline_stages => 0,
c_qce_joined => 0,
c_qualify_we => 0,
c_read_mif => 1,
c_reg_a_d_inputs => 0,
c_reg_dpra_input => 0,
c_sync_enable => 1,
c_width => 135
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ROM_GAUSS_COE
PORT MAP (
a => a,
d => d,
clk => clk,
we => we,
spo => spo
);
-- synthesis translate_on
END ROM_GAUSS_COE_a;
| gpl-3.0 | 8e619c156c384d57cf67c5fc26659526 | 0.529258 | 4.198174 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op337_3sk1_0.vhdl | 1 | 7,603 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.25e-06,
W => Wdiff_0,
Wdiff_0init => 2.525e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.25e-06,
W => Wdiff_0,
Wdiff_0init => 2.525e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => W_0,
W_0init => 6.165e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.25e-06,
W => Wdiff_0,
Wdiff_0init => 2.525e-05,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 2.25e-06,
W => Wdiff_0,
Wdiff_0init => 2.525e-05,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.1e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.1e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.1e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.1e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.75e-06,
W => Wsrc_2,
Wsrc_2init => 1.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.75e-06,
W => Wsrc_2,
Wsrc_2init => 1.5e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.3e-06,
W => Wcm_1,
Wcm_1init => 1.25e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.3e-06,
W => Wcmcout_1,
Wcmcout_1init => 3.65e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.35e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => (pfak)*(WBias),
WBiasinit => 1.35e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.35e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.35e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.35e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.85e-06,
W => WBias,
WBiasinit => 1.35e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | b1b62c0a020171374faa0ea42db224cc | 0.582139 | 2.869057 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op968_3.vhdl | 1 | 5,055 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9727d15c4a4269a2ba237494c784b9e9 | 0.579228 | 3.173258 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd | 1 | 3,472 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
entity zpu_system is
generic(
simulate : boolean := false);
port ( areset : in std_logic;
cpu_clk : in std_logic;
-- ZPU Control signals
enable : in std_logic;
interrupt : in std_logic;
zpu_status : out std_logic_vector(63 downto 0);
-- wishbone interfaces
zpu_wb_i : in wishbone_bus_out;
zpu_wb_o : out wishbone_bus_in);
end zpu_system;
architecture behave of zpu_system is
signal mem_req : std_logic;
signal mem_we : std_logic;
signal mem_ack : std_logic;
signal mem_read : std_logic_vector(wordSize-1 downto 0);
signal mem_write : std_logic_vector(wordSize-1 downto 0);
signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
begin
my_zpu_core:
zpu_core port map (
clk => cpu_clk,
areset => areset,
enable => enable,
mem_req => mem_req,
mem_we => mem_we,
mem_ack => mem_ack,
mem_read => mem_read,
mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
interrupt => interrupt,
zpu_status => zpu_status,
break => open);
my_zpu_wb_bridge:
zpu_wb_bridge port map (
clk => cpu_clk,
areset => areset,
mem_req => mem_req,
mem_we => mem_we,
mem_ack => mem_ack,
mem_read => mem_read,
mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
zpu_wb_i => zpu_wb_i,
zpu_wb_o => zpu_wb_o);
end behave;
| gpl-2.0 | 8f4b12a75b95a17f22432fa50a7deecb | 0.664459 | 3.170776 | false | false | false | false |
KB777/1541UltimateII | target/simulation/packages/vhdl_source/tl_flat_memory_model_pkg.vhd | 4 | 25,706 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
variable L : line;
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
| gpl-3.0 | 148c2104ff9065074730e4604caf4b4a | 0.520579 | 4.19074 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op324_2sk1_0.vhdl | 1 | 5,006 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.275e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.275e-05,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 6.305e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.25e-06,
W => Wcm_1,
Wcm_1init => 8.4e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.25e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.82e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | b5381562a719cfdd39da17d46796fb7f | 0.592089 | 3.039466 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/async_fifo/vhdl_source/async_fifo.vhd | 5 | 16,715 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
| gpl-3.0 | e1ca82bb9738a1b504fcb371d925e406 | 0.392103 | 4.709777 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/dpram_io.vhd | 4 | 3,453 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture xilinx of dpram_io is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
shared variable ram : t_ram := (others => g_default);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
signal b_address : unsigned(g_depth_bits-1 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_ack : std_logic := '0';
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
b_address <= b_req.address(g_depth_bits-1 downto 0);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_wdata <= b_req.data;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 8ceea975008bd1e29685cc5e7faf4841 | 0.433826 | 3.757345 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op966_6.vhdl | 1 | 5,444 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1d18478cd0438c093dd4bb4cc63d096e | 0.574026 | 3.134139 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi_peripheral_zpu.vhd | 5 | 5,466 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_peripheral_zpu is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
bus_read : in std_logic;
bus_write : in std_logic;
bus_rack : out std_logic;
bus_dack : out std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
SD_DETECTn : in std_logic;
SD_WRPROTn : in std_logic := '1';
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral_zpu;
architecture gideon of spi_peripheral_zpu is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
type t_state is (idle, writing, reading, receive);
signal state : t_state;
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
bus_rack <= '0';
bus_dack <= '0';
bus_rdata <= (others => '0');
case state is
when idle =>
if bus_write='1' then
state <= writing;
elsif bus_read='1' then
state <= reading;
end if;
when writing =>
if busy='0' then
bus_rack <= '1';
state <= idle;
case bus_addr is
when "00" =>
do_send <= '1';
wdata <= bus_wdata;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= bus_wdata;
rate(8) <= bus_wdata(7);
end if;
when "10" =>
force_ss <= bus_wdata(0);
level_ss <= bus_wdata(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
when reading =>
if busy='0' then
bus_rack <= '1';
case bus_addr is
when "00" =>
do_send <= '1';
wdata <= X"FF";
state <= receive;
when "01" =>
bus_rdata <= rate(7 downto 0);
bus_dack <= '1';
state <= idle;
when "10" =>
bus_rdata <= "0000" & not SD_WRPROTn & not SD_DETECTn & level_ss & force_ss;
bus_dack <= '1';
state <= idle;
when "11" =>
bus_rdata <= crc_out;
bus_dack <= '1';
state <= idle;
when others =>
null;
end case;
end if;
when receive =>
if do_send = '0' and busy = '0' then
bus_rdata <= rdata;
bus_dack <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
force_ss <= '0';
level_ss <= '1';
wdata <= (others => '0');
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 5464edcef2e3110d1ef24605e5ee7de6 | 0.34742 | 4.59714 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_PHYMI.vhd | 3 | 5,745 | ------------------------------------------------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2009-09-07 V0.02 zelenkaj Changed tristate port to In/Out and enable (Xilinx XPS doesn't like IO Ports...)
-- 2009-09-18 V0.03 zelenkaj Deleted NodeNr - isn't used by anyone...
-- 2011-11-28 V0.04 zelenkaj Changed reset level to high-active
-- 2012-07-30 V0.05 zelenkaj Omit internal tbuf
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
Mii_Do <= M_Dout;
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 | 917145b3267131d09844bf1dbd643d69 | 0.556658 | 3.328505 | false | false | false | false |
Sourangsu/RAM-Arbiter-VHDL-Code | RAM_TEST.vhd | 1 | 2,705 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ram_test IS
END ram_test;
ARCHITECTURE behavior OF ram_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RAM_NEW
PORT(
CLOCK : IN std_logic;
RST_N : IN std_logic;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
RD_ADDR : IN std_logic_vector(3 downto 0);
WR_ADDR : IN std_logic_vector(3 downto 0);
WR_DATA : IN std_logic_vector(7 downto 0);
RD_DATA : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLOCK : std_logic := '0';
signal RST_N : std_logic := '0';
signal RD_EN : std_logic := '0';
signal WR_EN : std_logic := '0';
signal RD_ADDR : std_logic_vector(3 downto 0) := (others => '0');
signal WR_ADDR : std_logic_vector(3 downto 0) := (others => '0');
signal WR_DATA : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal RD_DATA : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RAM PORT MAP (
CLOCK => CLOCK,
RST_N => RST_N,
RD_EN => RD_EN,
WR_EN => WR_EN,
RD_ADDR => RD_ADDR,
WR_ADDR => WR_ADDR,
WR_DATA => WR_DATA,
RD_DATA => RD_DATA
);
CLOCK_process :process
begin
CLOCK <= '0';
wait for 50 ns;
CLOCK <= '1';
wait for 50 ns;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100 ns;
RST_N<='1';
wait for 100 ns;
-------------------------------------------------------------------------------------------------------------------
-- Test Case 1: RAM Write Operation
-------------------------------------------------------------------------------------------------------------------
WR_EN<='1';
RD_EN<='0';
WR_ADDR<="1101";
WR_DATA<="11100111";
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
--Test Case 2: RAM Read Operation
wr_en<='0';
rd_en<='1';
RD_ADDR<= "1101";
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- Test Case 3: RAM Read & Write Operation
-------------------------------------------------------------------------------------------------------------------
WR_EN<='1';
RD_EN<='1';
RD_ADDR<= "1101";
WR_ADDR<="1011";
WR_DATA<="10111001";
wait for 1700 ns;
RD_ADDR<= "1011";
WR_ADDR <="1000";
WR_DATA <="10011111";
-------------------------------------------------------------------------------------------------------------------
wait;
end process;
END;
| bsd-3-clause | ed676d90459d0a82a77621d96b9ef2ff | 0.428835 | 3.989676 | false | true | false | false |
chrismasters/fpga-notes | sdramcontroller/ipcore_dir/clks.vhd | 1 | 6,296 | -- file: clks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT2___133.333____180.000______50.0______230.136____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clks;
architecture xilinx of clks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clks,clk_wiz_v3_6,{component_name=clks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 6,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 180.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
| mit | 8831c03c89c039500efff5437a306013 | 0.595457 | 4.164021 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd | 3 | 1,867 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
------------------------------------------------------------------------
-- Top level ZPU + wishbone componenent to use in a verilog design:
-- zpu_wb_top wraps around the zpu_system component.
-- All IO lines are exposed as std_logic for verilog.
------------------------------------------------------------------------
entity zpu_wb_top is
generic (
dat_w: integer := 32;
adr_w: integer := 16;
sel_w: integer := 4
);
port (
clk: in std_logic;
rst: in std_logic;
enb: in std_logic;
-- wishbone interface
dat_i: in std_logic_vector(dat_w-1 downto 0);
ack_i: in std_logic;
adr_o: out std_logic_vector(adr_w-1 downto 0);
sel_o: out std_logic_vector(sel_w-1 downto 0);
we_o: out std_logic;
dat_o: out std_logic_vector(dat_w-1 downto 0);
cyc_o: out std_logic;
stb_o: out std_logic;
-- misc zpu signals
interrupt: in std_logic;
zpu_status: out std_logic_vector(63 downto 0)
);
end zpu_wb_top;
architecture syn of zpu_wb_top is
--wishbone interface (records)
signal zpu_wb_i: wishbone_bus_out;
signal zpu_wb_o: wishbone_bus_in;
begin
--assign wishbone signals to records
zpu_wb_i.dat <= dat_i;
zpu_wb_i.ack <= ack_i;
adr_o <= zpu_wb_o.adr;
sel_o <= zpu_wb_o.sel;
we_o <= zpu_wb_o.we;
dat_o <= zpu_wb_o.dat;
cyc_o <= zpu_wb_o.cyc;
stb_o <= zpu_wb_o.stb;
--instantiate the zpu system
zpu_system0: zpu_system port map(
cpu_clk => clk,
areset => rst,
enable => enb,
interrupt => interrupt,
zpu_status => zpu_status,
zpu_wb_i => zpu_wb_i,
zpu_wb_o => zpu_wb_o
);
end architecture syn;
| gpl-2.0 | cbec74452ae009f5adcbc2aa6ce14eb4 | 0.566685 | 2.968203 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu.vhd | 5 | 8,493 | ------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
| gpl-3.0 | 3ee69157159115d1e8765f6e6fdd0f47 | 0.397739 | 4.293731 | false | false | false | false |
Cognoscan/BoostLogic | vhdl/src/basic/reset_sequencer_ea.vhd | 1 | 9,832 | --! @file reset_sequencer_ea.vhd
--! @brief Reset Sequencer for multiple reset signals
--! @author Scott Teal ([email protected])
--! @date 2013-09-25
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! @brief Reset Sequencer. Sequences reset signals and can check status signals.
--! @details
--! The reset sequencer is used to turn on a system in sequence, with the initial
--! asynchronous reset signal being debounced and then used to start a sequence
--! of turning off reset signals. Each signal has a time-out period, after
--! which it checks to see if the associated "check_good" line is high. If it
--! is, then the sequencer moves to turning off the next reset signal. If it is
--! not, then the system brings the reset high again for retry_time before
--! trying again. If the bit in move_fast associated with the reset signal is
--! high, then it will move to the next reset signal in sequence immediately
--! when the associated check_good signal is high.
--!
--! Sequence
--! 1. Come out of reset (rst goes to '0')
--! 2. Set first reset signal (rst_vector(0)) to '0'.
--! 3. If check_good(0) = '1' and move_fast(0) = '1', then repeat from step 2
--! with next signal. Else wait for wait_times(0).
--! 4. If check_good(0) = '1', then repeat from step 2 with next signal. Else
--! set rst_vector(0) to '1' and wait for retry_time before repeating from
--! step 2 with same signal.
--! 5. Sequence complete, set done = '1'
entity reset_sequencer is
generic (
clk_period : time := 20 ns; --! Period of clk signal
--! Vector of times to wait/timeout for each reset signal
wait_times : time_vector;
retry_time : time := 80 ns; --! Time to keep reset high while retrying
move_fast : std_logic_vector; --! If '1', go to next once check_good = '1'
debounce_time : time := 1 ms --! Time to wait before rst can change again
);
port (
clk : in std_logic; --! Reference clock
rst : in std_logic; --! Asynchronous reset
check_good : in std_logic_vector; --! Signals showing subsystems are ready
rst_vector : out std_logic_vector; --! Reset signals to subsystems
done : out std_logic --! Indicates sequencer is finished
);
end entity reset_sequencer;
architecture rtl of reset_sequencer is
type unsigned_vector is array(natural range <>) of unsigned;
function get_count(clk_period, count_time : time) return integer is
begin
assert count_time > clk_period
report "All wait_times must be > clk_period" severity error;
return (count_time / clk_period) + 1;
end function;
function get_counts(clk_period : time;
count_times : time_vector) return integer_vector is
variable counts : integer_vector(count_times'range);
begin
for i in count_times'range loop
counts(i) := get_count(clk_period, count_times(i));
end loop;
return counts;
end function;
function counter_width(count : integer) return integer is
begin
return integer(ceil(log2(real(count))));
end function;
function counter_widths(counts : integer_vector) return integer is
variable max_count : integer;
begin
max_count := 1;
for i in counts'range loop
max_count := maximum(max_count, counts(i));
end loop;
return counter_width(max_count);
end function;
function to_unsigned_vector(vals : integer_vector; width : positive)
return unsigned_vector is
variable unsigneds : unsigned_vector(vals'range)((width - 1) downto 0);
begin
for i in vals'range loop
unsigneds(i) := to_unsigned(vals(i), width);
end loop;
return unsigneds;
end function;
-- Debounce Counter Constants and signals
--! Value debounce counter will count down from
constant db_count_val : integer := get_count(clk_period, debounce_time);
--! Minimum possible width of debounce counter
constant db_counter_width : positive := counter_width(db_count_val);
--! Unsigned type value of db_count_val
constant db_counter_init : unsigned((db_counter_width - 1) downto 0) :=
to_unsigned(db_count_val, db_counter_width);
--! Debounce Counter register. Initialize to zero for simulation.
signal debounce_counter : unsigned((db_counter_width - 1) downto 0) :=
(others => '0');
-- Timer constants and signals
--! Values timer counter will count down from during sequencing
constant timer_vals : integer_vector := get_counts(clk_period, wait_times);
--! Value timer counter will count down from when retrying
constant retry_val : integer := get_count(clk_period, retry_time);
--! Minimum possible width of timer counter register
constant timer_width : positive := counter_widths(timer_vals & retry_val);
--! Unsigned type value of retry_val
constant retry_init : unsigned((timer_width - 1) downto 0) :=
to_unsigned(retry_val, timer_width);
--! Unsigned type values of timer_vals
constant timer_inits : unsigned_vector
(timer_vals'range)((timer_width - 1) downto 0) :=
to_unsigned_vector(timer_vals, timer_width);
--! Timer Register
signal timer : unsigned((timer_width - 1) downto 0);
--! rst synchronized to clk and debounced
signal sync_rst : std_logic;
constant reset_width : positive := counter_width(rst_vector'length);
--! Record current location in reset sequence
signal reset_stage : unsigned((reset_width - 1) downto 0);
--! Indicates if currently retrying a reset.
signal retry : std_logic;
begin
-- Verify all vectors are of equal length, otherwise the reset sequencer will
-- act in an unknown manner and probably will fail badly.
assert rst_vector'length = check_good'length
report "check_good not same length as rst_vector" severity error;
assert rst_vector'length = wait_times'length
report "wait_times not same length as rst_vector" severity error;
assert rst_vector'length = move_fast'length
report "move_fast not same length as rst_vector" severity error;
reset_sync : process(clk, rst) is
begin
if rising_edge(clk) then
if debounce_counter = to_unsigned(0, db_counter_width) then
if rst /= sync_rst then
debounce_counter <= db_counter_init;
sync_rst <= rst;
end if;
else
debounce_counter <= debounce_counter - 1;
end if;
end if;
end process;
boot_up : process(clk, sync_rst) is
begin
if rising_edge(clk) then
if sync_rst = '1' then
timer <= timer_inits(0);
reset_stage <= (others => '0');
retry <= '0';
done <= '0';
else
done <= '0';
timer <= timer - 1; -- Decrement unless overriden.
if retry <= '0' then
-- Go to next as soon as signal is good
if move_fast(to_integer(reset_stage)) = '1' then
-- System is good
if check_good(to_integer(reset_stage)) = '1' then
-- Check to see if done with sequence
if to_integer(reset_stage) = (rst_vector'length - 1) then
done <= '1';
timer <= (others => '0');
else
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
end if;
else
-- Expired before it went good
if timer = to_unsigned(0, timer_width) then
timer <= retry_init;
reset_stage <= reset_stage - 1;
retry <= '1';
end if; -- timer
end if; -- check_good
-- Change state once timer expires
else
if timer = to_unsigned(0, timer_width) then
-- Next in sequence if check_good is good
if check_good(to_integer(reset_stage)) = '1' then
-- Check to see if doen with sequence
if to_integer(reset_stage) = (rst_vector'length - 1) then
done <= '1';
timer <= (others => '0');
else
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
end if;
-- Retry if check_good is bad
else
reset_stage <= reset_stage - 1;
timer <= retry_init;
retry <= '1';
end if;
end if;
end if; -- move_fast
else -- retry = '1'
if timer = to_unsigned(0, timer_width) then
reset_stage <= reset_stage + 1;
timer <= timer_inits(to_integer(reset_stage) + 1);
retry <= '0';
end if;
end if; -- retry
end if; -- sync_rst
end if; -- clk
end process;
--! Sets reset vector according to what stage the reset sequencer is at.
set_resets : process(clk)
begin
if rising_edge(clk) then
if sync_rst = '1' then
rst_vector <= (rst_vector'range => '1');
else
for i in rst_vector'range loop
if reset_stage >= to_unsigned(i, reset_width) then
rst_vector(i) <= '1';
else
rst_vector(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
end rtl;
| apache-2.0 | 13a497f53fc773803cac3df1892df2fe | 0.627746 | 3.929656 | false | false | false | false |
chrismasters/fpga-notes | vga_test/vga_test.vhd | 1 | 1,595 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity vga_test is
port (
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
sw1 : in STD_LOGIC;
sw2 : in STD_LOGIC;
sw3 : in STD_LOGIC;
clk : in STD_LOGIC
);
end vga_test;
architecture Behavioral of vga_test is
component vga_clk
port (
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic
);
end component;
signal c25 : STD_LOGIC := '0';
signal hcount : STD_LOGIC_VECTOR(9 downto 0);
signal vcount : STD_LOGIC_VECTOR(9 downto 0);
begin
cc : vga_clk
port map (
CLK_IN1 => clk,
CLK_OUT1 => c25
);
process (c25)
begin
if rising_edge(c25) then
if (hcount = 799) then
hcount <= (others => '0');
if vcount = 524 then
vcount <= (others => '0');
else
vcount <= vcount + 1;
end if;
else
hcount<= hcount + 1;
end if;
if vcount >= 490 and vcount < 492 then
vsync <= '0';
else
vsync <= '1';
end if;
if hcount >=656 and hcount <752 then
hsync <= '0';
else
hsync <= '1';
end if;
if hcount< 630 and vcount < 480 then
if (sw1 = '1') then
red<="1111";
else
red<="0000";
end if;
if (sw2 = '1') then
green<="1111";
else
green<="0000";
end if;
if (sw3 = '1') then
blue<="1111";
else
blue<="0000";
end if;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
| mit | b9e8664d43d31ce6c017211b9dd29040 | 0.579937 | 2.658333 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op981_17.vhdl | 1 | 7,747 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
terminal net15: electrical;
terminal net16: electrical;
terminal net17: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net11
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net12,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net12
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net13
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net13,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net14,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net14
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net15
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net15,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net16,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net16
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net17
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net17,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 338fe418724f66be5d595360cfc31cd8 | 0.573383 | 3.063266 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/led.vhd | 1 | 1,331 | LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity LED_mov is
port
(
Clk : in std_logic;
CalculateSIGNAL: in std_logic;
Uin : in std_logic_vector(7 downto 0);
Vin : in std_logic_vector(7 downto 0);
AverageValU : in std_logic_vector(15 downto 0);
AverageValV : in std_logic_vector(15 downto 0);
Column : unsigned(10 downto 0);
aclr : in std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end LED_mov;
architecture str_LED of LED_mov is
signal AvUHigh : std_logic_vector(15 downto 0); --Threshold high value
signal AvULow : std_logic_vector(15 downto 0); --Threshold low value
begin
Average_thresh : process (AverageValU, AverageValV, aclr)
begin
if (aclr = '1') then
AvUHigh <= AverageValU + "0000000000000010";
AvULow <= AverageValU - "0000000000000010";
end if;
end process Average_thresh;
compare : process(Clk, Column, CalculateSIGNAL, Uin, Vin, AverageValU)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
if(Column <= "0010100000") then
if(AverageValU = Uin) then
LED1 <= '1';
else
LED1 <= '0';
end if;
end if;
end if;
end process compare;
end str_LED; | gpl-2.0 | 2c816dfe8c7b59b2f24f9f0e044f5147 | 0.644628 | 3.102564 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op330_1.vhdl | 1 | 4,928 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1a039e26e80dda89634c7edbd1dd69b2 | 0.579748 | 3.173213 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op8.vhdl | 1 | 12,919 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
terminal net15: electrical;
terminal net16: electrical;
terminal net17: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.8e-06,
W => Wdiff_0,
Wdiff_0init => 1.305e-05,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.8e-06,
W => Wdiff_0,
Wdiff_0init => 1.305e-05,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => W_0,
W_0init => 3.8e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.8e-06,
W => Wdiff_0,
Wdiff_0init => 1.305e-05,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.8e-06,
W => Wdiff_0,
Wdiff_0init => 1.305e-05,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.4e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.4e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.4e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.4e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 4e-07,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 2.1e-06,
W => Wsrc_1,
Wsrc_1init => 5.775e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 1e-14,
symmetry_scope => sym_3
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 2.1e-06,
W => Wsrc_1,
Wsrc_1init => 5.775e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 1e-14,
symmetry_scope => sym_3
)
port map(
P => net4,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 7.605e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net3,
G => vbias3,
S => net9
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8e-07,
W => Wcm_2,
Wcm_2init => 3.47e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8e-07,
W => Wcmout_2,
Wcmout_2init => 6.17e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net10,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 7.605e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net5,
G => vbias3,
S => net10
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 7.605e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net4,
G => vbias3,
S => net11
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8e-07,
W => Wcm_2,
Wcm_2init => 3.47e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8e-07,
W => Wcmout_2,
Wcmout_2init => 6.17e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net12,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 7.605e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net6,
G => vbias3,
S => net12
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.07e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.6e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_4,
C_4init => 3.34e-12,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net5
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.07e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.6e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_5,
C_5init => 7.73e-13,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net6
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcursrc_4,
Wcursrc_4init => 2.045e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => Wcursrc_4,
Wcursrc_4init => 2.045e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net13,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net13,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net16,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net15,
N => net13
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => W_1,
W_1init => 6.38e-05
)
port map(
D => net14,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.145e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 1.79e-05,
scope => private
)
port map(
D => net16,
G => vref,
S => net14
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.145e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 1.79e-05,
scope => private
)
port map(
D => net15,
G => net13,
S => net14
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 6.8e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.45e-06,
scope => private
)
port map(
D => net15,
G => net15,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 6.8e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.45e-06,
scope => private
)
port map(
D => net16,
G => net15,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 8e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.02e-05,
scope => private
)
port map(
D => out1,
G => net16,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 8e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.02e-05,
scope => private
)
port map(
D => out2,
G => net16,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => (pfak)*(WBias),
WBiasinit => 7.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.5e-07,
W => (pfak)*(WBias),
WBiasinit => 7.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.5e-07,
W => WBias,
WBiasinit => 7.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => WBias,
WBiasinit => 7.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net17
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => WBias,
WBiasinit => 7.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.5e-07,
W => WBias,
WBiasinit => 7.55e-06
)
port map(
D => net17,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9d0efeb2019289370fecd9a7d57c5105 | 0.564208 | 2.771128 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd | 2 | 13,444 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
--
-- $Date: 2004/03/14 10:17:03 $
-- $Revision: 1.7 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_top.vhd,v $
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = 4) ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
| gpl-2.0 | 3476ff9bd7b756359e288ed07ed5b5d0 | 0.501413 | 3.60429 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_sim/cache_tc_1.vhd | 5 | 5,701 |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
shared variable mm : p_mem_bus_master_bfm_object;
begin
i_harness: entity work.harness_dm_cache
;
process
variable read_data : std_logic_vector(7 downto 0);
procedure check_mem(addr : unsigned; expected : std_logic_vector) is
variable rd_data : std_logic_vector(7 downto 0);
begin
mem_read(mm, addr, rd_data);
assert rd_data = expected
report "Unexpected data on client " & hstr(addr) & ": Got " & hstr(rd_data) & " while " & hstr(expected) & " was expected."
severity error;
end procedure;
procedure check_dram(addr : unsigned; expected : std_logic_vector) is
variable rd_data : std_logic_vector(7 downto 0);
variable a : std_logic_vector(31 downto 0);
begin
a := (others => '0');
a(addr'length-1 downto 0) := std_logic_vector(addr);
rd_data := read_memory_8(dram, a);
assert rd_data = expected
report "Unexpected data in dram " & hstr(addr) & ": Got " & hstr(rd_data) & " while " & hstr(expected) & " was expected."
severity error;
end procedure;
begin
bind_mem_model("dram", dram);
bind_mem_bus_master_bfm("mem_master", mm);
wait for 100 ns;
for i in 0 to 254 loop
write_memory_8(dram, std_logic_vector(to_unsigned(i,32)), std_logic_vector(to_unsigned(i+1,8)));
end loop;
-- check if single entry gets written to dram, when cache line is empty
check_dram(X"0002", X"03"); -- see if the loop is correct
mem_write(mm, X"1802", X"55");
check_mem(X"0002", X"03"); -- written in the loop above, same cacheline!
wait for 200 ns;
check_dram(X"1802", X"55");
-- check if modified cacheline gets written back correctly upon read miss
check_mem(X"0010", X"11"); -- written in loop
mem_write(mm, X"0011", X"FB");
check_dram(X"0011", X"12"); -- should be OLD data!
mem_read(mm, X"7010", read_data); -- causes read miss
wait for 200 ns;
check_dram(X"0010", X"11");
check_dram(X"0011", X"FB");
check_dram(X"0012", X"13");
check_dram(X"0013", X"14");
-- check if modified cacheline gets written back correctly upon write miss
check_mem(X"0030", X"31"); -- written in loop
mem_write(mm, X"0031", X"FC");
check_dram(X"0031", X"32"); -- should be OLD data!
mem_write(mm, X"7031", X"99"); -- causes write miss
wait for 400 ns;
check_dram(X"0030", X"31");
check_dram(X"0031", X"FC");
check_dram(X"0032", X"33");
check_dram(X"0033", X"34");
-- check if a cacheline is not dirty, that it does not get written back
check_mem(X"0060", X"61"); -- cache line fill (cause: cache miss)
wait for 200 ns;
write_memory_8(dram, X"00000062", X"FF"); -- modify dram
mem_read(mm, X"3060", read_data); -- cache line fill again
wait for 200 ns;
check_dram(X"0062", X"FF");
-- other checks
mem_write(mm, X"1080", X"01");
mem_write(mm, X"1081", X"02");
mem_write(mm, X"1082", X"03");
mem_write(mm, X"1083", X"04");
report "Checking data that just got written in a hit..";
check_mem(X"1083", X"04");
check_mem(X"1082", X"03");
check_mem(X"5082", X"00");
mem_write(mm, X"5082", X"33");
check_mem(X"5082", X"33");
mem_read(mm, X"0081", read_data);
check_mem(X"5082", X"33");
mem_write(mm, X"0000", X"01");
mem_write(mm, X"0001", X"02");
mem_write(mm, X"0002", X"03");
mem_write(mm, X"0003", X"04");
mem_write(mm, X"0004", X"05");
mem_write(mm, X"0005", X"06");
mem_write(mm, X"0006", X"07");
mem_write(mm, X"0007", X"08");
mem_write(mm, X"0008", X"09");
mem_write(mm, X"0010", X"0A");
mem_write(mm, X"0020", X"0B");
mem_write(mm, X"0040", X"0C");
mem_write(mm, X"0080", X"0D");
mem_write(mm, X"0100", X"0E");
mem_write(mm, X"0200", X"0F");
mem_write(mm, X"0400", X"10");
mem_write(mm, X"0800", X"11");
mem_write(mm, X"1000", X"12");
mem_write(mm, X"2000", X"13");
mem_write(mm, X"4000", X"14");
mem_write(mm, X"8000", X"15");
check_mem(X"0010", X"0A");
check_mem(X"0020", X"0B");
check_mem(X"0040", X"0C");
check_mem(X"0080", X"0D");
check_mem(X"0100", X"0E");
check_mem(X"0200", X"0F");
check_mem(X"0400", X"10");
check_mem(X"0800", X"11");
check_mem(X"1000", X"12");
check_mem(X"2000", X"13");
check_mem(X"4000", X"14");
check_mem(X"8000", X"15");
check_mem(X"0000", X"01");
check_mem(X"0001", X"02");
check_mem(X"0002", X"03");
check_mem(X"0003", X"04");
check_mem(X"0004", X"05");
check_mem(X"0005", X"06");
check_mem(X"0006", X"07");
check_mem(X"0007", X"08");
check_mem(X"0008", X"09");
wait;
end process;
end tc;
| gpl-3.0 | b9ded9d3bd5b7d482813e27863d9883b | 0.515874 | 3.19742 | false | false | false | false |
pemb/siphash | siphash_package.vhd | 1 | 1,506 | library ieee;
use ieee.std_logic_1164.all;
package siphash_package is
constant BYTES_WIDTH : integer := 4;
constant BLOCK_WIDTH : integer := 2**(BYTES_WIDTH-1)*8;
constant V_WIDTH : integer := BLOCK_WIDTH;
constant HASH_WIDTH : integer := BLOCK_WIDTH;
constant KEY_WIDTH : integer := 2*BLOCK_WIDTH;
constant COUNT_WIDTH : integer := 8-(BYTES_WIDTH-1);
constant LENGTH_WIDTH : integer := COUNT_WIDTH + BYTES_WIDTH - 1;
constant V0_INIT : std_logic_vector := x"736f6d6570736575";
constant V1_INIT : std_logic_vector := x"646f72616e646f6d";
constant V2_INIT : std_logic_vector := x"6c7967656e657261";
constant V3_INIT : std_logic_vector := x"7465646279746573";
constant V2_FINAL : std_logic_vector := x"00000000000000ff";
type v_array is array (integer range <>) of std_logic_vector(V_WIDTH-1 downto 0);
component sipround is
port (
v0_in, v1_in, v2_in, v3_in : in std_logic_vector(V_WIDTH-1 downto 0);
v0_out, v1_out, v2_out, v3_out : out std_logic_vector(V_WIDTH-1 downto 0)
);
end component;
component siphash is
generic (c : integer := 2);
port (
m : in std_logic_vector (BLOCK_WIDTH-1 downto 0);
b : in std_logic_vector (BYTES_WIDTH-1 downto 0);
rst_n : in std_logic;
clk : in std_logic;
init : in std_logic;
load_k : in std_logic;
init_ready, hash_ready : buffer std_logic;
hash : out std_logic_vector(HASH_WIDTH-1 downto 0)
);
end component;
end package;
| gpl-3.0 | dc453cb388f205df89d16c0f18deeea1 | 0.648074 | 3.06721 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op991_9.vhdl | 1 | 7,073 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net12,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 8ec1d99ca0467d773d70d847b02c8c3f | 0.570762 | 3.053972 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/tb_RetinaDescriptorGenerator.vhd | 1 | 5,981 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:37:05 06/12/2014
-- Design Name:
-- Module Name: /media/DATA42/Dropbox/EmbeddedRetina/embeddedretina_ise/tb_RetinaDescriptorGenerator.vhd
-- Project Name: EmbeddedRetina_ISE
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RetinaDescriptorGenerator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_RetinaDescriptorGenerator IS
END tb_RetinaDescriptorGenerator;
ARCHITECTURE behavior OF tb_RetinaDescriptorGenerator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RetinaDescriptorGenerator
PORT(
CLK : IN std_logic;
ENABLE : IN std_logic;
IMG_BASE_ADDR : IN std_logic_vector(31 downto 0);
KPTS_ADDR : IN std_logic_vector(31 downto 0);
KPT_DATA : IN std_logic_vector(31 downto 0);
PIXEL_DATA : IN std_logic_vector(7 downto 0);
RST : IN std_logic;
KPT_ADDR_MEM : OUT std_logic_vector(31 downto 0);
PIXEL_ADDR_MEM : OUT std_logic_vector(31 downto 0);
DESCRIPTOR : OUT std_logic_vector(511 downto 0);
ENABLEOUT : OUT std_logic;
KPT_READ_MEM : OUT std_logic;
PIXEL_READ_MEM : OUT std_logic
);
END COMPONENT;
COMPONENT RAM
PORT(
clk: IN std_logic;
address: IN std_logic_vector(31 downto 0);
read_en: IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal ENABLE : std_logic := '0';
signal IMG_BASE_ADDR : std_logic_vector(31 downto 0) := (others => '0');
signal KPTS_ADDR : std_logic_vector(31 downto 0) := (others => '0');
signal KPT_DATA : std_logic_vector(31 downto 0) := (others => '0');
signal PIXEL_DATA : std_logic_vector(7 downto 0) := (others => '1');
signal RST : std_logic := '0';
--Outputs
signal KPT_ADDR_MEM : std_logic_vector(31 downto 0);
signal PIXEL_ADDR_MEM : std_logic_vector(31 downto 0);
signal DESCRIPTOR : std_logic_vector(511 downto 0);
signal ENABLEOUT : std_logic;
signal KPT_READ_MEM : std_logic;
signal PIXEL_READ_MEM : std_logic;
signal contador: integer range 0 to 4000000 := 0;
signal end_simulation: std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RetinaDescriptorGenerator PORT MAP (
CLK => CLK,
ENABLE => ENABLE,
IMG_BASE_ADDR => IMG_BASE_ADDR,
KPTS_ADDR => KPTS_ADDR,
KPT_DATA => KPT_DATA,
PIXEL_DATA => PIXEL_DATA,
RST => RST,
KPT_ADDR_MEM => KPT_ADDR_MEM,
PIXEL_ADDR_MEM => PIXEL_ADDR_MEM,
DESCRIPTOR => DESCRIPTOR,
ENABLEOUT => ENABLEOUT,
KPT_READ_MEM => KPT_READ_MEM,
PIXEL_READ_MEM => PIXEL_READ_MEM
);
comp_ram: RAM PORT MAP(
clk => CLK,
address => PIXEL_ADDR_MEM,
read_en => PIXEL_READ_MEM,
data_out => PIXEL_DATA
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
reset_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
-- wait for clk_period*100;
-- insert stimulus here
wait;
end process;
-- Stimulus process
stim_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IMG_BASE_ADDR <= "00000000000000000000001000000000";
KPTS_ADDR <= "00000000000000000000000000000000";
KPT_DATA <= "00000000000000110010000011001000";
ENABLE <= '0';
PIXEL_DATA <= (others => '1');
contador <= 0;
elsif contador = 0 then
contador <= contador +1;
ENABLE <= '1';
else
contador <= contador +1;
ENABLE <= '0';
end if;
if ENABLEOUT = '1' then
end_simulation <= '1';
end if;
if end_simulation = '1' then
assert false report "SUCCESSFUL: Simulation End." severity failure;
end if;
end if;
end process;
END;
| gpl-3.0 | cacfc3f6d93e89e8fa6203b02703ab85 | 0.607424 | 3.75691 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5.vhd | 3 | 11,994 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5 is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_burst_16_req;
resp : out t_mem_burst_16_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002A", "000" ), -- mode register, burstlen=4, writelen=4, CAS lat = 2, interleaved
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic_vector(1 downto 0) := "00";
signal r_valid : std_logic_vector(3 downto 0) := "0000";
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal cs_n_i : std_logic;
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_hi_d : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack : std_logic;
signal rack : std_logic;
signal dnext : std_logic;
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal addr_row : std_logic_vector(12 downto 0);
signal addr_column : std_logic_vector(9 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
-- attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
addr_bank <= std_logic_vector(req.address(3 downto 2));
addr_row <= std_logic_vector(req.address(24 downto 12));
addr_column <= std_logic_vector(req.address(11 downto 4)) & std_logic_vector(req.address(1 downto 0));
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_hi_d & rdata_lo;
resp.rack <= rack;
resp.dack <= dack;
resp.dnext <= dnext;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rwn_i <= req.read_writen;
last_bank <= addr_bank;
mem_a_i(12 downto 0) <= addr_row;
mem_a_i(14 downto 13) <= addr_bank;
col_addr <= addr_column;
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
dnext <= '1'; -- if we set delay to a value not equal to zero, we should not
-- set the dnext here.
end procedure;
begin
if rising_edge(clock) then
dack <= '0';
dnext <= '0';
inhibit_d <= inhibit;
rdata_hi_d <= rdata_hi;
cs_n_i <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
sram_d_t <= '0' & sram_d_t(1);
r_valid <= '0' & r_valid(3 downto 1);
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
cs_n_i <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
-- we always perform auto precharge.
-- If the next access is to ANOTHER bank, then
-- we do not have to wait AFTER issuing this CAS.
-- the delay after the CAS, causes the next RAS to
-- be further away in time. If there is NO access
-- pending, then we assume the same bank, and introduce
-- the delay.
if (req_i='1' and addr_bank=last_bank) or req_i='0' then
refr_delay <= 2;
end if;
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
if delay <= 1 then
dnext <= '1';
end if;
if delay = 0 then
if rwn_i='0' then
sram_d_t <= "11";
else
r_valid(3 downto 2) <= "11";
end if;
-- read or write with auto precharge
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 1;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
-- sram_d_t <= (others => '0');
delay <= 0;
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
process(state, do_refresh, inhibit, inhibit_d, req_i, refr_delay)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
null;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
MEM_D <= sram_d_o when sram_d_t(0)='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
select_out: FDDRRSE
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q0 => rdata_lo(i),
Q1 => rdata_hi(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D => MEM_D(i),
R => reset,
S => '0');
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sram_d_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => req.data(8+i),
D1 => req.data(i),
R => reset,
S => '0' );
end generate;
end Gideon;
| gpl-3.0 | a1659edad734d2f987ca62d27c9f8d28 | 0.440887 | 3.721378 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd | 2 | 10,212 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Sample client for loading an image to asynchronous SRAM
--
-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ram_loader is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
lamp_o : out std_logic;
-- Config Interface -------------------------------------------------------
cfg_clk_i : in std_logic;
cfg_data_i : in std_logic;
start_o : out std_logic;
mode_o : out std_logic;
done_o : out std_logic;
detached_i : in std_logic;
-- Asynchronous RAM Interface ---------------------------------------------
ram_addr_o : out std_logic_vector(15 downto 0);
ram_data_b : out std_logic_vector( 7 downto 0);
ram_ce_no : out std_logic_vector( 3 downto 0);
ram_oe_no : out std_logic;
ram_we_no : out std_logic
);
end ram_loader;
library ieee;
use ieee.numeric_std.all;
architecture rtl of ram_loader is
signal addr_q : unsigned(17 downto 0);
signal inc_addr_s : boolean;
signal shift_dat_q : std_logic_vector(7 downto 0);
signal ser_dat_q : std_logic_vector(7 downto 0);
signal bit_q : unsigned(2 downto 0);
signal bit_ovfl_q : boolean;
type fsm_t is (IDLE,
WE_ON,
WE_OFF,
INC_ADDR1, INC_ADDR2,
FINISHED);
signal fsm_s,
fsm_q : fsm_t;
signal done_q : std_logic;
signal done_s : boolean;
signal mode_q,
mode_s : std_logic;
signal ram_we_n_q,
ram_we_n_s : std_logic;
signal ram_ce_n_q,
ram_ce_n_s : std_logic_vector(3 downto 0);
type start_fsm_t is (WAIT_DETACH,
CHECK_NO_DONE,
WAIT_DONE);
signal start_fsm_s,
start_fsm_q : start_fsm_t;
signal start_s,
start_q : std_logic;
signal enable_s,
enable_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements clocked with cfg_clk_i.
--
seq: process (cfg_clk_i, reset_i)
begin
if reset_i = '0' then
addr_q <= (others => '0');
shift_dat_q <= (others => '0');
ser_dat_q <= (others => '0');
bit_q <= (others => '0');
bit_ovfl_q <= false;
fsm_q <= IDLE;
ram_we_n_q <= '1';
ram_ce_n_q <= (others => '1');
done_q <= '0';
mode_q <= '0';
elsif cfg_clk_i'event and cfg_clk_i = '1' then
if inc_addr_s then
addr_q <= addr_q + 1;
end if;
if enable_q then
bit_q <= bit_q + 1;
bit_ovfl_q <= bit_q = 7;
shift_dat_q(0) <= cfg_data_i;
shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0);
end if;
-- update register when 8 serial bits have been shifted in
if bit_ovfl_q then
ser_dat_q <= shift_dat_q;
end if;
fsm_q <= fsm_s;
ram_we_n_q <= ram_we_n_s;
ram_ce_n_q <= ram_ce_n_s;
-- done only settable once
if done_s then
done_q <= '1';
end if;
mode_q <= mode_s;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Implements the combinational logic of the RAM loader FSM.
--
fsm: process (fsm_q,
bit_ovfl_q,
start_q,
addr_q)
begin
-- default assignments
inc_addr_s <= false;
ram_we_n_s <= '1';
done_s <= false;
fsm_s <= IDLE;
lamp_o <= '1';
mode_s <= '0';
case fsm_q is
when IDLE =>
lamp_o <= '0';
if start_q = '1' then
if bit_ovfl_q then
fsm_s <= WE_ON;
end if;
end if;
when WE_ON =>
ram_we_n_s <= '0';
fsm_s <= WE_OFF;
when WE_OFF =>
fsm_s <= INC_ADDR1;
when INC_ADDR1 =>
fsm_s <= INC_ADDR2;
when INC_ADDR2 =>
if addr_q = "001111111111111111" then -- load only 64k
fsm_s <= FINISHED;
done_s <= true;
mode_s <= '1';
else
inc_addr_s <= true;
fsm_s <= IDLE;
end if;
when FINISHED =>
fsm_s <= FINISHED;
lamp_o <= '1';
mode_s <= '1';
when others =>
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ce_gen
--
-- Purpose:
-- Generates the four CE signals for the external RAM chips.
--
ce_gen: process (addr_q)
begin
ram_ce_n_s <= (others => '1');
ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0';
end process ce_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process start_seq
--
-- Purpose:
-- Implements the sequential elements clocked with clk_i.
--
start_seq: process (clk_i, reset_i)
begin
if reset_i = '0' then
start_fsm_q <= WAIT_DETACH;
start_q <= '0';
enable_q <= false;
elsif clk_i'event and clk_i = '1' then
start_fsm_q <= start_fsm_s;
enable_q <= enable_s;
start_q <= start_s;
end if;
end process start_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process start_comb
--
-- Purpose:
-- Implements the combinational logic of the start FSM.
--
start_comb: process (start_fsm_q,
detached_i,
done_q,
enable_q,
start_q)
begin
-- default assignments
start_fsm_s <= WAIT_DETACH;
enable_s <= enable_q;
start_s <= start_q;
case start_fsm_q is
-- Wait for detached_i to become '1'
-- This state is entered/left twice:
-- 1. after reset to start the data download
-- 2. after data download to start the next configuration cycle
when WAIT_DETACH =>
if detached_i = '1' then
start_fsm_s <= CHECK_NO_DONE;
enable_s <= true;
start_s <= '1';
else
start_fsm_s <= WAIT_DETACH;
end if;
-- Wait until done_q is '0'
-- This ensures that the FSM stalls when it has started the configuration
-- download. There must be no further action in this case.
when CHECK_NO_DONE =>
if done_q = '0' then
start_fsm_s <= WAIT_DONE;
else
start_fsm_s <= CHECK_NO_DONE;
end if;
-- Wait until done_q is '1'
-- done_q is the signal that the main FSM has finished its work. We
-- need to start the configuration download.
when WAIT_DONE =>
if done_q = '1' then
start_fsm_s <= WAIT_DETACH;
enable_s <= false;
start_s <= '0';
else
start_fsm_s <= WAIT_DONE;
end if;
when others =>
null;
end case;
end process start_comb;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
start_o <= start_q;
mode_o <= mode_q;
done_o <= done_q
when start_q = '1' else
'1';
ram_addr_o <= std_logic_vector(addr_q(15 downto 0));
ram_data_b <= ser_dat_q;
ram_oe_no <= '1';
ram_ce_no <= ram_ce_n_q;
ram_we_no <= ram_we_n_q;
end rtl;
| gpl-2.0 | 70525ff20a0f9f9216f75e48aaf7c9cf | 0.484626 | 3.926182 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op5.vhdl | 1 | 10,676 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.7e-06,
W => Wdiff_0,
Wdiff_0init => 3.515e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.7e-06,
W => Wdiff_0,
Wdiff_0init => 3.515e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => W_0,
W_0init => 5.56e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.7e-06,
W => Wdiff_0,
Wdiff_0init => 3.515e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.7e-06,
W => Wdiff_0,
Wdiff_0init => 3.515e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.28e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.8e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.28e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.8e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.28e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.8e-06,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.28e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.8e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 3.35e-06,
W => Wsrc_1,
Wsrc_1init => 7.54e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 1.2e-14,
symmetry_scope => sym_3
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 3.35e-06,
W => Wsrc_1,
Wsrc_1init => 7.54e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 1.2e-14,
symmetry_scope => sym_3
)
port map(
P => net4,
N => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 2.275e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.45e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => C_4,
C_4init => 1.231e-12,
symmetry_scope => sym_4
)
port map(
P => out1,
N => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 2.275e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.45e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => vdd
);
subnet0_subnet4_c1 : entity cap(behave)
generic map(
C => C_5,
C_5init => 2.046e-12,
symmetry_scope => sym_4
)
port map(
P => out2,
N => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => Wcursrc_3,
Wcursrc_3init => 5.33e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => Wcursrc_3,
Wcursrc_3init => 5.33e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => W_1,
W_1init => 6.53e-05
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.85e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.765e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.85e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.765e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 8.5e-07,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.55e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 8.5e-07,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.33e-05,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.33e-05,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.455e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.455e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4e-06,
W => WBias,
WBiasinit => 1.455e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => WBias,
WBiasinit => 1.455e-05
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => WBias,
WBiasinit => 1.455e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4e-06,
W => WBias,
WBiasinit => 1.455e-05
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6304d68fbd917dee5de98001367d38b7 | 0.566317 | 2.797694 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op946_0.vhdl | 1 | 3,737 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 586ce29afe2af1cb146ac4ed02c64a2f | 0.590313 | 3.310009 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v6_tb.vhd | 5 | 10,060 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v6_tb is
end ext_mem_ctrl_v6_tb;
architecture tb of ext_mem_ctrl_v6_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp : t_mem_burst_16_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
signal start : std_logic := '0';
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
begin
clock <= not clock after 12 ns;
clk_2x <= not clk_2x after 6 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
p_test: process
procedure queue_req(rw : std_logic; bank : integer; row : integer; col : integer) is
begin
req.request <= '1';
req.read_writen <= rw;
req.address <= to_unsigned(bank*8192 + col*8 + row*32768, req.address'length);
wait for 2 ns;
while resp.ready='0' loop
wait until clock='1';
end loop;
wait until clock='1';
req.request <= '0';
end procedure;
begin
req.read_writen <= '1'; -- read
req.request <= '0';
req.address <= unsigned(to_signed(-32, req.address'length));
req.data_pop <= '0';
wait until reset='0';
wait until clock='1';
while true loop
-- read-read, other row, other bank
queue_req('1', 0, 16, 127);
queue_req('1', 1, 17, 0);
-- read-read, other row, same bank
queue_req('1', 1, 18, 1);
-- read-read, same row, other bank
queue_req('1', 2, 18, 2);
-- read-read, same row, same bank
queue_req('1', 2, 18, 3);
-- read-write, other row, other bank
queue_req('0', 0, 16, 4);
-- read-write, other row, same bank
queue_req('1', 0, 16, 127);
queue_req('0', 0, 17, 5);
-- read-write, same row, other bank
queue_req('1', 0, 18, 127);
queue_req('0', 1, 18, 6);
-- read-write, same row, same bank
queue_req('1', 2, 19, 127);
queue_req('0', 2, 19, 7);
-- write-read, other row, other bank
queue_req('1', 3, 20, 8);
-- write-read, other row, same bank
queue_req('0', 0, 16, 127);
queue_req('1', 0, 17, 9);
-- write-read, same row, other bank
queue_req('0', 1, 18, 127);
queue_req('1', 2, 18, 10);
-- write-read, same row, same bank
queue_req('0', 3, 19, 127);
queue_req('1', 3, 19, 11);
-- write-write, other row, other bank
queue_req('0', 0, 20, 127);
queue_req('0', 1, 21, 12);
-- write-write, other row, same bank
queue_req('0', 1, 22, 13);
-- write-write, same row, other bank
queue_req('0', 2, 22, 14);
-- write-write, same row, same bank
queue_req('0', 2, 22, 15);
-- read write toggle performance tests..
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 1, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 1, i);
end loop;
for i in 1 to 1000 loop
queue_req('1', 0, 0, i);
end loop;
end loop;
wait;
end process;
p_write: process(clock)
variable v_data : unsigned(15 downto 0) := X"4001";
begin
if rising_edge(clock) then
if resp.wdata_full='0' and reset='0' then
req.data_push <= '1';
req.data <= std_logic_vector(v_data);
req.byte_en <= "01";
v_data := v_data + 1;
else
req.data_push <= '0';
end if;
end if;
end process;
i_sdram : entity work.mt48lc16m16a2
generic map(
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
-- SDRAM_A <= transport logic_A after 6 ns;
-- SDRAM_BA <= transport logic_BA after 6 ns;
-- SDRAM_CLK <= transport logic_CLK after 6 ns;
-- SDRAM_CKE <= transport logic_CKE after 6 ns;
-- SDRAM_CSn <= transport logic_CSn after 6 ns;
-- SDRAM_RASn <= transport logic_RASn after 6 ns;
-- SDRAM_CASn <= transport logic_CASn after 6 ns;
-- SDRAM_WEn <= transport logic_WEn after 6 ns;
-- SDRAM_DQM <= transport logic_DQM after 6 ns;
-- p_ram_read_emu: process(SDRAM_CLK)
-- variable count : integer := 10;
-- variable ba : std_logic_vector(3 downto 0);
-- begin
-- if rising_edge(SDRAM_CLK) then
-- start <= '0';
-- Qd <= Q;
-- if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
-- start <= '1';
-- ba := "00" & SDRAM_BA;
-- count := 0;
-- end if;
--
-- case count is
-- when 0 =>
-- Q <= ba & X"1";
-- when 1 =>
-- Q <= ba & X"2";
-- when 2 =>
-- Q <= ba & X"3";
-- when 3 =>
-- Q <= ba & X"4";
-- when 4 =>
-- Q <= ba & X"5";
-- when 5 =>
-- Q <= ba & X"6";
-- when 6 =>
-- Q <= ba & X"7";
-- when 7 =>
-- Q <= ba & X"8";
-- when others =>
-- Q <= (others => 'Z');
-- end case;
--
-- if Qd(0)='Z' then
-- MEM_D <= transport Qd after 3.6 ns;
-- else
-- MEM_D <= transport Qd after 5.6 ns;
-- end if;
--
-- count := count + 1;
-- end if;
-- end process;
end;
| gpl-3.0 | 04d202606fb993bfd5f3ce8462730d02 | 0.422962 | 3.490632 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/RetinaDescriptorGenerator.vhd | 1 | 8,944 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_S42m9M
-- /___/ /\ Timestamp : 05/09/2014 00:41:30
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity RetinaDescriptorGenerator is
port ( CLK : in std_logic;
ENABLE : in std_logic;
IMG_BASE_ADDR : in std_logic_vector (31 downto 0);
KPTS_ADDR : in std_logic_vector (31 downto 0);
KPT_DATA : in std_logic_vector (31 downto 0);
PIXEL_DATA : in std_logic_vector (PIXEL_BW-1 downto 0);
RST : in std_logic;
KPT_ADDR_MEM : out std_logic_vector (31 downto 0);
PIXEL_ADDR_MEM: out std_logic_vector (31 downto 0);
DESCRIPTOR : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
ENABLEOUT : out std_logic;
KPT_READ_MEM : out std_logic;
PIXEL_READ_MEM : out std_logic
);
end RetinaDescriptorGenerator;
architecture BEHAVIORAL of RetinaDescriptorGenerator is
component KeypointReader is
port ( addr : in std_logic_vector (31 downto 0);
enableIn : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (31 downto 0);
request : in std_logic;
rst : in std_logic;
busy : out std_logic;
kptCoordX : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's row possition
kptScale : out std_logic_vector(KPT_SCALE_BW-1 downto 0);
kptOctave : out std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
memAddr : out std_logic_vector (31 downto 0);
read_mem : out std_logic
);
end component;
--signals between KeypointReader and AddressGenerator:
---Control
signal sCtrlBusyKptAddr: std_logic;
signal sCtrlRequestKptAddr: std_logic;
---Data
signal skptCoordX: std_logic_vector (KPT_COORD_BW-1 downto 0);
signal skptCoordY: std_logic_vector (KPT_COORD_BW-1 downto 0);
signal skptScale : std_logic_vector(KPT_SCALE_BW-1 downto 0);
signal skptOctave : std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
component AddressGenerator is
port ( busy_in : in std_logic;
clk : in std_logic;
imgBaseAddr : in std_logic_vector (31 downto 0);
kptCoordX : in std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : in std_logic_vector (KPT_COORD_BW-1 downto 0); --keypoint's row possition
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
kptOctave : in std_logic_vector(KPT_OCTAVE_BW-1 downto 0);--keypoint's octave
request_in : in std_logic;
rst : in std_logic;
kptScaleOut : out std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
addr : out std_logic_vector (31 downto 0);
busy_out : out std_logic;
request_out : out std_logic
);
end component;
--signals between AddressGenerator and ImagePatchReader:
---Control
signal sCtrlBusyAddrImgRd: std_logic;
signal sCtrlRequestAddrImgRd: std_logic;
---Data
signal skptScaleOut : std_logic_vector(KPT_SCALE_BW-1 downto 0);
signal sGeneratedAddr: std_logic_vector (31 downto 0);
component ImagePatchReader is
port ( addr : in std_logic_vector (31 downto 0);
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
busy_in : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (PIXEL_BW-1 downto 0);
rst : in std_logic;
addrKernel : out std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
en_out : out std_logic;
memAddr : out std_logic_vector (31 downto 0);
patchColumn : out T_INPUT_VERTICAL_CONVOLUTION;
readMem : out std_logic;
request_out : out std_logic
);
end component;
--signals between ImagePatchReader and GaussianFilter:
---Control
signal sEnableImgRdGauss: std_logic;
---Data
signal sAddrKernel: std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
signal sPatchColumn: T_INPUT_VERTICAL_CONVOLUTION;
component GaussianFilter is
port ( ADDR : in std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
CLK : in std_logic;
ENABLEIN : in std_logic;
INPUTARRAY : in T_INPUT_VERTICAL_CONVOLUTION;
RST : in std_logic;
ENABLEOUT : out std_logic;
OUTPUTDATA : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
--signals between GaussianFilter and PointBuffer:
---Control
signal sEnableGaussOut: std_logic;
---Data
signal sPointValue: std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
component TopDescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end component;
begin
--mapping
keypoint_Reader: KeypointReader
port map( addr => KPTS_ADDR,
enableIn => ENABLE,
clk => CLK,
memData => KPT_DATA,
request => sCtrlRequestKptAddr,
rst => RST,
busy => sCtrlBusyKptAddr,
kptCoordX => skptCoordX,
kptCoordY => skptCoordY,
kptScale => skptScale,
kptOctave => skptOctave,
memAddr => KPT_ADDR_MEM,
read_mem => KPT_READ_MEM
);
address_Generator: AddressGenerator
port map( busy_in => sCtrlBusyKptAddr,
clk => CLK,
imgBaseAddr => IMG_BASE_ADDR,
kptCoordX => skptCoordX,
kptCoordY => skptCoordY,
kptScale => skptScale,
kptOctave => skptOctave,
request_in => sCtrlRequestAddrImgRd,
rst => RST,
kptScaleOut => skptScaleOut,
addr => sGeneratedAddr,
busy_out => sCtrlBusyAddrImgRd,
request_out => sCtrlRequestKptAddr
);
imagePatch_Reader: ImagePatchReader
port map( addr => sGeneratedAddr,
busy_in => sCtrlBusyAddrImgRd,
kptScale => skptScaleOut,
clk => CLK,
memData => PIXEL_DATA,
rst => RST,
addrKernel => sAddrKernel,
en_out => sEnableImgRdGauss,
memAddr => PIXEL_ADDR_MEM,
patchColumn => sPatchColumn,
readMem => PIXEL_READ_MEM,
request_out => sCtrlRequestAddrImgRd
);
gaussian_Filter: GaussianFilter
port map( ADDR => sAddrKernel,
CLK => CLK,
ENABLEIN => sEnableImgRdGauss,
INPUTARRAY => sPatchColumn,
RST => RST,
ENABLEOUT => sEnableGaussOut,
OUTPUTDATA => sPointValue
);
TopDescriptor_Maker: TopDescriptorMaker
port map(
clk => CLK,
rst => RST,
enableIn => sEnableGaussOut,
inputValue => sPointValue,
descriptor => DESCRIPTOR,
enableOut => ENABLEOUT
);
end BEHAVIORAL;
| gpl-3.0 | d8fb00f44f72c1bf75f4ba3726e9a3af | 0.576252 | 3.478802 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op332_7.vhdl | 1 | 4,589 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | f79a9a802c95e6fd5b4f66a3a992051b | 0.580519 | 3.202373 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi.vhd | 5 | 4,344 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
| gpl-3.0 | 26ce8a28f5fc492dc3dc818db2075de2 | 0.369475 | 4.414634 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom/simulation/rom_synth.vhd | 1 | 6,798 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY rom_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE rom_synth_ARCH OF rom_synth IS
COMPONENT rom_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: rom_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 6a5a28bad202f8a1d686ee40b18678fe | 0.578994 | 3.806271 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/dma_handler.vhd | 3 | 8,114 | -------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-- 2012-04-17 V0.07 zelenkaj Added forwarding of DMA read length
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
| gpl-2.0 | a0743010236a7734698b0613763871f8 | 0.609071 | 3.032138 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/synchroniser/vhdl_source/synchroniser.vhd | 5 | 5,719 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : synchroniser block
-------------------------------------------------------------------------------
-- Description: synchroniser block implementing the synchroniser described in
-- Rino Goslars paper:"Fourteen ways to fool your synchroniser"
--
-- Add a timing-ignore on all _tig signals in this module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchroniser is
generic (
g_data_width : natural := 16);
port (
tx_clock : in std_logic;
tx_reset : in std_logic;
tx_push : in std_logic;
tx_data : in std_logic_vector(g_data_width - 1 downto 0);
tx_done : out std_logic;
rx_clock : in std_logic;
rx_reset : in std_logic;
rx_new_data : out std_logic;
rx_data : out std_logic_vector(g_data_width - 1 downto 0));
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of synchroniser : entity is "no";
attribute register_balancing : string;
attribute register_balancing of synchroniser : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of synchroniser : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of synchroniser : entity is true;
end synchroniser;
architecture rtl of synchroniser is
type t_tx_fsm_state is (tx_idle, tx_req, tx_waiting);
type t_rx_fsm_state is (rx_idle, rx_ack);
signal tx_fsm_state : t_tx_fsm_state;
signal rx_fsm_state : t_rx_fsm_state;
signal ack : std_logic;
signal ack_d1_tig : std_logic;
signal ack_d2 : std_logic;
signal ack_d3 : std_logic;
signal req : std_logic;
signal req_d1_tig : std_logic;
signal req_d2 : std_logic;
signal req_d3 : std_logic;
signal tx_data_i : std_logic_vector(g_data_width - 1 downto 0);
signal rx_data_tig : std_logic_vector(g_data_width - 1 downto 0);
begin -- rtl
transmitter : process (tx_clock)
begin -- process transmitter
if tx_clock'event and tx_clock = '1' then -- rising clock edge
ack_d1_tig <= ack; -- async boundary
ack_d2 <= ack_d1_tig;
ack_d3 <= ack_d2;
tx_done <= not ack_d3 and ack_d2;
case tx_fsm_state is
when tx_idle =>
if tx_push = '1' then
tx_fsm_state <= tx_req;
req <= '1';
tx_data_i <= tx_data;
else
req <= '0';
end if;
when tx_req =>
if (ack_d2 = '1') then
tx_fsm_state <= tx_waiting;
req <= '0';
end if;
when tx_waiting =>
if ack_d2 = '0' then
tx_fsm_state <= tx_idle;
end if;
when others =>
tx_fsm_state <= tx_idle;
req <= '0';
end case;
if tx_reset = '1' then
ack_d1_tig <= '0';
ack_d2 <= '0';
ack_d3 <= '0';
tx_done <= '0';
tx_fsm_state <= tx_idle;
tx_data_i <= (others => '0');
end if;
end if;
end process transmitter;
receiver : process (rx_clock)
begin -- process receiver
if rx_clock'event and rx_clock = '1' then -- rising clock edge
req_d1_tig <= req; -- async boundary
req_d2 <= req_d1_tig;
req_d3 <= req_d2;
rx_new_data <= not req_d3 and req_d2;
case rx_fsm_state is
when rx_idle =>
if req_d2 = '1' then
rx_fsm_state <= rx_ack;
ack <= '1';
rx_data_tig <= tx_data_i; -- async boundary
else
ack <= '0';
end if;
when rx_ack =>
if req_d2 = '0' then
rx_fsm_state <= rx_idle;
ack <= '0';
end if;
when others =>
rx_fsm_state <= rx_idle;
ack <= '0';
end case;
if rx_reset = '1' then
req_d1_tig <= '0';
req_d2 <= '0';
req_d3 <= '0';
rx_new_data <= '0';
rx_data_tig <= (others => '0');
rx_fsm_state <= rx_idle;
end if;
end if;
end process receiver;
rx_data <= rx_data_tig;
end rtl;
| gpl-3.0 | 12c7a39ee1181287addab7235fc65b76 | 0.396748 | 4.389102 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/ulpi_bus.vhd | 3 | 7,397 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
| gpl-3.0 | a6e6d8f40ba69f72c56cd73687525729 | 0.446938 | 3.6856 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/mem_bus_slave_bfm.vhd | 5 | 1,640 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | a3a70835efe3887acbc03fee3bdec257 | 0.575 | 3.009174 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op952_11.vhdl | 1 | 5,526 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net5
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net6
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net7
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 03670302d3767994e25a4b35b3611130 | 0.578538 | 3.145134 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_16to32conv.vhd | 3 | 6,853 | -------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-- 2012-03-21 V0.03 zelenkaj Added endian generic
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
| gpl-2.0 | a91eea507c395c7e9528e955b9828e76 | 0.621626 | 3.483986 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/token_crc.vhd | 3 | 1,863 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc is
port (
clock : in std_logic;
sync : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc;
architecture Gideon of token_crc is
-- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0');
constant polynom : std_logic_vector(4 downto 0) := "00100";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | d01de6ab611fec4f294b4a7550b69606 | 0.401503 | 4.425178 | false | false | false | false |
KB777/1541UltimateII | target/simulation/vhdl_bfm/sram_model_8.vhd | 5 | 2,119 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | 556f891f5c88e47dc96b2b10cf30490f | 0.412459 | 4.289474 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op980_2.vhdl | 1 | 5,443 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | a112f542aa91e7877733fa51c4e95e3c | 0.573948 | 3.133564 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_sim/pll_tb.vhd | 5 | 3,453 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll_tb is
end pll_tb;
architecture tb of pll_tb is
signal clock : std_logic := '0';
signal sync_in : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal pll_clock : std_logic := '0';
signal pll_period : time := 41 ns;
signal n : unsigned(11 downto 0) := to_unsigned(1600-1, 12);
signal up, down : std_logic;
signal analog : std_logic := 'Z';
signal pixels_per_line : integer := 0;
begin
clock <= not clock after 10 ns;
pll_clock <= not pll_clock after (pll_period/2);
p_sync: process
begin
for i in 1 to 50 loop
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 59.3 us;
end loop;
sync_in <= '0'; wait for 4.7 us;
sync_in <= '1'; wait for 27.3 us;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 29.65 us;
sync_in <= '1'; wait for 2.35 us;
end loop;
for i in 1 to 5 loop
sync_in <= '0'; wait for 2.35 us;
sync_in <= '1'; wait for 29.65 us;
end loop;
end process;
i_sep: entity work.sync_separator
port map (
clock => clock,
sync_in => sync_in,
h_sync => h_sync,
v_sync => v_sync );
i_phase: entity work.phase_detector
port map (
n => n,
pll_clock => pll_clock,
h_sync => h_sync,
up => up,
down => down,
analog => analog );
process(pll_clock, h_sync)
variable pixel_count : integer;
begin
if rising_edge(pll_clock) then
pixel_count := pixel_count + 1;
end if;
if rising_edge(h_sync) then
pixels_per_line <= pixel_count;
pixel_count := 0;
end if;
end process;
-- process(analog)
-- variable last : std_logic := 'U';
-- variable duration : time;
-- variable last_time : time;
-- begin
-- if analog'event then
-- duration := now - last_time;
-- case last is
-- when '1' =>
-- report "Up for " & time'image(duration);
-- pll_period <= pll_period - (duration / 5000000);
-- when '0' =>
-- report "Down for " & time'image(duration);
-- pll_period <= pll_period + (duration / 5000000);
-- when others =>
-- null;
-- end case;
--
-- last := analog;
-- last_time := now;
-- end if;
-- end process;
process(clock)
begin
if rising_edge(clock) then
case analog is
when '1' =>
pll_period <= pll_period - 10 fs;
when '0' =>
pll_period <= pll_period + 10 fs;
when others =>
--pll_period <= pll_period + 1 fs;
null;
end case;
end if;
end process;
end tb;
| gpl-3.0 | 692c63024a1b0ce9d54bf436ad8a0dd4 | 0.437301 | 3.724919 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/itu/vhdl_source/itu_pkg.vhd | 3 | 1,270 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package itu_pkg is
constant c_itu_irq_global : unsigned(3 downto 0) := X"0";
constant c_itu_irq_enable : unsigned(3 downto 0) := X"1";
constant c_itu_irq_disable : unsigned(3 downto 0) := X"2";
constant c_itu_irq_edge : unsigned(3 downto 0) := X"3";
constant c_itu_irq_clear : unsigned(3 downto 0) := X"4";
constant c_itu_irq_active : unsigned(3 downto 0) := X"5";
constant c_itu_timer : unsigned(3 downto 0) := X"6";
constant c_itu_irq_timer_en : unsigned(3 downto 0) := X"7";
constant c_itu_irq_timer_hi : unsigned(3 downto 0) := X"8"; -- big endian word
constant c_itu_irq_timer_lo : unsigned(3 downto 0) := X"9";
constant c_itu_fpga_version : unsigned(3 downto 0) := X"B";
constant c_itu_capabilities0 : unsigned(3 downto 0) := X"C";
constant c_itu_capabilities1 : unsigned(3 downto 0) := X"D";
constant c_itu_capabilities2 : unsigned(3 downto 0) := X"E";
constant c_itu_capabilities3 : unsigned(3 downto 0) := X"F";
-- second block
constant c_itu_ms_timer_hi : unsigned(3 downto 0) := X"2";
constant c_itu_ms_timer_lo : unsigned(3 downto 0) := X"3";
end package;
| gpl-3.0 | c8b984cb9fa600205857ca78139ec008 | 0.614173 | 2.981221 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5_sdr.vhd | 5 | 14,469 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_sdr is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
req : in t_mem_burst_req;
resp : out t_mem_burst_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5_sdr;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5_sdr is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002A", "000" ), -- mode register, burstlen=4, writelen=4, CAS lat = 2, interleaved
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sdram_d_t : std_logic_vector(3 downto 0) := "0000";
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal cs_n_i : std_logic;
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(3 downto 0) := "0000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal addr_row : std_logic_vector(12 downto 0);
signal addr_column : std_logic_vector(9 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of rdata : signal is "true"; -- the general memctrl/rdata must be packed in IOB
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic;
signal push_cmd : std_logic;
begin
addr_bank <= address_fifo(3 downto 2);
addr_row <= address_fifo(24 downto 12);
addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
-- addr_row <= address_fifo(24 downto 12);
-- addr_bank <= address_fifo(11 downto 10);
-- addr_column <= address_fifo(9 downto 0);
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av;
resp.ready <= not cmd_af;
push_cmd <= req.request and not cmd_af;
-- resp.rack <= rack;
-- resp.dack <= dack(0);
-- resp.dnext <= dnext(0);
-- resp.blast <= (dack(0) and not dack(1)) or (dnext(0) and not dnext(1));
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(cmd_fifo_data_out'high);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_read_fifo: entity work.srl_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => dack(0),
FlushFifo => '0',
DataIn => rdata,
DataOut => resp.data,
SpaceInFifo => open,
AlmostFull => rdata_af,
DataInFifo => resp.rdata_av );
i_write_fifo: entity work.SRL_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => dnext(0),
PutElement => req.data_push,
FlushFifo => '0',
DataIn => req.data,
DataOut => wdata,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => open );
process(clock)
procedure send_refresh_cmd is
begin
if refr_delay = 0 then
do_refresh <= '0';
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
last_bank <= addr_bank;
mem_a_i(12 downto 0) <= addr_row;
mem_a_i(14 downto 13) <= addr_bank;
col_addr <= addr_column;
cs_n_i <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
if rwn_fifo='0' then
dnext <= "1111";
delay <= 0;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
cs_n_i <= '1';
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
sdram_d_o <= wdata;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
sdram_d_t <= '0' & sdram_d_t(3 downto 1);
dack <= '0' & dack(3 downto 1);
dnext <= '0' & dnext(3 downto 1);
rdata <= MEM_D;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
cs_n_i <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and next_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
-- we always perform auto precharge.
-- If the next access is to ANOTHER bank, then
-- we do not have to wait AFTER issuing this CAS.
-- the delay after the CAS, causes the next RAS to
-- be further away in time. If there is NO access
-- pending, then we assume the same bank, and introduce
-- the delay.
refr_delay <= 5;
if (req_i='1' and addr_bank=last_bank) or req_i='0' then
next_delay <= 5;
else
next_delay <= 2;
end if;
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
if rwn_i='0' then
if delay=0 then
-- write with auto precharge
sdram_d_t <= "1111";
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
delay <= 2;
state <= sd_wait;
end if;
else
if delay = 0 then
if rdata_af='0' then
-- read with auto precharge
cs_n_i <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
delay <= 2;
state <= sd_wait;
end if;
end if;
end if;
when sd_wait =>
if delay=1 then
state <= idle;
end if;
if delay=1 and rwn_i='1' then
dack <= "1111";
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sdram_d_t <= (others => '0');
delay <= 0;
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
process(state, do_refresh, inhibit, inhibit_d, req_i, next_delay)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
null;
elsif inhibit='0' then
if req_i='1' and next_delay = 0 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
MEM_D <= sdram_d_o after 7 ns when sdram_d_t(0)='1' else (others => 'Z') after 7 ns;
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
SDRAM_CSn <= cs_n_i;
end Gideon;
| gpl-3.0 | ecd2c799431648d9787c5c75cd5fb8bb | 0.441081 | 3.921138 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op958_8.vhdl | 1 | 5,686 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net6
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net6,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net7
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d4cb30ed460425e0269f412524faa8d3 | 0.575097 | 3.103712 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_sim/tb_oscillator.vhd | 5 | 3,080 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_oscillator is
end tb_oscillator;
architecture TB of tb_oscillator is
constant num_voices : integer := 8;
signal clk : std_logic := '0';
signal reset : std_logic;
signal freq : std_logic_vector(15 downto 0);
signal osc_val : std_logic_vector(23 downto 0);
signal voice_i : std_logic_vector(3 downto 0);
signal voice_o : std_logic_vector(3 downto 0);
signal voice_m : std_logic_vector(3 downto 0);
signal carry_20 : std_logic;
signal wave_out : std_logic_vector(7 downto 0);
signal wave_sel : std_logic_vector(3 downto 0);
type freq_array_t is array(natural range <>) of std_logic_vector(15 downto 0);
constant freq_array : freq_array_t(0 to 15) := ( X"A001", X"B003", X"B805", X"C000",
X"E00B", X"F00D", X"7011", X"FFFF",
X"0017", X"001D", X"0100", X"0200",
X"0400", X"0800", X"1000", X"2000" );
type sel_array_t is array(natural range <>) of std_logic_vector(3 downto 0);
constant sel_array : sel_array_t(0 to 15) := ( X"1", X"2", X"4", X"8", X"3", X"6", X"C", X"8",
X"9", X"7", X"E", X"D", X"B", X"5", X"A", X"F" );
type wave_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
signal wave_mem : wave_array_t (0 to num_voices-1) := (others => (others => '0'));
begin
clk <= not clk after 15 ns;
reset <= '1', '0' after 600 ns;
osc: entity work.oscillator
generic map (num_voices)
port map (
clk => clk,
reset => reset,
freq => freq,
voice_i => voice_i,
voice_o => voice_o,
osc_val => osc_val,
carry_20 => carry_20 );
process(clk)
begin
if rising_edge(clk) then
if reset='1' then
voice_i <= X"0";
elsif voice_i = num_voices-1 then
voice_i <= X"0";
else
voice_i <= voice_i + 1;
end if;
end if;
end process;
wmap: entity work.wave_map
generic map (
num_voices => 8, -- 8 or 16, clock should then be 8 or 16 MHz, too!
sample_bits=> 8 )
port map (
clk => clk,
reset => reset,
osc_val => osc_val,
carry_20 => carry_20,
voice_i => voice_o,
wave_sel => wave_sel,
sq_width => X"27D",
voice_o => voice_m,
wave_out => wave_out );
freq <= freq_array(conv_integer(voice_i));
wave_sel <= sel_array(conv_integer(voice_o));
process(clk)
begin
if rising_edge(clk) then
wave_mem(conv_integer(voice_m)) <= wave_out;
end if;
end process;
end TB;
| gpl-3.0 | d2566c094f01590318f501580fbbc48b | 0.48539 | 3.4375 | false | false | false | false |
chrismasters/fpga-notes | vga_test/ipcore_dir/vga_clk/example_design/vga_clk_exdes.vhd | 1 | 5,394 | -- file: vga_clk_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity vga_clk_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end vga_clk_exdes;
architecture xilinx of vga_clk_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component vga_clk is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : vga_clk
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| mit | 33e3488c46b247fbdb6132af78ad1252 | 0.616426 | 4.052592 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/clock/vhdl_sim/real_time_clock_tb.vhd | 5 | 735 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock_tb is
end;
architecture tb of real_time_clock_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : t_io_req := c_io_req_init;
signal resp : t_io_resp := c_io_resp_init;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_dut: entity work.real_time_clock
generic map (
g_freq => 100 )
port map (
clock => clock,
reset => reset,
req => req,
resp => resp );
end;
| gpl-3.0 | d4468ddc9e55ad5a6f7f7fce4f93efa4 | 0.49932 | 3.356164 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/tb_TopDescriptorMaker.vhd | 1 | 4,329 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:53:14 05/24/2014
-- Design Name:
-- Module Name: /media/DATA42/Dropbox/EmbeddedRetina/embeddedretina_ise/tb_DescriptorMaker.vhd
-- Project Name: EmbeddedRetina_ISE
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TopDescriptorMaker
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_TopDescriptorMaker IS
END tb_TopDescriptorMaker;
ARCHITECTURE behavior OF tb_TopDescriptorMaker IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopDescriptorMaker
PORT(
clk : IN std_logic;
rst : IN std_logic;
enableIn : IN std_logic;
inputValue : IN std_logic_vector(13 downto 0);
descriptor : OUT std_logic_vector(511 downto 0);
enableOut : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enableIn : std_logic := '0';
signal inputValue : std_logic_vector(13 downto 0) := (others => '0');
--Outputs
signal descriptor : std_logic_vector(511 downto 0);
signal enableOut : std_logic;
signal validOutputs: integer range 0 to 2 := 0;
signal end_simulation: std_logic := '0';
signal end_aux: std_logic := '0';
-- Clock period definitions
signal counter: integer range 0 to 86 := 0;
type T_INPUT_DATA is array (0 to 85) of integer range 0 to 16383;
constant clk_period : time := 10 ns;
constant inputdata: T_INPUT_DATA :=
(
1,10,2,20,3,30,4,40,5,50,6,60,7,70,8,80,9,90,10,100,11,110,12,120,13,130,14,140,15,150,16,160,
17,170,18,180,19,190,20,200,21,210,22,220,23,230,24,240,25,250,26,260,27,270,28,280,29,290,30,300,
31,310,32,320,33,330,34,340,35,350,36,360,37,370,38,380,39,390,40,400,41,410,42,420,43,430
);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TopDescriptorMaker PORT MAP (
clk => clk,
rst => rst,
enableIn => enableIn,
inputValue => inputValue,
descriptor => descriptor,
enableOut => enableOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
-- wait for clk_period*100;
-- insert stimulus here
wait;
end process;
--simulate the GaussianFilter output
stim_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= 0;
validOutputs <=0;
enableIn <= '0';
elsif end_aux = '0' then
if counter = 86 then
counter <= 0;
enableIn <= '0';
-- end_aux <= '1';
else
enableIn <= '1';
inputValue <= std_logic_vector(to_unsigned(inputdata(counter),inputValue'length));
counter <= counter +1;
end if;
end if;
if enableOut = '1' then
validOutputs <= validOutputs+1;
end if;
if validOutputs = 2 then
end_simulation <= '1';
end if;
if end_simulation = '1' then
assert false report "SUCCESSFUL: Simulation End." severity failure;
end if;
end if;
end process;
END;
| gpl-3.0 | d2b3808f1dafe2f8edb5a4f93280029c | 0.56803 | 3.767624 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_400a.vhd | 4 | 9,821 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_400a is
generic (
g_version : unsigned(7 downto 0) := X"F3" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_400a;
architecture structural of ultimate_1541_400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_fpga_type => 1,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => false,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | ec1b5fe97a5bb7e24f9f790295446694 | 0.477039 | 3.373755 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_13sk1_0.vhdl | 1 | 6,652 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.95e-06,
W => Wdiff_0,
Wdiff_0init => 5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.95e-06,
W => Wdiff_0,
Wdiff_0init => 5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => W_0,
W_0init => 1.5e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.35e-06,
W => Wcm_2,
Wcm_2init => 6.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.35e-06,
W => Wcmout_2,
Wcmout_2init => 7.985e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.35e-06,
W => Wcm_2,
Wcm_2init => 6.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.35e-06,
W => Wcmout_2,
Wcmout_2init => 7.985e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 5.135e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.1e-06,
W => Wcm_1,
Wcm_1init => 1.75e-06,
scope => private
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.1e-06,
W => Wcmout_1,
Wcmout_1init => 3.54e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 5.135e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => (pfak)*(WBias),
WBiasinit => 1.6e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.75e-06,
W => (pfak)*(WBias),
WBiasinit => 1.6e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.75e-06,
W => WBias,
WBiasinit => 1.6e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => WBias,
WBiasinit => 1.6e-05
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => WBias,
WBiasinit => 1.6e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.75e-06,
W => WBias,
WBiasinit => 1.6e-05
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 78ab8fef00ef820ae00c845629a1a59d | 0.583283 | 2.921388 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_logic.vhd | 1 | 33,467 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_logic is
generic (
g_version : unsigned(7 downto 0) := X"FF";
g_simulation : boolean := true;
g_clock_freq : natural := 50_000_000;
g_baud_rate : natural := 115_200;
g_timer_rate : natural := 200_000;
g_fpga_type : natural := 0;
g_boot_rom : boolean := false;
g_video_overlay : boolean := false;
g_icap : boolean := false;
g_uart : boolean := false;
g_drive_1541 : boolean := false;
g_drive_1541_2 : boolean := false;
g_hardware_gcr : boolean := false;
g_cartridge : boolean := false;
g_command_intf : boolean := false;
g_stereo_sid : boolean := false;
g_ram_expansion : boolean := false;
g_extended_reu : boolean := false;
g_hardware_iec : boolean := false;
g_iec_prog_tim : boolean := false;
g_c2n_streamer : boolean := false;
g_c2n_recorder : boolean := false;
g_drive_sound : boolean := false;
g_rtc_chip : boolean := false;
g_rtc_timer : boolean := false;
g_usb_host : boolean := false;
g_spi_flash : boolean := false;
g_vic_copper : boolean := false;
g_sampler : boolean := false;
g_analyzer : boolean := false );
port (
-- globals
sys_clock : in std_logic;
sys_reset : in std_logic;
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic := '1';
BUFFER_ENn : out std_logic := '1';
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
mem_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
-- actual levels of the pins --
iec_reset_i : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
iec_clock_i : in std_logic;
iec_srq_i : in std_logic;
iec_reset_o : out std_logic := '1';
iec_atn_o : out std_logic;
iec_data_o : out std_logic;
iec_clock_o : out std_logic;
iec_srq_o : out std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1) := "ZZ";
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Interface to other graphical output (Full HD of course and in 3D!) ;-)
vid_clock : in std_logic := '0';
vid_reset : in std_logic := '0';
vid_h_count : in unsigned(11 downto 0) := (others => '0');
vid_v_count : in unsigned(11 downto 0) := (others => '0');
vid_active : out std_logic;
vid_opaque : out std_logic;
vid_data : out unsigned(3 downto 0);
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
-- Buttons
button : in std_logic_vector(2 downto 0);
-- Simulation port
sim_io_req : in t_io_req := c_io_req_init;
sim_io_resp : out t_io_resp );
end ultimate_logic;
architecture logic of ultimate_logic is
function to_std(b : boolean) return std_logic is
begin
if b then
return '1';
end if;
return '0';
end function;
impure function create_capabilities return std_logic_vector is
variable cap : std_logic_vector(31 downto 0) := (others => '0');
begin
cap(00) := to_std(g_uart);
cap(01) := to_std(g_drive_1541);
cap(02) := to_std(g_drive_1541_2);
cap(03) := to_std(g_drive_sound);
cap(04) := to_std(g_hardware_gcr);
cap(05) := to_std(g_hardware_iec);
cap(06) := to_std(g_iec_prog_tim);
cap(07) := to_std(g_c2n_streamer);
cap(08) := to_std(g_c2n_recorder);
cap(09) := to_std(g_cartridge);
cap(10) := to_std(g_ram_expansion);
cap(11) := to_std(g_usb_host);
cap(12) := to_std(g_rtc_chip);
cap(13) := to_std(g_rtc_timer);
cap(14) := to_std(g_spi_flash);
cap(15) := to_std(g_icap);
cap(16) := to_std(g_extended_reu);
cap(17) := to_std(g_stereo_sid);
cap(18) := to_std(g_command_intf);
cap(19) := to_std(g_vic_copper);
cap(20) := to_std(g_video_overlay);
cap(21) := to_std(g_sampler);
cap(22) := to_std(g_analyzer);
cap(29 downto 28) := std_logic_vector(to_unsigned(g_fpga_type, 2));
cap(30) := to_std(g_boot_rom);
cap(31) := to_std(g_simulation);
return cap;
end function;
constant c_capabilities : std_logic_vector(31 downto 0) := create_capabilities;
constant c_tag_1541_cpu_1 : std_logic_vector(7 downto 0) := X"01";
constant c_tag_1541_floppy_1 : std_logic_vector(7 downto 0) := X"02";
constant c_tag_1541_audio_1 : std_logic_vector(7 downto 0) := X"03";
constant c_tag_1541_cpu_2 : std_logic_vector(7 downto 0) := X"04";
constant c_tag_1541_floppy_2 : std_logic_vector(7 downto 0) := X"05";
constant c_tag_1541_audio_2 : std_logic_vector(7 downto 0) := X"06";
constant c_tag_cpu : std_logic_vector(7 downto 0) := X"07";
constant c_tag_slot : std_logic_vector(7 downto 0) := X"08";
constant c_tag_reu : std_logic_vector(7 downto 0) := X"09";
-- Memory interface
signal mem_req_cpu : t_mem_req := c_mem_req_init;
signal mem_resp_cpu : t_mem_resp := c_mem_resp_init;
signal mem_req_1541 : t_mem_req := c_mem_req_init;
signal mem_resp_1541 : t_mem_resp := c_mem_resp_init;
signal mem_req_1541_2 : t_mem_req := c_mem_req_init;
signal mem_resp_1541_2 : t_mem_resp := c_mem_resp_init;
signal mem_req_cart : t_mem_req := c_mem_req_init;
signal mem_resp_cart : t_mem_resp := c_mem_resp_init;
signal mem_req_debug : t_mem_req := c_mem_req_init;
signal mem_resp_debug : t_mem_resp := c_mem_resp_init;
-- IO Bus
signal cpu_io_req : t_io_req;
signal cpu_io_resp : t_io_resp := c_io_resp_init;
signal io_req : t_io_req;
signal io_resp : t_io_resp := c_io_resp_init;
signal io_req_1541 : t_io_req;
signal io_resp_1541 : t_io_resp := c_io_resp_init;
signal io_req_1541_1 : t_io_req;
signal io_resp_1541_1 : t_io_resp := c_io_resp_init;
signal io_req_1541_2 : t_io_req;
signal io_resp_1541_2 : t_io_resp := c_io_resp_init;
signal io_req_itu : t_io_req;
signal io_resp_itu : t_io_resp := c_io_resp_init;
signal io_req_cart : t_io_req;
signal io_resp_cart : t_io_resp := c_io_resp_init;
signal io_req_io : t_io_req;
signal io_resp_io : t_io_resp := c_io_resp_init;
signal io_req_big_io : t_io_req;
signal io_resp_big_io : t_io_resp := c_io_resp_init;
signal io_req_sd : t_io_req;
signal io_resp_sd : t_io_resp := c_io_resp_init;
signal io_req_rtc : t_io_req;
signal io_resp_rtc : t_io_resp := c_io_resp_init;
signal io_req_rtc_tmr : t_io_req;
signal io_resp_rtc_tmr : t_io_resp := c_io_resp_init;
signal io_req_gcr_dec : t_io_req;
signal io_resp_gcr_dec : t_io_resp := c_io_resp_init;
signal io_req_flash : t_io_req;
signal io_resp_flash : t_io_resp := c_io_resp_init;
signal io_req_iec : t_io_req;
signal io_resp_iec : t_io_resp := c_io_resp_init;
signal io_req_usb : t_io_req;
signal io_resp_usb : t_io_resp := c_io_resp_init;
signal io_req_c2n : t_io_req;
signal io_resp_c2n : t_io_resp := c_io_resp_init;
signal io_req_c2n_rec : t_io_req;
signal io_resp_c2n_rec : t_io_resp := c_io_resp_init;
signal io_req_icap : t_io_req;
signal io_resp_icap : t_io_resp := c_io_resp_init;
signal io_req_aud_sel : t_io_req;
signal io_resp_aud_sel : t_io_resp := c_io_resp_init;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp := c_io_resp_init;
-- Audio routing
signal pwm : std_logic;
signal pwm_2 : std_logic := '0';
signal drive_sample : signed(12 downto 0);
signal drive_sample_2 : signed(12 downto 0);
-- IEC signal routing
signal atn_o, atn_i : std_logic := '1';
signal clk_o, clk_i : std_logic := '1';
signal data_o, data_i : std_logic := '1';
signal srq_i : std_logic := '1';
signal atn_o_2 : std_logic := '1';
signal clk_o_2 : std_logic := '1';
signal data_o_2 : std_logic := '1';
signal hw_atn_o : std_logic := '1';
signal hw_clk_o : std_logic := '1';
signal hw_data_o : std_logic := '1';
signal hw_srq_o : std_logic := '1';
-- miscellaneous interconnect
signal irq_i : std_logic := '0';
signal c64_irq_n : std_logic;
signal c64_irq : std_logic;
signal phi2_tick : std_logic;
signal c64_stopped : std_logic;
signal c2n_sense : std_logic := '0';
signal c2n_sense_in : std_logic := '0';
signal c2n_out_r : std_logic := '1';
signal c2n_out_w : std_logic := '1';
signal sd_busy : std_logic;
signal usb_busy : std_logic;
signal sd_act_stretched : std_logic;
signal error : std_logic;
signal act_led_n : std_logic := '1';
signal motor_led_n : std_logic := '1';
signal cart_led_n : std_logic := '1';
signal c2n_pull_sense : std_logic := '0';
signal freezer_state : std_logic_vector(1 downto 0);
signal dirty_led_1_n : std_logic := '1';
signal dirty_led_2_n : std_logic := '1';
signal sid_pwm_left : std_logic;
signal sid_pwm_right : std_logic;
signal samp_pwm_left : std_logic;
signal samp_pwm_right : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
begin
i_cpu: entity work.cpu_wrapper_zpu
generic map (
g_mem_tag => c_tag_cpu,
g_internal_prg => true,
g_boot_rom => g_boot_rom,
g_simulation => g_simulation )
port map (
clock => sys_clock,
reset => sys_reset,
break_o => open,
error => error,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
io_req => cpu_io_req,
io_resp => cpu_io_resp );
i_io_arb: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => sim_io_req,
reqs(1) => cpu_io_req,
resps(0) => sim_io_resp,
resps(1) => cpu_io_resp,
req => io_req,
resp => io_resp );
i_itu: entity work.itu
generic map (
g_version => g_version,
g_capabilities => c_capabilities,
g_uart => g_uart,
g_frequency => g_clock_freq,
g_edge_init => "00000001",
g_edge_write => false,
g_baudrate => g_baud_rate,
g_timer_rate => g_timer_rate)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_itu,
io_resp => io_resp_itu,
irq_in(7) => button(2),
irq_in(6) => button(1),
irq_in(5) => button(0),
irq_in(4) => c64_irq,
irq_in(3) => '0',
irq_in(2) => '0',
uart_txd => UART_TXD,
uart_rxd => UART_RXD );
r_drive: if g_drive_1541 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
-- master port on memory bus
mem_req => mem_req_1541,
mem_resp => mem_resp_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => act_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample,
dac_out => pwm );
end generate;
end generate;
r_drive_2: if g_drive_1541_2 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
-- master port on memory bus
mem_req => mem_req_1541_2,
mem_resp => mem_resp_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => open, --DISK_ACTn,
motor_led_n => open, --MOTOR_LEDn,
dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample_2'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample_2,
dac_out => pwm_2 );
end generate;
end generate;
r_cart: if g_cartridge generate
i_slot_srv: entity work.slot_server_v4
generic map (
g_tag_slot => c_tag_slot,
g_tag_reu => c_tag_reu,
g_ram_base_reu => X"1000000", -- should be on 16M boundary, or should be limited in size
g_rom_base_cart => X"0F00000", -- should be on a 1M boundary
g_ram_base_cart => X"0EF0000", -- should be on a 64K boundary
g_control_read => true,
g_ram_expansion => g_ram_expansion,
g_extended_reu => g_extended_reu,
g_command_intf => g_command_intf,
g_sampler => g_sampler,
g_implement_sid => g_stereo_sid,
g_sid_voices => 16,
g_vic_copper => g_vic_copper )
port map (
clock => sys_clock,
reset => sys_reset,
-- Cartridge pins
RSTn => RSTn,
IRQn => IRQn,
NMIn => NMIn,
PHI2 => PHI2,
IO1n => IO1n,
IO2n => IO2n,
DMAn => DMAn,
BA => BA,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
ADDRESS => SLOT_ADDR,
DATA => SLOT_DATA,
-- other hardware pins
BUFFER_ENn => BUFFER_ENn,
buttons => BUTTON,
cart_led_n => cart_led_n,
-- audio
sid_pwm_left => sid_pwm_left,
sid_pwm_right => sid_pwm_right,
samp_pwm_left => samp_pwm_left,
samp_pwm_right => samp_pwm_right,
-- debug
freezer_state => freezer_state,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
-- timing output
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
-- master on memory bus
memctrl_inhibit => mem_inhibit,
mem_req => mem_req_cart,
mem_resp => mem_resp_cart,
-- slave on io bus
io_req => io_req_cart,
io_resp => io_resp_cart );
end generate;
i_split1: entity work.io_bus_splitter
generic map (
g_range_lo => 17,
g_range_hi => 19,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_itu, -- 4000000 ( 16 ... 400000F)
reqs(1) => io_req_1541, -- 4020000 ( 8K... 4021FFF) & 4024000 for drive B
reqs(2) => io_req_cart, -- 4040000 (128K... 405FFFF)
reqs(3) => io_req_io, -- 4060000 ( 2K... 4060FFF)
reqs(4) => io_req_usb, -- 4080000 ( 8K... 4081FFF)
reqs(5) => io_req_c2n, -- 40A0000 ( 4K... 40A0FFF)
reqs(6) => io_req_c2n_rec, -- 40C0000 ( 4K... 40C0FFF)
reqs(7) => io_req_big_io, -- 40E0000 (128K... 40FFFFF)
resps(0) => io_resp_itu,
resps(1) => io_resp_1541,
resps(2) => io_resp_cart,
resps(3) => io_resp_io,
resps(4) => io_resp_usb,
resps(5) => io_resp_c2n,
resps(6) => io_resp_c2n_rec,
resps(7) => io_resp_big_io );
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 14,
g_range_hi => 15,
g_ports => 3 )
port map (
clock => sys_clock,
req => io_req_1541,
resp => io_resp_1541,
reqs(0) => io_req_1541_1, -- 4020000
reqs(1) => io_req_1541_2, -- 4024000
reqs(2) => io_req_iec, -- 4028000
resps(0) => io_resp_1541_1,
resps(1) => io_resp_1541_2,
resps(2) => io_resp_iec );
i_split3: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 11,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req_io,
resp => io_resp_io,
reqs(0) => io_req_sd, -- 4060000
reqs(1) => io_req_rtc, -- 4060100
reqs(2) => io_req_flash, -- 4060200
reqs(3) => io_req_debug, -- 4060300
reqs(4) => io_req_rtc_tmr, -- 4060400
reqs(5) => io_req_gcr_dec, -- 4060500
reqs(6) => io_req_icap, -- 4060600
reqs(7) => io_req_aud_sel, -- 4060700
resps(0) => io_resp_sd,
resps(1) => io_resp_rtc,
resps(2) => io_resp_flash,
resps(3) => io_resp_debug,
resps(4) => io_resp_rtc_tmr,
resps(5) => io_resp_gcr_dec,
resps(6) => io_resp_icap,
resps(7) => io_resp_aud_sel );
r_usb: if g_usb_host generate
i_usb: entity work.usb1_host_io
generic map (
g_simulation => g_simulation )
port map (
ulpi_clock => ULPI_CLOCK,
ulpi_reset => ulpi_reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
usb_busy => usb_busy, -- LED interface
-- register interface bus
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb );
end generate;
i_sd: entity work.spi_peripheral_io
generic map (
g_fixed_rate => false,
g_init_rate => 500,
g_crc => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_sd,
io_resp => io_resp_sd,
busy => sd_busy,
SD_DETECTn => SD_CARDDETn,
SD_WRPROTn => '1', --SD_WRPROTn,
SPI_SSn => SD_SSn,
SPI_CLK => SD_CLK,
SPI_MOSI => SD_MOSI,
SPI_MISO => SD_MISO );
i_stretch: entity work.pulse_stretch
generic map ( g_clock_freq / 200) -- 5 ms
port map (
clock => sys_clock,
reset => sys_reset,
pulse_in => sd_busy,
pulse_out => sd_act_stretched );
r_spi_flash: if g_spi_flash generate
i_spi_flash: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 0,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_flash,
io_resp => io_resp_flash,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => FLASH_CSn,
SPI_CLK => FLASH_SCK,
SPI_MOSI => FLASH_MOSI,
SPI_MISO => FLASH_MISO );
end generate;
r_no_spi_flash: if not g_spi_flash generate
i_flash_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_flash,
io_resp => io_resp_flash );
end generate;
r_rtc: if g_rtc_chip generate
signal spi_ss_n : std_logic;
begin
i_spi_rtc: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 31,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rtc,
io_resp => io_resp_rtc,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => spi_ss_n,
SPI_CLK => RTC_SCK,
SPI_MOSI => RTC_MOSI,
SPI_MISO => RTC_MISO );
RTC_CS <= not spi_ss_n;
end generate;
r_no_rtc: if not g_rtc_chip generate
i_rtc_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc,
io_resp => io_resp_rtc );
end generate;
r_rtc_timer: if g_rtc_timer generate
i_rtc_timer: entity work.real_time_clock
generic map (
g_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_rtc_tmr,
resp => io_resp_rtc_tmr );
end generate;
r_no_rtc_timer: if not g_rtc_chip generate
i_rtc_timer_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc_tmr,
io_resp => io_resp_rtc_tmr );
end generate;
r_gcr_codec: if g_hardware_gcr generate
i_gcr_codec: entity work.gcr_codec
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_gcr_dec,
resp => io_resp_gcr_dec );
end generate;
r_iec: if g_hardware_iec generate
i_iec: entity work.iec_processor_io
port map (
clock => sys_clock,
reset => sys_reset,
atn_i => atn_i,
atn_o => hw_atn_o,
clk_i => clk_i,
clk_o => hw_clk_o,
data_i => data_i,
data_o => hw_data_o,
req => io_req_iec,
resp => io_resp_iec );
end generate;
r_c2n: if g_c2n_streamer generate
i_c2n: entity work.c2n_playback_io
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n,
resp => io_resp_c2n,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
c2n_sense => c2n_sense,
c2n_motor => CAS_MOTOR,
c2n_out_r => c2n_out_r,
c2n_out_w => c2n_out_w );
end generate;
r_c2n_rec: if g_c2n_recorder generate
i_c2n: entity work.c2n_record
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n_rec,
resp => io_resp_c2n_rec,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
pull_sense => c2n_pull_sense,
c2n_sense => c2n_sense_in,
c2n_motor => CAS_MOTOR,
c2n_write => CAS_WRITE,
c2n_read => CAS_READ );
end generate;
r_icap: if g_icap generate
i_icap: entity work.icap
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_icap,
io_resp => io_resp_icap );
end generate;
r_overlay: if g_video_overlay generate
i_overlay: entity work.char_generator_peripheral
generic map (
g_screen_size => 11,
g_color_ram => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_big_io, -- to be split later
io_resp => io_resp_big_io,
keyb_col => keyb_col,
keyb_row => keyb_row,
overlay_on => overlay_on,
pix_clock => vid_clock,
pix_reset => vid_reset,
h_count => vid_h_count,
v_count => vid_v_count,
pixel_active => vid_active,
pixel_opaque => vid_opaque,
pixel_data => vid_data );
end generate;
CAS_SENSE <= '0' when (c2n_sense='1') or (c2n_pull_sense='1') else 'Z';
CAS_READ <= '0' when c2n_out_r='0' else 'Z';
CAS_WRITE <= '0' when c2n_out_w='0' else 'Z';
-- CAS_READ <= trigger_1;
-- CAS_WRITE <= trigger_2;
c2n_sense_in <= '1' when CAS_SENSE='0' else '0';
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 5,
g_registered => false )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_cart,
reqs(1) => mem_req_1541,
reqs(2) => mem_req_1541_2,
reqs(3) => mem_req_debug,
reqs(4) => mem_req_cpu,
resps(0) => mem_resp_cart,
resps(1) => mem_resp_1541,
resps(2) => mem_resp_1541_2,
resps(3) => mem_resp_debug,
resps(4) => mem_resp_cpu,
req => mem_req,
resp => mem_resp );
i_aud_select: entity work.audio_select
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_aud_sel,
resp => io_resp_aud_sel,
drive0 => pwm,
drive1 => pwm_2,
cas_read => CAS_READ,
cas_write => CAS_WRITE,
sid_left => sid_pwm_left,
sid_right => sid_pwm_right,
samp_left => samp_pwm_left,
samp_right => samp_pwm_right,
pwm_out => PWM_OUT );
iec_atn_o <= '0' when atn_o='0' or atn_o_2='0' or hw_atn_o='0' else '1';
iec_clock_o <= '0' when clk_o='0' or clk_o_2='0' or hw_clk_o='0' else '1';
iec_data_o <= '0' when data_o='0' or data_o_2='0' or hw_data_o='0' else '1';
iec_srq_o <= hw_srq_o; -- only source
DISK_ACTn <= act_led_n xor error;
MOTOR_LEDn <= motor_led_n xor error;
CART_LEDn <= cart_led_n xor error;
SDACT_LEDn <= (dirty_led_1_n and dirty_led_2_n and not (sd_act_stretched or usb_busy)) xor error;
-- DISK_ACTn <= not freezer_state(1);
-- MOTOR_LEDn <= not freezer_state(0);
-- CART_LEDn <= IRQn;
-- SDACT_LEDn <= NMIn;
filt1: entity work.spike_filter generic map (10) port map(sys_clock, iec_atn_i, atn_i);
filt2: entity work.spike_filter generic map (10) port map(sys_clock, iec_clock_i, clk_i);
filt3: entity work.spike_filter generic map (10) port map(sys_clock, iec_data_i, data_i);
filt4: entity work.spike_filter generic map (10) port map(sys_clock, iec_srq_i, srq_i);
filt5: entity work.spike_filter port map(sys_clock, IRQn, c64_irq_n);
c64_irq <= not c64_irq_n;
-- dummy
SD_DATA <= "ZZ";
g_ela: if g_analyzer generate
signal ev_data : std_logic_vector(15 downto 0);
begin
i_ela: entity work.logic_analyzer
generic map (
g_timer_div => 50,
g_change_width => 16,
g_data_length => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
ev_dav => '0',
ev_data => ev_data,
---
mem_req => mem_req_debug,
mem_resp => mem_resp_debug,
io_req => io_req_debug,
io_resp => io_resp_debug );
ev_data <= srq_i & atn_i & data_i & clk_i & '1' & atn_o_2 & data_o_2 & clk_o_2 &
'0' & atn_o & data_o & clk_o & hw_srq_o & hw_atn_o & hw_data_o & hw_clk_o;
end generate;
end logic;
| gpl-3.0 | 6e317e7c2921d7c978af22552211beab | 0.462157 | 3.213346 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op948_4.vhdl | 1 | 4,611 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net5
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 57ae4237b85130f2bb1c73ad6464e719 | 0.585556 | 3.217725 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/usb_memory_ctrl.vhd | 3 | 7,350 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_bus_pkg.all;
-- This module performs the memory operations that are instructed
-- by the nano_cpu. This controller copies data to or from a
-- designated BRAM, and notifies the nano_cpu that the transfer
-- is complete.
entity usb_memory_ctrl is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
clock : in std_logic;
reset : in std_logic;
-- cmd interface
cmd_addr : in std_logic_vector(3 downto 0);
cmd_valid : in std_logic;
cmd_write : in std_logic;
cmd_wdata : in std_logic_vector(15 downto 0);
cmd_ack : out std_logic;
cmd_ready : out std_logic;
-- BRAM interface
ram_addr : out std_logic_vector(10 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end entity;
architecture gideon of usb_memory_ctrl is
type t_state is (idle, reading, writing, init);
signal state : t_state;
signal mem_addr_r : unsigned(25 downto 0) := (others => '0');
signal mem_addr_i : unsigned(25 downto 0) := (others => '0');
signal ram_addr_i : unsigned(10 downto 0) := (others => '0');
signal remaining : unsigned(10 downto 0) := (others => '0');
signal mreq : std_logic := '0';
signal size : unsigned(1 downto 0) := (others => '0');
signal rwn : std_logic := '1';
signal addr_do_load : std_logic;
signal addr_do_inc : std_logic;
signal addr_inc_by_4 : std_logic;
signal rem_do_load : std_logic;
signal rem_do_dec : std_logic;
signal remain_is_0 : std_logic;
signal remain_less4 : std_logic;
begin
mem_req.tag <= g_tag;
mem_req.request <= mreq;
mem_req.address <= mem_addr_i;
mem_req.read_writen <= rwn;
mem_req.size <= size;
mem_req.data <= ram_rdata;
-- pop from fifo when we process the access
cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0';
process(state, mreq, mem_resp, ram_addr_i)
begin
ram_addr <= std_logic_vector(ram_addr_i);
ram_wdata <= mem_resp.data;
ram_we <= '0';
ram_en <= '0';
-- for writing to memory, we enable the BRAM only when we are going to set
-- the request, such that the data and the request comes at the same time
case state is
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
ram_en <= '1';
end if;
when others =>
null;
end case;
-- for reading from memory, it doesn't matter in which state we are:
if mem_resp.dack_tag=g_tag then
ram_we <= '1';
ram_en <= '1';
end if;
end process;
process(clock)
variable temp : unsigned(2 downto 0);
begin
if rising_edge(clock) then
rem_do_dec <= '0';
case state is
when idle =>
rwn <= '1';
if cmd_valid='1' then
if cmd_write='1' then
cmd_ready <= '0';
case cmd_addr is
when X"0" =>
mem_addr_r(15 downto 0) <= unsigned(cmd_wdata);
when X"1" =>
mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0));
when X"2" =>
rwn <= '0';
state <= init;
when X"3" =>
state <= init;
when others =>
null;
end case;
end if;
end if;
when init =>
ram_addr_i <= (others => '0');
if rwn='1' then
state <= reading;
else
state <= writing;
end if;
when reading =>
rwn <= '1';
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
if remain_less4='1' then
if remain_is_0='1' then
state <= idle;
cmd_ready <= '1';
mreq <= '0';
else
rem_do_dec <= '1';
mreq <= '1';
size <= "00";
end if;
else
rem_do_dec <= '1';
size <= "11";
mreq <= '1';
end if;
end if;
when writing =>
rwn <= '0';
size <= "00";
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
ram_addr_i <= ram_addr_i + 1;
if remain_is_0 = '1' then
mreq <= '0';
state <= idle;
cmd_ready <= '1';
else
mreq <= '1';
rem_do_dec <= '1';
end if;
end if;
when others =>
null;
end case;
if mem_resp.dack_tag=g_tag then
ram_addr_i <= ram_addr_i + 1;
end if;
if reset='1' then
state <= idle;
mreq <= '0';
cmd_ready <= '0';
end if;
end if;
end process;
addr_do_load <= '1' when (state = init) else '0';
addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) else '0';
addr_inc_by_4 <= '1' when (size = "11") else '0';
i_addr: entity work.mem_addr_counter
port map (
clock => clock,
load_value => mem_addr_r,
do_load => addr_do_load,
do_inc => addr_do_inc,
inc_by_4 => addr_inc_by_4,
address => mem_addr_i );
rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0';
-- rem_do_dec <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0' and state/=idle and state/=init) else '0';
i_rem: entity work.mem_remain_counter
port map (
clock => clock,
load_value => unsigned(cmd_wdata(10 downto 0)),
do_load => rem_do_load,
do_dec => rem_do_dec,
dec_by_4 => addr_inc_by_4,
remain => remaining,
remain_is_0 => remain_is_0,
remain_less4=> remain_less4 );
end architecture;
| gpl-3.0 | 70c331bf03bfccb7341ac6d72fc92360 | 0.424626 | 3.888889 | false | false | false | false |
pemb/siphash | siphash.vhd | 1 | 3,807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.siphash_package.all;
entity siphash is
generic (c : integer := 2);
port (
m : in std_logic_vector (BLOCK_WIDTH-1 downto 0);
b : in std_logic_vector (BYTES_WIDTH-1 downto 0);
rst_n : in std_logic;
clk : in std_logic;
init : in std_logic;
load_k : in std_logic;
init_ready, hash_ready : buffer std_logic;
hash : out std_logic_vector(HASH_WIDTH-1 downto 0)
);
end entity;
architecture rtl of siphash is
type state_t is (idle, compression, last_block, finalization);
signal state : state_t;
signal total_bytes : std_logic_vector(LENGTH_WIDTH-1 downto 0);
signal v0, v1, v2, v3 : v_array(c downto 0);
signal k : std_logic_vector(KEY_WIDTH-1 downto 0);
signal block_counter : unsigned(COUNT_WIDTH-1 downto 0);
signal current_count : unsigned(COUNT_WIDTH-1 downto 0);
signal this_m, last_m : std_logic_vector(BLOCK_WIDTH-1 downto 0);
begin
siprounds : for i in 0 to c-1 generate
round : sipround
port map (v0(i), v1(i), v2(i), v3(i),
v0(i+1), v1(i+1), v2(i+1), v3(i+1));
end generate;
current_count <= (others => '0') when init = '1' else block_counter;
total_bytes <= std_logic_vector(current_count) & b(BYTES_WIDTH-2 downto 0);
this_m <= m when b(BYTES_WIDTH-1) = '1' else
total_bytes & m(BLOCK_WIDTH-LENGTH_WIDTH-1 downto 0);
process(rst_n, clk)
begin
if rst_n = '0' then
k <= (others => '0');
elsif rising_edge(clk) then
if load_k = '1' then
k(KEY_WIDTH-1 downto BLOCK_WIDTH) <= m;
k(BLOCK_WIDTH-1 downto 0) <= k(KEY_WIDTH-1 downto BLOCK_WIDTH);
end if;
end if;
end process;
process (rst_n, clk, init)
begin
if rst_n = '0' then
v0(0) <= (others => '0');
v1(0) <= (others => '0');
v2(0) <= (others => '0');
v3(0) <= (others => '0');
last_m <= (others => '0');
block_counter <= (others => '0');
hash_ready <= '0';
init_ready <= '0';
hash <= (others => '0');
elsif rising_edge(clk) then
last_m <= this_m;
block_counter <= current_count + 1;
init_ready <= '0';
hash_ready <= '0';
v0(0) <= v0(c);
v1(0) <= v1(c);
v2(0) <= v2(c);
v3(0) <= v3(c);
case state is
when idle =>
init_ready <= '1';
hash_ready <= hash_ready;
when compression =>
v0(0) <= v0(c) xor last_m;
v3(0) <= v3(c) xor this_m;
when last_block =>
v0(0) <= v0(c) xor last_m;
v2(0) <= v2(c) xor V2_FINAL;
when finalization =>
if init_ready = '1' then
hash <= v0(c) xor v1(c) xor v2(c) xor v3(c);
hash_ready <= '1';
end if;
init_ready <= '1';
end case;
if init = '1' then
v0(0) <= V0_INIT xor k(BLOCK_WIDTH-1 downto 0);
v1(0) <= V1_INIT xor k(KEY_WIDTH-1 downto BLOCK_WIDTH);
v2(0) <= V2_INIT xor k(BLOCK_WIDTH-1 downto 0);
v3(0) <= V3_INIT xor k(KEY_WIDTH-1 downto BLOCK_WIDTH) xor this_m;
init_ready <= '0';
end if;
end if;
end process;
process (rst_n, clk)
begin
if rst_n = '0' then
state <= idle;
elsif rising_edge(clk) then
if init = '1' or state = compression then
if b(BYTES_WIDTH-1) = '1' then
state <= compression;
else
state <= last_block;
end if;
elsif state = last_block then
state <= finalization;
elsif state = finalization and init_ready = '1' then
state <= idle;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 89b2e7afe444a26e35fd09aa4d7c287b | 0.522196 | 3.055377 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/my_ioddr.vhd | 5 | 2,016 | -------------------------------------------------------------------------------
-- Title : ODDR Wrapper for Xilinx
-------------------------------------------------------------------------------
-- Description: Just a wrapper for an ODDR, trying to keep the clock inversion
-- local within the ODDR and not generated with a lut.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_ioddr is
port (
clock : in std_logic;
d0 : in std_logic;
d1 : in std_logic;
t0 : in std_logic;
t1 : in std_logic;
q0 : out std_logic;
q1 : out std_logic;
pin : inout std_logic );
attribute keep_hierarchy : string;
--attribute keep_hierarchy of my_ioddr : entity is "yes";
attribute ifd_delay_value : string;
attribute ifd_delay_value of pin : signal is "6";
end entity;
architecture gideon of my_ioddr is
signal q_i : std_logic;
signal t_i : std_logic;
signal not_clk : std_logic;
begin
not_clk <= not clock;
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => q_i,
C0 => clock,
C1 => not_clk,
CE => '1',
D0 => d0,
D1 => d1,
R => '0',
S => '0' );
i_tri: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => t_i,
C0 => clock,
C1 => not_clk,
CE => '1',
D0 => t0,
D1 => t1,
R => '0',
S => '0' );
pin <= q_i when t_i='0' else 'Z';
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
D => pin,
C0 => clock,
C1 => not_clk,
CE => '1',
Q0 => q0,
Q1 => q1,
R => '0',
S => '0' );
end architecture;
| gpl-3.0 | 2c5ba3e61bf99db8edd90bde571b337f | 0.431548 | 3.278049 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/sync_separator.vhd | 5 | 2,599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_separator is
generic (
g_clock_mhz : natural := 50 );
port (
clock : in std_logic;
sync_in : in std_logic;
mute : out std_logic;
h_sync : out std_logic;
v_sync : out std_logic );
end sync_separator;
architecture low_level of sync_separator is
constant c_delay : integer := 50;
signal h_sync_i : std_logic := '0';
signal release : std_logic := '0';
signal sync_c : std_logic := '0';
signal sync_d1 : std_logic := '0';
signal sync_d2 : std_logic := '0';
signal v_sync_pre : std_logic := '0';
signal delay : integer range 0 to c_delay * g_clock_mhz := 0;
signal raw_c : std_logic;
signal raw_d1 : std_logic;
signal raw_d2 : std_logic;
signal line_count : unsigned(8 downto 0) := (others => '0');
begin
h_sync <= h_sync_i;
process(sync_in, release)
begin
if release='1' then
h_sync_i <= '0';
elsif falling_edge(sync_in) then
h_sync_i <= '1';
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
sync_c <= h_sync_i;
sync_d1 <= sync_c;
sync_d2 <= sync_d1;
-- raw_c <= sync_in;
-- raw_d1 <= raw_c;
-- raw_d2 <= raw_d1;
--
-- if raw_d1='0' and raw_d2='1' then -- falling edge
-- if delay /= 0 then
-- mute <= '1';
-- else
-- mute <= '0';
-- end if;
-- end if;
if (line_count < 4) or (line_count > 305) then
mute <= '1';
else
mute <= '0';
end if;
release <= '0';
if sync_d1='1' and sync_d2='0' then -- rising edge
delay <= c_delay * g_clock_mhz;
if v_sync_pre = '1' then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
elsif delay /= 0 then
delay <= delay - 1;
end if;
if delay = 1 then
v_sync_pre <= not sync_in; -- sample
release <= '1';
end if;
end if;
end process;
v_sync <= v_sync_pre;
end low_level;
| gpl-3.0 | d233e859cad0162fd4b052d7a96147e7 | 0.418238 | 3.574966 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/PointFifo.vhd | 1 | 2,821 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F9LRRL
-- /___/ /\ Timestamp : 04/06/2014 00:33:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity PointFifo is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputValue: out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end PointFifo;
architecture BEHAVIORAL of PointFifo is
type T_POINT_ARRAY is array (NUMBER_OF_SCALES-1 downto 0) of (OUT_HORIZ_CONV_BW-1 downto 0);
signal s_point_array: T_POINT_ARRAY := (others => (others => '0'));
signal counter: integer range 0 to NUMBER_OF_SCALES-1 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_point_array <= (others => (others => '0'));
enableOut <= '0';
counter <= 0;
else
if enableIn = '1' then
s_point_array(0) <= inputValue;
for i in 1 to NUMBER_OF_SCALES-1 loop
s_point_array(i) <= s_point_array(i-1);
end loop;
if counter = NUMBER_OF_SCALES-1 then
enableOut <= '1';
counter <= 0;
else
counter <= counter +1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
outputValue <= s_point_array(NUMBER_OF_SCALES-1);
end BEHAVIORAL;
| gpl-3.0 | 44422f3a1ff9c7ef678e6a869cd64a36 | 0.587026 | 3.265046 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op968_5.vhdl | 1 | 5,995 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 30f3e837be5df07714a501de410c6c65 | 0.577815 | 3.127282 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_8sk1_0.vhdl | 1 | 7,641 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => W_0,
W_0init => 9.05e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcm_1,
Wcm_1init => 1.54e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcmout_1,
Wcmout_1init => 1.045e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 86514a9387370987a171b6314dd38fab | 0.582123 | 2.861798 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_par.vhd | 3 | 13,053 | ------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
| gpl-2.0 | 341860c3988d3ca3aba05c31a5572cea | 0.54838 | 3.315469 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_8sk1_0.vhdl | 1 | 7,612 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.2e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.2e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => W_0,
W_0init => 6.775e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.2e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.2e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.45e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.45e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.45e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 9.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.45e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 2.65e-06,
W => Wsrc_2,
Wsrc_2init => 1.22e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 2.65e-06,
W => Wsrc_2,
Wsrc_2init => 1.22e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 3.52e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.5e-07,
W => Wcm_1,
Wcm_1init => 7.3e-06,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.5e-07,
W => Wcmout_1,
Wcmout_1init => 5.605e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 3.52e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => (pfak)*(WBias),
WBiasinit => 9.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 8e-07,
W => (pfak)*(WBias),
WBiasinit => 9.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 8e-07,
W => WBias,
WBiasinit => 9.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => WBias,
WBiasinit => 9.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => WBias,
WBiasinit => 9.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 8e-07,
W => WBias,
WBiasinit => 9.55e-06
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | c0e653d5d2ab7c6e529303620e82992b | 0.581713 | 2.870287 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op950_3.vhdl | 2 | 4,591 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6376d46e7e63a9997baaf5a13b20fcae | 0.580701 | 3.203768 | false | false | false | false |
KB777/1541UltimateII | fpga/io/command_interface/vhdl_source/command_if_pkg.vhd | 1 | 2,906 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package command_if_pkg is
constant c_cif_io_slot_base : unsigned(3 downto 0) := X"0";
constant c_cif_io_slot_enable : unsigned(3 downto 0) := X"1";
constant c_cif_io_handshake_out : unsigned(3 downto 0) := X"2"; -- write will also cause pointers to be reset
constant c_cif_io_handshake_in : unsigned(3 downto 0) := X"3";
constant c_cif_io_command_start : unsigned(3 downto 0) := X"4"; -- read only; tells software where the buffers are.
constant c_cif_io_command_end : unsigned(3 downto 0) := X"5";
constant c_cif_io_response_start : unsigned(3 downto 0) := X"6"; -- read only; tells software where the buffers are.
constant c_cif_io_response_end : unsigned(3 downto 0) := X"7";
constant c_cif_io_status_start : unsigned(3 downto 0) := X"8"; -- read only; tells software where the buffers are.
constant c_cif_io_status_end : unsigned(3 downto 0) := X"9";
constant c_cif_io_status_length : unsigned(3 downto 0) := X"A"; -- write will reset status readout
constant c_cif_io_irq_mask : unsigned(3 downto 0) := X"B"; -- read/write
constant c_cif_io_response_len_l : unsigned(3 downto 0) := X"C"; -- write will reset response readout
constant c_cif_io_response_len_h : unsigned(3 downto 0) := X"D";
constant c_cif_io_command_len_l : unsigned(3 downto 0) := X"E"; -- read only
constant c_cif_io_command_len_h : unsigned(3 downto 0) := X"F";
constant c_cif_io_irq_mask_set : unsigned(3 downto 0) := X"4"; -- write only
constant c_cif_io_irq_mask_clear : unsigned(3 downto 0) := X"5"; -- write only
constant c_cif_slot_control : unsigned(1 downto 0) := "00"; -- R/W
constant c_cif_slot_command : unsigned(1 downto 0) := "01"; -- WO
constant c_cif_slot_response : unsigned(1 downto 0) := "10"; -- RO
constant c_cif_slot_status : unsigned(1 downto 0) := "11"; -- RO
constant c_cmd_if_command_buffer_addr : unsigned(10 downto 0) := to_unsigned( 0, 11);
constant c_cmd_if_response_buffer_addr : unsigned(10 downto 0) := to_unsigned( 896, 11);
constant c_cmd_if_status_buffer_addr : unsigned(10 downto 0) := to_unsigned(1792, 11);
constant c_cmd_if_command_buffer_size : integer := 896;
constant c_cmd_if_response_buffer_size : integer := 896;
constant c_cmd_if_status_buffer_size : integer := 256;
constant c_cmd_if_command_buffer_end : unsigned(10 downto 0) := to_unsigned( 0 + c_cmd_if_command_buffer_size-1, 11);
constant c_cmd_if_response_buffer_end : unsigned(10 downto 0) := to_unsigned( 896 + c_cmd_if_response_buffer_size-1, 11);
constant c_cmd_if_status_buffer_end : unsigned(10 downto 0) := to_unsigned(1792 + c_cmd_if_status_buffer_size-1, 11);
end package;
| gpl-3.0 | 08c4e40fc6cd62e1d30473bc06743239 | 0.63214 | 3.145022 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_decode.vhd | 4 | 9,778 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_decode is
end tb_decode;
architecture tb of tb_decode is
signal i_reg : std_logic_vector(7 downto 0);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_shift : boolean;
signal s_is_alu : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_is_illegal : boolean;
signal s_select_index_y : boolean;
signal s_store_a_from_alu : boolean;
signal s_load_a : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal opcode : string(1 to 13);
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_shift <= is_shift(i_reg);
s_is_alu <= is_alu(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_is_illegal <= is_illegal(i_reg);
s_select_index_y <= select_index_y(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
s_load_a <= load_a(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
test: process
begin
for i in 0 to 255 loop
i_reg <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
assert not (opcode(4)=' ' and s_is_illegal) report "Function says it's illegal, opcode does not." severity error;
assert not (opcode(4)='*' and not s_is_illegal) report "Opcode says it's illegal, function says it's not." severity error;
end loop;
wait;
end process;
dump: process
variable inst : std_logic_vector(7 downto 0);
variable bool : boolean;
variable L : line;
type t_bool_array is array(natural range <>) of boolean;
type t_sel_array is array(natural range <>) of std_logic_vector(1 downto 0);
variable b_is_absolute : t_bool_array(0 to 255);
variable b_is_abs_jump : t_bool_array(0 to 255);
variable b_is_immediate : t_bool_array(0 to 255);
variable b_is_implied : t_bool_array(0 to 255);
variable b_is_stack : t_bool_array(0 to 255);
variable b_is_push : t_bool_array(0 to 255);
variable b_is_zeropage : t_bool_array(0 to 255);
variable b_is_indirect : t_bool_array(0 to 255);
variable b_is_relative : t_bool_array(0 to 255);
variable b_is_load : t_bool_array(0 to 255);
variable b_is_store : t_bool_array(0 to 255);
variable b_is_shift : t_bool_array(0 to 255);
variable b_is_alu : t_bool_array(0 to 255);
variable b_is_rmw : t_bool_array(0 to 255);
variable b_is_jump : t_bool_array(0 to 255);
variable b_is_postindexed : t_bool_array(0 to 255);
variable b_select_index_y : t_bool_array(0 to 255);
variable b_store_a_from_alu : t_bool_array(0 to 255);
variable b_shift_sel : t_sel_array(0 to 255);
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
procedure output_bool(bool : boolean) is
begin
if bool then
write_str(L, " (*) ");
else
write_str(L, " . ");
end if;
end procedure;
procedure output_shift_sel(bool : boolean; sel: std_logic_vector(1 downto 0)) is
type t_string_array is array(natural range <>) of string(1 to 5);
constant c_shift_sel_str : t_string_array(0 to 3) := ( "0xFF ", "data ", "accu ", " A&D " );
begin
if bool then
write_str(L, c_shift_sel_str(conv_integer(sel)));
else
write_str(L, " . ");
end if;
end procedure;
procedure print_table(b : t_bool_array; title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := conv_std_logic_vector(x*32, 8);
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := conv_std_logic_vector(y, 8);
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_bool(b(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure print_sel_table(title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := conv_std_logic_vector(x*32, 8);
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := conv_std_logic_vector(y, 8);
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_shift_sel(b_is_shift(y + x*32), b_shift_sel(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
begin
for i in 0 to 255 loop
inst := conv_std_logic_vector(i, 8);
b_is_absolute(i) := is_absolute(inst);
b_is_abs_jump(i) := is_abs_jump(inst);
b_is_immediate(i) := is_immediate(inst);
b_is_implied(i) := is_implied(inst);
b_is_stack(i) := is_stack(inst);
b_is_push(i) := is_push(inst);
b_is_zeropage(i) := is_zeropage(inst);
b_is_indirect(i) := is_indirect(inst);
b_is_relative(i) := is_relative(inst);
b_is_load(i) := is_load(inst);
b_is_store(i) := is_store(inst);
b_is_shift(i) := is_shift(inst);
b_is_alu(i) := is_alu(inst);
b_is_rmw(i) := is_rmw(inst);
b_is_jump(i) := is_jump(inst);
b_is_postindexed(i) := is_postindexed(inst);
b_select_index_y(i) := select_index_y(inst);
b_store_a_from_alu(i) := store_a_from_alu(inst);
b_shift_sel(i) := shifter_in_select(inst);
end loop;
print_table(b_is_absolute , "is_absolute");
print_table(b_is_abs_jump , "is_abs_jump");
print_table(b_is_immediate , "is_immediate");
print_table(b_is_implied , "is_implied");
print_table(b_is_stack , "is_stack");
print_table(b_is_push , "is_push");
print_table(b_is_zeropage , "is_zeropage");
print_table(b_is_indirect , "is_indirect");
print_table(b_is_relative , "is_relative");
print_table(b_is_load , "is_load");
print_table(b_is_store , "is_store");
print_table(b_is_shift , "is_shift");
print_table(b_is_alu , "is_alu");
print_table(b_is_rmw , "is_rmw");
print_table(b_is_jump , "is_jump");
print_table(b_is_postindexed , "is_postindexed");
print_table(b_select_index_y , "Select index Y");
print_table(b_store_a_from_alu , "Store A from ALU");
print_sel_table("Shifter Input");
wait;
end process;
end tb;
| gpl-3.0 | 58f7413a38503cc81ce7a17fd2721834 | 0.464819 | 3.550472 | false | false | false | false |
tirfil/VhdI2CSlave | testbenches/tb_i2cdemo.vhd | 1 | 2,790 | --###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CDEMO is
end TB_I2CDEMO;
architecture stimulus of TB_I2CDEMO is
-- COMPONENTS --
component I2CDEMO
port(
MCLK : in std_logic;
nRST : in std_logic;
SCL : inout std_logic;
SDA : inout std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SCL : std_logic;
signal SDA : std_logic;
--
signal RUNNING : std_logic := '1';
signal result : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_I2CDEMO_0 : I2CDEMO
port map (
MCLK => MCLK,
nRST => nRST,
SCL => SCL,
SDA => SDA
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
procedure SendData(data : in std_logic_vector(7 downto 0)) is
variable d : std_logic_vector(7 downto 0);
begin
d := data;
SCL <= '0';
for i in 0 to 7 loop
if (d(7) = '1') then
SDA <= 'H';
else
SDA <= '0';
end if;
wait for 80 ns;
SCL <= 'H';
wait for 80 ns;
SCL <= '0';
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
end loop;
SDA <= 'H';
wait for 80 ns;
SCL <= 'H';
wait for 80 ns;
SCL <= '0';
wait for 80 ns;
end SendData;
procedure ReadData(nack: in std_logic) is
variable d: std_logic_vector(7 downto 0);
begin
SCL <= '0';
for i in 0 to 7 loop
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
SCL <= 'H';
d(0) := SDA;
wait for 80 ns;
SCL <= '0';
wait for 80 ns;
end loop;
SDA <= nack;
result <= d;
wait for 80 ns;
SCL <= 'H';
wait for 80 ns;
SCL <= '0';
wait for 80 ns;
SDA <= 'H';
end ReadData;
begin
result <= x"FF";
wait for 1 ns;
nRST <= '0';
SDA <= 'H';
SCL <= 'H';
wait for 1000 ns;
nRST <= '1';
SDA <= '0'; -- start
wait for 80 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"F0"); -- address
SendData(x"20");
SendData(x"03");
SendData(x"19");
SendData(x"64");
SDA <= 'H';
wait for 80 ns;
SCL <= 'H';
wait for 80 ns;
SDA <= '0'; -- start2
wait for 80 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"F0"); -- address
SDA <= 'H';
wait for 80 ns;
SCL <= 'H';
wait for 80 ns;
SDA <= '0'; -- start2
wait for 80 ns;
SendData(x"71"); -- 38 < 1 + read
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('1'); -- nack
SCL <= '1';
wait for 80 ns;
SDA <= '1'; -- stop
wait for 80 ns;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
| gpl-3.0 | 44c749ac2bf4a78be78e772090226ee9 | 0.521864 | 2.602612 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_peripheral.vhd | 4 | 3,696 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
signal sid_write : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt, -- 4042800
resps(0) => io_resp_regs,
resps(1) => io_resp_filt );
i_regs: entity work.sid_io_regs
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt => io_req_filt,
io_resp_filt => io_resp_filt,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
sid_write <= '1' when slot_req.bus_write='1' and slot_req.bus_address(15 downto 8)=X"D4" else '0';
end structural;
| gpl-3.0 | 49de0809b6ba1169e10fe616400a350a | 0.483225 | 3.623529 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/GaussianFilter.vhd | 1 | 5,651 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_hg0Oyc
-- /___/ /\ Timestamp : 04/05/2014 21:13:39
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
entity GaussianFilter is
port ( ADDR : in std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
CLK : in std_logic;
ENABLEIN : in std_logic;
INPUTARRAY : in T_INPUT_VERTICAL_CONVOLUTION;
RST : in std_logic;
ENABLEOUT : out std_logic;
OUTPUTDATA : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end GaussianFilter;
architecture BEHAVIORAL of GaussianFilter is
-- component ROM_GAUSS_COE is
-- PORT (
-- CLK: IN STD_LOGIC;
-- WE: IN STD_LOGIC;
-- SPO: OUT STD_LOGIC_VECTOR(KERNEL_ROM_BW-1 downto 0);
-- A: IN STD_LOGIC_VECTOR(3 downto 0);
-- D: IN STD_LOGIC_VECTOR(KERNEL_ROM_BW-1 downto 0)
-- );
-- end component;
component rom_coe is
port(
clk : in std_logic;
address : in std_logic_vector(N_GAUSS_KERNEL_BW-1 downto 0);
data_out: out std_logic_vector(KERNEL_ROM_BW-1 downto 0)
);
end component;
component VerticalConvolution is
port (
clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
gaussianKernel : in std_logic_vector (KERNEL_ROM_BW-1 downto 0);
inputArray : in T_INPUT_VERTICAL_CONVOLUTION;
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_VERT_CONV_BW-1 downto 0)
);
end component;
--component IntermediateBufferConv is
--port ( clk : in std_logic;
-- enableIn : in std_logic;
--inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
--rst : in std_logic;
--enableOut : out std_logic;
--outputData : out T_INPUT_HORIZONTAL_CONVOLUTION
-- );
--end component;
component IntermediateRegsConv is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputData : out T_INPUT_HORIZONTAL_CONVOLUTION
);
end component;
component HorizontalConvolution is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
gaussianKernel : in std_logic_vector (KERNEL_ROM_BW-1 downto 0);
inputData : in T_INPUT_HORIZONTAL_CONVOLUTION;
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
signal intermediate_registers: T_INPUT_HORIZONTAL_CONVOLUTION;
signal output_vert_conv: std_logic_vector(OUT_VERT_CONV_BW-1 downto 0);
signal gaussian_coefficients: std_logic_vector(KERNEL_ROM_BW-1 downto 0);
signal out_enable_vert_conv: std_logic;
signal in_enable_horiz_conv: std_logic;
-- signal WE: std_logic := '0';
-- signal D: std_logic_vector(KERNEL_ROM_BW-1 downto 0) := (others => '0');
begin
--mapping
-- gauss_coe: ROM_GAUSS_COE
-- port map(
-- CLK => CLK,
-- WE => WE,
-- SPO => gaussian_coefficients,
-- A => ADDR,
-- D => D
-- );
gauss_coe: rom_coe
port map(
clk => CLK,
data_out => gaussian_coefficients,
address => ADDR
);
vert_conv: VerticalConvolution
port map(
clk => CLK,
enableIn => ENABLEIN,
rst => RST,
inputArray => INPUTARRAY,
gaussianKernel => gaussian_coefficients,
outputData => output_vert_conv,
enableOut => out_enable_vert_conv
);
Intermediate_RegsConv: IntermediateRegsConv
port map(
clk => CLK,
enableIn => out_enable_vert_conv,
rst => RST,
inputValue => output_vert_conv,
enableOut => in_enable_horiz_conv,
outputData => intermediate_registers
);
horiz_conv: HorizontalConvolution
port map(
clk => CLK,
rst => RST,
enableIn => in_enable_horiz_conv,
inputData => intermediate_registers,
gaussianKernel => gaussian_coefficients,
outputData => OUTPUTDATA,
enableOut => ENABLEOUT
);
--end of mapping
end BEHAVIORAL;
| gpl-3.0 | 04a7c625f8de08687d06fdf2bff03eee | 0.585206 | 3.373731 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem/simulation/bmg_stim_gen.vhd | 1 | 7,560 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(5 DOWNTO 0) <= WRITE_ADDR(5 DOWNTO 0);
READ_ADDR_INT(5 DOWNTO 0) <= READ_ADDR(5 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | 98215372e4075b6d1a771db7660a27b0 | 0.55754 | 3.770574 | false | false | false | false |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/openMAC_DPR_Altera.vhd | 1 | 9,513 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Altera FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2010-05-03 V0.02 added packet buffer dpr
-- 2011-12-22 V0.03 added initialization files
-- removed dpr_8_8
-- 2012-01-04 V0.04 replaced initialization files with mif
-- 2012-02-21 V0.05 replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 16 / 16 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "../mif/dpr_16_16.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA, wren_b => WeB,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA, byteena_b => BeB,
address_a => AddrA, address_b => AddrB,
data_a => DiA, data_b => DiB,
q_a => DoA, q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- 16 / 32 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "../mif/dpr_16_32.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA,
address_a => AddrA, address_b => AddrB,
data_a => DiA,
q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- Packet buffer
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
ARCHITECTURE SYN OF openmac_dprpackets IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => memSize_g/2,
numwords_b => memSize_g/4,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => memSizeLOG2_g-1,
widthad_b => memSizeLOG2_g-2,
width_a => 16,
width_b => 32,
width_byteena_a => 2,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
rden_a => rden_a,
rden_b => rden_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | 85c054342f3e43fe6942a09320463f86 | 0.582887 | 3.045134 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_compare0.vhd | 1 | 3,968 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- lpm_compare
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AleB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
AleB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "1"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: AleB 0 0 0 0 OUTPUT NODEFVAL AleB
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: CONNECT: AleB 0 0 0 0 @AleB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd TRUE
| gpl-2.0 | 3bbe8dca39bd61496d9d3e1b6958f365 | 0.65121 | 3.81172 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/sync_fifo/vhdl_source/sync_fifo.vhd | 4 | 5,506 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
| gpl-3.0 | 307f90ff08cbd3121c9c7c382811e7a6 | 0.466764 | 3.743032 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_sim/iec_processor_tb.vhd | 5 | 5,679 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 | e131b904f7cffa6ea7bca47db6b9cdd7 | 0.430534 | 3.711765 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_dff1.vhd | 1 | 3,982 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff1.vhd
-- Megafunction Name(s):
-- lpm_ff
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff1 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_dff1;
ARCHITECTURE SYN OF lpm_dff1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 8
)
PORT MAP (
enable => enable,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1_inst.vhd TRUE
| gpl-2.0 | 2ca634bc3674654e163c4a37565b0605 | 0.636364 | 3.600362 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/stack/vhdl_source/distributed_stack.vhd | 3 | 4,066 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
-------------------------------------------------------------------------------
-- File : distributed_stack.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the RAMX1 properties,
-- implementing a 16-deep synchronous stack in only one LUT per
-- bit. The value to be popped is always visible.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity distributed_stack is
generic (
Width : integer := 32;
simultaneous_pushpop : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
pop : in std_logic;
push : in std_logic;
flush : in std_logic;
data_in : in std_logic_vector(Width-1 downto 0);
data_out : out std_logic_vector(Width-1 downto 0);
full : out std_logic;
data_valid : out std_logic );
end distributed_stack;
architecture Gideon of distributed_stack is
signal pointer : unsigned(3 downto 0);
signal address : unsigned(3 downto 0);
signal we : std_logic;
signal data_valid_i : std_logic;
signal full_i : std_logic;
signal filtered_pop : std_logic;
signal filtered_push : std_logic;
signal ram_data : std_logic_vector(Width-1 downto 0);
begin
filtered_pop <= data_valid_i and pop;
filtered_push <= not full_i and push;
full <= full_i;
process(filtered_push, pop, pointer, ram_data, data_in)
begin
we <= filtered_push;
data_out <= ram_data;
data_valid <= data_valid_i;
if filtered_push='1' then
address <= pointer + 1;
else
address <= pointer;
end if;
if simultaneous_pushpop then
if filtered_push='1' and pop='1' then
data_out <= data_in;
we <= '0';
data_valid <= '1';
end if;
end if;
end process;
process(clock)
variable new_pointer : unsigned(3 downto 0);--integer range 0 to Depth;
begin
if rising_edge(clock) then
if flush='1' then
new_pointer := X"F";
elsif (filtered_pop='1') and (filtered_push='0') then
new_pointer := pointer - 1;
elsif (filtered_pop='0') and (filtered_push='1') then
new_pointer := pointer + 1;
else
new_pointer := pointer;
end if;
pointer <= new_pointer;
if (new_pointer = X"F") then
data_valid_i <= '0';
else
data_valid_i <= '1';
end if;
if (new_pointer /= X"E") then
full_i <= '0';
else
full_i <= '1';
end if;
if reset='1' then
pointer <= X"F";
full_i <= '0';
data_valid_i <= '0';
end if;
end if;
end process;
RAMs : for ram2 in 0 to Width-1 generate
i_ram : RAM16X1S
port map (
WCLK => clock,
WE => we,
D => data_in(ram2),
A3 => address(3),
A2 => address(2),
A1 => address(1),
A0 => address(0),
O => ram_data(ram2) );
end generate;
end Gideon;
| gpl-3.0 | 684c1dded720370cf91ddb61359dd446 | 0.440974 | 4.362661 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/drive_registers.vhd | 4 | 7,872 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 0);
dirty_led_n : out std_logic;
stop_on_freeze : out std_logic;
param_write : out std_logic;
param_ram_en : out std_logic;
param_addr : out std_logic_vector(10 downto 0);
param_wdata : out std_logic_vector(7 downto 0);
param_rdata : in std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal dirty_bits : std_logic_vector(63 downto 0) := (others => '0');
signal any_dirty : std_logic;
signal irq_en : std_logic;
signal wr, wd : std_logic;
signal wa : integer range 0 to 63 := 0;
signal param_ack : std_logic;
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal inserted_i : std_logic;
signal stop_when_frozen : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
param_ack <= '0';
wr <= '0';
wa <= to_integer(unsigned(track(6 downto 1)));
if mode = '0' and motor_on='1' and inserted_i='1' then
wr <= '1';
wd <= '1';
any_dirty <= '1';
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(12 downto 11) is
when "00" => -- registers
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data;
when c_drvreg_anydirty =>
any_dirty <= '0';
when c_drvreg_dirtyirq =>
irq_en <= io_req.data(0);
when others =>
null;
end case;
when "01" => -- dirty block
wr <= '1';
wa <= to_integer(io_req.address(5 downto 0));
wd <= '0';
when "10" => -- param block
null;
when others => -- unused
null;
end case;
end if; -- write
if io_req.read='1' then
case io_req.address(12 downto 11) is
when "00" => -- registers
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i;
when c_drvreg_anydirty =>
io_resp.data(0) <= any_dirty;
when c_drvreg_dirtyirq =>
io_resp.data(0) <= irq_en;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= track(6 downto 0);
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
when c_drvreg_memmap =>
io_resp.data <= std_logic_vector(g_ram_base(23 downto 16));
when c_drvreg_audiomap =>
io_resp.data <= std_logic_vector(g_audio_base(23 downto 16));
when others =>
null;
end case;
when "01" => -- dirty block
io_resp.ack <= '1';
io_resp.data(0) <= dirty_bits(to_integer(io_req.address(5 downto 0)));
when "10" => -- param block
param_ack <= '1';
when others =>
io_resp.ack <= '1';
end case;
end if; -- read
-- param response
if param_ack='1' then
io_resp.ack <= '1';
io_resp.data <= param_rdata;
end if;
-- write into memory array
if wr='1' then
dirty_bits(wa) <= wd;
end if;
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
use_c64_reset_i <= '1';
any_dirty <= '0';
irq_en <= '0';
wd <= '0';
end if;
end if;
end process;
param_write <= '1' when io_req.write='1' and io_req.address(12 downto 11)="10" else '0';
param_ram_en <= '1' when (io_req.write='1' or io_req.read='1') and io_req.address(12 downto 11)="10" else '0';
param_addr <= std_logic_vector(io_req.address(10 downto 0));
param_wdata <= io_req.data;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
dirty_led_n <= not any_dirty;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
end rtl;
| gpl-3.0 | d667b391a01bd02081c71f6b8416afa1 | 0.420097 | 3.866405 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/harness_c1541.vhd | 4 | 5,613 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal clk_shifted : std_logic := '0';
signal cpu_clock_en : std_logic := '0';
signal drv_clock_en : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : unsigned(12 downto 0);
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0);
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
shared variable dram : h_mem_object;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
clk_shifted <= transport clock after 15 ns;
process(clock)
variable count : integer := 0;
begin
if rising_edge(clock) then
cpu_clock_en <= '0';
drv_clock_en <= '0';
case count is
when 0 | 12 | 25 | 37 =>
drv_clock_en <= '1';
count := count + 1;
when 49 =>
cpu_clock_en <= '1';
count := 0;
when others =>
count := count + 1;
end case;
end if;
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_audio => true,
g_audio_div => 100, -- for simulation: 500 ksps
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
cpu_clock_en => cpu_clock_en,
drv_clock_en => drv_clock_en,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clk_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => SDRAM_A,
MEM_D => SDRAM_DQ );
i_memory: entity work.dram_model_8
generic map (
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ );
process
begin
bind_mem_model("dram", dram);
load_memory("../../../software/1541u/application/ultimate/roms/1541-ii.bin", dram, X"0000C000");
load_memory("../../../software/1541u/application/ultimate/roms/sounds.bin", dram, X"00010000");
--wait for 3 ms;
--save_memory("datspace_sim.bin", ram, X"00068000", 8192);
wait;
end process;
end harness; | gpl-3.0 | d574bc7d29374f50400f4f3ada8e5e12 | 0.461607 | 3.497196 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op328_0sk1_0.vhdl | 1 | 5,741 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.4e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.4e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 5.96e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 7.995e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 7.995e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.65e-06,
W => Wcm_1,
Wcm_1init => 1.75e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.65e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.1e-06,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | de05b682c2bf7c4a2e09f331129770a5 | 0.58927 | 2.991662 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_pkg.vhd | 1 | 12,129 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb_pkg is
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token ->
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake <-
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token ->
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_split(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic;
type t_token is record
device_addr : std_logic_vector(6 downto 0);
endpoint_addr : std_logic_vector(3 downto 0);
end record;
constant c_token_init : t_token := ( "0000000", "0000" );
constant c_token_undefined : t_token := ( "XXXXXXX", "XXXX" );
type t_split_token is record
hub_address : std_logic_vector(6 downto 0);
sc : std_logic;
port_address : std_logic_vector(6 downto 0);
s : std_logic; -- start/speed (isochronous out start split), for interrupt/control transfers: Speed. 0=full, 1=low
e : std_logic; -- end (isochronous out start split) 00=middle, 10=beginning, 01=end, 11=all
et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
constant c_split_token_init : t_split_token := (
hub_address => "0000000",
sc => '0',
port_address => "0000000",
s => '0',
e => '0',
et => "00" );
constant c_split_token_undefined : t_split_token := (
hub_address => "XXXXXXX",
sc => 'X',
port_address => "XXXXXXX",
s => 'X',
e => 'X',
et => "XX" );
constant c_split_token_bogus : t_split_token := (
hub_address => "0000001",
sc => '0',
port_address => "0000010",
s => '0',
e => '0',
et => "11" );
type t_usb_rx is record
receiving : std_logic;
valid_token : std_logic;
valid_split : std_logic;
valid_handsh : std_logic;
valid_packet : std_logic;
error : std_logic;
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
data_valid : std_logic;
data_start : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_usb_tx_req is record
send_token : std_logic;
send_split : std_logic;
send_handsh : std_logic;
send_packet : std_logic;
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
no_data : std_logic;
data : std_logic_vector(7 downto 0);
data_valid : std_logic;
data_last : std_logic;
end record;
type t_usb_tx_resp is record
request_ack : std_logic;
busy : std_logic;
data_wait : std_logic;
end record;
type t_usb_tx_req_array is array(natural range <>) of t_usb_tx_req;
-- function or_reduce(a : t_usb_tx_req_array) return t_usb_tx_req;
constant c_usb_rx_init : t_usb_rx := (
receiving => '0',
valid_token => '0',
valid_split => '0',
valid_handsh => '0',
valid_packet => '0',
error => '0',
pid => X"0",
token => c_token_init,
split_token => c_split_token_init,
data_valid => '0',
data_start => '0',
data => X"00" );
constant c_usb_tx_req_init : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '0',
pid => c_pid_reserved,
token => c_token_init,
split_token => c_split_token_init,
no_data => '0',
data => X"00",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_ack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_ack,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nak,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nyet : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nyet,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_stall : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_stall,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_data_out0 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data0,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_data_out1 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data1,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
function token_to_vector(t : t_token) return std_logic_vector;
function vector_to_token(v : std_logic_vector) return t_token;
function split_token_to_vector(t : t_split_token) return std_logic_vector;
function vector_to_split_token(v : std_logic_vector) return t_split_token;
end package;
package body usb_pkg is
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_split(i : std_logic_vector(3 downto 0)) return boolean is
begin
return (i = c_pid_split);
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused! HUB reply to CSPLIT
when others => return false;
end case;
return false;
end function;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic is
begin
return i(3);
end function;
function split_token_to_vector(t : t_split_token) return std_logic_vector is
variable ret : std_logic_vector(18 downto 0);
begin
ret(18 downto 17) := t.et;
ret(16) := t.e;
ret(15) := t.s;
ret(14 downto 8) := t.port_address;
ret(7) := t.sc;
ret(6 downto 0) := t.hub_address;
return ret;
end function;
function vector_to_split_token(v : std_logic_vector) return t_split_token is
variable va : std_logic_vector(18 downto 0);
variable ret : t_split_token;
begin
va := v;
ret.et := va(18 downto 17);
ret.e := va(16);
ret.s := va(15);
ret.port_address := va(14 downto 8);
ret.sc := va(7);
ret.hub_address := va(6 downto 0);
return ret;
end function;
-- Token conversion
function token_to_vector(t : t_token) return std_logic_vector is
variable ret : std_logic_vector(10 downto 0);
begin
ret := t.endpoint_addr & t.device_addr;
return ret;
end function;
function vector_to_token(v : std_logic_vector) return t_token is
alias va : std_logic_vector(10 downto 0) is v;
variable ret : t_token;
begin
ret.device_addr := va(6 downto 0);
ret.endpoint_addr := va(10 downto 7);
return ret;
end function;
end;
| gpl-3.0 | 75634a38d48d2c636ed8cd096e9fa66b | 0.448017 | 3.769111 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_host_nano.vhd | 1 | 9,473 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-02-12
-- Author: Gideon
-- Description: Top level of second generation USB controller with memory
-- interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_nano is
generic (
g_tag : std_logic_vector(7 downto 0) := X"05";
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
--
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req_32;
sys_mem_resp: in t_mem_resp_32;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp;
sys_irq : out std_logic );
end entity;
architecture arch of usb_host_nano is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal nano_rdata_regs : std_logic_vector(15 downto 0);
signal nano_rdata_cmd : std_logic_vector(15 downto 0);
signal nano_stall : std_logic := '0';
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_address : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal reg_rdata : std_logic_vector(7 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal status : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
signal do_chirp : std_logic;
signal chirp_data : std_logic;
signal sof_enable : std_logic;
signal mem_ctrl_ready : std_logic;
signal buf_address : unsigned(10 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_addr : std_logic_vector(10 downto 2);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic_vector(3 downto 0);
signal sys_buf_wdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata : std_logic_vector(31 downto 0);
signal sys_buf_wdata_le: std_logic_vector(31 downto 0);
signal sys_buf_rdata_le: std_logic_vector(31 downto 0);
signal usb_tx_req : t_usb_tx_req;
signal usb_tx_resp : t_usb_tx_resp;
signal usb_rx : t_usb_rx;
signal usb_cmd_req : t_usb_cmd_req;
signal usb_cmd_resp : t_usb_cmd_resp;
signal frame_count : unsigned(15 downto 0);
signal sof_tick : std_logic;
signal interrupt : std_logic;
begin
i_intf: entity work.usb_host_interface
generic map (
g_simulation => g_simulation )
port map (
clock => clock,
reset => reset,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp,
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
reg_ack => reg_ack,
do_chirp => do_chirp,
chirp_data => chirp_data,
status => status,
speed => speed,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_seq: entity work.host_sequencer
port map (
clock => clock,
reset => reset,
buf_address => buf_address,
buf_en => buf_en,
buf_we => buf_we,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
frame_count => frame_count,
usb_cmd_req => usb_cmd_req,
usb_cmd_resp => usb_cmd_resp,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
i_buf_ram: RAMB16BWE_S36_S9
port map (
CLKB => clock,
SSRB => reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => std_logic_vector(buf_address),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata_le,
DIPA => "0000",
DOA => sys_buf_rdata_le );
sys_buf_wdata_le <= byte_swap(sys_buf_wdata);
sys_buf_rdata <= byte_swap(sys_buf_rdata_le);
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => clock,
ulpi_reset => reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_sync: entity work.level_synchronizer
port map (
clock => clock,
reset => reset,
input => cmd_ready,
input_c => mem_ctrl_ready );
i_nano_io: entity work.nano_minimal_io
generic map (
g_support_suspend => false )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata_regs,
stall => nano_stall,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
status => status,
mem_ctrl_ready => mem_ctrl_ready,
frame_count => frame_count,
do_chirp => do_chirp,
chirp_data => chirp_data,
connected => open,
operational => open,
suspended => open,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
interrupt_out => interrupt );
i_sync2: entity work.pulse_synchronizer
port map (
clock_in => clock,
pulse_in => interrupt,
clock_out => sys_clock,
pulse_out => sys_irq );
i_cmd_io: entity work.usb_cmd_nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata_cmd,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp );
i_nano: entity work.nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
nano_rdata <= nano_rdata_regs or nano_rdata_cmd;
end arch;
| gpl-3.0 | 478539a1f1a850442d85c00baddf0532 | 0.486013 | 3.549269 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/bit_cpx_cpy.vhd | 5 | 2,142 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bit_cpx_cpy is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1 downto 0)="00"
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
a_reg : in std_logic_vector(7 downto 0);
x_reg : in std_logic_vector(7 downto 0);
y_reg : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic );
end bit_cpx_cpy;
architecture gideon of bit_cpx_cpy is
signal reg : std_logic_vector(7 downto 0) := (others => '0');
signal diff : std_logic_vector(8 downto 0) := (others => '0');
signal zero_cmp : std_logic;
signal zero_ld : std_logic;
signal zero_bit : std_logic;
signal oper4 : std_logic_vector(3 downto 0);
begin
-- *** BIT *** *** STY LDY CPY CPX
reg <= x_reg when operation(0)='1' else y_reg;
diff <= ('1' & reg) - ('0' & data_in);
zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0';
zero_ld <= '1' when data_in=X"00" else '0';
zero_bit <= '1' when (data_in and a_reg)=X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
diff(8) when "1110" | "1111", -- CPX / CPY
c_in when others;
with oper4 select z_out <=
zero_cmp when "1110" | "1111", -- CPX / CPY
zero_ld when "1101",
zero_bit when "1001",
z_in when others;
with oper4 select n_out <=
diff(7) when "1110" | "1111", -- CPX / CPY
data_in(7) when "1101" | "1001", -- LDY / BIT
n_in when others;
with oper4 select v_out <=
data_in(6) when "1001", -- BIT
v_in when others;
end gideon;
| gpl-3.0 | 13d3a532b183677d6827c74ba761acf5 | 0.488796 | 3.1875 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op978_11.vhdl | 1 | 5,996 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9ee5febe0726e77e226065e152fe75c7 | 0.577885 | 3.127804 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/PixelProcessor.vhd | 1 | 3,642 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
--LIBRARY altera;
--USE altera.maxplus2.ALL;
--LIBRARY lpm;
--USE lpm.lpm_components.ALL;
-- VGA std format 640 by 480 pixels in a frame
-- register them, count line by line
-- checks the colour of each pixel, if it is ORANGE, then light an LED up
ENTITY PixelProcessor IS
PORT
(
clk : in std_logic;
TrainFLAG : in std_logic; -- '1'to '0' transition means take current frame target area average RGB/YUV colours for recognition
Aclr : in std_logic ; -- used to clear the accumulators used during training
VVV : in unsigned (7 downto 0) ;
Hsync : in std_logic; -- vertical and horizontal sync signals
Row : in unsigned (8 downto 0); -- 480 == 256+128+64 ie. "111000000"
Column : in unsigned (9 downto 0); -- 640 == 512+128 ie. "1010000000"
Vsync : in std_logic;
AccumulateSIGNAL : in std_logic; -- is HIGH during hysnc's within a frame, reset by Vsync
CalculateSIGNAL : in std_logic; -- is HIGH during gap between last hysnc in a frame, reset by Vsync
WindowROW : in std_logic; -- true for valid ROWs in specified processing window
WindowCOLUMN: in std_logic; -- true for valid COLUMNs in specified processing window
UflagREG,YflagREG,Y1flagREG,VFlagREG: out std_logic;
flag: out std_logic; -- debugging flag
PixelMATCH: out std_logic
-- Row & Column strobed are latched to ensure stable values in sync with pixel data
);
END PixelProcessor;
-- first register the pixel stream
ARCHITECTURE PixelProcessor_v1 OF PixelProcessor IS
signal p1: unsigned (7 downto 0);
signal r1: unsigned (9 downto 0);
signal tempV: integer range 0 to 512;
signal Window: std_logic;
signal VFlag: std_logic;
signal flagCLK: std_logic;
signal VVVmean: integer range 0 to 512;
--HERE can use 32bit integers to start then refine to change bit width to suit.
shared variable TESTpixCOUNT: natural range 0 to 307200 :=0; -- max range of full VGA resolution
shared variable TRAINpixCOUNT: natural range 0 to 307200 :=0;
BEGIN
---------------------------------------------------------------------------
TRAINaccumulate: process(clk, TrainFlag, aclr, AccumulateSIGNAL,Window)
begin
if (aclr = '1') then
--HERE
elsif (clk'event) and (clk='0') then
if (TrainFlag='1')and (AccumulateSIGNAL='1') and (Window ='1') then
--HERE
end if;
end if;
end process TRAINaccumulate;
---------------------------------------------------------------------------
TRAINcalculate: process(TrainFlag,CalculateSIGNAL) -- at end of training period do this, but only at start of a frame (and end of Vsync period)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
if (TrainFlag = '1')then
-- HERE
end if;
end if;
end process TRAINcalculate;
---------------------------------------------------------------------------
TESTaccumulate: process(clk, Vsync, TrainFLAG, AccumulateSIGNAL, Window)
begin
if (Vsync = '1') then -- clear count for every frame
--HERE
elsif (clk'event) and (clk='0') then -- when not training try testing for object
if (TrainFLAG='0') and (AccumulateSIGNAL ='1') and (Window='1') then
--HERE
end if;
end if;
end process TESTaccumulate;
---------------------------------------------------------------------------
TESTcalculate: process(TrainFLAG, CalculateSIGNAL)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') and (TrainFlag = '0') then
--HERE
end if;
end process TESTcalculate;
---------------------------------------------------------------------------
END PixelProcessor_v1;
| gpl-2.0 | 4b626ba20bc836aceaecb68b2a591de2 | 0.637287 | 3.708758 | false | true | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v7.vhd | 5 | 21,232 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (burst of 2), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v7 is
generic (
g_simulation : boolean := false;
g_read_fifo : boolean := false;
q_tcko_data : time := 100 ps;
A_Width : integer := 13;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
req : in t_mem_burst_32_req;
resp : out t_mem_burst_32_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_A : out std_logic_vector(A_Width-1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v7;
architecture Gideon of ext_mem_ctrl_v7 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002B", "000" ), -- mode register, burstlen=8, writelen=8, CAS lat = 2, interleaved
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ) );
type t_ints is array(natural range <>) of integer;
constant c_delays : t_ints(0 to 15) := (
2, 4, 2, 3, -- R2R (other row&other bank, other row, other bank, same row+bank)
4, 5, 4, 5, -- R2W
2, 5, 2, 3, -- W2R
2, 4, 2, 3 );-- W2W
type t_state is (boot, init, idle, sd_cas );
signal state : t_state;
signal sdram_d_o : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal sdram_d_t : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal wdata_tri : std_logic_vector(8 downto 0) := (others => '1');
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal mem_a_i : std_logic_vector(SDRAM_A'range) := (others => '0');
signal mem_ba_i : std_logic_vector(SDRAM_BA'range) := (others => '0');
signal cs_n_i : std_logic := '1';
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal do_refresh_d : std_logic := '0';
signal trigger_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_out : std_logic_vector(15 downto 0) := (others => '0');
signal wdata : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_i : std_logic_vector(35 downto 0) := (others => '0');
signal wdata_av : std_logic;
signal fifo_wdata_in : std_logic_vector(35 downto 0);
signal wdqm : std_logic_vector(1 downto 0);
signal dqm_override : std_logic := '1';
-- signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(5 downto 0) := "000000";
signal burst_start : std_logic_vector(5 downto 0) := "000000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal same_bank : std_logic;
signal last_row : std_logic_vector(12 downto 0) := "0101011010101";
signal addr_row : std_logic_vector(12 downto 0);
signal same_row : std_logic;
signal addr_column : std_logic_vector(9 downto 0);
signal next_activate : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal rwn_i : std_logic := '1';
signal tag_fifo : std_logic_vector(7 downto 0);
signal rdata_tag : std_logic_vector(7 downto 0);
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic := '0'; -- forced low for when there is no fifo
signal push_cmd : std_logic;
signal push_read_cmd : std_logic;
signal crazy_index_slv : std_logic_vector(3 downto 0);
signal crazy_index : integer range 0 to 15;
signal wtoggle : std_logic;
signal wdata_get : std_logic;
begin
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av and not do_refresh_d;
push_cmd <= req.request and not cmd_af;
push_read_cmd <= push_cmd and req.read_writen;
resp.ready <= not cmd_af;
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(address_fifo'length);
addr_bank <= address_fifo(14 downto 13);
addr_row <= address_fifo(24 downto 15) & address_fifo(12 downto 10);
addr_column <= address_fifo( 9 downto 0);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_tag_fifo: entity work.srl_fifo
generic map (
Width => 8,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => burst_start(1),
PutElement => push_read_cmd,
FlushFifo => '0',
DataIn => req.request_tag,
DataOut => tag_fifo,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => open );
rdata_out <= rdata_lo & rdata_hi;
b_read: block
signal rtoggle : std_logic;
signal rsp_data : std_logic_vector(31 downto 0);
signal rsp_data_tag : std_logic_vector(7 downto 0);
signal rsp_rdata_av : std_logic;
begin
-- data compacter 16->32
process(clock)
begin
if rising_edge(clock) then
-- handle reads
rsp_rdata_av <= '0';
if dack(0)='1' then
rtoggle <= not rtoggle;
if rtoggle='1' then
rsp_data(31 downto 16) <= rdata_out;
rsp_data_tag <= rdata_tag;
rsp_rdata_av <= '1';
else
rsp_data(15 downto 0) <= rdata_out;
end if;
end if;
-- reset
if reset='1' then
rtoggle <= '0';
rsp_data <= (others => '0');
rsp_data_tag <= (others => '0');
end if;
end if;
end process;
r_no_read_fifo: if not g_read_fifo generate
resp.rdata_av <= rsp_rdata_av;
resp.data <= rsp_data;
resp.data_tag <= rsp_data_tag;
end generate;
r_read_fifo: if g_read_fifo generate
i_read_fifo: entity work.srl_fifo
generic map (
Width => 40,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => rsp_rdata_av,
FlushFifo => '0',
DataIn(39 downto 32) => rsp_data_tag,
DataIn(31 downto 0) => rsp_data,
DataOut(39 downto 32) => resp.data_tag,
DataOut(31 downto 0) => resp.data,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => resp.rdata_av );
end generate;
end block;
fifo_wdata_in <= req.byte_en & req.data;
i_write_fifo: entity work.SRL_fifo
generic map (
Width => (c_data_width*9)/8,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => wdata_get,
PutElement => req.data_push,
FlushFifo => '0',
DataIn => fifo_wdata_in,
DataOut => wdata_i,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => wdata_av );
process(clock)
begin
if rising_edge(clock) then
if dnext(0)='1' then
wtoggle <= not wtoggle;
end if;
if reset='1' then
wtoggle <= '0';
end if;
end if;
end process;
wdata_get <= dnext(0) and wtoggle;
wdata(15 downto 0) <= wdata_i(15 downto 0) after 1 ns when wtoggle='0' else wdata_i(31 downto 16) after 1 ns;
wdata(17 downto 16) <= wdata_i(33 downto 32) after 1 ns when wtoggle='0' else wdata_i(35 downto 34) after 1 ns;
wdqm <= (others => '1') when dqm_override='1' else
(others => '0') when dnext(0)='0' else not wdata(17 downto 16);
same_row <= '1' when addr_row = last_row else '0';
same_bank <= '1' when addr_bank = last_bank else '0';
crazy_index_slv <= not rwn_i & not rwn_fifo & same_row & same_bank;
crazy_index <= to_integer(unsigned(crazy_index_slv));
trigger_refresh <= do_refresh_d and not (inhibit_d or inhibit);
process(clock)
procedure send_refresh_cmd is
begin
if next_delay = 0 then
do_refresh <= '0';
do_refresh_d <= '0';
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
col_addr <= addr_column;
last_bank <= addr_bank;
last_row <= addr_row;
mem_a_i(addr_row'range) <= addr_row;
mem_ba_i <= addr_bank;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
end procedure;
procedure issue_read_or_write is
begin
mem_a_i(9 downto 0) <= col_addr;
do_refresh_d <= do_refresh;
if req_i='0' or do_refresh='1' then
if rwn_i='0' then
next_delay <= 5;
else
next_delay <= 4;
end if;
mem_a_i(10) <= '1'; -- auto precharge
next_activate <= '1';
else
next_delay <= c_delays(crazy_index);
mem_a_i(10) <= not (same_row and same_bank); -- do not AP when we'll continue in same row
next_activate <= not (same_row and same_bank); -- only activate next time if we also AP.
end if;
if delay=0 then
if rwn_i='0' then
if wdata_av='1' then
wdata_tri(7 downto 0) <= (others => '0') after 1 ns;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
dnext <= "1111" after 1 ns;
state <= idle;
end if;
else
if rdata_af='0' then
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
dack(dack'high downto dack'high-3) <= (others => '1');
burst_start(2) <= '1';
state <= idle;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
cs_n_i <= '1' after 1 ns;
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
if burst_start(1)='1' then
rdata_tag <= tag_fifo;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
wdata_tri <= "11" & wdata_tri(wdata_tri'high downto 2) after 1 ns;
dack <= '0' & dack(dack'high downto 1);
burst_start <= '0' & burst_start(burst_start'high downto 1);
dnext <= '0' & dnext(dnext'high downto 1) after 1 ns;
case state is
when boot =>
enable_sdram <= '1';
if g_simulation then
state <= init;
elsif refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
mem_ba_i <= (others => '0'); -- for DDR and such, maybe the upper 2/3 bits
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if next_delay = 0 then
next_delay <= 7;
cs_n_i <= '0' after 1 ns;
if init_cnt = c_init_array'high then
state <= idle;
dqm_override <= '0';
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' then
if next_activate='1' and next_delay=0 then
accept_req;
elsif next_activate='0' and next_delay=1 then
rwn_i <= rwn_fifo;
col_addr <= addr_column;
state <= sd_cas;
end if;
else
do_refresh_d <= do_refresh;
end if;
end if;
when sd_cas =>
issue_read_or_write;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
rdata_tag <= (others => '0');
dqm_override <= '1';
state <= boot;
wdata_tri <= (others => '0');
delay <= 0;
next_delay <= 0;
do_refresh <= '0';
do_refresh_d <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
next_activate <= '1';
rwn_i <= '1';
end if;
end if;
end process;
-- Generate rack; the signal that indicates that a request is going to be issued
-- and thus taken from the command fifo.
process(state, trigger_refresh, inhibit, req_i, next_delay, next_activate)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
null;
elsif inhibit='0' and req_i='1' then
if next_activate='1' and next_delay = 0 then
rack <= '1';
elsif next_activate='0' and next_delay = 1 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
SDRAM_A <= mem_a_i;
SDRAM_BA <= mem_ba_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_dout: entity work.my_ioddr
port map (
pin => SDRAM_DQ(i),
clock => clock,
D0 => wdata(8+i),
D1 => wdata(i),
T0 => wdata_tri(1),
T1 => wdata_tri(0),
Q0 => rdata_hi(i),
Q1 => rdata_lo(i) );
end generate;
select_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
i_dqm_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => wdqm(1),
D1 => wdqm(0),
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 502812f56b46d806dc0f020d365fe2eb | 0.451253 | 3.813218 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate3_inst.vhd | 1 | 164 | altaccumulate3_inst : altaccumulate3 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
| gpl-2.0 | 6a6622c853e193835339fb65b8fe0d39 | 0.621951 | 2.827586 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/clock/vhdl_source/real_time_clock.vhd | 5 | 7,602 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity real_time_clock is
generic (
g_leap : boolean := true;
g_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end entity;
architecture gideon of real_time_clock is
signal year : unsigned(6 downto 0);
signal month : unsigned(3 downto 0);
signal date : unsigned(4 downto 0);
signal day : unsigned(2 downto 0);
signal hour : unsigned(4 downto 0);
signal minute : unsigned(5 downto 0);
signal second : unsigned(5 downto 0);
signal hundredths : unsigned(6 downto 0);
signal lock : std_logic;
signal tick : std_logic;
signal div_tick : std_logic;
signal div_count : integer range 0 to g_freq/100;
signal fat_packed : unsigned(31 downto 0);
type t_int5_array is array(natural range <>) of integer range 0 to 31;
constant c_month_length : t_int5_array(0 to 15) := (
31, -- dummy
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31, -- JAN - DEC
30, 30, 31 ); -- dummys
signal month_length : t_int5_array(0 to 15) := c_month_length;
--/* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */
--/* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */
begin
month_length(2) <= 29 when year(1 downto 0)="00" and g_leap else 28;
fat_packed <= year & month & date & hour & minute & second(5 downto 1);
process(clock)
variable tick_save : integer range 0 to 15 := 0;
begin
if rising_edge(clock) then
tick <= '0';
div_tick <= '0';
if div_count = 0 then
div_count <= (g_freq / 100) - 1;
div_tick <= '1';
-- tick_save := tick_save+1;
else
div_count <= div_count - 1;
end if;
if lock='0' then
if div_tick='1' then
tick <= '1';
elsif tick_save /= 0 then
tick_save := tick_save - 1;
tick <= '1';
end if;
elsif div_tick='1' then
tick_save := tick_save + 1;
end if;
if tick='1' then
if hundredths = 99 then
hundredths <= to_unsigned( 0, hundredths'length);
if second = 59 then
second <= to_unsigned(0, second'length);
if minute = 59 then
minute <= to_unsigned(0, minute'length);
if hour = 23 then
hour <= to_unsigned(0, hour'length);
if day = 6 or day = 7 then
day <= to_unsigned(0, day'length);
else
day <= day + 1;
end if;
if date = month_length(to_integer(month)) then
date <= to_unsigned(1, date'length);
if month = 12 then
month <= to_unsigned(1, month'length);
year <= year + 1;
else
month <= month + 1;
end if;
else
date <= date + 1;
end if;
else
hour <= hour + 1;
end if;
else
minute <= minute + 1;
end if;
else
second <= second + 1;
end if;
else
hundredths <= hundredths + 1;
end if;
end if;
resp <= c_io_resp_init;
if req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(year'range) <= std_logic_vector(year);
when X"1" =>
resp.data(month'range) <= std_logic_vector(month);
when X"2" =>
resp.data(date'range) <= std_logic_vector(date);
when X"3" =>
resp.data(day'range) <= std_logic_vector(day);
when X"4" =>
resp.data(hour'range) <= std_logic_vector(hour);
when X"5" =>
resp.data(minute'range) <= std_logic_vector(minute);
when X"6" =>
resp.data(second'range) <= std_logic_vector(second);
when X"7" =>
resp.data(hundredths'range) <= std_logic_vector(hundredths);
when X"8" =>
resp.data <= std_logic_vector(fat_packed(7 downto 0));
when X"9" =>
resp.data <= std_logic_vector(fat_packed(15 downto 8));
when X"A" =>
resp.data <= std_logic_vector(fat_packed(23 downto 16));
when X"B" =>
resp.data <= std_logic_vector(fat_packed(31 downto 24));
when others =>
null;
end case;
elsif req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
year <= unsigned(req.data(year'range));
when X"1" =>
month <= unsigned(req.data(month'range));
when X"2" =>
date <= unsigned(req.data(date'range));
when X"3" =>
day <= unsigned(req.data(day'range));
when X"4" =>
hour <= unsigned(req.data(hour'range));
when X"5" =>
minute <= unsigned(req.data(minute'range));
when X"6" =>
second <= unsigned(req.data(second'range));
when X"7" =>
hundredths <= unsigned(req.data(hundredths'range));
when X"C" =>
lock <= req.data(0);
when others =>
null;
end case;
end if;
if reset='1' then
year <= to_unsigned(30, year'length);
month <= to_unsigned( 4, month'length);
date <= to_unsigned( 6, date'length);
day <= to_unsigned( 2, day'length);
hour <= to_unsigned(15, hour'length);
minute <= to_unsigned(59, minute'length);
second <= to_unsigned(23, second'length);
hundredths <= to_unsigned( 0, hundredths'length);
lock <= '0';
div_count <= 0;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | f3f9e3809044553ff7ba6d02661c0b60 | 0.394896 | 4.456038 | false | false | false | false |
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